JPH10189491A - Formation of insulation protective barrier for ti-si-n and ti-b-n base having low defect density - Google Patents

Formation of insulation protective barrier for ti-si-n and ti-b-n base having low defect density

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Publication number
JPH10189491A
JPH10189491A JP9301179A JP30117997A JPH10189491A JP H10189491 A JPH10189491 A JP H10189491A JP 9301179 A JP9301179 A JP 9301179A JP 30117997 A JP30117997 A JP 30117997A JP H10189491 A JPH10189491 A JP H10189491A
Authority
JP
Japan
Prior art keywords
film
silicon
layer
atmosphere
boron
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9301179A
Other languages
Japanese (ja)
Other versions
JP4065351B2 (en
Inventor
Pin Ru Jion
− ピン ル ジオン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US08/784,657 external-priority patent/US6017818A/en
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of JPH10189491A publication Critical patent/JPH10189491A/en
Application granted granted Critical
Publication of JP4065351B2 publication Critical patent/JP4065351B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28556Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76843Barrier, adhesion or liner layers formed in openings in a dielectric
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76853Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855After-treatment introducing at least one additional element into the layer
    • H01L21/76856After-treatment introducing at least one additional element into the layer by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner

Abstract

PROBLEM TO BE SOLVED: To lower the defect density of an insulation protective film by providing a porous barrier layer containing titanium and nitrogen, performing post- treatment and introducing silicon into at least the uppermost face of the porous layer. SOLUTION: TDMAT and [(CH3 )2 N]4 Ti are thermally decomposed (104) and a wafer is heated while being exposed to a precursor substance thus decomposing the precursor substance thermally and bonding the decomposed precursor substance onto the wafer in the form of a film. The film is composed of Ti-N-C which is a porous material absorbing O2 easily. Subsequently, it is heated (106) preferably in pure silane atmosphere, diluted silane atmosphere, disilane atmosphere or any other atmosphere for forming silicon in a film. Thereafter, the wafer is further processed or exposed to oxygen atmosphere (108) before being processed furthermore. According to the method, oxygen is absorbed into the film.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は集積回路構造体と製
法に関する。
The present invention relates to an integrated circuit structure and a manufacturing method.

【0002】[0002]

【従来の技術】窒化チタン(TiN)はコンタクト、バ
イアス(vias)、トレンチ及び相互接続積層での拡
散障壁とし通常用いられている。また、窒化チタンは化
学的蒸着(CVD)タングステン用の接着層として、C
VDタングステン、CVDアルミニウムの核生成層とし
ての役目を果すこともできる。良好な障壁層は、段部被
覆法が良くて、無空隙プラグ形成を達成し、コンタクト
/バイアス/トレンチの底部で充分な障壁厚を達成する
こと、拡散障壁性が良くてタングステン蒸着中の金属拡
散を防止し、下層の金属又は珪素のWF6 攻撃を防止す
ること。熱サイクル中隣接材料に不活性であり、低反応
性であること、電気的性質が許容できること。例えばコ
ンタクト/バイアスの抵抗が低いこと、接合漏れが低い
ことが必要である。更に、障壁層は出来るだけ薄くして
相互接続積層の厚みを低下させることが必要である。
BACKGROUND OF THE INVENTION Titanium nitride (TiN) is commonly used as a diffusion barrier in contacts, vias, trenches and interconnect stacks. Titanium nitride is also used as an adhesion layer for chemical vapor deposition (CVD) tungsten.
VD tungsten and CVD aluminum can also serve as nucleation layers. A good barrier layer has good step coverage, achieves void-free plug formation, achieves a sufficient barrier thickness at the bottom of the contacts / bias / trench, has good diffusion barrier properties, Prevent diffusion and prevent WF 6 attack on underlying metal or silicon. Inert to adjacent materials during thermal cycling, low reactivity, and acceptable electrical properties. For example, low contact / bias resistance and low junction leakage are required. In addition, the barrier layers need to be as thin as possible to reduce the thickness of the interconnect stack.

【0003】反応性スパッターTixとチタンの急速熱
窒化で形成するTiNは拡散障壁として伝統的に用いら
れてきた。最近はPVDTiNをCVDTiNに換えて
0.35μm以下のコンタクト、トレンチ及びバイアス
に対する段部被覆性の要求を満たす傾向にある。CVD
TiNは金属の信頼性の問題と、PVDTiNが関係す
る接合漏れの問題とを克服するもので、CVDTiNは
接触抵抗と漏れを低く維持しながら、550℃での熱応
力に耐えることが出来る。更に、CVDTiNは平行化
PVDTiNよりも潜在的にクリーンな方法である。
[0003] Reactive sputter Tix and TiN formed by rapid thermal nitridation of titanium have traditionally been used as diffusion barriers. Recently, there has been a tendency to replace the PVD TiN with the CVD TiN to satisfy the requirement of step coverage for contacts, trenches and biases of 0.35 μm or less. CVD
TiN overcomes metal reliability issues and the joint leakage issues associated with PVD TiN, while CVD TiN can withstand thermal stress at 550 ° C. while maintaining low contact resistance and leakage. Further, CVDTiN is a potentially cleaner method than collimated PVD TiN.

【0004】TiC4 とNH3 の反応で付着させるCV
DTiNはこれまで利用されてきたが、幾つかの問題が
ある。問題のうちの幾つかは付着温度が高いこと、Ti
Nlのように塩素が取込まれること、気相中にNH4
l粒子が生成することである。塩素汚染は低減できる
が、このような方法では皆無とすることはできない。膜
は400℃よりも低い温度で付着させるときは、TiC
4 /NH3 法は利用できないが、金属−有機前駆物質を
用いることができる。通常用いられる2種の金属−有機
前駆物質はテトラキスメチルアミノチタン(TDMA
T)とテトラキスジエチルアミノチタン(TDEAT)
である。TDMATの熱分解に基づくCVDTiNの付
着では段部被覆性がよく、粒子の計数が少ない層が形成
するが、抵抗率の高い不安定な膜となる。抵抗率は金属
−有機前駆物質とアンモニアを反応させて改善できる
が、TDMATとNH3 の反応では段部被覆性の劣る膜
ができ、気相反応の関係する潜在的な問題、例えば粒子
生成がある。
CV deposited by reaction between TiC 4 and NH 3
Although DTiN has been used, there are several problems. Some of the problems are high deposition temperatures, Ti
Incorporation of chlorine like Nl, NH 4 C
1 particles are produced. Although chlorine contamination can be reduced, such methods cannot eliminate it. When the film is deposited at temperatures below 400 ° C., the TiC
The 4 / NH 3 method is not available, but metal-organic precursors can be used. Two commonly used metal-organic precursors are tetrakismethylaminotitanium (TDMA)
T) and tetrakisdiethylaminotitanium (TDEAT)
It is. The deposition of CVD TiN based on the thermal decomposition of TDMAT forms a layer with good step coverage and low particle count, but results in an unstable film with high resistivity. The resistivity can be improved by reacting the metal-organic precursor with ammonia, but the reaction of TDMAT and NH 3 results in a film with poor step coverage and potential problems associated with the gas phase reaction, such as particle formation. is there.

【0005】アンモニアを用いずにTDMAT又はTD
EATを用いてTiNを付着させる可能性が文献で論じ
られているが、以下のことは教示されていない。即ち、
アンモニアを用いずにTDEAT又はTDMATから付
着させた膜は性質が極めて劣ると言われている。例えば
スン(Sun )とツァイ(Tsai):「金属有機源からの低
圧化学蒸着窒化チタンの特色」〔(ESSDERC’9
4会報、第291−4頁)。この文献は言及することに
より本明細書に取り入れる〕参照のこと。
[0005] TDMAT or TD without ammonia
The possibility of depositing TiN using EAT has been discussed in the literature, but does not teach the following. That is,
Films deposited from TDEAT or TDMAT without the use of ammonia are said to have very poor properties. For example, Sun and Tsai: "Characteristics of low pressure chemical vapor deposited titanium nitride from metal organic sources" [(ESSDERC '9
4 Bulletin, pp. 291-4). This document is incorporated herein by reference].

【0006】Ti−Si−N化合物はTiNよりも更に
良好な拡散障壁を提供するので、最新のメタライゼイシ
ョンの応用にとって魅力がある。現在、Ti−Si−N
膜の製造上2つの主要な方法が研究中であり、両方とも
顕著な制限がある。(N2 雰囲気でのTi−Siターゲ
ットの反応性スパッターはカリフォルニヤ工科大学(C
al Tech)での広範囲の研究で代表されるように
もっとも確立された方法であるが、スパッター法の方向
性により、付着膜の段部被覆性は、高アスペクト比のコ
ンタクト、バイアス及びトレンチには極めて劣る。
[0006] Ti-Si-N compounds are attractive for modern metallization applications because they provide a better diffusion barrier than TiN. Currently, Ti-Si-N
Two major methods of membrane production are under investigation, both with significant limitations. (Reactive sputtering of Ti-Si target in N 2 atmosphere was performed at California Institute of Technology (C
al Tech), is the most established method, as represented by the extensive direction of sputtering, but due to the orientation of the sputtering method, the step coverage of the deposited film can be reduced for high aspect ratio contacts, vias and trenches. Very poor.

【0007】シラン、アンモニア、TDEATの混合物
を用いる化学的蒸着法はサンディア国立研究所で研究中
である、この方法は段部被覆性のより良い膜を提供でき
るが、TDEATとNH3 との気相反応では粒子が形成
し、生成膜の欠陥密度は高い。
A chemical vapor deposition method using a mixture of silane, ammonia and TDEAT is under study at Sandia National Laboratories. This method can provide a film with better step coverage, but has the disadvantage of combining TDEAT with NH 3. In the phase reaction, particles are formed, and the defect density of the resulting film is high.

【0008】[0008]

【発明が解決しようとする課題】本発明の目的は前述の
2つの方法での問題を解決する欠陥密度の低い絶縁保護
性のTi−Si−N膜の革新的製法を提供することにあ
る。
SUMMARY OF THE INVENTION It is an object of the present invention to provide an innovative method for producing an insulating and protective Ti-Si-N film having a low defect density and solving the above two problems.

【0009】[0009]

【課題を解決するための手段】上記の目的は本発明の方
法ではまずチタンと窒素を含有する多孔性障壁層を付着
し、次いで付着後の処理を行って多孔性層の少なくとも
最上面中に珪素を導入して、珪素濃度の高い表面を提供
することにより達成される。(別の態様では付着後の処
理は珪素の代わりに又は珪素に加えて硼素を導入す
る)。多孔性障壁層はまた好ましくは炭素をかなりの割
合で含み、必要あれば付着後の処理前に珪素をかなりの
割合で含む。
SUMMARY OF THE INVENTION The object of the present invention is to provide a method according to the invention in which a porous barrier layer containing titanium and nitrogen is first deposited and then a post-deposition treatment is carried out so that at least the top surface of the porous layer is This is achieved by introducing silicon to provide a silicon-rich surface. (In another embodiment, the post-deposition treatment introduces boron instead of or in addition to silicon). The porous barrier layer also preferably contains a significant proportion of carbon and, if necessary, a significant proportion of silicon before processing after deposition.

【0010】本発明の方法と構造体の長所としては、T
i−Si−N膜表面はSiに富むため(又はTi−B−
N膜表面はBに富むため)、膜中への酸素吸収が極小に
なり形成膜が安定化する。また、表面がSiに富むこと
又はBに富むことはAlのぬれとCuへの吸着向上に役
立つため、最新のメタライゼイションの適用に有用であ
る。スパッター法に較べて、本発明は段部被覆性が極め
て良く、Si/Ti比の制御が容易な膜の付着法が提供
される。TDEAT+NH3 +SiH4 法に較べて、本
発明はTi源とNH3 間の気相反応を皆無にする本発明
の方法は欠陥密度の低い絶縁保護性の膜を提供できる。
本発明の方法は表面組成を含む化学組成の制御に融通性
がある。本発明の方法は市販のCVD反応器で実施で
き、実施が容易である。
An advantage of the method and structure of the present invention is that T
Since the surface of the i-Si-N film is rich in Si (or Ti-B-
Since the N film surface is rich in B), the absorption of oxygen into the film is minimized, and the formed film is stabilized. In addition, the fact that the surface is rich in Si or B is useful for improving the wetting of Al and the adsorption to Cu, and is therefore useful for the application of the latest metallization. Compared with the sputter method, the present invention provides a method for adhering a film, in which the step coverage is extremely good and the control of the Si / Ti ratio is easy. Compared with the TDEAT + NH 3 + SiH 4 method, the present invention eliminates the gas phase reaction between the Ti source and NH 3 and can provide an insulating protective film having a low defect density.
The method of the present invention is flexible in controlling chemical composition, including surface composition. The method of the present invention can be carried out in a commercial CVD reactor and is easy to carry out.

【0011】[0011]

【発明の実施の形態】本発明を添付図に基づき説明す
る、添付図は本発明の重要な代表的な実施態様を示すも
ので、言及することで本明細書に組み入れる。
BRIEF DESCRIPTION OF THE DRAWINGS The invention will be described with reference to the accompanying drawings, which show important representative embodiments of the invention, and are incorporated herein by reference.

【0012】本発明の数多くの革新的な特徴を特に現在
の好ましい態様に基づいて説明するが、ここに示すこれ
らの実施態様は革新的な特徴のもつ多くの有用な用途の
うちの幾つかを示す実施例に過ぎないものである。一般
に、本明細書の開示は請求項に記載の各種の発明のいず
れの範囲を必ずしも限定するものではない。更に、幾つ
かの開示は本発明の幾つかの特徴についてのものであっ
て、その他の特徴についてのものでない。
While a number of innovative features of the present invention will be described with particular reference to the presently preferred embodiments, these embodiments set forth herein illustrate some of the many useful applications of the innovative features. It is only an example shown. In general, the disclosure herein does not necessarily limit any scope of the various claimed inventions. In addition, some disclosures are for some features of the invention and not for others.

【0013】図1は本発明の1実施態様の工程の流れを
示す流れ図である。本発明を用いるデバイスの製造出発
点は多くのデバイスの加工と同じである。事実、標準的
加工が中間レベルの誘電体の形成、バイアス/コンタク
ト用のトレンチ又は孔の形成に至る全部の工程に適用さ
れる。更に、標準的加工はTiN系層の形成後でも、本
発明の発明的焼鈍工程の後でも追加的に利用できる。本
発明の方法は、金属−有機化学的蒸着(MOCVD)を
行って窒化チタン膜を形成することが出発点である(工
程104)。この膜は中間レベルの誘電体上、トレンチ
又は孔の側壁上、トレンチ又は孔の底面、従来のTiN
が用いられてきた他の箇所に形成される。好ましくは、
工程104はTDMAT、[(CH3 2 N]4 Tiの
熱分解により行う。TDMATは液体であり、好ましく
は例えばHe又はN2 のような担体ガスを用いて反応器
中に導入する。この分解は好ましくは温度が300°〜
500℃の範囲、圧力が0.1〜50torrの範囲で
行う。分解時間は目的の膜厚で変わる。別の実施態様で
は、C2 5 をCH3 の代りに用いて前駆物質を[(C
2 5 2 N]4 Tiとすることができる。更に別の実
施態様では前駆物質は好ましくは[(CH3 )(C2
5 )N]4 Tiである。
FIG. 1 is a flowchart showing the flow of the process according to one embodiment of the present invention. The starting point for manufacturing a device using the present invention is the same as for processing many devices. In fact, standard processing applies to all steps from the formation of intermediate level dielectrics to the formation of trenches or holes for bias / contact. Furthermore, standard processing can be additionally used after the formation of the TiN-based layer and after the inventive annealing step of the present invention. The method of the present invention starts with a metal-organic chemical vapor deposition (MOCVD) process to form a titanium nitride film (step 104). This film may be on an intermediate level dielectric, on the sidewalls of the trench or hole, on the bottom of the trench or hole, in a conventional TiN
Are formed at other locations where they have been used. Preferably,
Step 104 is performed by thermal decomposition of TDMAT and [(CH 3 ) 2 N] 4 Ti. TDMAT is a liquid, preferably introduced into the reactor using a carrier gas such as He or N 2. This decomposition is preferably carried out at temperatures between 300 ° and
The process is performed at a temperature of 500 ° C. and a pressure of 0.1 to 50 torr. The decomposition time varies depending on the desired film thickness. In another embodiment, the C 2 H 5 the precursors used in place of CH 3 [(C
2 H 5 ) 2 N] 4 Ti. In yet another embodiment, the precursor is preferably [[CH 3 ) (C 2 H
5 ) N] 4 Ti.

【0014】更に工程104では、前駆物質に露出させ
ながらウェーハを加熱して前駆物質を熱分解させてウェ
ーハ上に膜として付着させる。形成膜はTi−N−Cか
ら構成され、多孔性材料であって、容易にO2 を吸収す
る。O2 の吸収によりこの膜は抵抗が高くなり、極めて
不安定になる。特に、この膜の抵抗率は膜を酸素含有空
気に露出するにつれて大きく増加する(図2の曲線20
2参照のこと)。
In step 104, the wafer is heated while being exposed to the precursor to thermally decompose the precursor and deposit the film on the wafer. The formed film is made of Ti—N—C, is a porous material, and easily absorbs O 2 . Due to the absorption of O 2 , this film has a high resistance and becomes extremely unstable. In particular, the resistivity of this film increases significantly as the film is exposed to oxygen-containing air (curve 20 in FIG. 2).
2).

【0015】次いで、加熱工程を行う(工程106)。
この工程は好ましくは純シラン雰囲気又は稀釈シラン雰
囲気、ジシラン雰囲気、B2 6 雰囲気、又は膜中に珪
素又は硼素を形成できる任意の他の雰囲気中で行う。好
ましくは、この工程は約350°〜500℃の温度、
0.1〜50torrの圧力下で約15〜240秒間行
う。焼鈍工程106は付着工程104と同じ反応器内で
行ってもよく、または同様の別の反応器で行ってもよ
い。若し、同一の反応器で行うときは、MOCVD工程
104と焼鈍工程106の両方で用いる温度は好ましく
はほぼ同一である。若し、両工程を別々の同様の反応器
で行うときは、工程104で形成した膜は工程102の
前に酸素にさらしてはならない。工程106が完了した
あとの膜は下記の構成をとる:Si含有ガス使用時はT
i−N−C−Si、B含有ガス使用時はTi−N−C−
B。膜内へのSiの取込みは図3bの曲線302から判
る。
Next, a heating step is performed (step 106).
This step is carried out preferably pure silane atmosphere or diluted silane atmosphere, disilane atmosphere, B 2 H 6 atmosphere or silicon or boron can be formed in the film in any other atmosphere. Preferably, this step is carried out at a temperature of about 350 ° -500 ° C.
This is performed under a pressure of 0.1 to 50 torr for about 15 to 240 seconds. Annealing step 106 may be performed in the same reactor as deposition step 104, or may be performed in another similar reactor. If performed in the same reactor, the temperatures used in both MOCVD step 104 and annealing step 106 are preferably substantially the same. If both steps are performed in separate and similar reactors, the film formed in step 104 must not be exposed to oxygen prior to step 102. After step 106 is completed, the film has the following structure: T when using a Si-containing gas.
When using i-NC-Si and B-containing gas, Ti-NC-
B. The incorporation of Si into the film can be seen from curve 302 in FIG. 3b.

【0016】工程106を行った後、ウェーハを更に加
工するか、又は酸素雰囲気にさらし(工程108)、次
いで更に加工する。工程108を行うと、酸素は膜中に
吸収されて膜は下記の構成をとる:Si含有ガス使用時
はTi−N−C−Si−O、B含有ガス使用時はTi−
N−C−B−O。しかし、ウェーハを酸素雰囲気に露出
しないと、酸素の吸収は行われない。
After performing step 106, the wafer is further processed or exposed to an oxygen atmosphere (step 108) and then further processed. After performing step 108, oxygen is absorbed into the film and the film assumes the following configuration: Ti-NC-Si-O when using a Si-containing gas, and Ti- when using a B-containing gas.
NCBO. However, oxygen is not absorbed unless the wafer is exposed to an oxygen atmosphere.

【0017】上記は特にチタンベース障壁膜の形成に関
するが、他の遷移金属をチタンの代りに使用してもよ
い。本発明の障壁層の形成に特に、タングステン、タン
タル又はモリブデンをチタンの代りに用いることができ
る。
Although the above is particularly concerned with the formation of a titanium-based barrier film, other transition metals may be used in place of titanium. In particular, tungsten, tantalum or molybdenum can be used instead of titanium for forming the barrier layer of the present invention.

【0018】図2は2種の異なる膜のシート抵抗RS
示す。図2のX軸は膜の空気露出時間量(分)を表わ
し、Y軸は膜のシート抵抗(オーム/□)を表わす。工
程106を行わない膜はシート抵抗が高い。これは図2
の曲線202で示される。更に、曲線202から判るよ
うに、工程106を行わないときの膜のシート抵抗は膜
を酸素に露出した後でかなり増加するが、工程106を
行った後では、シート抵抗は(曲線202と較べて)大
きさが小さく、空気中での安定性が極めて良い。これは
曲線204で示される。
FIG. 2 shows the sheet resistance R S of two different films. The X-axis in FIG. 2 represents the amount of air exposure time (minutes) of the film, and the Y-axis represents the sheet resistance (ohm / square) of the film. The film not subjected to the step 106 has a high sheet resistance. This is Figure 2
The curve 202 of FIG. Further, as can be seen from curve 202, the sheet resistance of the film without step 106 increases significantly after exposing the film to oxygen, but after performing step 106, the sheet resistance becomes (compared to curve 202). T) Small size and extremely good stability in air. This is shown by curve 204.

【0019】更に、実験データとして20nm膜のシー
ト抵抗の比較を表1に示す。これら3種の試験での変数
はシラン処理時間、急速熱焼鈍(RTA)の有無、各種
の実施温度である。
Further, Table 1 shows a comparison of the sheet resistance of the 20 nm film as experimental data. The variables in these three tests are the silane treatment time, the presence or absence of rapid thermal annealing (RTA), and the various operating temperatures.

【0020】[0020]

【表1】 [Table 1]

【0021】図3a、図3bは炭素、酸素、窒素、チタ
ン、珪素の種々の深さでの濃度を示すXPS深さ方向グ
ラフである。各図のX軸はそれぞれの深さに対応する。
スパッター時間の長さは深度距離を表わしている。これ
ら両図のY軸は全合計基準原子濃度(A.C.%)を表
わす。図3bの曲線302から工程106処理の膜は珪
素を含有しているが、工程106非処理の膜は珪素を含
有していないことが判る(図3aの曲線301では膜の
最上面は0秒で、底部は約16分で表示されている)。
珪素取込みは空気中からの酸素の取込み量の低下にとっ
て重要であり、これにより抵抗率は低下し、安定性は増
す。珪素又は硼素の取込みはこの後Cu又はAlのメタ
ライゼイションを行うときに有利となる。
FIGS. 3a and 3b are XPS depth graphs showing the concentration of carbon, oxygen, nitrogen, titanium and silicon at various depths. The X axis in each figure corresponds to each depth.
The length of the sputter time represents the depth distance. The Y-axis in both figures represents the total total reference atomic concentration (AC%). It can be seen from the curve 302 in FIG. 3B that the film treated in the step 106 contains silicon, but the film not treated in the step 106 does not contain silicon (in the curve 301 in FIG. 3A, the top surface of the film is 0 second). And the bottom is displayed in about 16 minutes).
Silicon uptake is important for reducing the uptake of oxygen from the air, which reduces resistivity and increases stability. The incorporation of silicon or boron is advantageous in the subsequent metallization of Cu or Al.

【0022】図3bの曲線304は工程106と108
処理後の膜中へ酸素吸収が限定されることを示す。
The curve 304 in FIG.
It shows that oxygen absorption is limited in the film after treatment.

【0023】図4は透過型電子回折(TEM)パターン
である。図4は工程106(0及び108)処理膜は非
晶質であることを示している。非晶質膜は障壁としての
用途では好ましい(多結晶膜とは反対である)。これは
多結晶構造では粒子境界中で金属拡散が速く進むからで
ある。
FIG. 4 is a transmission electron diffraction (TEM) pattern. FIG. 4 shows that the process 106 (0 and 108) processing film is amorphous. Amorphous films are preferred for use as barriers (as opposed to polycrystalline films). This is because in a polycrystalline structure, metal diffusion proceeds rapidly at grain boundaries.

【0024】図5は本発明の方法の第2の実施態様の流
れ図である。この方法は、シラン・ガスをMOCVD工
程で添加する以外は図1の方法と同じである。これによ
り珪素は層内により多く取込まれ、Si/Ti比のより
良い調整を容易にする。
FIG. 5 is a flow chart of a second embodiment of the method of the present invention. This method is the same as the method of FIG. 1 except that silane gas is added in the MOCVD step. This allows more silicon to be incorporated into the layer and facilitates better tuning of the Si / Ti ratio.

【0025】図8はTi−Si−N付着膜のシート抵抗
と、付着後のシラン焼鈍時間の関係を示すグラフであ
る。抵抗は2日間空気中に露出した後測定した。シート
抵抗はシラン中で約30秒焼鈍すると急激に低下するこ
とを明示している。
FIG. 8 is a graph showing the relationship between the sheet resistance of the Ti—Si—N deposited film and the silane annealing time after deposition. Resistance was measured after two days of exposure to air. It clearly shows that the sheet resistance drops sharply after annealing for about 30 seconds in silane.

【0026】図9はTi−Si−N付着膜のシート抵抗
と、Ti−Si−N付着中のシラン流量の関係を示すグ
ラフであり、測定は2日間空気漏出後に行った。これか
ら判るように、シラン流量が増加すると膜のシート抵抗
は増加し、従って珪素の取込みによる障壁層としての増
加値は珪素による高抵抗値と均合わせる必要がある。
FIG. 9 is a graph showing the relationship between the sheet resistance of the Ti-Si-N deposited film and the flow rate of silane during the deposition of Ti-Si-N. The measurement was performed after air leakage for two days. As can be seen, as the silane flow rate increases, the sheet resistance of the film increases, so the increase in barrier as a result of silicon incorporation must be balanced with the high resistance of silicon.

【0027】図10は本発明の層の断面構造を示す電子
顕微鏡写真であり、本方法は層の絶縁保護性が保持され
ていることを示している。
FIG. 10 is an electron micrograph showing the cross-sectional structure of the layer of the present invention, and shows that the method retains the insulating protection of the layer.

【0028】別の代表的付着法の実施態様 本実施態様は第1工程でTDMATを窒素の存在下熱分
解してTiN層を形成する。付着後直ちにこの層をシラ
ン雰囲気に露出して、シランとこの層を反応させて珪素
をこの層内に取込ませて珪素に富む表面層を形成させ
る。珪素の存在により層劣化を招く酸素吸収を抑制す
る。
Another Exemplary Deposition Method Embodiment In this embodiment, in a first step, TDMAT is pyrolyzed in the presence of nitrogen to form a TiN layer. Immediately after deposition, the layer is exposed to a silane atmosphere and the silane reacts with the layer to incorporate silicon into the layer to form a silicon-rich surface layer. Oxygen absorption that causes layer deterioration due to the presence of silicon is suppressed.

【0029】また、前駆物質としてTDMATを使用す
ると炭素を層内に高い百分率で取込むことができ、意外
にも層内の炭素は別に問題にはならないと考えられ、む
しろ層内の応力を低下させ、回路寿命には影響を与えな
いと考えられる。
Further, when TDMAT is used as a precursor, carbon can be taken into the layer in a high percentage, and it is thought that the carbon in the layer is not a problem. It does not affect the circuit life.

【0030】[0030]

【表2】 [Table 2]

【0031】付着法の実施態様2 本態様は第1工程でSiH4 、TDMAT、N2 (稀釈
剤を組合せて障壁層を形成する、深さが充分となったと
ころで、TDMATとN2 の流れを停止させるが、Si
4 は測定時間中連続して流す。記載の本実施態様は現
在の好ましい実施態様である。
Embodiment 2 of Deposition Method In this embodiment, in the first step, a barrier layer is formed by combining SiH 4 , TDMAT and N 2 (a diluent is used. When the depth becomes sufficient, the flow of TDMAT and N 2 Is stopped, but Si
H 4 flows continuously during the measurement time. The described embodiment is the presently preferred embodiment.

【0032】[0032]

【表3】 [Table 3]

【0033】付着法の実施態様3 SiH4 を他のSi源化合物、例えばSi2 6 に代替
することができる。本実施態様は、第1工程でSi2
6 とTDMATを不活性N2 と一緒に流し、第2工程で
TDMATとN2 の流れを停止させ、Si2 6 を流し
て、層表面中に珪素を余分に取込ませる。
Embodiment 3 of the Deposition Method SiH 4 can be replaced by another Si source compound, for example, Si 2 H 6 . In the present embodiment, in the first step, Si 2 H
6 and TDMAT are flowed together with the inert N 2 , the flow of TDMAT and N 2 is stopped in a second step, and Si 2 H 6 is flowed to allow extra silicon to be incorporated into the layer surface.

【0034】付着法の実施態様4 TDMATをTMEAT、即ちTi(NCH3
2 5 4 に代替させる、本実施例は、第1工程でシラ
ン、TMEAT、N2 を一緒に流す。第2工程では純シ
ランを流して表面層中に珪素を追加的に取込ませる。
Embodiment 4 of Deposition Method TDMAT was converted to TMEAT, ie, Ti (NCH 3 C
2 H 5) is replaced with 4, this embodiment, flow silane in the first step, TMEAT, the N 2 together. In the second step, pure silane is flown to additionally incorporate silicon into the surface layer.

【0035】付着法の実施態様5 TDMATをTDEAT、即ち、Ti(N(C2 5
2 4 に代替させる。この場合、TDEAT、シランを
2 又はその他の不活性稀釈剤と一緒に流してSi−N
−Ti層を付着させ、次の工程でシランだけを用いて上
表面中の珪素濃度を増加させる。
Embodiment 5 of Deposition Method TDMAT is converted to TDEAT, that is, Ti (N (C 2 H 5 )
2 ) Substitute 4 In this case, TDEAT, flowing silane with N 2 or other inert diluent Si-N
Depositing a Ti layer and increasing the silicon concentration in the upper surface using only silane in the next step.

【0036】付着法の実施態様6 本実施態様では、硼素源を用いてTix y N膜を形成
する。従って、硼素源成分(例えば、B2 6 )をSi
源成分の代りに多孔性TiN膜の付着際に用いる。本実
施例はTDEATとジボランをN2 又はその他の稀釈剤
と一緒に流してTi−B−N層を付着させ、次の工程で
ジボランのみを用いて上表面中の硼素濃度を増加させ
る。
Embodiment 6 of Deposition Method In this embodiment, a Ti x B y N film is formed using a boron source. Therefore, the boron source component (for example, B 2 H 6 )
Used when depositing a porous TiN film instead of the source component. This embodiment is adhered with Ti-B-N layer by flowing a TDEAT and diborane together with N 2 or other diluent, to increase the boron concentration in the upper surface by using only diborane in the next step.

【0037】代表的メタライゼイションの実施態様 本明細書に記載の本方法はメタライゼイションの適用、
特に銅(Cu)のメタライゼイションで使用できる。例
えば、図6に示す適用では、下部中間レベル誘電体51
5で包囲された導電層510(典型例としてアルミニウ
ム合金)の下にあるトランジスター(図示せず)を含む
半製品構造体を準備する。次いで、上部の中間レベル誘
電体520(例えば、TEOS付着SiO2 上のBPS
G)を付着させ、従来法(例えば、化学−機械的研磨又
はCMP)で平坦化する。次いで、(ダマセン(damasc
ene )型式の方法で)中間レベルの誘電体520をパタ
ーン化とエッチング処理してメタライゼイションライン
が所望されるスロット530を形成し、またバイアスが
所望される(即ち、下部電導層への電気的接触が所望さ
れる)より深い孔540を形成する。次いで、上記の方
法のうちの1つを用いて拡散障壁層530を付着させ
る。導電性の高い金属550(例えば銅)を従来法で全
体に付着させ、(例えばCMPを用いて)全体をエッチ
ングして中間レベルの誘電体520の平坦表面を金属5
50が存在しない箇所で露出させる。
Exemplary Metallization Embodiments The methods described herein apply metallization,
In particular, it can be used in copper (Cu) metallization. For example, in the application shown in FIG.
A semi-finished structure including a transistor (not shown) under a conductive layer 510 (typically an aluminum alloy) surrounded by 5 is provided. Then, the top intermediate level dielectric 520 (eg, BPS on TEOS deposited SiO 2 )
G) is deposited and planarized by conventional methods (eg, chemical-mechanical polishing or CMP). Next, (Damasc
ene) The intermediate level dielectric 520 is patterned and etched (in a manner of the type) to form the slots 530 where metallization lines are desired, and bias is desired (i.e., electrical connection to the lower conductive layer). (A contact is desired) to form a deeper hole 540. Next, a diffusion barrier layer 530 is deposited using one of the methods described above. A highly conductive metal 550 (e.g., copper) is deposited over the entire surface in a conventional manner, and the entire surface is etched (e.g., using CMP) to remove the flat surface of the intermediate level dielectric 520 to metal 5
It is exposed at a position where 50 does not exist.

【0038】本実施態様では、本発明の障壁層は中間レ
ベルの誘電体520の露出部上全部に形成される。即
ち、金属550が中間レベルの誘電体520と直接接触
する箇所は全然存在しない。これにより銅原子(又は寿
命短縮剤、例えば金)が中間レベルの誘電体を介して半
導体基板中に拡散する可能性が低減する。
In this embodiment, the barrier layer of the present invention is formed all over the exposed portion of the intermediate level dielectric 520. That is, there is no point where the metal 550 directly contacts the intermediate level dielectric 520. This reduces the likelihood of copper atoms (or lifetime shortening agent, eg, gold) diffusing into the semiconductor substrate through the intermediate level dielectric.

【0039】代表的メタライゼイションの実施態様2 図7に示す別のメタライゼイションの実施態様はソース
/ドレン拡散562方向に配列してポリサイド(ポリシ
リコン/シリサイド)ゲート560を有するトランジス
ターの形成を含む、次に、第1の中間レベルの誘電体層
564を形成する(必要あれば、このあと図示しないが
対応する複数の追加中間レベルの誘電体層を有する複数
の追加層を多重に付着、パターン化処理することもよく
行われる)。本明細書に開示の本発明の方法を用いて障
壁層570を付着させる前にコンタクト箇所566をパ
ターン化、エッチング処理する。次いで、金属層580
を付着させ、パターン化処理する。本代表的実施態様で
は、金属層580はアルミニウム合金であり、これは
(この好ましい実施態様ではフォースフィルTM(Force
FillTM)法で)高圧下、コンタクトホール中に強制注入
する。
Representative Metallization Embodiment 2 Another metallization embodiment shown in FIG. 7 is for forming a transistor having a polycide (polysilicon / silicide) gate 560 arranged in the direction of source / drain diffusion 562. Including, then, forming a first intermediate level dielectric layer 564 (if necessary, a plurality of additional layers, not shown but having a corresponding plurality of additional intermediate level dielectric layers, Patterning is often performed). The contact locations 566 are patterned and etched prior to depositing the barrier layer 570 using the inventive method disclosed herein. Next, the metal layer 580
And patterning is performed. In the present exemplary embodiment, the metal layer 580 is an aluminum alloy, which is (in this preferred embodiment, Forcefill ).
Fill TM ) method is forcibly injected into the contact hole under high pressure.

【0040】開示される革新的実施態様は、(a)半導
体材料の少なくとも1つの実質的にモノリシックな物体
を含む基板を準備する工程と、(b)チタンと窒素含有
雰囲気中でCVDで絶縁保護性層を付着させる工程と、
(c)上記絶縁保護性層を付着させたあとで、上記絶縁
保護性層を珪素又は硼素含有雰囲気に露出させる工程と
を含む薄膜形成法であって、前記工程(c)により上記
絶縁保護性層上に珪素又は硼素に富む表面を形成させる
薄膜形成法を提供される。
The disclosed innovative embodiments include (a) providing a substrate containing at least one substantially monolithic object of semiconductor material; and (b) isolating by CVD in a titanium and nitrogen containing atmosphere. Attaching a conductive layer;
(C) exposing the insulating protective layer to an atmosphere containing silicon or boron after attaching the insulating protective layer, wherein the step (c) comprises the steps of: A thin film forming method is provided for forming a silicon or boron rich surface on a layer.

【0041】開示される他の革新的実施態様は、チタン
と窒素とを含有する障壁薄膜層から成る集積回路であっ
て、上記薄膜は珪素又は硼素の組成が漸進的に変化し、
その第1表面では珪素又は硼素濃度が他に較べて高い集
積回路を提供される。
Another innovative embodiment disclosed is an integrated circuit comprising a barrier thin film layer containing titanium and nitrogen, wherein the thin film has a gradual change in the composition of silicon or boron,
An integrated circuit having a higher silicon or boron concentration on the first surface is provided.

【0042】改変と変更 当業者が認識するように、本明細書に記載の革新的概念
は広範囲の用途にわたり改変と変更が可能であり、従っ
て、本発明の主題の範囲は本明細書の特定の実施例の教
示に限定されない。
Modifications and Variations As will be appreciated by those skilled in the art, the innovative concepts described herein can be modified and varied over a wide range of applications, and the scope of the present subject matter is not limited to the particulars herein. Is not limited to the teachings of the embodiment.

【0043】CVDとメタライゼイションの一般的背景
は下記刊行物に記載されており、これら刊行物はその改
変と実施に就いて当業者の知識を示す一助となる:メタ
ライゼイションと金属−半導体の界面(バトラ編198
9);VLSIメタライゼイション:物理と技術(シエ
ナイ編1991);ムラルカ,「VLSIとULSI用
のメタライゼイション理論と実際(1993)」;集積
回路用マルチレベル・メタライゼイションハンドブック
(ウィルソン等編1993);ラオ,「マルチレベル・
インターコネクト技術(1993)」;化学蒸着(エム
・エル・ヒッチマン編1993);プラズマ加工に関す
る電気化学会の半年次学会会報;(これら全ての刊行物
は言及することにより本明細書に組み入れる)。
The general background of CVD and metallization is described in the following publications, which help show the knowledge of those skilled in the art in their modification and implementation: metallization and metal-semiconductors Interface (Batra edition 198)
9); VLSI Metallization: Physics and Technology (Siena, 1991); Muralka, "Metallization Theory and Practice for VLSI and ULSI (1993)"; Multilevel Metallization Handbook for Integrated Circuits (Wilson et al. 1993); Lao, "Multi-level
Interconnect Technology (1993) "; Chemical Vapor Deposition (M.L.Hitchmann, 1993); Report of the semiannual meeting of the Institute of Electrical Chemistry on Plasma Processing; (all of these publications are incorporated herein by reference).

【0044】以上の説明に関して更に以下の項を開示す
る。 (1)(a)半導体材料の少なくとも1つの実質的にモ
ノリシックな物体を含む基板を準備する工程と、(b)
チタンと窒素を含む雰囲気中でCVDで絶縁保護性層を
付着させる工程と、(c)上記絶縁保護性層を付着させ
たあとで、上記絶縁保護性層を珪素又は硼素を含有する
雰囲気に露出させる工程とを含む薄膜形成法であって、
前記工程(c)により上記絶縁保護性層上に珪素又は硼
素に富む表面を形成させる薄膜形成法。 (2)工程(c)は、中間工程を介在させずに工程
(b)の後直ちに行う、第1項記載の形成法。 (3)工程(b)は珪素又は硼素を含む雰囲気を用い
る、第1項記載の形成法。 (4)工程(b)はSiH4 を含む雰囲気を用いる、第
3項記載の形成法。 (5)工程(b)はTDMAT、TMEAT、TDEA
Tから成る群から選ばれたチタン源成分を含有する雰囲
気を用いる、第1項記載の形成法。 (6)急速熱焼鈍を次工程として更に含む、第1項記載
の形成法。 (7)チタンと窒素とを含有する障壁薄膜層から成る集
積回路であって、上記薄膜は珪素又は硼素の組成が漸進
的に変化し、その第1の表面では珪素又は硼素濃度が他
に較べて高い集積回路。 (8)薄膜は炭素を少なくとも10%含有する、第7項
記載の集積回路。 (9)薄膜は非晶質SiNX とTiNX とから成る、第
7項記載の集積回路。 (10)薄膜はTiNx と硼素との非晶質の組合せであ
る、第7項記載の集積回路。 (11)珪素又は硼素に富むと上記薄膜中への酸素の吸
収が低下する、第7項記載の集積回路。 (12)基板上に障壁層を形成して、コンタクト/バイ
アスを接合させる方法において、下部構造体を準備する
工程と、上記基板上に誘電体層を形成する工程と、上記
基板中に開孔を形成して上記下部構造の少なくとも1部
を露出させる工程(上記開口は側壁を有する)と、金属
−有機前駆物質を用いて膜を形成する工程(上記膜は上
記誘電体層上、上記開口側壁上、及び上記下部構造体の
上記露出部上に形成する)と、活性ガス雰囲気中で加熱
工程を行い、珪素又は硼素を上記膜中に取込む工程とを
含む方法。 (13)金属−有機前駆物が[(CH3 2 N]4
i、[(C2 5 2 N]4 Ti、[(CH3 )(C2
5 )N]4 Tiから成る群から選ばれた材料から成
る、第12項記載の方法。 (14)活性ガスが上記金属−有機膜中に珪素又は硼素
を取込ませる任意のガスから成る、第12項記載の方
法。 (15)活性ガスがシラン、ジシラン、ジボラン又はこ
れらの任意の組合から成る群から選ばれる、第12項に
記載の方法。 (16)下部構造体の基板である、第12項記載の方
法。 (17)下部構造体は電導層である、第12項記載の方
法。 (18)Ti−Si−N又はTi−B−N用CVD法で
あって、単一供給ガス(好ましくはTDMAT)がチタ
ンと窒素源の役割を果し、もう1つの供給ガスを珪素又
は硼素源として用いる。これにより気相粒子核生成が回
避され、一方、良好な絶縁保護性が得られる。所定の層
厚が付着されたとき、チタン/窒素又はチタン/硼素源
の流れを停止したのち、珪素又は硼素供給ガスをある期
間連続して流す。これにより、欠陥密度の低く、Si又
はBに富む、絶縁保護性のTi−N膜が形成される。第
2の実施態様では、単一供給ガス、例えばTDMATを
熱分解してTi−N層を形成させる。付着後の焼鈍を珪
素又は硼素を供給するガス中で行い、これらの物質を層
中に取込ませる。この層中への珪素又は硼素の取込みは
膜中への酸素吸収を最小にし、従って形成膜を安定化さ
せる。Si又はBに富む表面もAlのぬれとCuへの接
着を向上させるのに役立ち、従って最新のメタライゼイ
ションの適用に有用である。スパッター法に較べて、本
発明は段部被覆性が極めて良好で、Si/Ti比の制御
が容易な膜の付着法を提供する。TDEAT+NH3
SiH4 法に較べて、本発明はTi源とNH3 との気相
反応を皆無にする。
With respect to the above description, the following items are further disclosed. (1) (a) providing a substrate including at least one substantially monolithic object of a semiconductor material; (b)
Depositing an insulating protective layer by CVD in an atmosphere containing titanium and nitrogen, and (c) exposing the insulating protective layer to an atmosphere containing silicon or boron after depositing the insulating protective layer. And a step of forming a thin film,
A thin film forming method for forming a surface rich in silicon or boron on the insulating protective layer in the step (c). (2) The forming method according to (1), wherein the step (c) is performed immediately after the step (b) without an intermediate step. (3) The method according to (1), wherein the step (b) uses an atmosphere containing silicon or boron. (4) The method according to (3), wherein the step (b) uses an atmosphere containing SiH 4 . (5) Step (b) includes TDMAT, TMEAT, and TDEA.
2. The forming method according to claim 1, wherein an atmosphere containing a titanium source component selected from the group consisting of T is used. (6) The forming method according to (1), further comprising rapid thermal annealing as a next step. (7) An integrated circuit comprising a barrier thin film layer containing titanium and nitrogen, wherein the thin film has a composition of silicon or boron gradually changed, and a silicon or boron concentration on a first surface thereof is higher than that of the other. High integrated circuit. (8) The integrated circuit according to (7), wherein the thin film contains at least 10% of carbon. (9) The integrated circuit according to (7), wherein the thin film is made of amorphous SiN x and TiN x . (10) The integrated circuit according to (7), wherein the thin film is an amorphous combination of TiN x and boron. (11) The integrated circuit according to (7), wherein the richness of silicon or boron decreases the absorption of oxygen into the thin film. (12) In a method of forming a barrier layer on a substrate and joining contacts / bias, a step of preparing a lower structure, a step of forming a dielectric layer on the substrate, and an opening in the substrate. Exposing at least a part of the lower structure (the opening has a side wall); and forming a film using a metal-organic precursor (the film is formed on the dielectric layer and the opening is formed on the dielectric layer). Forming on the side wall and the exposed portion of the lower structure), and performing a heating step in an active gas atmosphere to incorporate silicon or boron into the film. (13) The metal-organic precursor is [(CH 3 ) 2 N] 4 T
i, [(C 2 H 5 ) 2 N] 4 Ti, [(CH 3 ) (C 2
H 5) N] consisting of a material selected from the group consisting of 4 Ti, method of paragraph 12, wherein. 14. The method of claim 12, wherein the active gas comprises any gas that incorporates silicon or boron into said metal-organic film. (15) The method according to item 12, wherein the active gas is selected from the group consisting of silane, disilane, diborane or any combination thereof. (16) The method according to (12), which is a substrate of a lower structure. (17) The method according to (12), wherein the lower structure is a conductive layer. (18) A CVD method for Ti-Si-N or Ti-BN, wherein a single supply gas (preferably TDMAT) serves as a titanium and nitrogen source and another supply gas is silicon or boron. Use as a source. This avoids gas phase particle nucleation, while providing good insulation protection. When the predetermined layer thickness has been deposited, the flow of the titanium / nitrogen or titanium / boron source is stopped and then the silicon or boron feed gas is flowed continuously for a period of time. Thereby, a Ti—N film having a low defect density and rich in Si or B and having an insulating protection property is formed. In a second embodiment, a single feed gas, such as TDMAT, is pyrolyzed to form a Ti-N layer. Annealing after deposition is performed in a gas that supplies silicon or boron to incorporate these substances into the layer. Incorporation of silicon or boron into this layer minimizes oxygen absorption into the film and thus stabilizes the formed film. Surfaces rich in Si or B also help improve Al wetting and adhesion to Cu, and are therefore useful for modern metallization applications. Compared with the sputter method, the present invention provides a method for depositing a film having excellent step coverage and easy control of the Si / Ti ratio. TDEAT + NH 3 +
Compared to the SiH 4 method, the present invention eliminates the gas phase reaction between the Ti source and NH 3 .

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の1実施態様を示す流れ図である。FIG. 1 is a flowchart illustrating one embodiment of the present invention.

【図2】先行技術の膜形成法を用いて形成した膜と本発
明の1実施態様を用いて形成した膜の(空気露出時の関
数としての)シート抵抗を示すグラフである。
FIG. 2 is a graph showing sheet resistance (as a function of air exposure) of a film formed using a prior art film forming method and a film formed using one embodiment of the present invention.

【図3】a及びbはそれぞれ、X線光電子分光法(XP
S)深さ方向断面解析から得たデータを示すグラフであ
り、aは先行技術の方法を用いて形成した膜内の炭素、
酸素、窒素、チタン、珪素の原子濃度を示し、bは本発
明の方法を用いて形成した膜内の炭素、酸素、窒素、チ
タン、珪素の原子濃度を示す。
FIGS. 3a and 3b are X-ray photoelectron spectroscopy (XP
S) is a graph showing data obtained from a cross-sectional analysis in a depth direction, where a is carbon in a film formed using a method of the related art,
B represents the atomic concentration of oxygen, nitrogen, titanium, and silicon, and b represents the atomic concentration of carbon, oxygen, nitrogen, titanium, and silicon in the film formed using the method of the present invention.

【図4】本発明の方法を用いて形成した膜の透過形電子
回折図である。
FIG. 4 is a transmission electron diffraction diagram of a film formed using the method of the present invention.

【図5】本発明の第2の実施態様を示す流れ図である。FIG. 5 is a flowchart showing a second embodiment of the present invention.

【図6】本発明の革新的方法で付着させた障壁膜層上で
のメタライゼイションの例を示す。
FIG. 6 shows an example of metallization on a barrier film layer deposited by the innovative method of the present invention.

【図7】本発明の革新的方法で付着させた障壁膜層上で
のメタライゼイションの例を示す。
FIG. 7 shows an example of metallization on a barrier film layer deposited by the innovative method of the present invention.

【図8】付着済みTi−Si−Nのシート抵抗と付着後
のシラン焼鈍時間との関係を示すグラフである。
FIG. 8 is a graph showing the relationship between the sheet resistance of deposited Ti—Si—N and the silane annealing time after deposition.

【図9】付着済みTi−Si−Nのシート抵抗と、Ti
−Si−Nの付着中のシラン流量との関係を示すグラフ
である。
FIG. 9 shows the sheet resistance of deposited Ti—Si—N and Ti
4 is a graph showing a relationship with the flow rate of silane during the deposition of -Si-N.

【図10】本発明の革新的な層の断面構造を示す顕微鏡
写真(本発明の方法が層の絶縁保護性を保持しているこ
とを示す)である。
FIG. 10 is a photomicrograph showing the cross-sectional structure of the innovative layer of the present invention (showing that the method of the present invention retains the insulating properties of the layer).

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 (a)半導体材料の少なくとも1つの実
質的にモノリシックな物体を含む基板を準備する工程
と、(b)チタンと窒素を含む雰囲気中でCVDで絶縁
保護性層を付着させる工程と、(c)上記絶縁保護性層
を付着させた後で、上記絶縁保護性層を珪素又は硼素を
含有する雰囲気に露出させる工程とを含む薄膜形成法で
あって、前記工程(c)により上記絶縁保護性層上に珪
素又は硼素濃度の高い表面を形成させる薄膜形成法。
1. A method comprising: (a) providing a substrate comprising at least one substantially monolithic object of a semiconductor material; and (b) depositing a conformal layer by CVD in an atmosphere comprising titanium and nitrogen. And (c) exposing the insulating protective layer to an atmosphere containing silicon or boron after depositing the insulating protective layer, the method comprising: A thin film forming method for forming a surface having a high silicon or boron concentration on the insulating protective layer.
【請求項2】 チタンと窒素とを含有する障壁薄膜層か
ら成る集積回路であって、上記薄膜は珪素又は硼素の組
成が漸進的に変化し、その第1の表面では珪素又は硼素
濃度が他に較べて高い集積回路。
2. An integrated circuit comprising a barrier thin film layer containing titanium and nitrogen, wherein the thin film has a composition of silicon or boron that changes gradually, and the first surface has a silicon or boron concentration other than that of silicon or boron. Higher integrated circuit than.
JP30117997A 1996-10-31 1997-10-31 Method for producing an insulating protective barrier film based on Ti-Si-N and Ti-BN with low defect density Expired - Fee Related JP4065351B2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US2879896P 1996-10-31 1996-10-31
US784657 1997-01-21
US08/784,657 US6017818A (en) 1996-01-22 1997-01-21 Process for fabricating conformal Ti-Si-N and Ti-B-N based barrier films with low defect density
US028798 1997-01-21

Publications (2)

Publication Number Publication Date
JPH10189491A true JPH10189491A (en) 1998-07-21
JP4065351B2 JP4065351B2 (en) 2008-03-26

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JP (1) JP4065351B2 (en)
KR (1) KR19980032971A (en)
TW (1) TW363213B (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6475912B1 (en) 1998-06-01 2002-11-05 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method and apparatus for fabricating the same while minimizing operating failures and optimizing yield
JP2003045960A (en) * 2001-08-01 2003-02-14 Matsushita Electric Ind Co Ltd Semiconductor device and method of manufacturing same
WO2007094044A1 (en) * 2006-02-14 2007-08-23 Fujitsu Limited Semiconductor device manufacturing method and semiconductor manufacturing apparatus
JP2008041977A (en) * 2006-08-08 2008-02-21 Nec Electronics Corp Manufacturing method of semiconductor circuit device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6475912B1 (en) 1998-06-01 2002-11-05 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method and apparatus for fabricating the same while minimizing operating failures and optimizing yield
US6683381B2 (en) 1998-06-01 2004-01-27 Matsushita Electric Industrsial Co., Ltd. Semiconductor device having a copper interconnect layer
US6906420B2 (en) 1998-06-01 2005-06-14 Matsushita Electric Industrial Co., Ltd. Semiconductor device
JP2003045960A (en) * 2001-08-01 2003-02-14 Matsushita Electric Ind Co Ltd Semiconductor device and method of manufacturing same
WO2007094044A1 (en) * 2006-02-14 2007-08-23 Fujitsu Limited Semiconductor device manufacturing method and semiconductor manufacturing apparatus
JP2008041977A (en) * 2006-08-08 2008-02-21 Nec Electronics Corp Manufacturing method of semiconductor circuit device

Also Published As

Publication number Publication date
TW363213B (en) 1999-07-01
JP4065351B2 (en) 2008-03-26
KR19980032971A (en) 1998-07-25

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