WO2007084749A2 - Method and system for error correction in flash memory - Google Patents

Method and system for error correction in flash memory Download PDF

Info

Publication number
WO2007084749A2
WO2007084749A2 PCT/US2007/001620 US2007001620W WO2007084749A2 WO 2007084749 A2 WO2007084749 A2 WO 2007084749A2 US 2007001620 W US2007001620 W US 2007001620W WO 2007084749 A2 WO2007084749 A2 WO 2007084749A2
Authority
WO
WIPO (PCT)
Prior art keywords
data
solid state
volatile memory
state non
series
Prior art date
Application number
PCT/US2007/001620
Other languages
French (fr)
Other versions
WO2007084749A3 (en
Inventor
Aditya Ramamoorthy
Zining Wu
Pantas Sutardja
Original Assignee
Marvell World Trade Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Marvell World Trade Ltd. filed Critical Marvell World Trade Ltd.
Priority to CN2007800099871A priority Critical patent/CN101405810B/en
Priority to JP2008551451A priority patent/JP5232013B2/en
Priority to EP07718293.9A priority patent/EP1987519B1/en
Priority to KR1020087020392A priority patent/KR101410434B1/en
Publication of WO2007084749A2 publication Critical patent/WO2007084749A2/en
Publication of WO2007084749A3 publication Critical patent/WO2007084749A3/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1072—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in multilevel memories
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1666—Error detection or correction of the data by redundancy in hardware where the redundant component is memory or memory area
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C27/00—Electric analogue stores, e.g. for storing instantaneous values
    • G11C27/005—Electric analogue stores, e.g. for storing instantaneous values with non-volatile charge storage, e.g. on floating gate or MNOS
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/02—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/16—Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters 
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/1177—Regular LDPC codes with parity-check matrices wherein all rows and columns have the same row weight and column weight, respectively
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • H03M13/1515—Reed-Solomon codes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/40—Specific encoding of data in memory or cache
    • G06F2212/403—Error protection encoding, e.g. using parity or ECC codes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C2029/0411—Online error correction
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/16—Solid state audio
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/562—Multilevel memory programming aspects
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/563—Multilevel memory reading aspects
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation

Definitions

  • the present invention relates generally to integrated circuits. More particularly, the invention relates to a method and system for performing error correction in multi-level solid state non- volatile memories.
  • Flash memories are used in a variety of electronics applications. Flash memories are used in a number of memory card formats, such as CompactFlash (CF), MultiMediaCard (MMC) and Secure Digital (SD). Electronic systems in which such cards are used include personal and notebook computers, hand-held computing devices, cameras, MP3 audio players, and the like. Flash EEPROM memories are also utilized as bulk mass storage in many host systems.
  • CF CompactFlash
  • MMC MultiMediaCard
  • SD Secure Digital
  • a 512 byte data sector may have 16 bytes of ECC data appended, resulting in a 528 byte page.
  • the redundant data included in the 16 bytes of ECC data is utilized to detect and correct errors in the data read out from the flash memory.
  • the maximum storage density is determined by the size of the individual storage elements and the number of storage elements that can be integrated onto a single integrated circuit chip.
  • increases in memory density have been provided by shrinking the linewidth of the process geometry used to fabricate the memory cells.
  • multi-level memory cell storing more than one bit per memory cell, also referred to as a multi-level memory cell.
  • a sense amplifier that senses the amount of charge stored in a capacitive storage cell.
  • the memory density can be increased.
  • a cell may be programmed to produce four distinct threshold levels, which results in four distinct read-back levels.
  • FIG. 1 is a simplified probability distribution function (PDF) as a function of voltage for a solid state non- volatile memory cell having a 4-level quantization.
  • PDF probability distribution function
  • read disturbs occur when the distribution of one signal level overlaps the distribution of an adjacent signal level. Because the signal distance is reduced, the increase in the number of discrete values stored in the cell reduces the noise margin of the cell as compared to a binary storage cell, making the storage element more prone to erroneous readout. Read disturbs are more common for low-level signals, which are characterized by larger noise distributions as shown in FIG. 1. [0010] The reduction in voltage separation between adjacent levels in a multi-level solid state non-volatile memory may lead to an increase in the number of errors in comparison with conventional solid state non-volatile memory cells. Thus, it would be desirable to provide improved methods and techniques for operating solid state non-volatile memory with multilevel cells.
  • a solid state non-volatile memory unit includes a multi-level solid state non- volatile memory array adapted to store data characterized by a first number of digital levels.
  • the memory unit also includes an analog-to-digital converter.
  • the analog-to-digital converter is adapted to receive data from the multi-level solid state non- volatile memory array.
  • the analog-to-digital converter is also adapted to output a digital signal characterized by a second number of digital levels greater than the first number of digital levels.
  • a method of operating a solid state non- volatile memory unit includes encoding a first data and storing the encoded first data in a multi-level solid state non- volatile memory array.
  • the stored encoded first data is characterized by a first number of digital levels.
  • the method also includes retrieving the first encoded data from the memory array and digitizing the retrieved data to a number of digital levels greater than the number of digital levels associated with the multi-level solid state non-volatile memory array.
  • a controller for a multi-level solid state non- volatile memory array characterized by a first number of digital levels includes a first encoder adapted to receive a series of data bits and provide a series of encoded data bits.
  • the controller also includes a mapper adapted to convert the series of encoded data bits into a series of data symbols for storage in the multi-level solid state non-volatile memory array.
  • the controller further includes a first decoder adapted to receive a series of voltage signals from the multi-level solid state nonvolatile memory array and generate a series of output data symbols characterized by a second number of digital levels greater than the first number of digital levels.
  • a method of operating a controller for a multi-level solid state non-volatile memory array characterized by a first number of digital levels includes encoding a first series of data bits to provide a series of encoded data bits and converting the series of encoded data bits into a series of data symbols.
  • the method also includes storing the series of data symbols in the multi-level solid state non- volatile memory array and retrieving the series of data symbols.
  • the method further includes decoding the series of data symbols to provide a series of output data symbols characterized by a second number of digital levels greater than the first number of digital levels.
  • a solid state nonvolatile memory unit includes means for encoding a first data and means for storing the encoded first data in a multi-level solid state non-volatile memory array.
  • the stored encoded first data is characterized by a first number of digital levels.
  • the memory unit also includes means for retrieving the first encoded data from the memory array and means for digitizing the retrieved data to a number of digital levels greater than the number of digital levels associated with the multi-level solid state non-volatile memory array.
  • a controller for a multi-level solid state non- volatile memory array characterized by a first number of digital levels includes means for encoding a first series of data bits to provide a series of encoded data bits and means for converting the series of encoded data bits into a series of data symbols.
  • the controller also includes means for storing the series of data symbols in the multi-level solid state non- volatile memory array and means for retrieving the series of data symbols.
  • the controller further includes means for decoding the series of data symbols to provide a series of output data symbols characterized by a second number of digital levels greater than the first number of digital levels.
  • Still other embodiments of the present invention may be implemented in code, for example, by a digital signal processor (DSP).
  • DSP digital signal processor
  • One such embodiment includes code for encoding a first data and means for storing the encoded first data in a multi-level solid state non- volatile memory array.
  • the stored encoded first data is characterized by a first number of digital levels.
  • the embodiment also includes code for retrieving the first encoded data from the memory array and code for digitizing the retrieved data to a number of digital levels greater than the number of digital levels associated with the multi-level solid state nonvolatile memory array.
  • code for controlling a multi-level solid state non- volatile memory array characterized by a first number of digital levels includes code for encoding a first series of data bits to provide a series of encoded data bits and code for converting the series of encoded data bits into a series of data symbols.
  • the embodiment also includes code for storing the series of data symbols in the multi-level solid state non- volatile memory array and code for retrieving the series of data symbols.
  • the embodiment further includes code for decoding the series of data symbols to provide a series of output data symbols characterized by a second number of digital levels greater than the first number of digital levels.
  • FIG. 1 is a simplified probability distribution function as a function of voltage for a solid state non- volatile memory cell having a 4-level quantization
  • FIG. 2A is a constellation diagram for an uncoded one bit PAM scheme
  • FIG. 2B is a constellation diagram for a two-bit data modulated using a PAM scheme having an average power of 1;
  • FIG. 2C is a constellation diagram for a two-bit data modulated using a PAM scheme having a peak limit of ⁇ 1 for use in a solid state non-volatile memory cell;
  • FIG. 3 A is a simplified block diagram of an exemplary solid state non- volatile memory unit with error correction code according to an embodiment of the present invention
  • FIG. 3B is a simplified block diagram of a solid state non- volatile memory unit incorporating an analog-to-digital converter according to an embodiment of the present invention
  • FIG. 4 is a simplified block diagram of a solid state non- volatile memory unit with error correction according to another embodiment of the present invention.
  • FIG. 5 shows a word error rate (WER) of a memory unit, in accordance with one exemplary embodiment of the present invention, as compared to a conventional uncoded system;
  • WER word error rate
  • FIG. 6 shows various blocks of an exemplary rate 1/2 convolutional encoder according to an embodiment of the present invention
  • FIG. 7 shows an example of 2-D set partitioning according to an embodiment of the present invention
  • FIG. 8 is a simplified block diagram of a conventional TCM encoder
  • FIG. 9 illustrates an example of combining set-partitioning with iterative code according to an embodiment of the present invention
  • FIG. 1OA is a simplified illustration of a two-level system that includes an inner code and an outer code according to an embodiment of the present invention
  • FIG. 1OB is a simplified block diagram of a two-level encoding channel according to another exemplary embodiment of the present invention.
  • FIGS. 11 A-11 C show a number of exemplary sector and codeword sizes, in accordance with the present invention
  • FIG. 12 illustrates an exemplary 3 -way interleaved cell according to an embodiment of the present invention
  • FIG. 13 A is a simplified schematic diagram of an interleaving technique provided according to an exemplary embodiment of the present invention.
  • FIG. 13B is a plot of SER as a function of SNR for an interleaved system as illustrated in FIG. 13 A;
  • FIGS. 14A-14H show various devices in which the present invention may be embodied.
  • FIG. 2A is a constellation diagram for an uncoded one bit PAM (pulse amplitude modulation) scheme according to which, information is stored as either a 0 (-1 volts) or a 1 (+1 volts).
  • FIG. 2B is a constellation diagram for a two-bit data modulated using a PAM scheme having an average power of 1.
  • the four states defined by the two bits, namely states (00, 01, 10, and 11) are mapped to one of four possible levels, for example, -3/ ⁇ 5 volts, -lW5 volts, +1/V5 volts, and +3/V5 volts.
  • both the 2-points PAM (2-PAM) and the 4-points PAM (4-PAM) with 1/2 code rate provide a 1 bit/cell spectral efficiency and are characterized by equal power.
  • the 4- state code with Gray mapping reduces bit error rate over the 4-state natural mapping.
  • the maximum voltage applied at the floating gate limits the maximum voltage available for mapping of multi-level symbols. This voltage limitation results in a peak constraint on the constellation values of the applied modulation and encoding scheme. Thus, for a solid state non-volatile memory device, the constellation points must account for this limitation.
  • the maximum voltage constraint characteristic of solid state non- volatile memory systems constrasts with other channels in which additional power increases are available. Accordingly, embodiments of the present invention utilize modulation and encoding schemes for multi-level non- volatile solid state memories designed to be operable in spite of such constraints. [0041] FIG.
  • 2C is a constellation diagram for a two-bit data modulated using a PAM scheme having a peak value limited to ⁇ 1 for use in a solid state non-volatile memory cell.
  • Symbol 00 is mapped to a signal amplitude of -1 volts and symbol 10 is mapped to a signal amplitude of +1 volts, which in this example, correspond to the maximum voltages stored by a given solid state non- volatile memory cell.
  • the signal to noise ratio decreases.
  • the slope of the SNR decrease is not the same for these two systems.
  • the SNR is related to the minimum distance between the nearest neighbors in the constellation map. Consequently, voltage constraints in solid state non-volatile memory devices reduce the available minimum distance and the SNR. Therefore, for a given number of levels, memory systems generally have a lower SNR compared to other known systems.
  • the encoding and modulation techniques in accordance with various embodiments of the present invention, are adapted to the environment characteristic of solid state non- volatile memories.
  • the asymptotic coding gain is defined by:
  • the minimum distance d/ ree is generally increased in comparison to the uncoded system, resulting in an asymptotic coding gain greater than one.
  • the number of nearest neighbors also increases so the real coding gain is somewhat reduced.
  • FIG. 3 A is a simplified block diagram of an exemplary solid state non-volatile memory unit 300 with an ECC according to an embodiment of the present invention.
  • User data to be written into the multi-level memory cells of multi-level solid state non-volatile memory 314 are ECC encoded by encoder 310 to add redundant symbols.
  • the encoded data is passed to modulator 312 for channel encoding.
  • modulator 312 any one of a number of encoding and modulation techniques may be used.
  • Multi -level solid state non- volatile memory 314 receives encoded and modulated data from modulator 312.
  • Multi-level solid state non- volatile memory 314 may be a flash EEPROM, or the like.
  • a multi-level flash memory includes one or more flash memory cell arrays and read and write (program) circuitry.
  • Floating gate memory cells such as flash memories are discussed herein merely by way of example. Embodiments of the present invention as described throughout the present specification also apply to other memory technologies other than floating gate technology with the appropriate modifications.
  • One of ordinary skill in the art would recognize many variations, modifications, and alternatives.
  • Data is read from multi-level solid state non- volatile memory 314 and passes to demodulator 316 and decoder 318.
  • the demodulator in embodiments of the present invention includes signal processing logic adapted to extract soft information related to the data stored in the multi -level solid state non- volatile memory 314.
  • a threshold detector is utilized to determine if a voltage value associated with a particular cell is less than or greater than a given threshold value. This threshold-based approach is also utilized in multi-level memory systems, where the threshold detection circuit merely utilizes a greater number of threshold values.
  • multi- level memory systems include circuitry that tracks process or other variations and adjusts the threshold values accordingly, these systems output a value from a number of possible values that is equal to the number of levels in the multi-level system.
  • the sense amplifier will produce a data signal representing one of the four levels.
  • embodiments of the present invention utilize a demodulator that produces an output having a number of possible values greater than the number of levels provided by the multi-level solid state non- volatile memory 314.
  • This information is sometimes referred to as soft information since the output includes information in addition to the value stored in the multi-level memory.
  • an analog-to-digital (A/D) converter or detector provided as part of or working in conjunction with demodulator 316 provides an output signal with, for example, 32 possible values in response to the values detected by a sense amplifier disposed in communication with, for example, a four-level memory.
  • Embodiments of the present invention are not limited to using an output signal with 32 levels, as other output signals, with, for example, 8, 16, or more levels are included within the scope of the present invention.
  • the soft information is passed to a soft information decoder (not shown) for processing.
  • the soft information provided by the demodulator 316 is utilized during signal processing operations to improve the reliability with which data from the solid state non- volatile memory 314 is read.
  • encoder 310, modulator 312, demodulator 316, and decoder 318 are components of a controller in communication with multi-level solid state non- volatile memory 314.
  • Memory devices typically include one or more memory chips that are mounted on a card. Each of the memory chips may include an array of memory cells as well as integrated circuits performing such operations as program, read, and erase. According to embodiments of the present invention, a controller circuit performing these operations may or may not be disposed in the integrated circuits (IC) in which the memory chip (s) are also disposed. Controllers provided herein are not limited to performing encoding/decoding and modulation/demodulation processes, but may also provide for other functionality such as wear leveling and interfacing processes.
  • Embodiments of the present invention enable system designers to increase the memory density of existing solid state non-volatile memories. As described more fully throughout the present specification, in comparison with conventional systems, increased levels of read and write errors are corrected utilizing the techniques and methods provided herein. Thus, although attempting to utilize, for example, a four-level- memory system for, for example, eight-level applications by introducing additional levels may produce a greater number of errors during read operations than is otherwise acceptable under a given performance measure, techniques described herein may be utilized to correct such errors during the demodulation process and enable the use, for instance, of a four-level memory system in an eight-level application.
  • FIG. 3B is a simplified block diagram of a solid state non-volatile memory unit 350 incorporating an A/D converter according to an embodiment of the present invention.
  • an encoder 360 and a modulator 362 provide encoded and modulated data to the multi-level non-volatile solid state memory 364.
  • A/D converter 366 receives signals from the multi-level non-volatile solid state memory 364.
  • the digital signal output by the A/D converter 366 is of higher resolution (characterized by more levels) than the number of levels associated with the multi-level non- volatile solid state memory 364.
  • the multi-level non- volatile solid state memory 364 is, for example, a four-level memory, providing storage for 2 bits in each cell.
  • the A/D converter 366 converts an analog signal associated with one or more cells of the memory 364 into one of, for example, 8, 16, 32, or 64 levels depending on the particular application. Other numbers of levels greater than four levels are used in other embodiments.
  • Signal processing algorithms resident in demodulator 368 utilize the output of the A/D converter 366 to determine the likelihood that the cell contains data associated with one of the four levels stored in the cell.
  • One of ordinary skill in the art would recognize many variations, modifications, and alternatives.
  • ECC techniques are utilized to detect and correct errors in data as the data is read out from the memory. Such ECC techniques simply operate on binary or multi-level digital data produced by a sense amplifier.
  • soft information produced and utilized by the demodulator 316 does not merely include the binary or multi -level digital data, but additional information as well. Soft information is typically represented by distributions that are useful in performing signal processing techniques not generally applicable once the data has been reduced to threshold-based digital values equal in number to the number of levels in the multi-level system.
  • Table 1 illustrates an exemplary coding gain from convolutional coded 2 bit/cell multi-level non-volatile memory over an uncoded 1 bit/cell non-volatile memory as a function of the number of states of the code. As shown in the first row entry, for a 4-state system (illustrated by FIGS. 2A-2C), the coding gain in comparison to an uncoded system is 0 dB. However, as the number of states is increased, the coding gain in comparison to an uncoded system is positive.
  • Table 2 illustrates the coding gain for convolutional coded 3 bit/cell multi-level non- volatile memory over uncoded 2 bit/cell multi-level non-volatile memory as a function of the number of states of the code. As shown for 1 bit/cell multi-level non- volatile memory with four or more states, the coding gain in comparison to an uncoded system is positive for systems with four or more states.
  • FIG. 4 is a simplified block diagram of a solid state non-volatile memory unit with error correction according to another embodiment of the present invention.
  • an outer encoder 410 provides encoded data to an inner encoder 412.
  • outer encoder 410 may be a Reed-Solomon encoder and inner encoder may be an LDPC encoder.
  • Modulator 414 receives encoded data from inner encoder 412 and modulates the data prior to storage in multi-level solid state nonvolatile memory 416 during a program operation. During a read operation, the data stored in the multi-level solid state non-volatile memory 416 is retrieved and provided to demodulator 418, inner decoder 420, and outer decoder 422.
  • ECCs Error Correcting Codes
  • FEC Forward Error Correction
  • block codes may be used to encode a block of data for channels with additive burst noise (random multi-bit errors). It is understood that the present invention is applicable to both systematic encoders that do not manipulate the user data prior to encoding and storage, as well as to non-systematic encoders.
  • Any one of a number of different linear block codes including, for example, binary codes such as Hamming code, BCH code, Reed-Muller code and Array Code, and non-binary codes such as Reed-Solomon (RS) code may be used.
  • the word error rate (WER) of such a coded system is compared to a 4-level uncoded system in FIG. 5. It can be seen at WER ⁇ 10 "8 , the RS coded system outperforms the uncoded system. Therefore, with the above RS code, better reliability and higher capacity is achieved.
  • convolutional codes are used to encode the data.
  • Convolutional codes introduce correlation into coded data and thus increase the minimum distance at the decoder.
  • Convolutional codes are applied to serially- transmitted data stored in or read from solid state non- volatile memories, which are subject to Gaussian noise.
  • Convolutional codes are progressive codes. At any point in time, the output of a convolutional encoder may depend upon both the past and present input values.
  • convolutional codes are generally directed to correcting errors that span an ordered progression of data values. Accordingly, such codes maybe used in multi-level solid state non-volatile memories that store and read out data in the form of an ordered, progressive stream (i.e., a data stream).
  • the decoder receives either hard decision inputs or multi-level quantized inputs. Soft inputs are known to cause fewer errors at the detector.
  • Trellis coded modulation combines convolutional code with set partitioning to achieve high code rate, high coding gain, and low decoding complexity.
  • a set of constellation points can be partitioned to a smaller subset, where points in each subset are separated further than in the original constellation.
  • FIG. 7 shows an example of 2-D set partitioning where dots, " o ", represent one subset, and crosses, "x", represent the other. If the minimum distance between the original constellation points is d, then the minimum distance between points in each subset is V2d .
  • the parameter governing the performance of the system is not the free Hamming distance of the convolutional code, but rather the free Euclidean distance between the transmitted signal sequences. Accordingly, the optimization of the TCM design is based on the Euclidean distances rather than, the Hamming distances.
  • AWGN additive white Gaussian Noise
  • TCM An example of TCM is shown in FIG. 8. Input bits are separated into two groups ⁇ a first group with k] bits, going through a rate ki/(k ⁇ +l) encoder 802 to select subsets; a second group with k-ki bits, which select constellation points, using constellation mapper 804, within each subset.
  • a first group with k] bits going through a rate ki/(k ⁇ +l) encoder 802 to select subsets
  • k-ki bits which select constellation points, using constellation mapper 804, within each subset.
  • Some codes based on random construction may be effectively decoded by iterative detection methods. These codes include Turbo codes, i.e., serially concatenated convolutional codes, or parallel concatenated convolutional codes, low-density parity-check (LDPC) codes, Turbo Product code, and their variations.
  • Turbo codes i.e., serially concatenated convolutional codes, or parallel concatenated convolutional codes, low-density parity-check (LDPC) codes, Turbo Product code, and their variations.
  • Coding gain of TCM comes from two areas — set partitioning to increase the distance between constellation points within each subset, and convolutional code to achieve high Euclidean distance between different subsets, the latter of which can also be achieved if other high gain codes are substituted for convolutional code.
  • An example of combining set- partitioning with iterative code is shown in FIG. 9.
  • LDPC encoder 902 Assume a 16-PAM system is partitioned into 4 subsets. Then the minimum distance between points in each subset is 4do, hence providing a 12dB gain compared to uncoded system. However, between different subsets, the minimum distance remains at do. Since the selection of subset depends on LDPC coded bits supplied by LDPC encoder 902, then the overall system has an approximate gain of 12dB if an LDPC code having a gain of 12dB is used. In general, the overall system gain is the minimum of the set-partitioning gain and the iterative coding gain. LDPC encoder 902 shown in FIG. 9 is required to operate on a whole codeword defined by the iterative code block size. In addition to iterative codes, other high gain codes including RS code and BCH code may be used to code a portion of the input for subset selection.
  • RS code and BCH code may be used to code a portion of the input for subset selection.
  • multi-level coding may be used.
  • a two-level encoding that includes an inner encoder and an outer encoder is shown in FIG. 10.
  • outer code encoder 1002 may be a RS encoder
  • inner code encoder 1004 may be a TCM encoder. Bursty errors caused by TCM decoder 1006 are corrected by RS decoder 1008.
  • inner encoder 1004 is adapted to perform iterative codes, such as LDPC codes or Turbo codes
  • outer encoder 1002 is adapted to perform RS code.
  • Iterative codes may be binary codes or symbol-based codes. Each symbol may contain multiple bits. Iterative codes may be decoded using a ⁇ soft-input soft-output (SISO) decoder, while RS codes may be decoded using either a SISO or a hard-decision decoder.
  • the outer RS decoder 1008 may iterate with inner decoder 1006 to exchange soft information. Such iteration would improve the quality of soft information and thereby decrease the number of bit errors after each iteration.
  • the PDF of the programmed cells is different depending on the cell's threshold voltage. If the four levels are spaced equally, then the level corresponding to cells with a PDF defined by a threshold voltage ranging between 2 and 4 volts is more prone to errors than other levels due to its wider distribution. Accordingly, in some embodiments, constrained coding is used to inhibit certain patterns or reduce their frequency. For example, lowering the frequency of data corresponding to cells with a PDF defined by a threshold voltage ranging between 2 and 4 volts lowers the overall error probability.
  • the codeword size is aligned with the sector size.
  • the sector size is, for example, 256 kbits
  • the inner code and outer code may be configured such that one outer codeword is 256 kbits.
  • Smaller or larger codeword sizes relative to the sector size may also be used.
  • FIG. 1 IA the sector size is shown as being equal to the codeword size.
  • each sector includes several codewords, as shown in FIG. 1 IB.
  • each codeword includes several sectors, as shown in FIG. 11C.
  • the larger the codeword size the larger the coding gain, the longer decoding delay, and the higher is the decoder complexity.
  • Codewords may be interleaved before being stored.
  • FIG. 12 shows an exemplary 3- way interleaved cell in which cells 1202 form codeword 1, cells 1204 form codeword 2, and cells 1206 form codeword 3. If a defect spans no more than three cells, it causes only one symbol error in each codeword, which is easier to correct than a burst of three symbol errors.
  • FIG. 13 A is a simplified schematic diagram of an interleaving technique provided according to an exemplary embodiment of the present invention. As illustrated in FIG.
  • an inner encoder for example, a TCM encoder
  • an outer encoder for example, an RS encoder
  • block columns of data This exemplary embodiment may be used, for example, in solid state non-volatile memories, in which the data is written to the memory cells in a rectangular format, i.e., blocks.
  • embodiments of the present invention provide that several independent outer RS codes process data corrupted by the multi-bit error. Accordingly, the number of errors impacting an individual RS code is limited.
  • the number of columns in a particular implementation is determined, in part, by the maximum error burst length.
  • the number of rows is determined, in part, by the number of sectors per block codeword.
  • the number of columns is predetermined depending on the particular application. For example, if the number of columns (related to the interleaving depth) is larger than the maximum error burst length, then the outer encoder operating on the columns is similar to a memoryless channel characterized by a particular symbol error rate. Accordingly, error bursts that occur affect different outer encoder codes.
  • the symbol error rate is typically determined by using TCM simulations independently, and the error probability may be estimated by independent modeling.
  • the percentage of overhead of the outer encoder for example, an RS encoder, may be reduced by increasing the row dimension of the block codeword. Alternatively, one can increase the row dimension of the RS code while keeping the overhead percentage constant, thereby allowing for a higher correction power per column.
  • FIG. 13B is a plot of SER as a function of SNR for an interleaved system as illustrated in FIG. 13 A.
  • 10 columns and 10 sectors per block codeword were utilized.
  • Other embodiments will utilize a varying number of columns and sectors per block codeword depending on the particular application.
  • the SER for an uncoded 2 bits/cell 4-PAM system is illustrated for purposes of comparison.
  • a multi-level solid state non-volatile memory includes, for example, 2.5 bits/cell. In such embodiments, two adjacent 8-level cells
  • the code rate is 5/6 and the number of branches per state is equal to four.
  • the coding gain in comparison with an uncoded 4-PAM system may be, for example, 0.423 dB for 16 states. It should be noted that calculation results will be modified as multiplicities are included in such calculations. For example, losses of approximately 0.2 dB are expected with the doubling of multiplicities.
  • multiplicities are included in such calculations. For example, losses of approximately 0.2 dB are expected with the doubling of multiplicities.
  • multi-level solid state non- volatile memory systems with, for example, 3.5 bits/cell are provided.
  • two adjacent 16-level cells (4 bits/cell) form a 256-QAM modulation symbol.
  • seven bits are utilized for data and one bit is used for encoding.
  • the code rate is 7/8 and the number of branches per state is equal to four.
  • Such a system provides 3.5 bits/cell as 7 data bits are stored between two adjacent cells.
  • the coding gain in comparison with an uncoded 8-PAM system may be, for example, 0.527 dB for 8 states and 1.317 dB for 16 states.
  • FIGS. 14 A- 14G various exemplary implementations of the present invention are shown.
  • the present invention may be embodied in a hard disk drive 1400.
  • the present invention may implement either or both signal ' processing and/or control circuits, which are generally identified in FIG. 14A at 1402.
  • signal processing and/or control circuit 1402 and/or other circuits (not shown) in HDD 1400 may process data, perform coding and/or encryption, perform calculations, and/or format data that is output to and/or received from a magnetic storage medium 1406.
  • HDD 1400 may communicate with a host device (not shown) such as a computer, mobile computing devices such as personal digital assistants, cellular phohes, media or MP3 players and the like, and/or other devices via one or more wired or wireless communication links 1408.
  • a host device such as a computer, mobile computing devices such as personal digital assistants, cellular phohes, media or MP3 players and the like, and/or other devices via one or more wired or wireless communication links 1408.
  • HDD 1400 maybe connected to memory 1409, such as random access memory (RAM), a low latency nonvolatile memory such as flash memory, read only memory (ROM) and/or other suitable electronic data storage.
  • RAM random access memory
  • ROM read only memory
  • the present invention may be embodied in a digital versatile disc (DVD) drive 1410.
  • the present invention may implement either or both signal processing and/or control circuits, which are generally identified in FIG. 14B at 1412, and/or mass data storage 1418 of DVD drive 1410.
  • Signal processing and/or control circuit 1412 and/or other circuits (not shown) in DVD drive 1410 may process data, perform coding and/or encryption, perform calculations, and/or format data that is read from and/or data written to an optical storage medium 1416.
  • signal processing and/or control circuit 1412 and/or other circuits (not shown) in DVD drive 1410 can also perform other functions such as encoding and/or decoding and/or any other signal processing functions associated with a DVD drive.
  • DVD drive 1410 may communicate with an output device (not shown) such as a computer, television or other device via one or more wired or wireless communication links 1417.
  • DVD drive 1410 may communicate with mass data storage 1418 that stores data in a nonvolatile manner.
  • Mass data storage 1418 may include a hard disk drive (HDD) such as that shown in FIG. 14A.
  • the HDD may be a mini HDD that includes one or more platters having a diameter that is smaller than approximately 1.8".
  • DVD drive 1410 may be connected to memory 1419, such as RAM, ROM, low latency nonvolatile memory such as flash memory, and/or other suitable electronic data storage.
  • the present invention may be embodied in a high definition television (HDTV) 1420.
  • the present invention may implement either or both signal processing and/or control circuits, which are generally identified in FIG. 14C at 1422, a WLAN interface and/or mass data storage of the HDTV 1420.
  • HDTV 1420 receives HDTV input signals in either a wired or wireless format and generates HDTV output signals for a display 1426.
  • signal processing circuit and/or control circuit 1422 and/or other circuits (not shown) of HDTV 1420 may process data, perform coding and/or encryption, perform calculations, format data and/or perform any other type of HDTV processing that may be required.
  • HDTV 1420 may communicate with mass data storage 1427 that stores data in a nonvolatile manner such as optical and/or magnetic storage devices. At least one HDD may have the configuration shown in FIG. 14A and/or at least one DVD drive may have the configuration shown in FIG. 14B. The HDD may be a mini HDD that includes one or more platters having a diameter that is smaller than approximately 1.8". HDTV 1420 may be connected to memory 1428 such as RAM, ROM, low latency nonvolatile memory such as flash memory and/or other suitable electronic data storage. HDTV 1420 also may support connections with a WLAN via a WLAN network interface 1429. [0084] Referring now to FIG.
  • the present invention may be embodied in a control system, a WLAN interface and/or mass data storage of a vehicle 1030.
  • the present invention implements apowertrain control system 1432 that receives inputs from one or more sensors such as temperature sensors, pressure sensors, rotational sensors, airflow sensors and/or any other suitable sensors and/or that generates one or more output control signals such as engine operating parameters, transmission operating parameters, and/or other control signals.
  • control system 1440 may likewise receive signals from input sensors 1442 and/or output control signals to one or more output devices 1444.
  • control system 1440 may be part of an anti-lock braking system (ABS), a navigation system, a telematics system, a vehicle telematics system, a lane departure system, an adaptive cruise control system, a vehicle entertainment system such as a stereo, DVD, compact disc system and the like. Still other implementations are contemplated.
  • Powertrain control system 1432 may communicate with mass data storage 1446 that stores data in a nonvolatile manner.
  • Mass data storage 1446 may include optical and/or magnetic storage devices for example HDDs and/or DVD drives. At least one HDD may have the configuration shown in FIG. 14A and/or at least one DVD drive may have the configuration shown in FIG. 14B.
  • the HDD may be a mini HDD that includes one or more platters having a diameter that is smaller than approximately 1.8".
  • Powertrain control system 1432 may be connected to memory 1447 such as RAM, ROM, low latency . nonvolatile memory such as flash memory and/or other suitable electronic data storage.
  • Powertrain control system 1432 also may support connections with a WLAN via a WLAN network interface 1448.
  • the control system 1440 may also include mass data storage, memory and/or a WLAN interface (all not shown).
  • the present invention may be embodied in a cellular phone 1450 that may include a cellular antenna 1451.
  • the present invention may implement either or both signal processing and/or control circuits, which are generally identified in FIG. 14E at 1452, a WLAN interface and/or mass data storage of the cellular phone 1450.
  • cellular phone 1450 includes a microphone 1456, an audio output 1458 such as a speaker and/or audio output jack, a display 1460 and/or an input device 1462 such as a keypad, pointing device, voice actuation and/or other input device.
  • Signal processing and/or control circuits 1452 and/or other circuits (not shown) in cellular phone 1450 may process data, perform coding and/or encryption, perform calculations, format data and/or perform other cellular phone functions.
  • Cellular phone 1450 may communicate with mass data storage 1464 that stores data in a nonvolatile manner such as optical and/or magnetic storage devices for example HDDs and/or DVD drives. At least one HDD may have the configuration shown in FIG. 14A and/or at least one DVD drive may have the configuration shown in FIG. 14B. The HDD may be a mini HDD that includes one or more platters having a diameter that is smaller than approximately 1.8".
  • Cellular phone 1450 maybe connected to memory 1466 such as RAM, ROM, low latency nonvolatile memory such as flash memory and/or other suitable electronic data storage.
  • Cellular phone 1450 also may support connections with a WLAN via a WLAN network interface 1468.
  • the present invention may be embodied in a set top box 1480.
  • the present invention may implement either or both signal processing and/or control circuits, which are generally identified in FIG. 14F at 1484, a WLAN interface and/or mass data storage of the set top box 1480.
  • Set top box 1480 receives signals from a source such as a broadband source and outputs standard and/or high definition audio/video signals suitable for a display 1488 such as a television and/or monitor and/or other video and/or audio output devices.
  • Signal processing and/or control circuits 1484 and/or other circuits (not shown) of the set top box 1480 may process data, perform coding and/or encryption, perform calculations, format data and/or perform any other set top box function.
  • Set top box 1480 may communicate with mass data storage 1490 that stores data in a nonvolatile manner.
  • Mass data storage 1490 may include optical and/or magnetic storage devices for example HDDs and/or DVD drives. At least one HDD may have the configuration shown in FIG. 14A and/or at least one DVD drive may have the configuration shown in FIG. 14B.
  • the HDD may be a mini HDD that includes one or more platters having a diameter that is smaller than approximately 1.8".
  • Set top box 1480 may be connected to memory 1494 such as RAM, ROM, low latency nonvolatile memory such as flash memory and/or other suitable electronic data storage.
  • Set top box 1480 also may support connections with a WLAN via a WLAN network interface 1496.
  • the present invention may be embodied in a media player 1472.
  • the present invention may implement either or both signal processing and/or control circuits, which are generally identified in FIG. 14G at 1471, a WLAN interface and/or mass data storage of the media player 1472.
  • media player 1472 includes a display 1476 and/or a user input 1477 such as a keypad, touchpad and the like.
  • media player 1472 may employ a graphical user interface (GUI) that typically employs menus, drop down menus, icons and/or a point-and-click interface via display 1476 and/or user input 1477.
  • GUI graphical user interface
  • Media player 1472 further includes an audio output 1475 such as a speaker and/or audio output jack.
  • Signal processing and/or control circuits 1471 and/or other circuits (not shown) of media player 1472 may process data, perform coding and/or encryption, perform calculations, format data and/or perform any other media player function.
  • Media player 1472 may communicate with mass data storage 1470 that stores data such as compressed audio and/or video content in a nonvolatile manner.
  • the compressed audio files include files that are compliant with MP3 format or other suitable compressed audio and/or video formats.
  • the mass data storage may include optical and/or magnetic storage devices for example HDDs and/or DVD drives. At least one HDD may have the configuration shown in FIG.
  • the HDD may be a mini HDD that includes one or more platters having a diameter that is smaller than approximately 1.8".
  • Media player 1472 may be connected to memory 1473 such as RAM, ROM, low latency nonvolatile memory such as flash memory and/or other suitable electronic data storage. Media player 1472 also may support connections with a WLAN via a WLAN network interface 1474.
  • VoIP phone 1483 may include an antenna 1439.
  • the present invention may implement either or both signal processing and/or control circuits, which are generally identified in FIG. 14H at 1482, a wireless interface and/or mass data storage of the VoIP phone 1483.
  • VoIP phone 1483 includes, in part, a microphone 1487, an audio output 1489 such as a speaker and/or audio output jack, a display monitor 1491, an input device 1492 such as a keypad, pointing device, voice actuation and/or other input devices, and a Wireless Fidelity (Wi-Fi) communication module 1486.
  • Wi-Fi Wireless Fidelity
  • VoIP phone 1483 may process data, perform coding and/or encryption, perform calculations, format data and/or perform other VoIP phone functions.
  • VoIP phone 1483 may communicate with mass data storage 1402 that stores data in a nonvolatile manner such as optical and/or magnetic storage devices, for example hard disk drives HDD and/or DVDs.
  • mass data storage 1402 stores data in a nonvolatile manner such as optical and/or magnetic storage devices, for example hard disk drives HDD and/or DVDs.
  • At least one HDD may have the configuration shown in FIG. 14A and/or at least one DVD may have the configuration shown in FIG. 14B.
  • the HDD may be a mini HDD that includes one or more platters having a diameter that is smaller than approximately 1.8".
  • VoIP phone 1483 may be connected to memory 1485, which may be a RAM, ROM, low latency nonvolatile memory such as flash memory and/or other suitable electronic data storage. VoIP phone 1483 is configured to establish communications link with a VoIP network (not shown) via Wi-Fi communication module 1486. Still other implementations in addition to those described above are contemplated. [0095] The above embodiments of the present invention are illustrative and not limitative. Various alternatives and equivalents are possible. The invention is not limited by the type of comparator, counter, pulse-width modulator, driver, or filter used. The invention is not limited by the type of amplifier used to establish the reference charging and discharging currents. The invention is not limited by the of oscillator.
  • CMOS complementary metal-oxide-semiconductor
  • Bipolar complementary metal-oxide-semiconductor
  • BICMOS complementary metal-oxide-semiconductor

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Algebra (AREA)
  • Pure & Applied Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Read Only Memory (AREA)
  • Error Detection And Correction (AREA)

Abstract

A solid state non-volatile memory unit. The memory unit includes a multi-level solid state non-volatile memory array adapted to store data characterized by a first number of digital levels. The memory unit also includes an analog-to-digital converter having an input and an output. The input of the analog-to-digital converter is adapted to receive data from the multi-level solid state non-volatile memory array. The output of the analog-to-digital converter is adapted to output a digital signal characterized by a second number of digital levels greater than the first number of digital levels.

Description

METHOD AND SYSTEM FOR ERROR CORRECTION IN FLASH
MEMORY
CROSS-REFERENCES TO RELATED APPLICATIONS [0001] The present application claims benefit under 35 U.S.C. § 119(e) of the following U.S. provisional applications, all of which are commonly assigned and incorporated herein by reference in their entirety:
Provisional Application No. 60/760,622, entitled "Flash Memory - Error Correction Issues," filed on January 20, 2006; Provisional Application No. 60/761,888, entitled "Increase Storage Capacity of
Flash Memory through Coding and Signal Processing," filed on January 25, 2006; and
Provisional Application No. 60/771,621, entitled "Increase Storage Capacity of Flash Memory through Coding and Signal Processing," filed on February 8, 2006;
[0002] The present application is also related to concurrently filed U.S. Patent Application No. 11 /598,178, entitled "Flash Memory with Coding and Signal Processing," filed on
November 8, 2006 commonly assigned and incorporated herein by reference in its entirety.
BACKGROUND OF THE INVENTION
[0003] The present invention relates generally to integrated circuits. More particularly, the invention relates to a method and system for performing error correction in multi-level solid state non- volatile memories.
[0004] Solid state non-volatile memories, such as flash EEPROM memories, are used in a variety of electronics applications. Flash memories are used in a number of memory card formats, such as CompactFlash (CF), MultiMediaCard (MMC) and Secure Digital (SD). Electronic systems in which such cards are used include personal and notebook computers, hand-held computing devices, cameras, MP3 audio players, and the like. Flash EEPROM memories are also utilized as bulk mass storage in many host systems.
[0005] Conventional solid state memories store information as a series of binary digits or "bits," which can take on one of two different values (0 or 1). Bits are grouped together to represent larger numbers. [0006] As with most solid state non- volatile memory devices, flash EEPROMs are susceptible to defects and failures. Errors result from several factors including the gradual shirting of the threshold level of the memory states as a result of ambient conditions and stress from normal operations of the memory device including program, erase, and read operations. In order to prevent errors during operation, error correction code (ECC) techniques are utilized in flash memory devices. Typically, a controller generates redundant bits (parity bits) that are appended to the end of data sectors during program operations. For example, a 512 byte data sector may have 16 bytes of ECC data appended, resulting in a 528 byte page. During read operations, the redundant data included in the 16 bytes of ECC data is utilized to detect and correct errors in the data read out from the flash memory.
[00071 F°r a conventional memory, the maximum storage density is determined by the size of the individual storage elements and the number of storage elements that can be integrated onto a single integrated circuit chip. Typically, increases in memory density have been provided by shrinking the linewidth of the process geometry used to fabricate the memory cells.
[0008] Another technique used to increase solid state non-volatile memory density is storing more than one bit per memory cell, also referred to as a multi-level memory cell. Rather than sensing whether or not charge is stored in a given memory cell (i.e., a binary cell), multi-level memories utilize a sense amplifier that senses the amount of charge stored in a capacitive storage cell. By quantizing information into units greater than binary, e.g., 4- level (2 bits/cell), 8-level (3 bits/cell), 16-level (4 bits/cell) units, and the like, and storing these multi-level units, the memory density can be increased. As an example, a cell may be programmed to produce four distinct threshold levels, which results in four distinct read-back levels. With a four level signal available per cell, two data bits can be encoded into each solid state non- volatile memory cell. Multi-level memories enable the manufacturing of higher density memories without increasing the number of memory cells since each memory cell can store more than a single bit. Merely by way of example, for a memory cell capable of storing 2 bits/cell, there may be three programmed states and an erased state. FIG. 1 is a simplified probability distribution function (PDF) as a function of voltage for a solid state non- volatile memory cell having a 4-level quantization. In the memory cell illustrated in FIG. 1 , four programmed states are utilized. As illustrated, in some solid state non- volatile memories, the PDF of programming characteristics has a wider distribution at lower voltage levels. [0009] However, increasing the number of quantization levels in a cell results in a reduction in the voltage difference between adjacent levels. In multi-level encoding systems, this reduction is sometimes referred to as reduced signal distance (reduced Dmjn). Reduced signal distance may impact non-volatile memory performance in both write (program) as well as read operations. During programming, it is more difficult to transfer multiple discrete units of charge to a capacitive cell than it is simply to fully charge or fully discharge the cell. Thus, uncertainty in the amount of charge transferred to a given cell may result in a level shift, resulting in a "program disturb" in which the wrong level is stored in the cell. During reading, "read disturbs" occur when the distribution of one signal level overlaps the distribution of an adjacent signal level. Because the signal distance is reduced, the increase in the number of discrete values stored in the cell reduces the noise margin of the cell as compared to a binary storage cell, making the storage element more prone to erroneous readout. Read disturbs are more common for low-level signals, which are characterized by larger noise distributions as shown in FIG. 1. [0010] The reduction in voltage separation between adjacent levels in a multi-level solid state non-volatile memory may lead to an increase in the number of errors in comparison with conventional solid state non-volatile memory cells. Thus, it would be desirable to provide improved methods and techniques for operating solid state non-volatile memory with multilevel cells.
SUMMARY OF THE INVENTION
[0011] According to an embodiment of the present invention, a solid state non-volatile memory unit is provided. The memory unit includes a multi-level solid state non- volatile memory array adapted to store data characterized by a first number of digital levels. The memory unit also includes an analog-to-digital converter. The analog-to-digital converter is adapted to receive data from the multi-level solid state non- volatile memory array. The analog-to-digital converter is also adapted to output a digital signal characterized by a second number of digital levels greater than the first number of digital levels.
[0012] According to another embodiment of the present invention, a method of operating a solid state non- volatile memory unit is provided. The method includes encoding a first data and storing the encoded first data in a multi-level solid state non- volatile memory array. The stored encoded first data is characterized by a first number of digital levels. The method also includes retrieving the first encoded data from the memory array and digitizing the retrieved data to a number of digital levels greater than the number of digital levels associated with the multi-level solid state non-volatile memory array.
[0013] According to an alternative embodiment of the present invention, a controller for a multi-level solid state non- volatile memory array characterized by a first number of digital levels is provided. The controller includes a first encoder adapted to receive a series of data bits and provide a series of encoded data bits. The controller also includes a mapper adapted to convert the series of encoded data bits into a series of data symbols for storage in the multi-level solid state non-volatile memory array. The controller further includes a first decoder adapted to receive a series of voltage signals from the multi-level solid state nonvolatile memory array and generate a series of output data symbols characterized by a second number of digital levels greater than the first number of digital levels.
[0014] According to yet another embodiment of the present invention, a method of operating a controller for a multi-level solid state non-volatile memory array characterized by a first number of digital levels is provided. The method includes encoding a first series of data bits to provide a series of encoded data bits and converting the series of encoded data bits into a series of data symbols. The method also includes storing the series of data symbols in the multi-level solid state non- volatile memory array and retrieving the series of data symbols. The method further includes decoding the series of data symbols to provide a series of output data symbols characterized by a second number of digital levels greater than the first number of digital levels.
[0015] According to a particular embodiment of the present invention, a solid state nonvolatile memory unit is provided. The memory unit includes means for encoding a first data and means for storing the encoded first data in a multi-level solid state non-volatile memory array. The stored encoded first data is characterized by a first number of digital levels. The memory unit also includes means for retrieving the first encoded data from the memory array and means for digitizing the retrieved data to a number of digital levels greater than the number of digital levels associated with the multi-level solid state non-volatile memory array.
[0016] According to another particular embodiment of the present invention, a controller for a multi-level solid state non- volatile memory array characterized by a first number of digital levels is provided. The controller includes means for encoding a first series of data bits to provide a series of encoded data bits and means for converting the series of encoded data bits into a series of data symbols. The controller also includes means for storing the series of data symbols in the multi-level solid state non- volatile memory array and means for retrieving the series of data symbols. The controller further includes means for decoding the series of data symbols to provide a series of output data symbols characterized by a second number of digital levels greater than the first number of digital levels.
[0017] Still other embodiments of the present invention may be implemented in code, for example, by a digital signal processor (DSP). One such embodiment includes code for encoding a first data and means for storing the encoded first data in a multi-level solid state non- volatile memory array. The stored encoded first data is characterized by a first number of digital levels. The embodiment also includes code for retrieving the first encoded data from the memory array and code for digitizing the retrieved data to a number of digital levels greater than the number of digital levels associated with the multi-level solid state nonvolatile memory array.
[0018] In another embodiment implemented in code, for example, by a DSP, code for controlling a multi-level solid state non- volatile memory array characterized by a first number of digital levels is provided. The embodiment includes code for encoding a first series of data bits to provide a series of encoded data bits and code for converting the series of encoded data bits into a series of data symbols. The embodiment also includes code for storing the series of data symbols in the multi-level solid state non- volatile memory array and code for retrieving the series of data symbols. The embodiment further includes code for decoding the series of data symbols to provide a series of output data symbols characterized by a second number of digital levels greater than the first number of digital levels.
[0019] Many benefits are achieved by way of the present invention over conventional techniques. For example, embodiments of the present invention provide solid state non- volatile memory systems with increased storage density. Moreover, some embodiments improve the reliability of data read from solid state non- volatile memories. Depending upon the embodiment, one or more of these benefits, as well as other benefits, may be achieved. These and other benefits will be described in more detail throughout the present specification and more particularly below in conjunction with the following drawings. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] FIG. 1 is a simplified probability distribution function as a function of voltage for a solid state non- volatile memory cell having a 4-level quantization;
[0021] FIG. 2A is a constellation diagram for an uncoded one bit PAM scheme; [0022] FIG. 2B is a constellation diagram for a two-bit data modulated using a PAM scheme having an average power of 1;
[0023] FIG. 2C is a constellation diagram for a two-bit data modulated using a PAM scheme having a peak limit of ±1 for use in a solid state non-volatile memory cell;
[0024] FIG. 3 A is a simplified block diagram of an exemplary solid state non- volatile memory unit with error correction code according to an embodiment of the present invention;
[0025] FIG. 3B is a simplified block diagram of a solid state non- volatile memory unit incorporating an analog-to-digital converter according to an embodiment of the present invention;
[0026] FIG. 4 is a simplified block diagram of a solid state non- volatile memory unit with error correction according to another embodiment of the present invention;
[0027] FIG. 5 shows a word error rate (WER) of a memory unit, in accordance with one exemplary embodiment of the present invention, as compared to a conventional uncoded system;
[0028] FIG. 6 shows various blocks of an exemplary rate 1/2 convolutional encoder according to an embodiment of the present invention;
[0029] FIG. 7 shows an example of 2-D set partitioning according to an embodiment of the present invention;
[0030] FIG. 8 is a simplified block diagram of a conventional TCM encoder;
[0031] FIG. 9 illustrates an example of combining set-partitioning with iterative code according to an embodiment of the present invention;
[0032] FIG. 1OA is a simplified illustration of a two-level system that includes an inner code and an outer code according to an embodiment of the present invention;
[0033] FIG. 1OB is a simplified block diagram of a two-level encoding channel according to another exemplary embodiment of the present invention; [0034] FIGS. 11 A-11 C show a number of exemplary sector and codeword sizes, in accordance with the present invention;
[0035] FIG. 12 illustrates an exemplary 3 -way interleaved cell according to an embodiment of the present invention; [0036] FIG. 13 A is a simplified schematic diagram of an interleaving technique provided according to an exemplary embodiment of the present invention;
[0037] FIG. 13B is a plot of SER as a function of SNR for an interleaved system as illustrated in FIG. 13 A; and
[0038] FIGS. 14A-14H show various devices in which the present invention may be embodied.
DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS
[0039] FIG. 2A is a constellation diagram for an uncoded one bit PAM (pulse amplitude modulation) scheme according to which, information is stored as either a 0 (-1 volts) or a 1 (+1 volts). FIG. 2B is a constellation diagram for a two-bit data modulated using a PAM scheme having an average power of 1. The four states defined by the two bits, namely states (00, 01, 10, and 11) are mapped to one of four possible levels, for example, -3/^5 volts, -lW5 volts, +1/V5 volts, and +3/V5 volts. Given these voltages, both the 2-points PAM (2-PAM) and the 4-points PAM (4-PAM) with 1/2 code rate provide a 1 bit/cell spectral efficiency and are characterized by equal power. For the modulation scheme illustrated by FIG. 2B, the 4- state code with Gray mapping reduces bit error rate over the 4-state natural mapping.
[0040] In solid state non-volatile memory devices, the maximum voltage applied at the floating gate limits the maximum voltage available for mapping of multi-level symbols. This voltage limitation results in a peak constraint on the constellation values of the applied modulation and encoding scheme. Thus, for a solid state non-volatile memory device, the constellation points must account for this limitation. The maximum voltage constraint characteristic of solid state non- volatile memory systems constrasts with other channels in which additional power increases are available. Accordingly, embodiments of the present invention utilize modulation and encoding schemes for multi-level non- volatile solid state memories designed to be operable in spite of such constraints. [0041] FIG. 2C is a constellation diagram for a two-bit data modulated using a PAM scheme having a peak value limited to ±1 for use in a solid state non-volatile memory cell. Symbol 00 is mapped to a signal amplitude of -1 volts and symbol 10 is mapped to a signal amplitude of +1 volts, which in this example, correspond to the maximum voltages stored by a given solid state non- volatile memory cell. Applying power scaling to account for the maximum allowable voltage across the non-volatile solid state memory cells, it is seen that the squared free distance is reduced by a factor of 5/9, resulting in a 0 dB coding gain over an uncoded 2-PAM system.
[0042] As the number of levels increases, the signal to noise ratio (SNR) decreases. However, the slope of the SNR decrease is not the same for these two systems. Referring to FIGS. 2B and 2C, the SNR is related to the minimum distance between the nearest neighbors in the constellation map. Consequently, voltage constraints in solid state non-volatile memory devices reduce the available minimum distance and the SNR. Therefore, for a given number of levels, memory systems generally have a lower SNR compared to other known systems. As a result of these differences, the encoding and modulation techniques, in accordance with various embodiments of the present invention, are adapted to the environment characteristic of solid state non- volatile memories.
[0043] Assuming equal energy constellations, for an uncoded system, the error probability (Puncoded) is upper bounded by :
P,mcoded ≤ « 4*L eXpf Z≤J , (1)
Figure imgf000009_0001
where Amιn is the number of nearest neighbors, dmin is the minimum distance squared between two points in a constellation, and Q(x) is the complementary error function (co-error function).
[0044] For a coded system:
* coded
Figure imgf000009_0002
where djree is the minimum distance.
[0045] The asymptotic coding gain is defined by:
Figure imgf000010_0001
[0046J For the coded system, the minimum distance d/ree is generally increased in comparison to the uncoded system, resulting in an asymptotic coding gain greater than one. However, the number of nearest neighbors also increases so the real coding gain is somewhat reduced.
[0047] FIG. 3 A is a simplified block diagram of an exemplary solid state non-volatile memory unit 300 with an ECC according to an embodiment of the present invention. User data to be written into the multi-level memory cells of multi-level solid state non-volatile memory 314 are ECC encoded by encoder 310 to add redundant symbols. The encoded data is passed to modulator 312 for channel encoding. According to embodiments of the present invention, any one of a number of encoding and modulation techniques may be used.
[0048] Multi -level solid state non- volatile memory 314 receives encoded and modulated data from modulator 312. Multi-level solid state non- volatile memory 314 may be a flash EEPROM, or the like. Generally, a multi-level flash memory includes one or more flash memory cell arrays and read and write (program) circuitry. In addition to a multi-level flash memory, there are other types of solid state non-volatile memory technologies that are included within the scope of the present invention. Floating gate memory cells such as flash memories are discussed herein merely by way of example. Embodiments of the present invention as described throughout the present specification also apply to other memory technologies other than floating gate technology with the appropriate modifications. One of ordinary skill in the art would recognize many variations, modifications, and alternatives.
[0049] Data is read from multi-level solid state non- volatile memory 314 and passes to demodulator 316 and decoder 318. The demodulator in embodiments of the present invention includes signal processing logic adapted to extract soft information related to the data stored in the multi -level solid state non- volatile memory 314. In conventional binary non-volatile memory systems, a threshold detector is utilized to determine if a voltage value associated with a particular cell is less than or greater than a given threshold value. This threshold-based approach is also utilized in multi-level memory systems, where the threshold detection circuit merely utilizes a greater number of threshold values. Although some multi- level memory systems include circuitry that tracks process or other variations and adjusts the threshold values accordingly, these systems output a value from a number of possible values that is equal to the number of levels in the multi-level system. Thus, for example, for a conventional four-level non- volatile memory, the sense amplifier will produce a data signal representing one of the four levels.
[0050] In contrast with conventional multi-level memory systems, embodiments of the present invention utilize a demodulator that produces an output having a number of possible values greater than the number of levels provided by the multi-level solid state non- volatile memory 314. This information is sometimes referred to as soft information since the output includes information in addition to the value stored in the multi-level memory. Merely by way of example, an analog-to-digital (A/D) converter or detector provided as part of or working in conjunction with demodulator 316 provides an output signal with, for example, 32 possible values in response to the values detected by a sense amplifier disposed in communication with, for example, a four-level memory. Embodiments of the present invention are not limited to using an output signal with 32 levels, as other output signals, with, for example, 8, 16, or more levels are included within the scope of the present invention. In some applications, the soft information is passed to a soft information decoder (not shown) for processing. In embodiments of the present invention, the soft information provided by the demodulator 316 is utilized during signal processing operations to improve the reliability with which data from the solid state non- volatile memory 314 is read.
[0051] In an embodiment of the present invention, encoder 310, modulator 312, demodulator 316, and decoder 318 are components of a controller in communication with multi-level solid state non- volatile memory 314. Memory devices typically include one or more memory chips that are mounted on a card. Each of the memory chips may include an array of memory cells as well as integrated circuits performing such operations as program, read, and erase. According to embodiments of the present invention, a controller circuit performing these operations may or may not be disposed in the integrated circuits (IC) in which the memory chip (s) are also disposed. Controllers provided herein are not limited to performing encoding/decoding and modulation/demodulation processes, but may also provide for other functionality such as wear leveling and interfacing processes.
[0052] Embodiments of the present invention enable system designers to increase the memory density of existing solid state non-volatile memories. As described more fully throughout the present specification, in comparison with conventional systems, increased levels of read and write errors are corrected utilizing the techniques and methods provided herein. Thus, although attempting to utilize, for example, a four-level- memory system for, for example, eight-level applications by introducing additional levels may produce a greater number of errors during read operations than is otherwise acceptable under a given performance measure, techniques described herein may be utilized to correct such errors during the demodulation process and enable the use, for instance, of a four-level memory system in an eight-level application. Thus, in accordance with the present invention, the memory density of existing solid state non-volatile memory systems may be increased while still using some of the same components, including memory arrays, sense amplifiers, and the like. [0053] FIG. 3B is a simplified block diagram of a solid state non-volatile memory unit 350 incorporating an A/D converter according to an embodiment of the present invention. As illustrated in FIG. 3B, an encoder 360 and a modulator 362 provide encoded and modulated data to the multi-level non-volatile solid state memory 364. A/D converter 366 receives signals from the multi-level non-volatile solid state memory 364. The digital signal output by the A/D converter 366 is of higher resolution (characterized by more levels) than the number of levels associated with the multi-level non- volatile solid state memory 364. Merely by way of example, in a particular embodiment, the multi-level non- volatile solid state memory 364 is, for example, a four-level memory, providing storage for 2 bits in each cell. During a read operation, the A/D converter 366 converts an analog signal associated with one or more cells of the memory 364 into one of, for example, 8, 16, 32, or 64 levels depending on the particular application. Other numbers of levels greater than four levels are used in other embodiments. Signal processing algorithms resident in demodulator 368 utilize the output of the A/D converter 366 to determine the likelihood that the cell contains data associated with one of the four levels stored in the cell. One of ordinary skill in the art would recognize many variations, modifications, and alternatives.
[0054] In conventional solid state memories, ECC techniques are utilized to detect and correct errors in data as the data is read out from the memory. Such ECC techniques simply operate on binary or multi-level digital data produced by a sense amplifier. On the other hand, in accordance with the present invention, soft information produced and utilized by the demodulator 316 does not merely include the binary or multi -level digital data, but additional information as well. Soft information is typically represented by distributions that are useful in performing signal processing techniques not generally applicable once the data has been reduced to threshold-based digital values equal in number to the number of levels in the multi-level system.
[0055] Utilizing embodiments of the present invention, positive coding gain is achieved for multi-level solid state non-volatile memory systems in comparison to uncoded systems. Table 1 illustrates an exemplary coding gain from convolutional coded 2 bit/cell multi-level non-volatile memory over an uncoded 1 bit/cell non-volatile memory as a function of the number of states of the code. As shown in the first row entry, for a 4-state system (illustrated by FIGS. 2A-2C), the coding gain in comparison to an uncoded system is 0 dB. However, as the number of states is increased, the coding gain in comparison to an uncoded system is positive.
Table 1
Figure imgf000013_0001
[0056] Table 2 illustrates the coding gain for convolutional coded 3 bit/cell multi-level non- volatile memory over uncoded 2 bit/cell multi-level non-volatile memory as a function of the number of states of the code. As shown for 1 bit/cell multi-level non- volatile memory with four or more states, the coding gain in comparison to an uncoded system is positive for systems with four or more states.
Table 2
Figure imgf000013_0002
[0057] FIG. 4 is a simplified block diagram of a solid state non-volatile memory unit with error correction according to another embodiment of the present invention. As illustrated in FIG. 4, an outer encoder 410 provides encoded data to an inner encoder 412. As an example, outer encoder 410 may be a Reed-Solomon encoder and inner encoder may be an LDPC encoder. These encoding techniques are used merely as examples and are not intended to limit the scope of the present invention. One of ordinary skill in the art would recognize many variations, modifications, and alternatives. Modulator 414 receives encoded data from inner encoder 412 and modulates the data prior to storage in multi-level solid state nonvolatile memory 416 during a program operation. During a read operation, the data stored in the multi-level solid state non-volatile memory 416 is retrieved and provided to demodulator 418, inner decoder 420, and outer decoder 422.
[0058] Any number of Error Correcting Codes (ECCs) including Forward Error Correction (FEC) codes may be used according to embodiments of the present invention to improve the bit error rate (BER) performance of power-limited and/or bandwidth-limited channels by adding structured redundancy to the transmitted data. For example, block codes may be used to encode a block of data for channels with additive burst noise (random multi-bit errors). It is understood that the present invention is applicable to both systematic encoders that do not manipulate the user data prior to encoding and storage, as well as to non-systematic encoders.
[0059] Any one of a number of different linear block codes including, for example, binary codes such as Hamming code, BCH code, Reed-Muller code and Array Code, and non-binary codes such as Reed-Solomon (RS) code may be used. Choice of block size depends on SNR and the code used. For example, assume that the voltage levels are increased from 4 to 8 per cell, and that each three cells are grouped together to form a 9-bit symbol. Applying a (511, 451) Reed-Solomon code, based on GF(29), the codeword length is 511 *9 = 4599 bits, and the code rate is 451/51 l~=0.883. Therefore, the storage capacity for the coded system is 3*451/511~=2.6 bits/cell, which represents a 32% capacity increase over uncoded 4-level system. The word error rate (WER) of such a coded system is compared to a 4-level uncoded system in FIG. 5. It can be seen at WER<10"8, the RS coded system outperforms the uncoded system. Therefore, with the above RS code, better reliability and higher capacity is achieved.
[0060] In accordance with other exemplary embodiments of the present invention, for example, when the noise is independent from symbol to symbol, convolutional codes are used to encode the data. Convolutional codes introduce correlation into coded data and thus increase the minimum distance at the decoder. Convolutional codes are applied to serially- transmitted data stored in or read from solid state non- volatile memories, which are subject to Gaussian noise. Convolutional codes are progressive codes. At any point in time, the output of a convolutional encoder may depend upon both the past and present input values. Thus, convolutional codes are generally directed to correcting errors that span an ordered progression of data values. Accordingly, such codes maybe used in multi-level solid state non-volatile memories that store and read out data in the form of an ordered, progressive stream (i.e., a data stream).
[0061] The decoder receives either hard decision inputs or multi-level quantized inputs. Soft inputs are known to cause fewer errors at the detector. FIG. 6 shows various blocks of an exemplary rate 1/2 convolutional encoder 600. Output C2 generated by modulo-2 adder 610 is defined by shift registers 602, 606 and input U. For example, if the voltage levels are increased from four to eight, applying a rate 3/4 convolutional code to get 3*3/4=2.25 bits/cell, results in a 10% increase in storage capacity. To achieve the same error rate as uncoded 4-level system, the free distance of the convolutional code must be greater than (7/3)2=5.44. A 3/4 convolutional encoder with six memory units would require a Viterbi decoder with 2δ=64 states. [0062] Trellis coded modulation (TCM) combines convolutional code with set partitioning to achieve high code rate, high coding gain, and low decoding complexity. A set of constellation points can be partitioned to a smaller subset, where points in each subset are separated further than in the original constellation. FIG. 7 shows an example of 2-D set partitioning where dots, " o ", represent one subset, and crosses, "x", represent the other. If the minimum distance between the original constellation points is d, then the minimum distance between points in each subset is V2d . hi systems with additive white Gaussian Noise (AWGN) channels, such as flash memory systems read path channels, the parameter governing the performance of the system is not the free Hamming distance of the convolutional code, but rather the free Euclidean distance between the transmitted signal sequences. Accordingly, the optimization of the TCM design is based on the Euclidean distances rather than, the Hamming distances.
[0063] An example of TCM is shown in FIG. 8. Input bits are separated into two groups ~ a first group with k] bits, going through a rate ki/(kι+l) encoder 802 to select subsets; a second group with k-ki bits, which select constellation points, using constellation mapper 804, within each subset. Below is a description of an exemplary increase in capacity from 2bits/cell to 2.5bits/cell. Assume that there are 8 voltage levels and that each two adjacent cells is combined to form a 64 QAM constellation. The 64 QAM is partitioned into 4 cosets. Distance between any two points in each coset is 8*dO. Assume a rate 3/ 4 convolutional code is used to select a coset, and two uncoded bits are used to select a point within any given coset. The overall code rate would thus become 5/6, leading to 2.5 bits/cell. The overall coding gain is 0.43 dB. Therefore, such a TCM coded system has a better performance than the uncoded 4 level system while increasing the storage capacity by 25%.
[0064] Some codes based on random construction may be effectively decoded by iterative detection methods. These codes include Turbo codes, i.e., serially concatenated convolutional codes, or parallel concatenated convolutional codes, low-density parity-check (LDPC) codes, Turbo Product code, and their variations. [0065] Coding gain of TCM comes from two areas — set partitioning to increase the distance between constellation points within each subset, and convolutional code to achieve high Euclidean distance between different subsets, the latter of which can also be achieved if other high gain codes are substituted for convolutional code. An example of combining set- partitioning with iterative code is shown in FIG. 9. Assume a 16-PAM system is partitioned into 4 subsets. Then the minimum distance between points in each subset is 4do, hence providing a 12dB gain compared to uncoded system. However, between different subsets, the minimum distance remains at do. Since the selection of subset depends on LDPC coded bits supplied by LDPC encoder 902, then the overall system has an approximate gain of 12dB if an LDPC code having a gain of 12dB is used. In general, the overall system gain is the minimum of the set-partitioning gain and the iterative coding gain. LDPC encoder 902 shown in FIG. 9 is required to operate on a whole codeword defined by the iterative code block size. In addition to iterative codes, other high gain codes including RS code and BCH code may be used to code a portion of the input for subset selection.
[0066] In accordance with some embodiments, to further improve coding gain, multi-level coding may be used. A two-level encoding that includes an inner encoder and an outer encoder is shown in FIG. 10. In one exemplary embodiment, outer code encoder 1002 may be a RS encoder, and inner code encoder 1004 may be a TCM encoder. Bursty errors caused by TCM decoder 1006 are corrected by RS decoder 1008.
[0067] Ln another exemplary embodiment, inner encoder 1004 is adapted to perform iterative codes, such as LDPC codes or Turbo codes, and outer encoder 1002 is adapted to perform RS code. Iterative codes may be binary codes or symbol-based codes. Each symbol may contain multiple bits. Iterative codes may be decoded using a~soft-input soft-output (SISO) decoder, while RS codes may be decoded using either a SISO or a hard-decision decoder. The outer RS decoder 1008 may iterate with inner decoder 1006 to exchange soft information. Such iteration would improve the quality of soft information and thereby decrease the number of bit errors after each iteration. [0068] The descriptions of the various embodiments provided herein are provided merely by way of example, and are not intended to limit the scope of the present invention. Various other coding techniques, interleaving techniques, modulation techniques, demodulation techniques, decoding techniques, mapping techniques, and the like are included within the scope of the present invention.
[0069] As seen from FIG. 1, the PDF of the programmed cells is different depending on the cell's threshold voltage. If the four levels are spaced equally, then the level corresponding to cells with a PDF defined by a threshold voltage ranging between 2 and 4 volts is more prone to errors than other levels due to its wider distribution. Accordingly, in some embodiments, constrained coding is used to inhibit certain patterns or reduce their frequency. For example, lowering the frequency of data corresponding to cells with a PDF defined by a threshold voltage ranging between 2 and 4 volts lowers the overall error probability.
[0070] In some embodiments, the codeword size is aligned with the sector size. For example, if the sector size is, for example, 256 kbits, the inner code and outer code may be configured such that one outer codeword is 256 kbits. Smaller or larger codeword sizes relative to the sector size may also be used. In FIG. 1 IA, the sector size is shown as being equal to the codeword size. In the case of smaller codeword size, each sector includes several codewords, as shown in FIG. 1 IB. In the case of larger codeword size, each codeword includes several sectors, as shown in FIG. 11C. In general, the larger the codeword size, the larger the coding gain, the longer decoding delay, and the higher is the decoder complexity.
[0071] Codewords may be interleaved before being stored. FIG. 12 shows an exemplary 3- way interleaved cell in which cells 1202 form codeword 1, cells 1204 form codeword 2, and cells 1206 form codeword 3. If a defect spans no more than three cells, it causes only one symbol error in each codeword, which is easier to correct than a burst of three symbol errors.
[0072] In accordance with other exemplary embodiments of the present invention, coding of data, as described above may be applied across a multitude of non- volatile solid-state semiconductor memories, that in some embodiments are physically stacked on top of one another. For example, if 8 such non- volatile solid-state semiconductor memories are stacked together, a GF(28)-based RS code may be applied across these memories, where each bit of a RS code symbol comes from one of these memories. Coding across such memories improves error recovery in the event one of these memories has large defects. [0073] FIG. 13 A is a simplified schematic diagram of an interleaving technique provided according to an exemplary embodiment of the present invention. As illustrated in FIG. 13 A, an inner encoder, for example, a TCM encoder, is utilized on rows of data and an outer encoder, for example, an RS encoder, is utilized on block columns of data. This exemplary embodiment may be used, for example, in solid state non-volatile memories, in which the data is written to the memory cells in a rectangular format, i.e., blocks. In situations in which a multi-bit error of significant length is present on the inner TCM code, embodiments of the present invention provide that several independent outer RS codes process data corrupted by the multi-bit error. Accordingly, the number of errors impacting an individual RS code is limited. Referring to FIG. 13 A, the number of columns in a particular implementation is determined, in part, by the maximum error burst length. The number of rows is determined, in part, by the number of sectors per block codeword.
[0074] According to some embodiments of the present invention, the number of columns is predetermined depending on the particular application. For example, if the number of columns (related to the interleaving depth) is larger than the maximum error burst length, then the outer encoder operating on the columns is similar to a memoryless channel characterized by a particular symbol error rate. Accordingly, error bursts that occur affect different outer encoder codes. The symbol error rate is typically determined by using TCM simulations independently, and the error probability may be estimated by independent modeling. The percentage of overhead of the outer encoder, for example, an RS encoder, may be reduced by increasing the row dimension of the block codeword. Alternatively, one can increase the row dimension of the RS code while keeping the overhead percentage constant, thereby allowing for a higher correction power per column.
[0075J FIG. 13B is a plot of SER as a function of SNR for an interleaved system as illustrated in FIG. 13 A. To compute the data presented in FIG. 13B, 10 columns and 10 sectors per block codeword were utilized. Other embodiments will utilize a varying number of columns and sectors per block codeword depending on the particular application. The SER for an uncoded 2 bits/cell 4-PAM system is illustrated for purposes of comparison. The SER values for implementations in which the strength of the outer encoder (an RS encoder in this example) is varied over a range of correction powers are shown (tRs=12, 14, and 16, respectively). As the correction power or strength of the outer encoding increases, the SNR at which the coded system drops to a level equal to the uncoded system decreases. Referring to FIG. 13B, this cross-over point is at approximately 22.4 dB, 22.2 dB, and 22.0 dB for tRs=12, 14, and 16, respectively.
[0076] In a particular exemplary embodiment, a multi-level solid state non-volatile memory includes, for example, 2.5 bits/cell. In such embodiments, two adjacent 8-level cells
(3 bits/cell) form a 64-QAM modulation symbol. Of the six bits in the 64-QAM modulation symbol, five bits are utilized for data and one bit is used for encoding. Thus, in such exemplary embodiments, the code rate is 5/6 and the number of branches per state is equal to four. Such a system provides 2.5 bits/cell as 5 data bits are stored between two adjacent cells. In such exemplary embodiments, the coding gain in comparison with an uncoded 4-PAM system may be, for example, 0.423 dB for 16 states. It should be noted that calculation results will be modified as multiplicities are included in such calculations. For example, losses of approximately 0.2 dB are expected with the doubling of multiplicities. One of ordinary skill in the art would recognize many variations, modifications, and alternatives.
[0077] In another particular exemplary embodiment of the present invention, multi-level solid state non- volatile memory systems with, for example, 3.5 bits/cell are provided. In such embodiments, two adjacent 16-level cells (4 bits/cell) form a 256-QAM modulation symbol. Of the eight bits in the 256-QAM modulation symbol, seven bits are utilized for data and one bit is used for encoding. Thus, in such exemplary embodiments the code rate is 7/8 and the number of branches per state is equal to four. Such a system provides 3.5 bits/cell as 7 data bits are stored between two adjacent cells. The coding gain in comparison with an uncoded 8-PAM system may be, for example, 0.527 dB for 8 states and 1.317 dB for 16 states. It should be noted that calculation results will be modified as multiplicities are included in such calculations. For example, losses of approximately 0.2 dB are expected with the doubling of multiplicities. One of ordinary skill in the art would recognize many variations, modifications, and alternatives. [0078] Referring now to FIGS. 14 A- 14G, various exemplary implementations of the present invention are shown. Referring to FIG. 14A, the present invention may be embodied in a hard disk drive 1400. The present invention may implement either or both signal ' processing and/or control circuits, which are generally identified in FIG. 14A at 1402. In some implementations, signal processing and/or control circuit 1402 and/or other circuits (not shown) in HDD 1400 may process data, perform coding and/or encryption, perform calculations, and/or format data that is output to and/or received from a magnetic storage medium 1406.
[0079] HDD 1400 may communicate with a host device (not shown) such as a computer, mobile computing devices such as personal digital assistants, cellular phohes, media or MP3 players and the like, and/or other devices via one or more wired or wireless communication links 1408. HDD 1400 maybe connected to memory 1409, such as random access memory (RAM), a low latency nonvolatile memory such as flash memory, read only memory (ROM) and/or other suitable electronic data storage.
[0080] Referring now to FIG. 14B, the present invention may be embodied in a digital versatile disc (DVD) drive 1410. The present invention may implement either or both signal processing and/or control circuits, which are generally identified in FIG. 14B at 1412, and/or mass data storage 1418 of DVD drive 1410. Signal processing and/or control circuit 1412 and/or other circuits (not shown) in DVD drive 1410 may process data, perform coding and/or encryption, perform calculations, and/or format data that is read from and/or data written to an optical storage medium 1416. In some implementations, signal processing and/or control circuit 1412 and/or other circuits (not shown) in DVD drive 1410 can also perform other functions such as encoding and/or decoding and/or any other signal processing functions associated with a DVD drive.
[0081] DVD drive 1410 may communicate with an output device (not shown) such as a computer, television or other device via one or more wired or wireless communication links 1417. DVD drive 1410 may communicate with mass data storage 1418 that stores data in a nonvolatile manner. Mass data storage 1418 may include a hard disk drive (HDD) such as that shown in FIG. 14A. The HDD may be a mini HDD that includes one or more platters having a diameter that is smaller than approximately 1.8". DVD drive 1410 may be connected to memory 1419, such as RAM, ROM, low latency nonvolatile memory such as flash memory, and/or other suitable electronic data storage. [0082] Referring now to FIG. 14C, the present invention may be embodied in a high definition television (HDTV) 1420. The present invention may implement either or both signal processing and/or control circuits, which are generally identified in FIG. 14C at 1422, a WLAN interface and/or mass data storage of the HDTV 1420. HDTV 1420 receives HDTV input signals in either a wired or wireless format and generates HDTV output signals for a display 1426. In some implementations, signal processing circuit and/or control circuit 1422 and/or other circuits (not shown) of HDTV 1420 may process data, perform coding and/or encryption, perform calculations, format data and/or perform any other type of HDTV processing that may be required.
[0083] HDTV 1420 may communicate with mass data storage 1427 that stores data in a nonvolatile manner such as optical and/or magnetic storage devices. At least one HDD may have the configuration shown in FIG. 14A and/or at least one DVD drive may have the configuration shown in FIG. 14B. The HDD may be a mini HDD that includes one or more platters having a diameter that is smaller than approximately 1.8". HDTV 1420 may be connected to memory 1428 such as RAM, ROM, low latency nonvolatile memory such as flash memory and/or other suitable electronic data storage. HDTV 1420 also may support connections with a WLAN via a WLAN network interface 1429. [0084] Referring now to FIG. 14D, the present invention may be embodied in a control system, a WLAN interface and/or mass data storage of a vehicle 1030. In some implementations, the present invention implements apowertrain control system 1432 that receives inputs from one or more sensors such as temperature sensors, pressure sensors, rotational sensors, airflow sensors and/or any other suitable sensors and/or that generates one or more output control signals such as engine operating parameters, transmission operating parameters, and/or other control signals.
[0085] The present invention may also be embodied in other control system 1440 of vehicle 1430. Control system 1440 may likewise receive signals from input sensors 1442 and/or output control signals to one or more output devices 1444. In some implementations, control system 1440 may be part of an anti-lock braking system (ABS), a navigation system, a telematics system, a vehicle telematics system, a lane departure system, an adaptive cruise control system, a vehicle entertainment system such as a stereo, DVD, compact disc system and the like. Still other implementations are contemplated.
[0086] Powertrain control system 1432 may communicate with mass data storage 1446 that stores data in a nonvolatile manner. Mass data storage 1446 may include optical and/or magnetic storage devices for example HDDs and/or DVD drives. At least one HDD may have the configuration shown in FIG. 14A and/or at least one DVD drive may have the configuration shown in FIG. 14B. The HDD may be a mini HDD that includes one or more platters having a diameter that is smaller than approximately 1.8". Powertrain control system 1432 may be connected to memory 1447 such as RAM, ROM, low latency . nonvolatile memory such as flash memory and/or other suitable electronic data storage. Powertrain control system 1432 also may support connections with a WLAN via a WLAN network interface 1448. The control system 1440 may also include mass data storage, memory and/or a WLAN interface (all not shown).
[0087] Referring now to FIG. 14E, the present invention may be embodied in a cellular phone 1450 that may include a cellular antenna 1451. The present invention may implement either or both signal processing and/or control circuits, which are generally identified in FIG. 14E at 1452, a WLAN interface and/or mass data storage of the cellular phone 1450. In some implementations, cellular phone 1450 includes a microphone 1456, an audio output 1458 such as a speaker and/or audio output jack, a display 1460 and/or an input device 1462 such as a keypad, pointing device, voice actuation and/or other input device. Signal processing and/or control circuits 1452 and/or other circuits (not shown) in cellular phone 1450 may process data, perform coding and/or encryption, perform calculations, format data and/or perform other cellular phone functions.
[0088] Cellular phone 1450 may communicate with mass data storage 1464 that stores data in a nonvolatile manner such as optical and/or magnetic storage devices for example HDDs and/or DVD drives. At least one HDD may have the configuration shown in FIG. 14A and/or at least one DVD drive may have the configuration shown in FIG. 14B. The HDD may be a mini HDD that includes one or more platters having a diameter that is smaller than approximately 1.8". Cellular phone 1450 maybe connected to memory 1466 such as RAM, ROM, low latency nonvolatile memory such as flash memory and/or other suitable electronic data storage. Cellular phone 1450 also may support connections with a WLAN via a WLAN network interface 1468.
[0089] Referring now to FIG. 14F, the present invention may be embodied in a set top box 1480. The present invention may implement either or both signal processing and/or control circuits, which are generally identified in FIG. 14F at 1484, a WLAN interface and/or mass data storage of the set top box 1480. Set top box 1480 receives signals from a source such as a broadband source and outputs standard and/or high definition audio/video signals suitable for a display 1488 such as a television and/or monitor and/or other video and/or audio output devices. Signal processing and/or control circuits 1484 and/or other circuits (not shown) of the set top box 1480 may process data, perform coding and/or encryption, perform calculations, format data and/or perform any other set top box function.
[0090] Set top box 1480 may communicate with mass data storage 1490 that stores data in a nonvolatile manner. Mass data storage 1490 may include optical and/or magnetic storage devices for example HDDs and/or DVD drives. At least one HDD may have the configuration shown in FIG. 14A and/or at least one DVD drive may have the configuration shown in FIG. 14B. The HDD may be a mini HDD that includes one or more platters having a diameter that is smaller than approximately 1.8". Set top box 1480 may be connected to memory 1494 such as RAM, ROM, low latency nonvolatile memory such as flash memory and/or other suitable electronic data storage. Set top box 1480 also may support connections with a WLAN via a WLAN network interface 1496.
[0091] Referring now to FIG. 14G, the present invention may be embodied in a media player 1472. The present invention may implement either or both signal processing and/or control circuits, which are generally identified in FIG. 14G at 1471, a WLAN interface and/or mass data storage of the media player 1472. In some implementations, media player 1472 includes a display 1476 and/or a user input 1477 such as a keypad, touchpad and the like. In some implementations, media player 1472 may employ a graphical user interface (GUI) that typically employs menus, drop down menus, icons and/or a point-and-click interface via display 1476 and/or user input 1477. Media player 1472 further includes an audio output 1475 such as a speaker and/or audio output jack. Signal processing and/or control circuits 1471 and/or other circuits (not shown) of media player 1472 may process data, perform coding and/or encryption, perform calculations, format data and/or perform any other media player function. [0092] Media player 1472 may communicate with mass data storage 1470 that stores data such as compressed audio and/or video content in a nonvolatile manner. In some implementations, the compressed audio files include files that are compliant with MP3 format or other suitable compressed audio and/or video formats. The mass data storage may include optical and/or magnetic storage devices for example HDDs and/or DVD drives. At least one HDD may have the configuration shown in FIG. 14A and/or at least one DVD drive may have the configuration shown in FIG. 14B. The HDD may be a mini HDD that includes one or more platters having a diameter that is smaller than approximately 1.8". Media player 1472 may be connected to memory 1473 such as RAM, ROM, low latency nonvolatile memory such as flash memory and/or other suitable electronic data storage. Media player 1472 also may support connections with a WLAN via a WLAN network interface 1474.
[0093] Referring to FIG. 14H5 the present invention may be embodied in a Voice over Internet Protocol (VoIP) phone 1483 that may include an antenna 1439. The present invention may implement either or both signal processing and/or control circuits, which are generally identified in FIG. 14H at 1482, a wireless interface and/or mass data storage of the VoIP phone 1483. In some implementations, VoIP phone 1483 includes, in part, a microphone 1487, an audio output 1489 such as a speaker and/or audio output jack, a display monitor 1491, an input device 1492 such as a keypad, pointing device, voice actuation and/or other input devices, and a Wireless Fidelity (Wi-Fi) communication module 1486. Signal processing and/or control circuits 1482 and/or other circuits (not shown) in VoIP phone 1483 may process data, perform coding and/or encryption, perform calculations, format data and/or perform other VoIP phone functions. [0094] VoIP phone 1483 may communicate with mass data storage 1402 that stores data in a nonvolatile manner such as optical and/or magnetic storage devices, for example hard disk drives HDD and/or DVDs. At least one HDD may have the configuration shown in FIG. 14A and/or at least one DVD may have the configuration shown in FIG. 14B. The HDD may be a mini HDD that includes one or more platters having a diameter that is smaller than approximately 1.8". VoIP phone 1483 may be connected to memory 1485, which may be a RAM, ROM, low latency nonvolatile memory such as flash memory and/or other suitable electronic data storage. VoIP phone 1483 is configured to establish communications link with a VoIP network (not shown) via Wi-Fi communication module 1486. Still other implementations in addition to those described above are contemplated. [0095] The above embodiments of the present invention are illustrative and not limitative. Various alternatives and equivalents are possible. The invention is not limited by the type of comparator, counter, pulse-width modulator, driver, or filter used. The invention is not limited by the type of amplifier used to establish the reference charging and discharging currents. The invention is not limited by the of oscillator. The invention is not limited by the type of integrated circuit in which the present disclosure may be disposed. Nor is the invention limited to any specific type of process technology, e.g., CMOS, Bipolar, or BICMOS that may be used to manufacture the present disclosure. Other additions, subtractions or modifications are obvious in view of the present disclosure and are intended to fall within the scope of the appended claims.

Claims

WHAT IS CLAIMED IS:
L A solid state non- volatile memory unit comprising: a multi-level solid state non- volatile memory array adapted to store data characterized by a first number of digital levels; and an analog-to-digital converter adapted to receive data from the multi-level solid state non-volatile memory array and output a digital signal characterized by a second number of digital levels greater than the first number of digital levels.
2. The solid state non- volatile memory unit of claim 1 wherein the multi- level solid state non-volatile memory array is a flash EEPROM array.
3. The solid state non- volatile memory unit of claim 1 wherein the solid state non-volatile memory unit is disposed in an integrated circuit.
4. The solid state non-volatile memory unit of claim 1 further comprising: a first encoder adapted to provide encoded data; and a first decoder adapted to decode data retrieved from the solid state non- volatile memory array.
5. The solid state non- volatile memory unit of claim 4 further comprising: a second encoder in communication with the first encoder; and a second decoder in communication with the first decoder.
6. The solid state non-volatile memory unit of claim 5 wherein the first encoder is adapted to perform a first ECC technique and the second encoder is adapted to perform a second ECC technique.
7. The solid state non- volatile memory unit of claim 6 wherein the first ECC technique is different from the second ECC technique.
8. The solid state non- volatile memory unit of claim 5 wherein the second encoder comprises a Reed-Solomon encoder.
9. The solid state non-volatile memory unit of claim 4 further comprising: a modulator adapted to modulate the encoded data; a demodulator adapted to demodulate the modulated data retrieved from the solid state non-volatile memory array.
10. The solid state non-volatile memory unit of claim 9 wherein the first encoder and the modulator both comprise a trellis-coded modulator.
11. The solid state non- volatile memory unit of claim 4 wherein the first encoder is a binary encoder.
12. The solid state non- volatile memory unit of claim 4 wherein the first encoder is a convolutional encoder.
13. The solid state non-volatile memory unit of claim 4 wherein the first encoder is an iterative encoder.
14. A method of operating a solid state non- volatile memory unit, the method comprising: storing a first data in a multi-level solid state non- volatile memory array, wherein the stored first data is characterized by a first number of digital levels; retrieving the stored first data from the memory array; and digitizing the retrieved data to a second number of digital levels greater than the first number of digital levels.
15. The method of claim 14 wherein the multi-level solid state non-volatile memory array is a flash EEPROM array.
16. The method of claim 14 wherein the solid state non- volatile memory unit is disposed in an integrated circuit.
17. The method of claim 14 further comprising: encoding the first data; and decoding the retrieved data.
18. The method of claim 17 further comprising: encoding a second data to generate the first data; decoding the decoded retrieved data to generate the second data.
19. The method of claim 18 wherein the encoding of the first data is performed in accordance a first ECC technique and the encoding of the second data is performed in accordance with a second ECC technique.
20. The method of claim 19 wherein the first ECC technique is different from the second ECC technique.
21. The method of claim 18 wherein encoding the second data comprises performing a Reed-Solomon encoding technique.
22. The method of claim 17 further comprising: modulating the encoded first data; storing the modulated first data in the multi-level solid state non-volatile memory array; retrieving the modulated first data from the multi-level solid state non- volatile memory array; and demodulating the first data retrieved from the multi-level solid state non- volatile memory array.
23. The method of claim 22 wherein said encoding and modulating both comprise performing trellis-coded modulation.
24. The method of claim 17 wherein encoding the first data is performed in accordance with a binary encoding technique.
25. The method of claim 17 wherein encoding the first data is performed in accordance with a convolutional encoding technique.
26. The method of claim 17 wherein encoding the first data is performed in accordance with an iterative encoding technique.
27. A controller for a multi-level solid state non-volatile memory array characterized by a first number of digital levels, the controller comprising: a first encoder adapted to receive a series of data bits and provide a series of encoded data bits; a mapper adapted to convert the series of encoded data bits into a series of data symbols for storage in the multi-level solid state non-volatile memory array; and a first decoder adapted to receive a series of voltage signals from the multi- level solid state non- volatile memory array and generate a series of output data symbols characterized by a second number of digital levels greater than the first number of digital levels.
28. The controller of claim 27 further comprising: a second encoder in communication with the first encoder; and a second decoder in communication with the first decoder.
29. The controller of claim 28 wherein the first encoder is adapted to perform a first ECC technique and the second encoder is adapted to perform a second ECC technique.
30. The controller of claim 29 wherein the first ECC technique is different from the second ECC technique.
31. The controller of claim 27 wherein the multi-level solid state non- volatile memory array comprises one or more flash EEPROM arrays.
32. The controller of claim 27 wherein the first decoder comprises a soft information decoder.
33. A method of operating a controller for a multi-level solid state non- volatile memory array characterized by a first number of digital levels, the method comprising: encoding a first series of data bits to provide a series of encoded data bits; converting the series of encoded data bits into a series of data symbols; storing the series of data symbols in the multi-level solid state non- volatile memory array; retrieving the series of data symbols; and decoding the series of retrieved data symbols to provide a series of output data symbols characterized by a second number of digital levels greater than the first number of digital levels.
34. The method of claim 33 further comprising: encoding a second series of data bits to generate the first series of data bits; and decoding the series of output data symbols.
35. The method of claim 34 wherein the encoding of the first series of data bits is performed in accordance with a first ECC technique and the encoding of the second series of data bits is performed in accordance with a second ECC technique.
36. The method of claim 35 wherein the first ECC technique is different from the second ECC technique.
37. The method of claim 33 wherein the multi-level solid state non-volatile memory array comprises one or more flash EEPROM arrays.
38. The method of claim 33 further comprising processing soft information associated with the data symbols.
39. A controller for a multi-level solid state non- volatile memory array characterized by a first number of digital levels, the controller comprising: means for encoding a first series of data bits to provide a series of encoded data bits; means for converting the series of encoded data bits into a series of data symbols; means for storing the series of data symbols in the multi -level solid state non- volatile memory array; means for retrieving the series of data symbols; and means for decoding the series of retrieved data symbols to provide a series of output data symbols characterized by a second number of digital levels greater than the first number of digital levels.
40. The controller of claim 39 further comprising: means for encoding a second series of data bits to generate the first series of data bits; and means for decoding the series of output data symbols.
.
41. The controller of claim 40 wherein the encoding of the first series of data bits is performed in accordance with a first ECC technique and the encoding of the second series of data bits is performed in accordance with a second ECC technique.
42. The controller of claim 41 wherein the first ECC technique is different from the second ECC technique.
43. The controller of claim 39 wherein the multi-level solid state non- volatile memory array comprises one or more flash EEPROM arrays.
44. The controller of claim 39 further comprising means for processing soft information associated with the data symbols.
PCT/US2007/001620 2006-01-20 2007-01-19 Method and system for error correction in flash memory WO2007084749A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN2007800099871A CN101405810B (en) 2006-01-20 2007-01-19 Method and system for error correction in flash memory
JP2008551451A JP5232013B2 (en) 2006-01-20 2007-01-19 Method and system for error correction in flash memory
EP07718293.9A EP1987519B1 (en) 2006-01-20 2007-01-19 Method and system for error correction in flash memory
KR1020087020392A KR101410434B1 (en) 2006-01-20 2007-01-19 Method and system for error correction in flash memory

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US76062206P 2006-01-20 2006-01-20
US60/760,622 2006-01-20
US76188806P 2006-01-25 2006-01-25
US60/761,888 2006-01-25
US77162106P 2006-02-08 2006-02-08
US60/771,621 2006-02-08

Publications (2)

Publication Number Publication Date
WO2007084749A2 true WO2007084749A2 (en) 2007-07-26
WO2007084749A3 WO2007084749A3 (en) 2008-04-10

Family

ID=38288304

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/001620 WO2007084749A2 (en) 2006-01-20 2007-01-19 Method and system for error correction in flash memory

Country Status (6)

Country Link
US (5) US7844879B2 (en)
EP (1) EP1987519B1 (en)
JP (1) JP5232013B2 (en)
KR (1) KR101410434B1 (en)
TW (2) TWI367492B (en)
WO (1) WO2007084749A2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8370702B2 (en) 2009-06-10 2013-02-05 Micron Technology, Inc. Error correcting codes for increased storage capacity in multilevel memory devices
US8966352B2 (en) 2007-11-21 2015-02-24 Micron Technology, Inc. Memory controller supporting rate-compatible punctured codes and supporting block codes
US9030902B2 (en) 2011-05-12 2015-05-12 Micron Technology, Inc. Programming memory cells

Families Citing this family (259)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8055979B2 (en) * 2006-01-20 2011-11-08 Marvell World Trade Ltd. Flash memory with coding and signal processing
US8848442B2 (en) * 2006-03-06 2014-09-30 Sandisk Il Ltd. Multi-bit-per-cell flash memory device with non-bijective mapping
US7388781B2 (en) * 2006-03-06 2008-06-17 Sandisk Il Ltd. Multi-bit-per-cell flash memory device with non-bijective mapping
US8645793B2 (en) 2008-06-03 2014-02-04 Marvell International Ltd. Statistical tracking for flash memory
CN103280239B (en) 2006-05-12 2016-04-06 苹果公司 Distortion estimation in memory device and elimination
US8239735B2 (en) * 2006-05-12 2012-08-07 Apple Inc. Memory Device with adaptive capacity
US20070266296A1 (en) * 2006-05-15 2007-11-15 Conley Kevin M Nonvolatile Memory with Convolutional Coding
US7840875B2 (en) * 2006-05-15 2010-11-23 Sandisk Corporation Convolutional coding methods for nonvolatile memory
US7818653B2 (en) 2006-09-28 2010-10-19 Sandisk Corporation Methods of soft-input soft-output decoding for nonvolatile memory
US7805663B2 (en) * 2006-09-28 2010-09-28 Sandisk Corporation Methods of adapting operation of nonvolatile memory
US7904783B2 (en) * 2006-09-28 2011-03-08 Sandisk Corporation Soft-input soft-output decoder for nonvolatile memory
US7904780B2 (en) * 2006-11-03 2011-03-08 Sandisk Corporation Methods of modulating error correction coding
US8001441B2 (en) * 2006-11-03 2011-08-16 Sandisk Technologies Inc. Nonvolatile memory with modulated error correction coding
US7827450B1 (en) 2006-11-28 2010-11-02 Marvell International Ltd. Defect detection and handling for memory based on pilot cells
US8316206B2 (en) 2007-02-12 2012-11-20 Marvell World Trade Ltd. Pilot placement for non-volatile memory
US8595573B2 (en) 2006-12-03 2013-11-26 Apple Inc. Automatic defect management in memory devices
KR100785925B1 (en) * 2006-12-06 2007-12-17 삼성전자주식회사 Multi-level cell memory device using tcm
KR100822030B1 (en) * 2006-12-26 2008-04-15 삼성전자주식회사 Multi-level cell memory device using high rate code
US8583981B2 (en) * 2006-12-29 2013-11-12 Marvell World Trade Ltd. Concatenated codes for holographic storage
WO2008111058A2 (en) 2007-03-12 2008-09-18 Anobit Technologies Ltd. Adaptive estimation of memory cell read thresholds
US7904793B2 (en) * 2007-03-29 2011-03-08 Sandisk Corporation Method for decoding data in non-volatile storage using reliability metrics based on multiple reads
US7958427B1 (en) * 2007-03-30 2011-06-07 Link—A—Media Devices Corporation ECC with out of order completion
US8281212B1 (en) * 2007-03-30 2012-10-02 Link—A—Media Devices Corporation Iterative ECC decoder with out of order completion
US7971127B2 (en) * 2007-03-31 2011-06-28 Sandisk Technologies Inc. Guided simulated annealing in non-volatile memory error correction control
US7975209B2 (en) * 2007-03-31 2011-07-05 Sandisk Technologies Inc. Non-volatile memory with guided simulated annealing error correction control
US7966546B2 (en) * 2007-03-31 2011-06-21 Sandisk Technologies Inc. Non-volatile memory with soft bit data transmission for error correction control
US7966550B2 (en) * 2007-03-31 2011-06-21 Sandisk Technologies Inc. Soft bit data transmission for error correction control in non-volatile memory
US7808834B1 (en) 2007-04-13 2010-10-05 Marvell International Ltd. Incremental memory refresh
US8234545B2 (en) 2007-05-12 2012-07-31 Apple Inc. Data storage with incremental redundancy
WO2008139441A2 (en) 2007-05-12 2008-11-20 Anobit Technologies Ltd. Memory device with internal signal processing unit
US8117520B2 (en) * 2007-06-15 2012-02-14 Micron Technology, Inc. Error detection for multi-bit memory
US8051358B2 (en) * 2007-07-06 2011-11-01 Micron Technology, Inc. Error recovery storage along a nand-flash string
US8065583B2 (en) * 2007-07-06 2011-11-22 Micron Technology, Inc. Data storage with an outer block code and a stream-based inner code
KR101480383B1 (en) * 2007-07-25 2015-01-09 삼성전자주식회사 Apparatus for code encoding
US8259497B2 (en) 2007-08-06 2012-09-04 Apple Inc. Programming schemes for multi-level analog memory cells
US8386879B2 (en) * 2007-08-23 2013-02-26 Nec Laboratories America, Inc. GLDPC encoding with Reed-Muller component codes for optical communications
US8031526B1 (en) 2007-08-23 2011-10-04 Marvell International Ltd. Write pre-compensation for nonvolatile memory
US8189381B1 (en) 2007-08-28 2012-05-29 Marvell International Ltd. System and method for reading flash memory cells
US8085605B2 (en) 2007-08-29 2011-12-27 Marvell World Trade Ltd. Sequence detection for flash memory with inter-cell interference
US8300478B2 (en) 2007-09-19 2012-10-30 Apple Inc. Reducing distortion using joint storage
US8174905B2 (en) 2007-09-19 2012-05-08 Anobit Technologies Ltd. Programming orders for reducing distortion in arrays of multi-level analog memory cells
WO2009095902A2 (en) 2008-01-31 2009-08-06 Densbits Technologies Ltd. Systems and methods for handling immediate data errors in flash memory
WO2009037697A2 (en) 2007-09-20 2009-03-26 Densbits Technologies Ltd. Improved systems and methods for determining logical values of coupled flash memory cells
US8527819B2 (en) 2007-10-19 2013-09-03 Apple Inc. Data storage in analog memory cell arrays having erase failures
US8694715B2 (en) 2007-10-22 2014-04-08 Densbits Technologies Ltd. Methods for adaptively programming flash memory devices and flash memory systems incorporating same
WO2009053961A2 (en) * 2007-10-25 2009-04-30 Densbits Technologies Ltd. Systems and methods for multiple coding rates in flash devices
KR101509836B1 (en) 2007-11-13 2015-04-06 애플 인크. Optimized selection of memory units in multi-unit memory devices
US8046542B2 (en) 2007-11-21 2011-10-25 Micron Technology, Inc. Fault-tolerant non-volatile integrated circuit memory
US8499229B2 (en) * 2007-11-21 2013-07-30 Micro Technology, Inc. Method and apparatus for reading data from flash memory
US8225181B2 (en) * 2007-11-30 2012-07-17 Apple Inc. Efficient re-read operations from memory devices
WO2009072105A2 (en) 2007-12-05 2009-06-11 Densbits Technologies Ltd. A low power chien-search based bch/rs decoding system for flash memory, mobile communications devices and other applications
WO2009072103A2 (en) 2007-12-05 2009-06-11 Densbits Technologies Ltd. Flash memory apparatus and methods using a plurality of decoding stages including optional use of concatenated bch codes and/or designation of 'first below' cells
US8453022B2 (en) 2007-12-05 2013-05-28 Densbits Technologies Ltd. Apparatus and methods for generating row-specific reading thresholds in flash memory
US8209588B2 (en) * 2007-12-12 2012-06-26 Anobit Technologies Ltd. Efficient interference cancellation in analog memory cell arrays
US8359516B2 (en) * 2007-12-12 2013-01-22 Densbits Technologies Ltd. Systems and methods for error correction and decoding on multi-level physical media
WO2009074979A2 (en) 2007-12-12 2009-06-18 Densbits Technologies Ltd. Chien-search system employing a clock-gating scheme to save power for error correction decoder and other applications
US8456905B2 (en) 2007-12-16 2013-06-04 Apple Inc. Efficient data storage in multi-plane memory devices
WO2009078006A2 (en) 2007-12-18 2009-06-25 Densbits Technologies Ltd. Apparatus for coding at a plurality of rates in multi-level flash memory systems, and methods useful in conjunction therewith
US8230300B2 (en) 2008-03-07 2012-07-24 Apple Inc. Efficient readout from analog memory cells using data compression
US8179719B1 (en) 2008-03-10 2012-05-15 Marvell International Ltd. Systems and methods for improving error distributions in multi-level cell memory systems
KR20090097673A (en) * 2008-03-12 2009-09-16 삼성전자주식회사 Apparatus for detecting memory data based on soft decision value
US8400858B2 (en) 2008-03-18 2013-03-19 Apple Inc. Memory device with reduced sense time readout
US8493783B2 (en) 2008-03-18 2013-07-23 Apple Inc. Memory device readout using multiple sense times
US8972472B2 (en) 2008-03-25 2015-03-03 Densbits Technologies Ltd. Apparatus and methods for hardware-efficient unbiased rounding
US8533563B2 (en) * 2008-03-31 2013-09-10 Qimonda Ag Memory read-out
US8086940B2 (en) * 2008-04-28 2011-12-27 Newport Media, Inc. Iterative decoding between turbo and RS decoders for improving bit error rate and packet error rate
US8090999B2 (en) * 2008-06-10 2012-01-03 Micron Technology, Inc. Memory media characterization for development of signal processors
US7995388B1 (en) 2008-08-05 2011-08-09 Anobit Technologies Ltd. Data storage using modified voltages
US8332725B2 (en) 2008-08-20 2012-12-11 Densbits Technologies Ltd. Reprogramming non volatile memory portions
US8949684B1 (en) 2008-09-02 2015-02-03 Apple Inc. Segmented data storage
US8482978B1 (en) 2008-09-14 2013-07-09 Apple Inc. Estimation of memory cell read thresholds by sampling inside programming level distribution intervals
US9378835B2 (en) * 2008-09-30 2016-06-28 Seagate Technology Llc Methods and apparatus for soft data generation for memory devices based using reference cells
US8239734B1 (en) * 2008-10-15 2012-08-07 Apple Inc. Efficient data storage in storage device arrays
US8321772B1 (en) 2008-10-20 2012-11-27 Link—A—Media Devices Corporation SOVA sharing during LDPC global iteration
US8261159B1 (en) 2008-10-30 2012-09-04 Apple, Inc. Data scrambling schemes for memory devices
US8208304B2 (en) 2008-11-16 2012-06-26 Anobit Technologies Ltd. Storage at M bits/cell density in N bits/cell analog memory cell devices, M>N
US8291297B2 (en) * 2008-12-18 2012-10-16 Intel Corporation Data error recovery in non-volatile memory
US9449719B2 (en) * 2008-12-19 2016-09-20 Seagate Technology Llc Solid-state storage device including a high resolution analog-to-digital converter
US8174857B1 (en) 2008-12-31 2012-05-08 Anobit Technologies Ltd. Efficient readout schemes for analog memory cell devices using multiple read threshold sets
US8248831B2 (en) 2008-12-31 2012-08-21 Apple Inc. Rejuvenation of analog memory cells
US8924661B1 (en) 2009-01-18 2014-12-30 Apple Inc. Memory system including a controller and processors associated with memory devices
KR101519626B1 (en) * 2009-02-27 2015-05-14 삼성전자주식회사 Semiconductor memory device and data processing method thereof
US8228701B2 (en) * 2009-03-01 2012-07-24 Apple Inc. Selective activation of programming schemes in analog memory cell arrays
US8259506B1 (en) 2009-03-25 2012-09-04 Apple Inc. Database of memory read thresholds
US8832354B2 (en) 2009-03-25 2014-09-09 Apple Inc. Use of host system resources by memory controller
US8418021B2 (en) 2009-03-27 2013-04-09 Mediatek Inc. Storage controller with encoding/decoding circuit programmable to support different ECC requirements and related method thereof
US8819385B2 (en) 2009-04-06 2014-08-26 Densbits Technologies Ltd. Device and method for managing a flash memory
US8458574B2 (en) 2009-04-06 2013-06-04 Densbits Technologies Ltd. Compact chien-search based decoding apparatus and method
US8238157B1 (en) 2009-04-12 2012-08-07 Apple Inc. Selective re-programming of analog memory cells
US8370709B2 (en) * 2009-04-16 2013-02-05 Micron Technology, Inc. Multiple-level memory cells and error detection
US8560918B1 (en) * 2009-04-21 2013-10-15 Marvell International Ltd. Method and apparatus for dynamically selecting an error correction code to be applied to data in a communication system
US8566510B2 (en) 2009-05-12 2013-10-22 Densbits Technologies Ltd. Systems and method for flash memory management
US8479080B1 (en) 2009-07-12 2013-07-02 Apple Inc. Adaptive over-provisioning in memory systems
EP2299362A3 (en) * 2009-08-18 2011-05-04 ViaSat, Inc. Forward error correction for memories
US8995197B1 (en) 2009-08-26 2015-03-31 Densbits Technologies Ltd. System and methods for dynamic erase and program control for flash memory device memories
US8305812B2 (en) 2009-08-26 2012-11-06 Densbits Technologies Ltd. Flash memory module and method for programming a page of flash memory cells
US8868821B2 (en) 2009-08-26 2014-10-21 Densbits Technologies Ltd. Systems and methods for pre-equalization and code design for a flash memory
US9330767B1 (en) 2009-08-26 2016-05-03 Avago Technologies General Ip (Singapore) Pte. Ltd. Flash memory module and method for programming a page of flash memory cells
US8495465B1 (en) 2009-10-15 2013-07-23 Apple Inc. Error correction coding over multiple memory pages
US8730729B2 (en) 2009-10-15 2014-05-20 Densbits Technologies Ltd. Systems and methods for averaging error rates in non-volatile devices and storage systems
US8724387B2 (en) 2009-10-22 2014-05-13 Densbits Technologies Ltd. Method, system, and computer readable medium for reading and programming flash memory cells using multiple bias voltages
US8626988B2 (en) 2009-11-19 2014-01-07 Densbits Technologies Ltd. System and method for uncoded bit error rate equalization via interleaving
US8677054B1 (en) 2009-12-16 2014-03-18 Apple Inc. Memory management schemes for non-volatile memory devices
US9037777B2 (en) 2009-12-22 2015-05-19 Densbits Technologies Ltd. Device, system, and method for reducing program/read disturb in flash arrays
US8607124B2 (en) 2009-12-24 2013-12-10 Densbits Technologies Ltd. System and method for setting a flash memory cell read threshold
CN103222005B (en) 2009-12-31 2016-08-24 美光科技公司 Method for phase change memory array
US8694814B1 (en) 2010-01-10 2014-04-08 Apple Inc. Reuse of host hibernation storage space by memory controller
US8572311B1 (en) 2010-01-11 2013-10-29 Apple Inc. Redundant data storage in multi-die memory systems
KR101678404B1 (en) * 2010-02-25 2016-11-23 삼성전자주식회사 MEMORY SYSTEM USING A PRIORI PROBABILITY Information AND DATA PROCESSING METHOD THEREOF
US8700970B2 (en) 2010-02-28 2014-04-15 Densbits Technologies Ltd. System and method for multi-dimensional decoding
US9104610B2 (en) 2010-04-06 2015-08-11 Densbits Technologies Ltd. Method, system and medium for analog encryption in a flash memory
US8527840B2 (en) 2010-04-06 2013-09-03 Densbits Technologies Ltd. System and method for restoring damaged data programmed on a flash device
US8745317B2 (en) 2010-04-07 2014-06-03 Densbits Technologies Ltd. System and method for storing information in a multi-level cell memory
US9021177B2 (en) 2010-04-29 2015-04-28 Densbits Technologies Ltd. System and method for allocating and using spare blocks in a flash memory
US8694853B1 (en) 2010-05-04 2014-04-08 Apple Inc. Read commands for reading interfering memory cells
US8386895B2 (en) * 2010-05-19 2013-02-26 Micron Technology, Inc. Enhanced multilevel memory
US8572457B2 (en) * 2010-05-28 2013-10-29 Seagate Technology Llc Outer code protection for solid state memory devices
US8489979B2 (en) * 2010-05-28 2013-07-16 Seagate Technology Llc Methods and devices to reduce outer code failure rate variability
US8656263B2 (en) * 2010-05-28 2014-02-18 Stec, Inc. Trellis-coded modulation in a multi-level cell flash memory device
US11336303B2 (en) * 2010-06-04 2022-05-17 Micron Technology, Inc. Advanced bitwise operations and apparatus in a multi-level system with nonvolatile memory
US8615703B2 (en) 2010-06-04 2013-12-24 Micron Technology, Inc. Advanced bitwise operations and apparatus in a multi-level system with nonvolatile memory
US8572423B1 (en) 2010-06-22 2013-10-29 Apple Inc. Reducing peak current in memory systems
US8539311B2 (en) 2010-07-01 2013-09-17 Densbits Technologies Ltd. System and method for data recovery in multi-level cell memories
US8510639B2 (en) 2010-07-01 2013-08-13 Densbits Technologies Ltd. System and method for multi-dimensional encoding and decoding
US20120008414A1 (en) 2010-07-06 2012-01-12 Michael Katz Systems and methods for storing, retrieving, and adjusting read thresholds in flash memory storage system
US8595591B1 (en) 2010-07-11 2013-11-26 Apple Inc. Interference-aware assignment of programming levels in analog memory cells
US9104580B1 (en) 2010-07-27 2015-08-11 Apple Inc. Cache memory for hybrid disk drives
US8767459B1 (en) 2010-07-31 2014-07-01 Apple Inc. Data storage in analog memory cells across word lines using a non-integer number of bits per cell
US8856475B1 (en) 2010-08-01 2014-10-07 Apple Inc. Efficient selection of memory blocks for compaction
US8493781B1 (en) 2010-08-12 2013-07-23 Apple Inc. Interference mitigation using individual word line erasure operations
WO2012020278A1 (en) * 2010-08-13 2012-02-16 Sandisk Il Ltd. Data coding using divisions of memory cell states
US8694854B1 (en) 2010-08-17 2014-04-08 Apple Inc. Read threshold setting based on soft readout statistics
US8595585B2 (en) * 2010-08-20 2013-11-26 Nec Laboratories America, Inc. Reverse concatenated encoding and decoding
US8964464B2 (en) 2010-08-24 2015-02-24 Densbits Technologies Ltd. System and method for accelerated sampling
US9116826B2 (en) * 2010-09-10 2015-08-25 Trellis Phase Communications, Lp Encoding and decoding using constrained interleaving
US8508995B2 (en) 2010-09-15 2013-08-13 Densbits Technologies Ltd. System and method for adjusting read voltage thresholds in memories
US9021181B1 (en) 2010-09-27 2015-04-28 Apple Inc. Memory management for unifying memory cell conditions by using maximum time intervals
US8892809B2 (en) 2010-10-25 2014-11-18 Marvell World Trade Ltd. Data compression and encoding in a memory system
US9063878B2 (en) 2010-11-03 2015-06-23 Densbits Technologies Ltd. Method, system and computer readable medium for copy back
KR101250672B1 (en) * 2010-12-03 2013-04-09 한국과학기술원 Trellis coded modulation method for reducing inter-cell interference of flash memory device, trellis coded modulation circuit, error correct circuit and flash memory device using same
US8850100B2 (en) 2010-12-07 2014-09-30 Densbits Technologies Ltd. Interleaving codeword portions between multiple planes and/or dies of a flash memory device
KR20120082230A (en) * 2011-01-13 2012-07-23 에스케이하이닉스 주식회사 Semiconductor apparatus and semiconductor system having random code generation circuit and method of programming data
US10079068B2 (en) 2011-02-23 2018-09-18 Avago Technologies General Ip (Singapore) Pte. Ltd. Devices and method for wear estimation based memory management
US8693258B2 (en) 2011-03-17 2014-04-08 Densbits Technologies Ltd. Obtaining soft information using a hard interface
US8621330B2 (en) * 2011-03-21 2013-12-31 Microsoft Corporation High rate locally decodable codes
US8990665B1 (en) 2011-04-06 2015-03-24 Densbits Technologies Ltd. System, method and computer program product for joint search of a read threshold and soft decoding
US9110785B1 (en) 2011-05-12 2015-08-18 Densbits Technologies Ltd. Ordered merge of data sectors that belong to memory space portions
US9501392B1 (en) 2011-05-12 2016-11-22 Avago Technologies General Ip (Singapore) Pte. Ltd. Management of a non-volatile memory module
US9195592B1 (en) 2011-05-12 2015-11-24 Densbits Technologies Ltd. Advanced management of a non-volatile memory
US9396106B2 (en) 2011-05-12 2016-07-19 Avago Technologies General Ip (Singapore) Pte. Ltd. Advanced management of a non-volatile memory
US8996790B1 (en) 2011-05-12 2015-03-31 Densbits Technologies Ltd. System and method for flash memory management
US9372792B1 (en) 2011-05-12 2016-06-21 Avago Technologies General Ip (Singapore) Pte. Ltd. Advanced management of a non-volatile memory
US8667211B2 (en) 2011-06-01 2014-03-04 Densbits Technologies Ltd. System and method for managing a non-volatile memory
US9130596B2 (en) * 2011-06-29 2015-09-08 Seagate Technology Llc Multiuse data channel
US8588003B1 (en) 2011-08-01 2013-11-19 Densbits Technologies Ltd. System, method and computer program product for programming and for recovering from a power failure
US8553468B2 (en) 2011-09-21 2013-10-08 Densbits Technologies Ltd. System and method for managing erase operations in a non-volatile memory
US8456919B1 (en) * 2011-11-10 2013-06-04 Sandisk Technologies Inc. Method and apparatus to provide data including hard bit data and soft bit data to a rank modulation decoder
US8996788B2 (en) 2012-02-09 2015-03-31 Densbits Technologies Ltd. Configurable flash interface
US8947941B2 (en) 2012-02-09 2015-02-03 Densbits Technologies Ltd. State responsive operations relating to flash memory cells
US9026887B2 (en) 2012-03-15 2015-05-05 Micron Technology, Inc. Physical page, logical page, and codeword correspondence
US8996793B1 (en) 2012-04-24 2015-03-31 Densbits Technologies Ltd. System, method and computer readable medium for generating soft information
US9021333B1 (en) 2012-05-22 2015-04-28 Pmc-Sierra, Inc. Systems and methods for recovering data from failed portions of a flash drive
US9183085B1 (en) 2012-05-22 2015-11-10 Pmc-Sierra, Inc. Systems and methods for adaptively selecting from among a plurality of error correction coding schemes in a flash drive for robustness and low latency
US8788910B1 (en) 2012-05-22 2014-07-22 Pmc-Sierra, Inc. Systems and methods for low latency, high reliability error correction in a flash drive
US9135106B2 (en) * 2012-05-22 2015-09-15 Hgst Technologies Santa Ana, Inc. Read level adjustment using soft information
US8972824B1 (en) 2012-05-22 2015-03-03 Pmc-Sierra, Inc. Systems and methods for transparently varying error correction code strength in a flash drive
US8793556B1 (en) 2012-05-22 2014-07-29 Pmc-Sierra, Inc. Systems and methods for reclaiming flash blocks of a flash drive
US9047214B1 (en) 2012-05-22 2015-06-02 Pmc-Sierra, Inc. System and method for tolerating a failed page in a flash device
US9021337B1 (en) 2012-05-22 2015-04-28 Pmc-Sierra, Inc. Systems and methods for adaptively selecting among different error correction coding schemes in a flash drive
US8996957B1 (en) 2012-05-22 2015-03-31 Pmc-Sierra, Inc. Systems and methods for initializing regions of a flash drive having diverse error correction coding (ECC) schemes
KR101991911B1 (en) * 2012-05-22 2019-06-24 삼성전자주식회사 Code modulation incoder and decoder, memory controller including them, and flash memory system
US9021336B1 (en) 2012-05-22 2015-04-28 Pmc-Sierra, Inc. Systems and methods for redundantly storing error correction codes in a flash drive with secondary parity information spread out across each page of a group of pages
US9176812B1 (en) 2012-05-22 2015-11-03 Pmc-Sierra, Inc. Systems and methods for storing data in page stripes of a flash drive
US8838937B1 (en) 2012-05-23 2014-09-16 Densbits Technologies Ltd. Methods, systems and computer readable medium for writing and reading data
US8879325B1 (en) 2012-05-30 2014-11-04 Densbits Technologies Ltd. System, method and computer program product for processing read threshold information and for reading a flash memory module
US9413490B2 (en) * 2012-06-27 2016-08-09 Broadcom Corporation Set-partitioned coded modulation with multiple encodings
US9921954B1 (en) 2012-08-27 2018-03-20 Avago Technologies General Ip (Singapore) Pte. Ltd. Method and system for split flash memory management between host and storage controller
US9577673B2 (en) 2012-11-08 2017-02-21 Micron Technology, Inc. Error correction methods and apparatuses using first and second decoders
US9368225B1 (en) 2012-11-21 2016-06-14 Avago Technologies General Ip (Singapore) Pte. Ltd. Determining read thresholds based upon read error direction statistics
US10085017B2 (en) * 2012-11-29 2018-09-25 Advanced Micro Devices, Inc. Bandwidth saving architecture for scalable video coding spatial mode
KR101545512B1 (en) * 2012-12-26 2015-08-24 성균관대학교산학협력단 Semiconductor memory apparatus, verify read method and system
US9069659B1 (en) 2013-01-03 2015-06-30 Densbits Technologies Ltd. Read threshold determination using reference read threshold
US8995302B1 (en) 2013-01-16 2015-03-31 Pmc-Sierra Us, Inc. Method and apparatus for translated routing in an interconnect switch
US9092353B1 (en) 2013-01-29 2015-07-28 Pmc-Sierra Us, Inc. Apparatus and method based on LDPC codes for adjusting a correctable raw bit error rate limit in a memory system
WO2014127169A1 (en) * 2013-02-15 2014-08-21 Cortina Systems, Inc. Apparatus and method for communicating data over a communication channel
US9813080B1 (en) 2013-03-05 2017-11-07 Microsemi Solutions (U.S.), Inc. Layer specific LDPC decoder
US8990661B1 (en) 2013-03-05 2015-03-24 Pmc-Sierra Us, Inc. Layer specific attenuation factor LDPC decoder
US10230396B1 (en) 2013-03-05 2019-03-12 Microsemi Solutions (Us), Inc. Method and apparatus for layer-specific LDPC decoding
US9053012B1 (en) 2013-03-15 2015-06-09 Pmc-Sierra, Inc. Systems and methods for storing data for solid-state memory
US9009565B1 (en) 2013-03-15 2015-04-14 Pmc-Sierra, Inc. Systems and methods for mapping for solid-state memory
US9026867B1 (en) 2013-03-15 2015-05-05 Pmc-Sierra, Inc. Systems and methods for adapting to changing characteristics of multi-level cells in solid-state memory
US9081701B1 (en) 2013-03-15 2015-07-14 Pmc-Sierra, Inc. Systems and methods for decoding data for solid-state memory
US9450610B1 (en) 2013-03-15 2016-09-20 Microsemi Storage Solutions (Us), Inc. High quality log likelihood ratios determined using two-index look-up table
US9208018B1 (en) 2013-03-15 2015-12-08 Pmc-Sierra, Inc. Systems and methods for reclaiming memory for solid-state memory
US9136876B1 (en) 2013-06-13 2015-09-15 Densbits Technologies Ltd. Size limited multi-dimensional decoding
US9112653B2 (en) * 2013-06-19 2015-08-18 Mitsubishi Electric Research Laboratories, Inc. Method and system for modulating optical signals as high-dimensional lattice constellation points to increase tolerance to noise
US9313561B1 (en) * 2013-07-11 2016-04-12 Inphi Corporation Integrated driver redundancy for a silicon photonics device
US9444580B2 (en) 2013-08-06 2016-09-13 OptCTS, Inc. Optimized data transfer utilizing optimized code table signaling
US10523490B2 (en) 2013-08-06 2019-12-31 Agilepq, Inc. Authentication of a subscribed code table user utilizing optimized code table signaling
US9455799B2 (en) 2013-08-06 2016-09-27 OptCTS, Inc. Dynamic control of quality of service (QOS) using derived QOS measures
US9413491B1 (en) 2013-10-08 2016-08-09 Avago Technologies General Ip (Singapore) Pte. Ltd. System and method for multiple dimension decoding and encoding a message
US9397706B1 (en) 2013-10-09 2016-07-19 Avago Technologies General Ip (Singapore) Pte. Ltd. System and method for irregular multiple dimension decoding and encoding
US9348694B1 (en) 2013-10-09 2016-05-24 Avago Technologies General Ip (Singapore) Pte. Ltd. Detecting and managing bad columns
US9786388B1 (en) 2013-10-09 2017-10-10 Avago Technologies General Ip (Singapore) Pte. Ltd. Detecting and managing bad columns
US9559725B1 (en) 2013-10-23 2017-01-31 Seagate Technology Llc Multi-strength reed-solomon outer code protection
US9230655B2 (en) 2013-12-20 2016-01-05 Apple Inc. Data storage management in analog memory cells using a non-integer number of bits per cell
US9645763B2 (en) 2014-01-13 2017-05-09 Seagate Technology Llc Framework for balancing robustness and latency during collection of statistics from soft reads
US9536612B1 (en) 2014-01-23 2017-01-03 Avago Technologies General Ip (Singapore) Pte. Ltd Digital signaling processing for three dimensional flash memory arrays
US10120792B1 (en) 2014-01-29 2018-11-06 Avago Technologies General Ip (Singapore) Pte. Ltd. Programming an embedded flash storage device
US9685242B2 (en) * 2014-03-11 2017-06-20 Kabushiki Kaisha Toshiba Memory system
US9319178B2 (en) 2014-03-14 2016-04-19 Qualcomm Incorporated Method for using error correction codes with N factorial or CCI extension
US9542262B1 (en) 2014-05-29 2017-01-10 Avago Technologies General Ip (Singapore) Pte. Ltd. Error correction
TWI530959B (en) 2014-06-17 2016-04-21 慧榮科技股份有限公司 Method for controlling a memory apparatus, and associated memory apparatus thereof and associated controller thereof
US9892033B1 (en) 2014-06-24 2018-02-13 Avago Technologies General Ip (Singapore) Pte. Ltd. Management of memory units
GB2527604A (en) * 2014-06-27 2015-12-30 Ibm Data encoding in solid-state storage devices
US10056919B2 (en) 2014-07-02 2018-08-21 Agilepq, Inc. Data recovery utilizing optimized code table signaling
US9584159B1 (en) 2014-07-03 2017-02-28 Avago Technologies General Ip (Singapore) Pte. Ltd. Interleaved encoding
US9972393B1 (en) 2014-07-03 2018-05-15 Avago Technologies General Ip (Singapore) Pte. Ltd. Accelerating programming of a flash memory module
US9417804B2 (en) 2014-07-07 2016-08-16 Microsemi Storage Solutions (Us), Inc. System and method for memory block pool wear leveling
US9449702B1 (en) 2014-07-08 2016-09-20 Avago Technologies General Ip (Singapore) Pte. Ltd. Power management
WO2016051599A1 (en) * 2014-10-03 2016-04-07 株式会社日立製作所 Memory controller and data control method
US9524211B1 (en) 2014-11-18 2016-12-20 Avago Technologies General Ip (Singapore) Pte. Ltd. Codeword management
US10404409B2 (en) * 2014-12-11 2019-09-03 Kabushiki Kaisha Toshiba Reconfigurable encoding arrays for reduced outage probability sensor networks
US9613664B2 (en) * 2015-01-20 2017-04-04 Samsung Electronics Co., Ltd. Method of operating memory device including multi-level memory cells
US10305515B1 (en) 2015-02-02 2019-05-28 Avago Technologies International Sales Pte. Limited System and method for encoding using multiple linear feedback shift registers
US10332613B1 (en) 2015-05-18 2019-06-25 Microsemi Solutions (Us), Inc. Nonvolatile memory system with retention monitor
US10628255B1 (en) 2015-06-11 2020-04-21 Avago Technologies International Sales Pte. Limited Multi-dimensional decoding
US9851921B1 (en) 2015-07-05 2017-12-26 Avago Technologies General Ip (Singapore) Pte. Ltd. Flash memory chip processing
US9799405B1 (en) 2015-07-29 2017-10-24 Ip Gem Group, Llc Nonvolatile memory system with read circuit for performing reads using threshold voltage shift read instruction
US9577854B1 (en) * 2015-08-20 2017-02-21 Micron Technology, Inc. Apparatuses and methods for asymmetric bi-directional signaling incorporating multi-level encoding
KR20170068681A (en) * 2015-12-09 2017-06-20 에스케이하이닉스 주식회사 Data storage device and operating method thereof
US9886214B2 (en) 2015-12-11 2018-02-06 Ip Gem Group, Llc Nonvolatile memory system with erase suspend circuit and method for erase suspend management
US9892794B2 (en) 2016-01-04 2018-02-13 Ip Gem Group, Llc Method and apparatus with program suspend using test mode
US9899092B2 (en) 2016-01-27 2018-02-20 Ip Gem Group, Llc Nonvolatile memory system with program step manager and method for program step management
US9954558B1 (en) 2016-03-03 2018-04-24 Avago Technologies General Ip (Singapore) Pte. Ltd. Fast decoding of data stored in a flash memory
JP2019518397A (en) 2016-06-06 2019-06-27 アジャイルピーキュー， インコーポレイテッド Data conversion system and method
US10291263B2 (en) 2016-07-28 2019-05-14 Ip Gem Group, Llc Auto-learning log likelihood ratio
US10283215B2 (en) 2016-07-28 2019-05-07 Ip Gem Group, Llc Nonvolatile memory system with background reference positioning and local reference positioning
US10236915B2 (en) 2016-07-29 2019-03-19 Microsemi Solutions (U.S.), Inc. Variable T BCH encoding
US10175890B2 (en) 2016-12-22 2019-01-08 Western Digital Technologies, Inc. Non-binary ECCs for low latency read, fractional bits per cell of NAND flash
US10263639B2 (en) 2017-02-07 2019-04-16 Alibaba Group Holding Limited Managing soft information in high-capacity solid state drive
US10164817B2 (en) 2017-03-21 2018-12-25 Micron Technology, Inc. Methods and apparatuses for signal translation in a buffered memory
CN107705817B (en) * 2017-09-22 2020-09-08 山东存储之翼电子科技有限公司 Decoding method and device using flash memory channel characteristics and data storage system
US10725913B2 (en) 2017-10-02 2020-07-28 Micron Technology, Inc. Variable modulation scheme for memory device access or operation
US11403241B2 (en) 2017-10-02 2022-08-02 Micron Technology, Inc. Communicating data with stacked memory dies
US10355893B2 (en) 2017-10-02 2019-07-16 Micron Technology, Inc. Multiplexing distinct signals on a single pin of a memory device
US10446198B2 (en) 2017-10-02 2019-10-15 Micron Technology, Inc. Multiple concurrent modulation schemes in a memory system
US10304550B1 (en) 2017-11-29 2019-05-28 Sandisk Technologies Llc Sense amplifier with negative threshold sensing for non-volatile memory
US10411808B2 (en) * 2018-01-05 2019-09-10 Zte Corporation Probabilistically shaped multi-level pulse modulation with gray code mapping
DE102018112215B3 (en) * 2018-04-30 2019-07-25 Basler Ag Quantizer determination, computer readable medium, and apparatus implementing at least two quantizers
US10910044B2 (en) 2018-09-28 2021-02-02 Sandisk Technologies Llc State coding for fractional bits-per-cell memory
US10643695B1 (en) 2019-01-10 2020-05-05 Sandisk Technologies Llc Concurrent multi-state program verify for non-volatile memory
US11024392B1 (en) 2019-12-23 2021-06-01 Sandisk Technologies Llc Sense amplifier for bidirectional sensing of memory cells of a non-volatile memory
US11231870B1 (en) 2020-08-11 2022-01-25 Micron Technology, Inc. Memory sub-system retirement determination
US11556416B2 (en) 2021-05-05 2023-01-17 Apple Inc. Controlling memory readout reliability and throughput by adjusting distance between read thresholds
US11847342B2 (en) 2021-07-28 2023-12-19 Apple Inc. Efficient transfer of hard data and confidence levels in reading a nonvolatile memory
US11960776B2 (en) * 2022-06-02 2024-04-16 Micron Technology, Inc. Data protection for stacks of memory dice
US12093124B2 (en) * 2022-09-29 2024-09-17 Advanced Micro Devices, Inc. Multi-level signal reception
TWI819876B (en) * 2022-11-02 2023-10-21 群聯電子股份有限公司 Memory management method, memory storage device and memory control circuit unit

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010025358A1 (en) 2000-01-28 2001-09-27 Eidson Donald Brian Iterative decoder employing multiple external code error checks to lower the error floor
US20020038440A1 (en) 1998-04-20 2002-03-28 Moti Barkan Digital data representation for multi-bit data storage and transmission

Family Cites Families (59)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6011360B2 (en) 1981-12-15 1985-03-25 ケイディディ株式会社 Audio encoding method
US4675863A (en) * 1985-03-20 1987-06-23 International Mobile Machines Corp. Subscriber RF telephone system for providing multiple speech and/or data signals simultaneously over either a single or a plurality of RF channels
NL9100218A (en) 1991-02-07 1992-09-01 Philips Nv ENCODE / DECODE SWITCH AND DIGITAL VIDEO SYSTEM FITTED WITH THE SWITCH.
US6222762B1 (en) * 1992-01-14 2001-04-24 Sandisk Corporation Multi-state memory
US5365530A (en) 1992-05-12 1994-11-15 Mitsubishi Denki Kabushiki Kaisha Error-correction encoding and decoding system
JP3999822B2 (en) * 1993-12-28 2007-10-31 株式会社東芝 Storage system
JPH09251427A (en) 1996-03-18 1997-09-22 Nec Home Electron Ltd Code error correction device for flash memory and its method
US5969985A (en) * 1996-03-18 1999-10-19 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device
JPH09284348A (en) * 1996-04-15 1997-10-31 Ricoh Co Ltd Decoding method
JP3200012B2 (en) * 1996-04-19 2001-08-20 株式会社東芝 Storage system
US5815439A (en) 1996-04-30 1998-09-29 Agate Semiconductor, Inc. Stabilization circuits and techniques for storage and retrieval of single or multiple digital bits per memory cell
JPH1055687A (en) * 1996-08-09 1998-02-24 Sony Corp Non-volatile semiconductor memory
DE59701778D1 (en) 1996-08-30 2000-06-29 Siemens Ag ERROR DETECTION IN A STORAGE SYSTEM
KR100219842B1 (en) * 1997-03-12 1999-09-01 서평원 Mobile telephone system
KR100246184B1 (en) 1997-07-02 2000-03-15 김영환 Flash memory managing method using reed-solomon error correction code
JPH1173797A (en) * 1997-08-27 1999-03-16 Sony Corp Storage device
JPH11136139A (en) * 1997-11-04 1999-05-21 Hitachi Ltd Decoding method and device therefor, storage device, information device using it, memory chip, record code and optical communication system
JPH11143787A (en) * 1997-11-06 1999-05-28 Hitachi Ltd Recording and reproducing device
US6279133B1 (en) * 1997-12-31 2001-08-21 Kawasaki Steel Corporation Method and apparatus for significantly improving the reliability of multilevel memory architecture
JPH11213693A (en) * 1998-01-27 1999-08-06 Sony Corp Memory device
US7083108B2 (en) * 1998-07-10 2006-08-01 Silverbrook Research Pty Ltd Redundantly encoded data structure for encoding a surface
JP2000286719A (en) * 1999-03-31 2000-10-13 Mitsubishi Electric Corp Error correction system
JP4074029B2 (en) 1999-06-28 2008-04-09 株式会社東芝 Flash memory
US7404032B2 (en) * 2000-01-05 2008-07-22 Rambus Inc. Configurable width buffered module having switch elements
US7363422B2 (en) * 2000-01-05 2008-04-22 Rambus Inc. Configurable width buffered module
US7356639B2 (en) * 2000-01-05 2008-04-08 Rambus Inc. Configurable width buffered module having a bypass circuit
US7890846B2 (en) 2000-01-06 2011-02-15 Supertalent Electronics, Inc. Electronic data flash card with Reed Solomon error detection and correction capability
US6715116B2 (en) 2000-01-26 2004-03-30 Hewlett-Packard Company, L.P. Memory data verify operation
JP2001332982A (en) * 2000-05-18 2001-11-30 Mitsubishi Electric Corp Optical transmission system, fec multiplexer, fec demultiplexer and error correcting method
JP2002100192A (en) 2000-09-22 2002-04-05 Toshiba Corp Non-volatile semiconductor memory
US20040096007A1 (en) * 2000-10-16 2004-05-20 Volker Aue Method for generating soft bit information from gray coded signals
US20030126545A1 (en) * 2001-10-05 2003-07-03 Tan Alfred Keng Tiong Non-linear code-division multiple access technology with improved detection algorithms and error correction coding
JP3515519B2 (en) * 2000-12-28 2004-04-05 三洋電機株式会社 Data receiving device
US6724658B2 (en) * 2001-01-15 2004-04-20 Stmicroelectronics S.R.L. Method and circuit for generating reference voltages for reading a multilevel memory cell
EP1399819A2 (en) 2001-04-24 2004-03-24 Koninklijke Philips Electronics N.V. Improved error correction scheme for use in flash memory allowing bit alterability
JP3578736B2 (en) * 2001-08-07 2004-10-20 Ｎｅｃマイクロシステム株式会社 Branch metric calculation device and its calculation method
US7142612B2 (en) * 2001-11-16 2006-11-28 Rambus, Inc. Method and apparatus for multi-level signaling
KR100487417B1 (en) * 2001-12-13 2005-05-03 주식회사 하이닉스반도체 nonvolatile ferroelectric memory device and method for operating write and read of multiple-bit data thereof
EP1355234B1 (en) 2002-04-15 2016-06-29 Micron Technology, Inc. Use of an error correction circuit in program and erase verify procedures
US6751766B2 (en) * 2002-05-20 2004-06-15 Sandisk Corporation Increasing the effectiveness of error correction codes and operating multi-level memory systems by using information about the quality of the stored data
TW575806B (en) 2002-07-15 2004-02-11 Silicon Motion Tech Inc A method for enhancing flash memory error correction capability and providing data encryption in the same time
JP4086583B2 (en) * 2002-08-08 2008-05-14 シャープ株式会社 Nonvolatile semiconductor memory device and data write control method
US20040083334A1 (en) 2002-10-28 2004-04-29 Sandisk Corporation Method and apparatus for managing the integrity of data in non-volatile memory system
US7379505B2 (en) * 2003-02-13 2008-05-27 Broadcom Corporation Method and apparatus for performing trellis coded modulation of signals for transmission on a TDMA channel of a cable network
JP4188744B2 (en) * 2003-04-08 2008-11-26 株式会社ルネサステクノロジ Memory card
JP2005078721A (en) * 2003-09-01 2005-03-24 Nippon Telegr & Teleph Corp <Ntt> Error correcting method and memory circuit
US7012835B2 (en) 2003-10-03 2006-03-14 Sandisk Corporation Flash memory data correction and scrub techniques
KR100547146B1 (en) 2003-10-06 2006-01-26 삼성전자주식회사 Image processing apparatus and the method thereof
JP4056488B2 (en) * 2004-03-30 2008-03-05 エルピーダメモリ株式会社 Semiconductor device testing method and manufacturing method
US7057939B2 (en) * 2004-04-23 2006-06-06 Sandisk Corporation Non-volatile memory and control with improved partial page program capability
JP4135680B2 (en) * 2004-05-31 2008-08-20 ソニー株式会社 Semiconductor memory device and signal processing system
JP2006048783A (en) * 2004-08-02 2006-02-16 Renesas Technology Corp Nonvolatile memory and memory card
JP4614732B2 (en) 2004-10-22 2011-01-19 パナソニック株式会社 Decoding device
JP2006134536A (en) * 2004-11-09 2006-05-25 Matsushita Electric Ind Co Ltd Nonvolatile semiconductor memory and its read method
US7408804B2 (en) * 2005-03-31 2008-08-05 Sandisk Corporation Systems for soft programming non-volatile memory utilizing individual verification and additional soft programming of subsets of memory cells
US7457166B2 (en) * 2005-03-31 2008-11-25 Sandisk Corporation Erase voltage manipulation in non-volatile memory for controlled shifts in threshold voltage
KR100680473B1 (en) 2005-04-11 2007-02-08 주식회사 하이닉스반도체 Flash memory device with reduced access time
US7366022B2 (en) * 2005-10-27 2008-04-29 Sandisk Corporation Apparatus for programming of multi-state non-volatile memory using smart verify
US7535766B2 (en) * 2006-10-13 2009-05-19 Sandisk Corporation Systems for partitioned soft programming in non-volatile memory

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020038440A1 (en) 1998-04-20 2002-03-28 Moti Barkan Digital data representation for multi-bit data storage and transmission
US20010025358A1 (en) 2000-01-28 2001-09-27 Eidson Donald Brian Iterative decoder employing multiple external code error checks to lower the error floor

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP1987519A4

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8966352B2 (en) 2007-11-21 2015-02-24 Micron Technology, Inc. Memory controller supporting rate-compatible punctured codes and supporting block codes
TWI479506B (en) * 2007-11-21 2015-04-01 美光科技公司 Memory controller supporting rate-compatible punctured codes
US9442796B2 (en) 2007-11-21 2016-09-13 Micron Technology, Inc. Memory controller supporting rate-compatible punctured codes
US8370702B2 (en) 2009-06-10 2013-02-05 Micron Technology, Inc. Error correcting codes for increased storage capacity in multilevel memory devices
US8745463B2 (en) 2009-06-10 2014-06-03 Micron Technology, Inc. Error correcting codes for increased storage capacity in multilevel memory devices
US9030902B2 (en) 2011-05-12 2015-05-12 Micron Technology, Inc. Programming memory cells

Also Published As

Publication number Publication date
TW201126527A (en) 2011-08-01
US8677215B2 (en) 2014-03-18
TWI367492B (en) 2012-07-01
WO2007084749A3 (en) 2008-04-10
US8473812B2 (en) 2013-06-25
US20140201600A1 (en) 2014-07-17
US20070171730A1 (en) 2007-07-26
US20110060969A1 (en) 2011-03-10
EP1987519B1 (en) 2015-08-19
TWI455137B (en) 2014-10-01
KR101410434B1 (en) 2014-07-02
US20150058702A1 (en) 2015-02-26
JP2009524176A (en) 2009-06-25
US8856622B2 (en) 2014-10-07
EP1987519A4 (en) 2009-07-29
EP1987519A2 (en) 2008-11-05
TW200737213A (en) 2007-10-01
US9053051B2 (en) 2015-06-09
US7844879B2 (en) 2010-11-30
JP5232013B2 (en) 2013-07-10
KR20080098040A (en) 2008-11-06
US20130290813A1 (en) 2013-10-31

Similar Documents

Publication Publication Date Title
EP1987519B1 (en) Method and system for error correction in flash memory
EP1984923B1 (en) Flash memory with coding and signal processing
JP5356214B2 (en) Multilevel signal memory with LDPC and interleaving
TWI451430B (en) System and method for correcting errors in non-volatile memory using product codes
JP5345201B2 (en) Encoding and / or decoding memory device and method
CN101405811B (en) Flash memory with coding and signal processing
JP4099844B2 (en) Memory device
Oh et al. Performance Comparison of Multi-level Coding Schemes for NAND Flash Memory

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 2008551451

Country of ref document: JP

NENP Non-entry into the national phase

Ref country code: DE

WWE Wipo information: entry into national phase

Ref document number: 2007718293

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 1020087020392

Country of ref document: KR

WWE Wipo information: entry into national phase

Ref document number: 200780009987.1

Country of ref document: CN