JP3515519B2 - Data receiving device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data receiving device, and more particularly to a digital broadcast receiving device for receiving digital television broadcast.

[0002]

2. Description of the Related Art In recent years, BS digital broadcasting, which has started broadcasting, uses two error correction methods, a convolutional code and a block code. Although the convolutional code cannot be completely corrected in a low C / N environment (low carrier-to-noise environment), it has an error improving effect. On the other hand, the block code has the property of being able to completely correct an error if it is within the correction capability.

Due to these two characteristics, in order to realize stronger error correction, concatenated coding is often used in which information code is first block coded and then convolutional coding is performed to generate a transmission code. To be Since the residual error of the convolutional code is burst-like, an RS (Reed-Solomon) code is generally used as the block code.

In the block diagram of the entire system including the transmitting side and the receiving side of the BS digital broadcasting, the block coding section and the decoding section are located outside and the convolutional coding section and the decoding section are located inside. Therefore, the convolutional code may be called an inner code and the block code may be called an outer code.

The combination of the inner code error correction system and the modulation system of BS digital broadcasting will be described. In the case of modulation by 8PSK, error correction by trellis coding is performed. In this case, the coding rate is 2/3. This combination is hereafter referred to as TC8PSK. The coding rate of 2/3 indicates that conversion is performed from 2 bits to 3 bits.

On the other hand, in the case of modulation by QPSK or BPSK, convolutional coding is used as an error correction method. The coding rates in this case are 1/2, 2/3, 3/4, 5
/ 6, 7/8. When the coding rates are 2/3 to 7/8, the coding rate is 1/2, the constraint length is 7, and the generator polynomial 1 is further added.
Coding into a punctured code is performed using the 71, 133 (octal) code as the source signal.

The coded signal of the inner code is obtained as a 2-bit output by inputting a 1-bit bit string to the encoder.
Convolutional coding uses this 2-bit output to map to QPSK or BPSK. In trellis encoding, 1 bit is further used to perform 3 bit encoding, and mapping to 8PSK is performed.

The Viterbi decoding output is a decoding of the above inner code, which is a 2-bit serial output in the case of TC8PSK and a 1-bit serial output in the other modes.

On the other hand, the outer code error correction method is a shortened RS.
(Reed-Solomon) (204,188) code is an 8-bit parallel signal.

The signal flow in the receiver is subjected to RS decoding (outer code error correction) after Viterbi decoding (inner code error correction). Since the bit width of signal processing is different between Viterbi decoding and RS decoding, 1-bit or 2-bit serial output of Viterbi decoding is serialized into an 8-bit parallel signal.
It is necessary to perform parallel conversion and perform signal processing. In addition, the circuit after parallel conversion must perform parallel signal processing without interrupting the signal.

FIG. 10 shows a serial-converted Viterbi decoding output used in a conventional digital broadcast receiving apparatus.
FIG. 6 is a block diagram showing a configuration of a parallel conversion circuit 502.

Referring to FIG. 10, the serial-parallel conversion circuit 502 includes serial data D0,
A data conversion unit 504 that converts D1 into parallel data POUT0 to POUT7 and a clock generation unit 506 that receives the serial clock SCLK and outputs the parallel clock PCLK are included.

The clock generator 506 receives the serial clock SCLK, an octal counter 518, a clock generator 520 which outputs a clock signal CLK0 according to the count value of the octal counter 518, and a count operation according to the serial clock SCLK. Quaternary counter 5
14 and a clock generation circuit 516 that outputs a clock signal CLK1 according to the count value of the quaternary counter 514.
And a clock signal CL according to the operation mode signal MODE
Either K0 or CLK1 is the parallel clock PCLK
And a selector 522 for outputting as.

The clock generation circuit 520 outputs the H level when the count value of the oscillation counter 518 is 0 to 3, and outputs the L level when the count value is 4 to 7. Further, the clock generation circuit 516 uses the quaternary counter 5
When the count value of 14 is 0 or 1, the H level is output, and when the count value is 2 or 3, the L level is output.

The serial-parallel conversion circuit 502 is
It has two operation modes A and B. Operation mode A
Corresponds to the case where the output of the Viterbi decoding circuit is given by 2 bits, and in the operation mode B, the output of the Viterbi decoding circuit is 1
Corresponds to when given in bits.

The selector 522 has an operation mode of mode A.
If the clock signal CLK1 is parallel clock P
CLK, and when the operation mode is mode B, the clock signal CLK0 is output as the parallel clock PCLK.

The data conversion unit 504 uses the clock signal CL.
A serial-parallel conversion circuit 510 for converting the serial data D0 into 8-bit parallel data according to K0.
And the serial data D according to the clock signal CLK1.
A serial-parallel conversion circuit 508 for converting 2-bit data of 0 and D1 into 8-bit parallel data, and one of the outputs of the serial-parallel conversion circuits 508 and 510 depending on the mode signal MODE is parallel data PO.
A selector 512 for outputting as UT0 to POUT7.

The selector 512 operates in the mode A.
In the case of, the output of the serial-parallel conversion circuit 508 is output as parallel data POUT0 to POUT7,
When the operation mode is the mode B, the output of the serial-parallel conversion circuit 510 is set to parallel data POUT0-PO.
Output as UT7.

That is, in the configuration shown in FIG.
A serial-parallel conversion circuit 508 is provided for 8PSK, and a serial-parallel conversion circuit 5 is provided for other modes.
10 are provided to perform serial-parallel conversion independently, and the selector 512 selects the output of any serial-parallel conversion circuit to output parallel data POUT0.
It was output as ~ POUT7.

Further, regarding the clock generation, TC8
The quaternary counter 51 4 and the clock generator 5 16 provided for the PSK, 8-ary counter 5 for other modes
1 8 and is provided with a clock generating circuit 5 20, parallel clock PCL either by the selector 522
It was output as K.

FIG. 11 is a circuit diagram showing a configuration of a data conversion unit 532 used in place of the data conversion unit 504 in another conventional serial-parallel conversion circuit.

Referring to FIG. 11, data conversion unit 532
Are flip-flops 540 to 547 and a selector 550.
.About.556.

Flip-flop 540 receives serial data D0 and B input of selector 550 and selector 5
The data is output to the A input of 51. Selector 55
Serial data D1 is given to the A input of 0. The flip-flop 541 outputs the data captured by the output of the selector 550 into the B input of the selector 551 and the A input of the selector 552. Flip-flop 542
Receives the output of the selector 551 and outputs the received data to the B input of the selector 552 and the A input of the selector 553. The flip-flop 543 receives the output of the selector 552 and outputs the received data to the B input of the selector 553 and the A input of the selector 554.

The flip-flop 544 is a selector 55.
3 output, the received data is B of the selector 554
Output to the input and the A input of the selector 555. The flip-flop 545 receives the output of the selector 554, and outputs the received data to the B input of the selector 555 and the A input of the selector 556. Flip flop 5
46 receives the output of the selector 555 and outputs the received data to the B input of the selector 556. Flip-flop 547 receives the output of selector 556.

When the operation mode is the mode A, the selectors 550 to 556 output the signal applied to the A input. On the other hand, when the operation mode is B, the selectors 550-5
56 outputs the signal given to the B input.

The flip-flops 540 to 547 each have parallel data POUT0 at a predetermined timing.
~ Output POUT7.

That is, the serial-parallel conversion circuit 5
In 32, a selector is used in front of the flip-flop of the shift register that outputs the bits of each parallel data. When the Viterbi output is a 1-bit serial output, the mode B is selected and the data input as the serial data D0 is The flip-flops 540 to 547 are sequentially shifted. When the data is accumulated in all the flip-flops 540 to 547, the accumulated data is latched as parallel data POUT0 to POUT7 in the circuit of the next stage.

On the other hand, when the Viterbi output is 2-bit serial data D0, D1, the mode is set to A, and the data input to the flip-flop 540 is sequentially shifted to the flip-flops 542, 544, 546. The data input to the flip-flop 541 receiving the serial data D1 is the flip-flops 543, 545, 545.
It is sequentially shifted to 547. And flip-flop 5
When the data is accumulated in all of 40 to 547, the parallel data POUT0 to POUT7 are latched in the circuit of the next stage.

[0029]

As described above,
In the configuration of the digital broadcast receiver shown in FIG. 10, the serial-parallel conversion circuit and the clock generation circuit for generating the parallel clock are each included in two systems, and the circuit scale is large.

When the configuration shown in FIG. 11 is adopted, the number of selectors is 1 from the number of bits of parallel data.
Only a small number is required, and the larger the number of bits of parallel data, the larger the circuit scale.
Therefore, there is a problem that the digital broadcast receiving apparatus becomes expensive.

An object of the present invention is to provide a digital broadcast receiving device having a reduced circuit scale.

[0032]

According to the present invention, there is provided a data receiving apparatus for decoding a convolutional code, and in accordance with a modulation system of a received signal, a serial decoded signal having a 2-bit width in a first operation mode. To output a 1-bit wide serial decoded signal in the second operation mode, and to receive the data according to the output of the first decoding means and to decode the block code. Is provided on the path through which data is transmitted from the first decoding means to the second decoding means, receives serial data according to the output of the first decoding means, and receives the serial data of the first decoding means. A serial-parallel conversion circuit for outputting parallel data having a bit width wider than the output, wherein the serial data has a 2-bit width in the first operation mode and 1-bit in the second operation mode. And a serial - parallel converter circuit, in a first mode of operation, and outputs the serial data as a signal as 2-bit wide, in the second mode of operation, by distributing the serial data alternately 2
A data converter that outputs a signal having a bit width, and the least significant bit (LSB) and the most significant bit (M) of the output of the data converter.
SB) to receive the respective shifts, and when the predetermined data is accumulated, the parallel data are collectively output.
And a shift register of.

Preferably, the serial-parallel conversion circuit outputs a parallel data in the first mode in response to a counter for receiving a serial clock given in synchronization with the serial data and performing a counting operation, and a count value of the counter. First clock generating means for generating a parallel clock synchronized with the timing, and second clock generating means for generating a parallel clock synchronized with the timing of outputting the parallel data in the second mode according to the count value of the counter. , And selecting means for selecting and outputting one of the outputs of the first and second clock generating means.

Preferably, the serial-parallel conversion circuit has a counter which receives a serial clock applied in synchronization with serial data and performs a counting operation, and an internal circuit which has a cycle twice as long as the serial clock in accordance with the count value of the counter. A clock generating circuit for outputting a clock;
In the second mode, the serial clock is output as a first shift clock that indicates the shift operation timing of the first shift register, and in the second mode, the first shift clock that outputs the first shift clock according to the internal clock. In the first mode, the clock selecting means outputs the serial clock as the second shift clock indicating the shift operation timing of the second shift register, and in the second mode, the second shift clock according to the internal clock. And second shift clock selection means for outputting

More preferably, the first and second shift clocks are two serial clocks in the second mode.
The clocks have a doubled cycle and are complementary to each other.

Preferably, the first shift register includes a plurality of first flip-flops that output data corresponding to even bits of parallel data, and the second shift register corresponds to odd bits of parallel data. It includes a plurality of second flip-flops for outputting data.

Preferably, the first decoding means includes a Viterbi decoding means for decoding the convolutional code by the maximum likelihood decoding method,
The second decoding means includes Reed-Solomon decoding means for decoding the Reed-Solomon code.

[0038]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The same reference numerals in the drawings indicate the same or corresponding parts.

FIG. 1 is a schematic block diagram showing a main part extracted from the configuration of a data receiving apparatus 1000 according to an embodiment of the present invention.

Referring to FIG. 1, data receiving device 1000
In, the RF signal received from the antenna (not shown) is tuned by tuners 100.1 and 100.2 and given to 8PSK demodulators 102.1 and 102.2, respectively.

8PSK demodulators 102.1 and 102.
The demodulated signals from 2 are transport stream decoders (hereinafter referred to as TS decoders) 104.1 and 10
4.2 to the MPEG decoding unit 110 via the changeover switch 106. That is, from the TS decoders 104.1 and 104.2,
The baseband signal is extracted from the selected channel.

The MPEG decoding unit 110 receives the data stream supplied from the changeover switch 106, and uses a random access memory (hereinafter, referred to as RAM) 112 as a buffer for temporarily storing the data, so that a video signal and an audio signal. Convert to.

Data receiving apparatus 1000 further receives a signal from TS decoders 104.1 and 104.2 via data bus BS1 and a built-in storage device 148 for storing the signal, and via data bus BS1. An arithmetic processing unit 144 for performing a predetermined process on the data stored in the built-in storage device 148 and outputting the processed data.
A ROM 140 for recording a program in the arithmetic processing of the arithmetic processing unit 144, a RAM 142 providing a memory area for the operation of the arithmetic processing unit 144, and a data input / output between the data bus BS1 and the outside. And a high speed digital interface 146. Although not particularly limited, the built-in storage device 148 and the ROM 1
As 40, for example, a flash memory capable of electrically writing / reading data can be used.

After the arithmetic processing unit 144 processes the data stored in the built-in storage device 148 in accordance with an instruction given from the outside, the data is combined from the on-screen display processing unit 130. To the vessel 160.2.

The synthesizer 160.2 synthesizes the output from the MPEG decoding unit 110 and the output from the on-screen display processing unit 130, and then outputs the video output terminal 16
Give to 4. The output from the video output terminal 164 is given to the display unit 1004.

The data receiving apparatus 1000 further receives the result data processed by the arithmetic processing unit 144 based on the data stored in the built-in storage device 148, and outputs the sound effect for the image output on the display unit. Additional sound generator 1 for generating and giving to the synthesizer 160.1.
20 and the data processed by the arithmetic processing unit 144 based on the data stored in the built-in storage device 148 and the like to generate a voice signal and give it to the synthesizer 160.1.
The M decoder 122 is provided.

The synthesizer 160.1 outputs the output from the MPEG decoding unit 110, the additional sound generator 120 and the PCM.
Upon receiving the output from the decoder 122, the synthesis result is given to the audio output terminal 162. The audio signal given to the audio output terminal 162 is output from the audio output unit 1002 as an audio signal.

The data receiving apparatus 1000 may be provided with a modem 150 for exchanging data with the outside and an IC card interface 152 for receiving information from an IC card, if necessary. .

Through the high-speed digital interface 146, for example, an external storage device 180 such as a HDD device for a home server and a remote controller (or keyboard or the like) 182 which is an external input device are connected to the data bus BS1.
Connected with.

Further, the data receiving apparatus 1000 has a structure integrated with a display unit 1004 which receives a video output and displays it on a display and a voice output unit 1002 such as a speaker which receives a voice output signal and outputs a voice. Is also good.

FIG. 2 shows the TS decoder 10 shown in FIG.
It is a block diagram which shows the structure of 4.1. The TS decoder 104.2 also has the same configuration as the TS decoder 104.1.

Referring to FIG. 2, TS decoder 104.1
Is a Viterbi decoding circuit 202 that receives the output of the 8PSK demodulator 102.1 and performs Viterbi decoding, and a Viterbi decoding circuit 2
02 output to receive parallel data POUT0 to POU
A serial-parallel conversion circuit 204 that outputs T7 and generates a parallel clock PCLK, a deinterleave circuit 206 that receives the output of the serial-parallel conversion circuit 204 and rearranges data, and a burst error detection / correction And a Reed-Solomon decoding circuit 208 for decoding a Reed-Solomon code, which is one of the block coding schemes. The TS decoder 104.1 further includes a synchronization processing unit (not shown). Also, FIG.
Then, the serial-parallel conversion circuit 204 is arranged between the Viterbi decoding circuit 202 and the deinterleave circuit 206, but it may be arranged in the deinterleave circuit 206 and the Reed-Solomon decoding circuit 208.

The output of the 8PSK demodulator 102.1 is a convolutional code that is convolutional processed on the transmitting side so that error correction can be performed. Viterbi decoding is commonly used to decode this convolutional code.

Viterbi decoding is widely used as a method for efficiently implementing maximum likelihood decoding of convolutional codes and also as a digital signal error correction method for satellite communication systems and mobile communication systems due to its strong error correction capability. ing. Viterbi decoding is one of the maximum likelihood decoding methods for estimating the transmission sequence that is the closest to the transmitted reception sequence and decoding the original information sequence.

The modulation method in BS digital broadcasting is
8PSK, QPSK, BP depending on the content of information to be transmitted
SK is used as appropriate.

When the modulation method is 8PSK, trellis coding (coding rate 2/3) is used as the error correction method.
Hereinafter, this combination is referred to as TC8PSK. In this case, the Viterbi decoding circuit 202 outputs a 2-bit signal of D0 and D1. Hereinafter, the mode for performing the serial-parallel conversion operation corresponding to this output is referred to as operation mode A.

On the other hand, when the modulation method is QPSK or BPSK, the error correction method is convolutional coding (coding rate 1 /
2, 2/3, 3/4, 5/6, 7/8) are used.
When the coding rate is 2/3 to 7/8, the coding rate is 1
/ 2, constraint length 7, generator polynomials 171 and 133 (Octa
punctuated code (punctu)
red convolutional code) is being encoded. In this case, the Viterbi decoding circuit 202 outputs a 1-bit signal including only D0. Hereinafter, the mode in which the serial-parallel conversion operation is performed in response to this output is referred to as operation mode B.

FIG. 3 is a circuit diagram showing a configuration of serial-parallel conversion circuit 204 shown in FIG.

Referring to FIG. 3, serial-parallel conversion circuit 204 receives serial data output of 1-bit (D0) or 2-bit (D0, D1) output from Viterbi decoding circuit 202 depending on the modulation method. Parallel signals POUT0 to PO converted and suitable for Reed-Solomon decoding
The data conversion unit 212 that outputs the UT 7 and the clock generation unit 214 that receives the serial clock SCLK and outputs the parallel clock PCLK are included. The parallel clock PCLK is a clock signal synchronized with the parallel signals POUT0 to POUT7, and is used for processing the parallel signals POUT0 to POUT7 in the deinterleave circuit 206, the Reed-Solomon decoding circuit 208, etc. in the subsequent stage.

FIG. 4 shows the clock generator 21 shown in FIG.
4 is a circuit diagram showing the configuration of FIG. Referring to FIG. 4, clock generation unit 214 includes an octal counter 216 that performs a count operation according to serial clock SCLK, and a parallel clock PC according to the count value of octal counter 216.
A parallel clock generator 220 that outputs LK, and clocks FCLK1 and FCLK for data conversion according to the serial clock SCLK and the count value of the octal counter 216.
And a conversion clock generator 218 for outputting CLK2 and SCLK2.

The conversion clock generation unit 218 receives the clock SCLK2 and inverts it when the count value of the octal counter 216 is 0, 2, 4, and 6, and sets the clock SCLK2 to the H level. An inverting circuit 222; a selector 226 that outputs a serial clock SCLK as a clock FCLK1 when the operation mode is A; and a selector 226 that receives the clock SCLK2 when the operation mode is B and outputs it as a clock FCLK1; In the case of, the serial clock SCLK is output as the clock FCLK2, and when the operation mode is mode B, the output of the inverting circuit 222 is output as the clock FCLK2.
2 and a selector 224 for outputting as 2.

The parallel clock generating section 220 includes selectors 228 and 234 and clock generating circuits 230 and 232.
Including and

Selector 228 gives the count value of octal counter 216 to clock generation circuit 230 when the operation mode is mode A, and gives it to clock generation circuit 232 when the operation mode is mode B.

The selector 234 operates in the mode A.
In this case, the clock generated by the clock generation circuit 230 is output as the parallel clock PCLK. On the other hand, when the operation mode is mode B, the selector 234 outputs the clock generated by the clock generation circuit 232 as the parallel clock PCLK.

The clock generation circuit 230 sets the output clock to the H level when the count value of the octal counter 216 is 0, 1, 4, and 5, and the count value of the octal counter 216 is 2, 3, 6, and 7. In this case, the output clock is set to L level. The clock generation circuit 232 sets the output clock to the H level when the count value of the octal counter 216 is 0, 1, 2, 3, and when the count value of the octal counter 216 is 4, 5, 6, 7. Sets the output clock to L level.

FIG. 5 shows the data converter 212 shown in FIG.
3 is a circuit diagram showing the configuration of FIG. Referring to FIG. 5, data conversion unit 212 receives serial data D0 and D1 and performs data conversion in accordance with mode signal MODE and conversion clock SCLK2, and internal data DI0 and DI1. Clock FCLK1, FC
A data holding unit 244 for fetching and holding data according to LK2 is included.

The data conversion section 242 includes the selectors 246 and 246.
248 and signal switching circuit 250. The signal switching circuit 250 includes selectors 252 and 254.

Selector 246 receives serial data D0 as an input and transmits serial data D0 to A input of selector 254 when the operation mode is mode A. On the other hand, the selector 246 outputs the serial data D0 to the selector 248 when the operation mode is the mode B. The selector 248 uses the data conversion clock SCLK.
According to 2, the data received from the selector 246 is alternately output to the B input of the selector 252 and the B input of the selector 254.

When the operation mode is A, the selectors 252 and 254 output the data applied to the A input as each bit of the 2-bit internal data DI1 and DI0. On the other hand, when the operation mode is the mode B, the selectors 252 and 254 output the data received at the B input as each bit of the internal data DI1 and DI0.

The data holding unit 244 is provided in the shift register 2
56,258 are included. The shift register 256 sequentially flips the internal data DI1 according to the data conversion clock FCLK1.
5, Including FF7.

The shift register 258 stores the internal data DI
Flip-flops FF0, FF2, FF4, FF that sequentially shift 0 according to the data conversion clock FCLK2
Including 6. The flip-flops FF0 to FF7 are
The parallel data POUT0 to POUT7 are output respectively. Therefore, the flip-flop FF0 is the least significant bit (LS) of the parallel data POUT0 to POUT7.
It outputs POUT0 which is B). Flip flop F
F7 outputs POUT7 which is the most significant bit (MSB) of the parallel data POUT0 to POUT7.

FIG. 6 is a diagram for explaining an operation example of the serial-parallel conversion circuit when the Viterbi decoding output is 2 bits.

Referring to FIG. 6, first, the 0th data and the 1st data are simultaneously applied to the parallel-serial conversion circuit. After one serial clock, the flip-flops FF0 and FF1 hold the 1st and 0th data, respectively. Then, two serial clocks later, the flip-flops FF0, FF1, FF2, and FF3 hold the third, second, first, and zeroth data, respectively.

After three serial clocks, the fifth and fourth data are held in the flip-flops FF0 and FF1, respectively, and the flip-flops FF2 and FF3 are held.
Holds the 3rd and 2nd data respectively, and the flip-flops FF4 and FF5 respectively hold the 1st and 0th data.

Then, after 4 serial clocks, the flip-flops FF0, FF1, FF2, FF3
Holds the 7th, 6th, 5th and 4th data respectively. Also, flip-flops FF4, FF5,
FF6 and FF7 have 3rd, 2nd, 1st,
The 0th data is held.

That is, after four serial clocks, the 0th to 7th data are held in all the flip-flops, and these 8 data are collectively output as parallel data to the circuit in the next stage.

FIG. 7 is an operation waveform diagram for explaining in more detail the operation when the Viterbi decoding output is 2 bits.

Referring to FIGS. 5 and 7, in mode A where the Viterbi decoding output is 2 bits, serial data D0 is converted to internal data DI by data conversion unit 242.
0 is output and the serial data D1 is the internal data D
It is output as I1. In addition, the shift register 256,
Data conversion clock FCLK1, which is applied to 258
The serial clock SCLK is used as the FCLK2.

At time t1, internal data DI0 and DI1 are taken into flip-flops FF0 and FF1, respectively, in synchronization with the rise of the clock signal. Therefore, in the time t1 to t2, the flip-flop FF1
Holds data DATA0, and flip-flop FF0
Holds the data DATA1.

Subsequently, at time t2, the data DATA0 held by the flip-flop FF1 is shifted to the flip-flop FF3. Further, the data DATA1 held by the flip-flop FF0 is shifted to the flip-flop FF2. Then, the flip-flop 1 receives the data DATA given as the internal data DI1.
Flip-flop FF0 takes in internal data DI
The data DATA3 given as 0 is held.

Therefore, from time t2 to t3, the flip-flop FF1 holds the data DATA2, and the flip-flop FF3 holds the data DATA0. The flip-flop FF0 holds the data DATA3, and the flip-flop FF2 holds the data DATA1.

Similarly, as a result of sequentially shifting the data, the flip-flops FF1 and FF1 are generated between times t4 and t5.
FF3, FF5, FF7 are data DATA6, respectively.
Holds DATA4, DATA2, and DATA0. Further, the flip-flops FF0, FF2, FF4, FF6 are used for data DATA7, DATA5, DATA3, D, respectively.
Hold ATA1. Therefore, since the data is stored in all the flip-flops, at the subsequent time t5, the parallel data is latched by the circuit at the next stage in response to the rise of the parallel clock PCLK.

Thereafter, similar operations are repeated at times t5 to t9. FIG. 8 is a diagram showing the states of the flip-flops when the Viterbi decoding output is 1 bit.

Referring to FIG. 8, when the Viterbi decoding output is 1 bit, the 0th to 7th data are sequentially provided to the serial-parallel conversion circuit bit by bit as serial data D0. First, after one serial clock, the flip-flop FF1 holds the 0th data. After two subsequent serial clocks, the flip-flop FF0 holds the first data and the flip-flop FF1 holds the 0th data. To do.

After the subsequent three serial clocks, the flip-flop FF0 holds the first data and the flip-flop FF1 holds the second data. Then, the flip-flop FF3 holds the 0th data.

Then, after 4 serial clocks, the flip-flops FF0, FF1, FF2, FF3
Holds the 3rd, 2nd, 1st, and 0th data, respectively. After 5 serial clocks, the flip-flops FF0, FF1, FF2, FF3 are each 3
The second, fourth, first, and second data are held, and the flip-flop FF5 holds the 0th data.

After 6 serial clocks, the flip-flops FF0, FF1, FF2, and FF3 hold the fifth, fourth, third, and second data, respectively, and the flip-flops FF4 and FF5 each have the first and 0th data.
Hold the second data.

After the subsequent 7 serial clocks, the flip-flops FF0, FF1, FF2, FF3 hold the fifth, sixth, third and fourth data, respectively. The flip-flops FF4 and FF5 hold the first and second data, respectively. Then, the flip-flop FF7 holds the 0th data.

After 8 serial clocks, the flip-flops FF0, FF1, FF2, and FF3 hold the 7th, 6th, 5th, and 4th data, respectively, and the flip-flops FF4, FF5, FF6, and FF7 have 3 bits respectively. Holds the 2nd, 2nd, 1st, and 0th data. At this time, flip-flops FF0 to FF7
In this case, since all the data have been accumulated, these eight data are transmitted to the next stage as parallel data.

FIG. 9 is an operation waveform diagram for explaining the operation when the Viterbi decoding output is 1 bit.

Referring to FIGS. 5 and 9, in mode B in which the Viterbi decoding output is 2 bits, the Viterbi decoding output is given only to serial data D0. A clock SCLK2 is used as the conversion clocks FCLK1 and FCLK2.
A complementary clock based on is provided. Selector 2
Data DATA0 to DATA7 provided as serial data D0 by the function of 48 are internal data DI1,
Alternately assigned to DI0.

At time t1, the data DATA0 is transferred to the flip-flop F in synchronization with the rising edge of the clock.
Captured by F1. Then, at time t2, the data DA
TA1 is taken into the flip-flop FF0. Time t
In 3, the data DATA0 held by the flip-flop FF1 is output to the flip-flop FF3, and the flip-flop FF1 takes in the data DATA2. At time t4, the data DATA1 held by the flip-flop FF0 is shifted, and the flip-flop FF0 takes in the data DATA3.

At time t5, flip-flop FF
Data DATA2 and DATA held in FF1 and FF3
0 is shifted to the flip-flops FF3 and FF5, respectively, and the flip-flop FF1 takes in the data DATA4. Flip-flops FF0 and FF at time t6
The data DATA3 and DATA1 held by 2 are respectively shifted to the flip-flops FF2 and FF4, and the flip-flop FF0 newly takes in the data DATA5. At time t7, the flip-flops FF1 and F
Data DATA4, DAT held by F3, FF5
A2 and DATA0 are shifted to the next stage, and the flip-flop FF1 newly takes in data DATA6. Time t8
At the flip-flops FF0, FF2, FF4 respectively, the data DATA5, DATA3, D
ATA1 is shifted to the next stage and flip-flop FF0
Captures new data DATA7. As a result of the shift operation being alternately performed in the shift registers 256 and 258 in this manner, the flip-flop FF is generated at time t8 to t9.
Eight pieces of data are held in 0 to FF7.

At time t9, the parallel clock P
A circuit connected to the next stage latches the data held by the flip-flops FF0 to FF7 as parallel data in response to the rise of CLK.

As described above, according to the present invention, the flip-flops of the serial-parallel conversion circuit are configured as two shift registers, and the data is appropriately distributed according to the number of bits of the Viterbi decoding output. Therefore, serial mode of multiple modes with a small circuit scale
A parallel conversion operation can be realized.

Although the 8-bit parallel data has been described in the present embodiment, 16-bit, 32-bit data is used.
The present invention can also be applied to serial-parallel conversion with other numbers of bits such as bits. Furthermore, in the present embodiment, a BS digital broadcast receiver is shown as an example of the data receiving device, but the present invention is not limited to this, and the present invention is a concatenated code that uses a plurality of encodings in combination. Any data receiving device that receives and decodes a transmission code whose error correction is enhanced by the conversion can be suitably used.

The embodiments disclosed this time are to be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description but by the claims, and is intended to include meanings equivalent to the claims and all modifications within the scope.

[0098]

According to the present invention, the flip-flops of the serial-parallel conversion circuit are configured as two shift registers, and the data is appropriately distributed according to the number of bits of the Viterbi decoding output. It is possible to realize serial-parallel conversion operations in a plurality of modes on a circuit scale.

[Brief description of drawings]

FIG. 1 is a data receiving device 1 according to an embodiment of the present invention.
000 is a schematic block diagram showing a main part extracted from the configuration of FIG.

FIG. 2 is a block diagram showing a configuration of a TS decoder 104.1 shown in FIG.

FIG. 3 is a serial-parallel conversion circuit 2 shown in FIG.
It is a circuit diagram which shows the structure of 04.

4 is a circuit diagram showing a configuration of a clock generator 214 shown in FIG.

5 is a circuit diagram showing a configuration of a data conversion unit 212 shown in FIG.

FIG. 6 is a diagram for explaining an operation example of the serial-parallel conversion circuit when the Viterbi decoding output is 2 bits.

FIG. 7 is an operation waveform diagram for explaining in more detail the operation when the Viterbi decoded output is 2 bits.

FIG. 8 is a diagram showing a state of a flip-flop when a Viterbi decoding output is 1 bit.

FIG. 9 is an operation waveform diagram for explaining an operation when the Viterbi decoding output is 1 bit.

FIG. 10 is a block diagram showing a configuration of a serial-parallel conversion circuit 502 that converts a Viterbi decoded output used in a conventional digital broadcast receiving apparatus.

FIG. 11 is a circuit diagram showing a configuration of a data conversion unit 532 used in place of the data conversion unit 504 in another example of the conventional serial-parallel conversion circuit.

[Explanation of symbols]

100 tuner, 102 8PSK demodulator, 104
TS decoder, 106 selector switch, 110 MPEG
Decoding unit, 120 Additional sound generator, 122 PCM decoder, 130 On-screen display processing unit, 1
44 arithmetic processing unit, 146 high-speed digital interface, 148 built-in storage device, 150 modem, 1
52 card interface, 160 synthesizer, 16
2 audio output terminals, 164 video output terminals, 180 external storage device, 202 Viterbi decoding circuit, 204 serial-parallel conversion circuit, 206 deinterleave circuit, 208 Reed-Solomon decoding circuit, 212 data conversion unit, 214 clock generation unit, 2168 Advance counter, 218 conversion clock generator, 220, 230,
232 clock generation circuit, 220 parallel clock generation unit, 222 inversion circuit, 224, 226, 228, 2
34, 246, 248, 252, 254 selector, 2
42 data conversion unit, 504 data conversion unit, 244
Data holding unit, 250 signal switching circuit, 256, 258
Shift register, 1000 data receiving device, 1002
Audio output unit, 1004 display unit, BS1 data bus, FF0 to FF7 flip-flops.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI H04N 7/00 H04N 7/00 Z 7/24 7/13 A (56) Reference JP-A-11-177642 (JP, A) JP 5-91150 (JP, A) JP 6-13913 (JP, A) JP 7-288479 (JP, A) JP 3-253122 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H04L 27/00-27/38

Claims (6)

(57) [Claims] 1. A convolutional code is decoded, a 2-bit width serial decoded signal is output in a first operation mode, and a 1-bit is output in a second operation mode according to a modulation system of a received signal.
First decoding means for outputting a serial decoded signal having a bit width; second decoding means for receiving data corresponding to the output of the first decoding means and decoding a block code; and the first decoding means. Is provided on a path through which data is transmitted from the means to the second decoding means, receives serial data according to the output of the first decoding means, and has a bit width larger than that of the output of the first decoding means. A serial-parallel conversion circuit for outputting wide parallel data, wherein the serial data has a 2-bit width in the first operation mode and a 1-bit width in the second operation mode; The parallel conversion circuit outputs the serial data as a 2-bit width signal as it is in the first operation mode, and outputs the serial data as it is in the second operation mode. A data conversion section for outputting a signal of two bit wide by distributing the real data alternately, the least significant bits of the output of the data converter and (LSB) top
A data receiving device, comprising: first and second shift registers that receive the upper bits (MSBs) and shift them, and collectively output the parallel data when predetermined data is accumulated. 2. The serial-parallel conversion circuit includes a counter that performs a counting operation by receiving a serial clock that is applied in synchronization with the serial data, and the parallel mode in the first mode according to a count value of the counter. First clock generating means for generating a parallel clock synchronized with the timing of outputting data, and a parallel clock synchronized with the timing of outputting the parallel data in the second mode according to the count value of the counter. The data receiving apparatus according to claim 1, further comprising: a second clock generating unit; and a selecting unit that selects and outputs one of outputs of the first and second clock generating units. 3. The serial-parallel conversion circuit includes a counter that performs a counting operation by receiving a serial clock that is applied in synchronization with the serial data, and a cycle that is twice as long as the serial clock in accordance with the count value of the counter. A clock generation circuit for outputting an internal clock having: a first shift clock indicating a shift operation timing of the first shift register in the first mode; and a second shift mode in the second mode. A first shift clock selecting means for outputting the first shift clock according to the internal clock; and a second shift clock indicating a shift operation timing of the serial clock for the second shift register in the first mode. Output as the shift clock of the Further comprising a second shift clock selecting means for outputting said second shift clock in accordance with the internal clock, the data receiving apparatus according to claim 1. 4. The first and second shift clocks are clocks that have a cycle twice that of the serial clock in the second mode and are complementary to each other.
The data receiving device according to 1. 5. The first shift register includes a plurality of first flip-flops for outputting data corresponding to even bits of the parallel data, and the second shift register includes odd bits of the parallel data. 2. A plurality of second flip-flops that output data corresponding to
The data receiving device according to 1. 6. The first decoding means includes a Viterbi decoding means for decoding a convolutional code by a maximum likelihood decoding method, and the second decoding means includes a Reed-Solomon decoding means for decoding a Reed-Solomon code. The data receiving apparatus according to claim 1.