JP4780048B2 - Receiving apparatus and method - Google Patents

Description

  The present invention relates to a receiving apparatus and method, and more particularly, to a receiving apparatus and method capable of quickly outputting CSI before calculating high-accuracy CSI (Channel State Information).

  One transmission method in which a signal to be transmitted may take multiple frame lengths is the DVB-S.2 (Digital Video Broadcasting over Satellite Second Generation) standard, which is a digital satellite broadcasting standard.

  The DVB-S.2 standard is a standard that is standardized by the ETSI (European Telecommunications Standards Organization) and corresponds to the higher rank of the DVB-S standard being used. Compared to the DVB-S standard, the DVB-S.2 standard introduces multi-level phase modulation and LDPC (Low Density Parity Check) codes to improve frequency utilization efficiency per unit frequency and C / N ratio ( Carrier to Noise ratio is improved. Also, in order to ensure synchronization performance even at a low C / N ratio, a PL (physical layer) header for transmitting physical layer transmission information and a synchronous pilot signal have been introduced as standards. In the DVB-S.2 standard, the PL header and the synchronous pilot signal are modulated by π / 2 shift BPSK (Binary Phase Shift Keying) and transmitted.

  FIG. 1 shows a frame format in the DVB-S.2 standard.

  A 90-symbol header consisting of a SOF (Start Of Frame) area and a PLS (Physical Layer Signaling) area is placed at the beginning of each frame, and a plurality of slots of 90 symbols per slot are placed behind the header. Is placed. A main signal symbol (data symbol) is inserted into the slot. Depending on the setting, a pilot block for synchronization may be inserted into the main signal every 16 slots. When there are pilot blocks, pilot blocks are inserted at intervals of 16 slots, for example.

  As described above, the header is composed of a 26-symbol SOF region and a 64-symbol PLS region.

  The SOF area is composed of a 26-bit fixed value representing the beginning of the frame. That is, the SOF area indicates a synchronization word for frame synchronization.

The PLS area contains 7-bit information indicating transmission parameters related to signal transmission, (64,7) Reed-
It consists of a 64-bit codeword encoded in Muller code (RM code). The 7-bit transmission parameter consists of a 5-bit MODCOD area and a 2-bit TYPE area.

  The MODCOD area indicates a frame modulation method and an error correction code coding rate.

  MSB (Most Significant Bit) in the TYPE area indicates a frame length (in bits) and is set to 0 (normal) or 1 (short). That is, the TYPE field indicates the frame length and the presence / absence of a pilot block.

  In such a DVB-S.2 standard frame, a header composed of an SOF area and a PLS area and a pilot block are known symbols, and a main signal symbol is arranged in the slot. Hereinafter, of the demodulated signal symbol sections obtained by demodulating the modulated signal, the known symbol section is referred to as a known section, and the main signal symbol section is referred to as a main signal section.

  The configuration of a receiver that receives a DVB-S.2 standard signal having the above-described frame configuration is as shown in FIG.

  FIG. 2 is a block diagram showing a configuration of a conventional receiver.

  In FIG. 2, the receiver 11 includes a tuner 21, an AD (Analog Digital) converter 22, a channel equalizer 23, a synchronization circuit 24, an error correction decoder 25, and a CSI calculation circuit 26.

  The radio wave received by the antenna 12 is selected in a desired band by the tuner 21. The selected signal is converted from an analog signal to a digital signal by the AD converter 22, and so-called multipath interference is equalized by the channel equalizer 23.

  Subsequently, the synchronization circuit 24 synchronizes with the symbol timing, the frame timing, and the carrier frequency. At this time, a synchronization flag is generated that outputs High when synchronization is achieved and outputs Low when synchronization is not achieved. The synchronization circuit 24 also generates known symbol information that outputs High in the known section and Low in the main signal section, using the detected frame timing and a known frame format that complies with the standard. These synchronization flags and known symbol information are output to the CSI calculation circuit 26.

  In the error correction decoder 25, after the LDPC code as the inner code is soft-decision decoded, the BCH (Bose, Chadhuri and Hoquengem) code as the outer code is hard-decision decoded and a desired MPEG (Moving Picture Experts Group) bit is obtained. A stream is output.

  When synchronization is established in the synchronization circuit 24, the CSI calculation circuit 26 calculates CSI based on the distribution of received symbols and supplies it to the error correction decoder 25 as shown in Expression (1).

  However, in Formula (1), it has the relationship of following Formula (2).

In Equations (1) and (2), r _I is the I-axis component of vector r on the IQ plane, and the average received amplitude is normalized to 1, as shown in FIG. Shall. Vector R is a received symbol, and vector S is the result of a hard decision on a known symbol or main signal symbol.

  The CSI calculated by the CSI calculation circuit 26 is used when the LDPC code is subjected to soft decision decoding by the error correction decoder 25.

  As described above, the conventional receiver 11 decodes the received DVB-S.2 standard signal and outputs it as an MPEG bit stream.

Patent Document 1 proposes a C / N measurement method capable of measuring the C / N ratio in fine steps.
Japanese Patent Laid-Open No. 11-215202

  However, high-precision CSI is required for LDPC codes to exhibit high soft decision decoding performance, but when only known sections are used for CSI calculation, the percentage of known symbols is a small percentage of all symbols. Therefore, there is a problem that the CSI value does not converge unless the measurement cycle is lengthened.

  Therefore, if the CSI is not given to the error correction decoder until the highly accurate CSI is calculated, the operation of the error correction decoder is delayed, and the MPEG that has been sufficiently error correction decoded to a viewable quality. There was a problem that it took time to output the bitstream.

  Further, when not only the known interval but also the main signal interval is used for CSI calculation, the convergence of CSI is accelerated, but the CSI calculation accuracy deteriorates due to a hard decision error in the main signal interval. Therefore, if the reception level of radio waves is low and sufficient calculation accuracy cannot be obtained due to a hard decision error, there is a problem that the error correction decoding capability is remarkably deteriorated and the broadcast viewing is hindered.

  The present invention has been made in view of such circumstances, and by switching the CSI calculation method, it is possible to output CSI quickly before calculating high-precision CSI.

  A receiving apparatus according to an aspect of the present invention uses a known section that is a section of a known symbol inserted in a demodulated signal obtained by demodulating the modulated signal in a receiving apparatus that receives a modulated signal obtained by digitally modulating a carrier wave. First channel state information calculating means for calculating first channel state information used for likelihood calculation in soft decision decoding, and until the calculation of the first channel state information converges, Channel state information output means for outputting second channel state information that can be output faster than the channel state information of the channel state information, and the channel state information output means, when calculation of the first channel state information has converged The calculated first channel state information is output instead of the output second channel state information.

  It further comprises channel state information holding means for holding transmission information related to transmission of the modulated signal and the predetermined second channel state information in correspondence with each other, and the channel state information output means includes the first Until the calculation of the channel state information converges, the second channel state information corresponding to the transmission information obtained by decoding the known section from the second channel state information held. Can be output.

  Second channel state information calculating means for calculating the second channel state information using the known signal period and a main signal period that is a main signal symbol period, further comprising: Until the calculation of the first channel state information converges, the calculated second channel state information can be output.

  In the channel state information output means, when the calculated variation of the first channel state information falls within a predetermined range, the calculated second channel state information is replaced with the calculated second channel state information. The first channel state information can be output.

  The channel state information output means replaces the second channel state information that has been output when the predetermined time has elapsed after the synchronization of the demodulated signal has been established with the calculated first channel state information. Channel state information can be output.

  A receiving method according to an aspect of the present invention is a receiving method of a receiving apparatus that receives a modulated signal obtained by digitally modulating a carrier wave, and is a known symbol section inserted in a demodulated signal obtained by demodulating the modulated signal. The first channel state information used for likelihood calculation in soft decision decoding is calculated using the interval, and the calculation of the first channel state information is converged until the first channel state information converges. When the second channel state information that can be output quickly is output and the calculation of the first channel state information has converged, the calculated first channel state information is used instead of the output second channel state information. Output channel status information.

  As described above, according to one aspect of the present invention, it is possible to output CSI quickly before calculating high-precision CSI.

  Embodiments of the present invention will be described below. Correspondences between constituent elements of the present invention and the embodiments described in the specification or the drawings are exemplified as follows. This description is intended to confirm that the embodiments supporting the present invention are described in the specification or the drawings. Therefore, even if there is an embodiment which is described in the specification or the drawings but is not described here as an embodiment corresponding to the constituent elements of the present invention, that is not the case. It does not mean that the form does not correspond to the constituent requirements. Conversely, even if an embodiment is described here as corresponding to a configuration requirement, that means that the embodiment does not correspond to a configuration requirement other than the configuration requirement. Not something to do.

A receiving device according to one aspect of the present invention includes:
In a receiving apparatus (for example, the receiver 51 in FIG. 4) that receives a modulated signal obtained by digitally modulating a carrier wave,
First channel state information (for example, CSI2) used for likelihood calculation in soft decision decoding using a known section that is a section of a known symbol inserted in a demodulated signal obtained by demodulating the modulated signal. First channel state information calculating means for calculating (for example, the high-precision CSI calculating circuit 71 in FIG. 5);
Until the calculation of the first channel state information converges, channel state information output means for outputting second channel state information (for example, CSI1) that can be output faster than the first channel state information ( For example, the selection circuit 74) of FIG.
When the calculation of the first channel state information converges, the channel state information output means outputs the calculated first channel state information instead of the output second channel state information. (For example, CSI timing chart of FIG. 7).

Channel state information holding means (for example, CSI in FIG. 5) that holds transmission information (for example, MODCOD) related to the transmission of the modulated signal and predetermined second channel state information (for example, CSI1). A fixed value table 72);
The channel state information output means is a transmission obtained by decoding the known section from the second channel state information held until the calculation of the first channel state information converges. The second channel state information (for example, CSI1) corresponding to the information (for example, MODCOD) is output (for example, the CSI timing chart in FIG. 7).

Second channel state information calculating means for calculating the second channel state information (for example, CSI1) by using the known signal and the main signal period which is the main signal symbol period (for example, high-speed CSI calculation in FIG. 8). A circuit 91),
The channel state information output means outputs the calculated second channel state information until the calculation of the first channel state information converges (for example, the CSI timing chart of FIG. 7).

  The channel state information output means replaces the output second channel state information with the calculated first channel state information when the variation of the calculated first channel state information falls within a predetermined range. 1 channel state information is output (for example, the selection circuit 74 in FIG. 5 that operates according to the RDY signal output when the variation of the calculated value of CSI2 falls within a predetermined range).

  The channel state information output means replaces the output second channel state information and outputs the calculated first channel when a predetermined time has elapsed after synchronization of the demodulated signal is established. Status information is output (for example, the CSI timing chart of FIG. 7).

An information processing method according to one aspect of the present invention includes:
In a receiving method of a receiving apparatus (for example, the receiver 51 in FIG. 4) that receives a modulated signal obtained by digitally modulating a carrier wave,
First channel state information (for example, CSI2) used for likelihood calculation in soft decision decoding using a known section that is a section of a known symbol inserted in a demodulated signal obtained by demodulating the modulated signal. (For example, the CSI timing chart of FIG. 7)
Until the calculation of the first channel state information converges, second channel state information (for example, CSI1) that can be output faster than the first channel state information is output, and the first channel When the calculation of the state information converges, the calculated first channel state information is output instead of the output second channel state information (for example, the CSI timing chart of FIG. 7).
Includes steps.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  The present invention can be applied to all digital transmission systems in which an error correction code that can be decoded by soft decision decoding is used. Hereinafter, DVB-S.2, which is a second generation satellite digital video broadcast, is applied as an example. Will be described.

  FIG. 4 is a block diagram showing a configuration of an embodiment of a receiver to which the present invention is applied.

  In FIG. 4, a receiver 51 is a device that receives and demodulates a broadcast signal (hereinafter also referred to as a received signal) compliant with the DVB-S.2 standard. The receiver 51 includes a tuner 61, an AD converter 62, a channel equalizer 63, a synchronization circuit 64, an error correction decoder 65, and a CSI calculation circuit 66.

  The receiver 51 in FIG. 4 differs from the conventional receiver 11 (FIG. 2) in the following points. That is, in the receiver 51 of FIG. 4, in addition to the synchronization flag and the known symbol information, the synchronization circuit 64 outputs MODCOD to the CSI calculation circuit 66, and the CSI calculation circuit 66 uses the information including MODCOD. CSI is calculated.

  Therefore, the tuner 61 through the channel equalizer 63 and the error correction decoder 65 in FIG. 4 have the same functions as the tuner 21 through the channel equalizer 23 and the error correction decoder 25 in FIG.

  To repeat, for example, a broadcast wave of a BS (Broadcasting Satellite) digital broadcast is received by an antenna 52 and a modulated signal that is an IF (Intermediate Frequency) signal, that is, a carrier wave is transmitted in a broadcast station that performs BS digital broadcast. A digitally modulated IF signal of the modulation signal is supplied to the tuner 61.

  The tuner 61 multiplies the IF signal of the modulation signal supplied thereto by a carrier wave, thereby converting the IF signal of the modulation signal into a demodulated signal composed of an I component in phase with the carrier wave and a Q component orthogonal to the carrier wave. Demodulate and supply the demodulated signal to the AD converter 62.

  The AD converter 62 AD converts the analog demodulated signal supplied from the tuner 61 and supplies the digital demodulated signal obtained as a result to the channel equalizer 63.

  The channel equalizer 63 equalizes the demodulated signal supplied from the AD converter 62 and supplies the demodulated signal with multipath interference equalized to the synchronization circuit 64.

  The synchronization circuit 64 is synchronized with the symbol timing, frame timing, and carrier frequency based on the demodulated signal supplied from the channel equalizer 63.

  Specifically, the synchronization circuit 64 generates a synchronization flag that outputs High when synchronization is achieved, and outputs Low when synchronization is not achieved, and uses a known frame format that complies with the detected frame timing and standard. Thus, known symbol information that outputs High in the known section and Low in the main signal section is generated.

  In addition to the synchronization flag and the known symbol information, the synchronization circuit 64 supplies MODCOD obtained by decoding the PLS area after establishing synchronization to the CSI calculation circuit 66. As described above, MODCOD is information indicating a frame modulation scheme and an error correction code coding rate.

  In addition to the I and Q components, the synchronization flag, and the known symbol information, MODCOD is supplied from the synchronization circuit 64 to the CSI calculation circuit 66. The CSI calculation circuit 66 calculates CSI based on the information and supplies it to the error correction decoder 65.

  Here, a detailed configuration of the CSI calculation circuit 66 will be described with reference to FIG.

  The CSI calculation circuit 66 includes a high-precision CSI calculation circuit 71, a CSI fixed value table 72, an RDY signal generation circuit 73, a selection circuit 74, and a selection circuit 75.

  The high-precision CSI calculation circuit 71 is supplied with the I and Q components, the synchronization flag, and the known symbol information from the synchronization circuit 64. The high-accuracy CSI calculation circuit 71 uses the information to calculate CSI2 based on the distribution of received symbol points. The high-precision CSI calculation circuit 71 outputs the calculated CSI2 to the RDY signal generation circuit 73 and the selection circuit 74.

  That is, since CSI2 is information calculated using only known sections based on known symbol information, CSI2 is highly accurate.

  The CSI fixed value table 72 stores CSI1 obtained in advance so as to correspond to MODCOD that is transmission information related to transmission of a modulated signal. The CSI fixed value table 72 outputs CSI1 corresponding to the modulation scheme and coding rate specified by MODCOD supplied from the synchronization circuit 64 to the selection circuit 75.

  That is, since CSI1 is a fixed value obtained in advance, CSI1 can be output at high speed (rapidly).

  Here, a specific example of the CSI fixed value table will be described with reference to FIG.

  In FIG. 6, the CSI fixed value table holds CSI1 converted from the required CNR (C / N ratio (Carrier to Noise ratio)) satisfying pseudo error free for each combination of modulation scheme and coding rate. To do. The CSI fixed value table outputs the held CSI1 value corresponding to the input MODCOD value.

  In FIG. 6, the first column indicates the value of “MODCOD”, and the second to fourth columns indicate information on “modulation scheme”, “coding rate”, and “CSI1” corresponding to the value of MODCOD. Respectively.

  Specifically, in the CSI fixed value table of FIG. 6, the second line is CSI1 when MODCOD 4 with a modulation scheme of QPSK (Quadrature Phase Shift Keying) and a coding rate of 1/2 is notified. Represents the output of 2.52.

  The third and subsequent lines have the same meaning as the second line. That is, the third line outputs 3.34 as CSI1 when MODCOD 5 with a modulation scheme of QPSK and a coding rate of 3/5 is notified, and the fourth line has a modulation scheme of QPSK and code When MODCOD 6 with an encoding rate of 2/3 is notified, 4.08 is output as CSI1, and the fifth line is notified of MODCOD 7 with a modulation scheme of QPSK and an encoding rate of 3/4 In this case, 5.01 is output as CSI1.

  The sixth line outputs 5.88 as CSI1 when MODCOD 8 with a modulation scheme of QPSK and a coding rate of 4/5 is notified, and the seventh line has a modulation scheme of QPSK and code When MODCOD 9 with a conversion rate of 5/6 is notified, 6.59 is output as CSI1, and the 8th line is notified of MODCOD 10 with a modulation scheme of QPSK and a coding rate of 8/9 In this case, 8.14 is output as CSI1. Furthermore, the 9th line outputs 8.77 as CSI1 when the MODCOD 11 with a modulation scheme of QPSK and a coding rate of 9/10 is notified, and the 10th line outputs a modulation scheme of 8PSK (8 In Phase Shift Keying, when MODCOD 12 with a coding rate of 3/5 is notified, 7.10 is output as CSI1, and the 11th line is a modulation scheme of 8PSK and a coding rate of 2/3 When a certain MODCOD 13 is notified, 9.18 is output as CSI1, and the 12th line is 12.16 as CSI1 when MODCOD 14 with a modulation scheme of 8PSK and a coding rate of 3/4 is notified. It represents output.

  Furthermore, the 13th line outputs 17.21 as CSI1 when the MODCOD 15 with a modulation scheme of 8PSK and a coding rate of 5/6 is notified, and the 14th line encodes the modulation system with 8PSK. When MODCOD 16 with a coding rate of 8/9 is notified, 23.44 is output as CSI1, and the 15th line is notified of MODCOD 17 with a modulation scheme of 8PSK and a coding rate of 9/10 In this case, 25.06 is output as CSI1.

  As described above, the CSI fixed value table 72 stores the information shown in FIG. 6, and based on MODCOD information (control information notifying the modulation scheme and coding rate) obtained from the PLS code decoding result, The corresponding CSI1 is output to the selection circuit 75.

  The relationship between CNR and CSI (CSI1) is calculated by the following equation (3).

  That is, in the CSI fixed value table 72, for example, a value obtained by doubling a required CNR is held as a CSI fixed value. Here, the reason why CSI1 converted from the required CNR is a CSI fixed value is that if the actual operating point is sufficiently higher than the required CNR, it can be decoded even if the CSI accuracy is somewhat bad, so the actual operating point is This is to obtain the highest decoding performance in the vicinity of the required CNR.

  Returning to FIG. 5, the selection circuit 75 is supplied with the synchronization flag from the synchronization circuit 64 in addition to CSI1 from the CSI fixed value table 72. The selection circuit 75 outputs CSI1 from the CSI fixed value table 72 to the selection circuit 74 when the synchronization flag is 1, and outputs 0 to the selection circuit 74 when the synchronization flag is 0. Accordingly, 0 is input from the selection circuit 75 to the selection circuit 74 before the synchronization is established, and CSI1 is input from the selection circuit 75 after the synchronization is established.

  The selection circuit 74 is supplied with the RDY signal from the RDY signal generation circuit 73 in addition to the CSI2 from the high-precision CSI calculation circuit 71 and the output (CSI1 or 0) from the selection circuit 75. The selection circuit 74 outputs the output of the selection circuit 75 when the RDY signal is 0, and CSI2 to the error correction decoder 65 as CSI when the RDY signal is 1.

  The RDY signal generation circuit 73 is supplied with the synchronization flag from the synchronization circuit 64 and CSI2 from the high-precision CSI calculation circuit 71. The RDY signal generation circuit 73 outputs the RDY signal to the selection circuit 74 when the variation of the calculated value of CSI2 by the high-precision CSI calculation circuit 71 falls within a certain range based on CSI2.

  Note that the timing at which the RDY signal is output by the RDY signal generation circuit 73 is not limited to when the calculated value of CSI2 falls within a predetermined range. For example, transmission line synchronization is established based on a synchronization flag. Any timing may be used as long as it is optimal for switching between CSI1 and CSI2, such as outputting when a predetermined time has passed.

  As described above, when the CSI calculation circuit 66 outputs the CSI to the error correction decoder 65, the CSI calculation circuit 66 temporarily outputs CSI1 that can be output at high speed while calculating the high-accuracy CSI2, and thereafter, CSI2 Is output, CSI2 is output instead of CSI1.

  Returning to FIG. 4, the error correction decoder 65 is supplied with the I and Q components from the synchronization circuit 64 and the CSI from the CSI calculation circuit 66. The error correction decoder 65 uses CSI to soft-decode the LDPC code that is the inner code, and then hard-decodes the BCH code that is the outer code, and outputs a desired MPEG bit stream. That is, in the error correction decoder 65, CSI is used for likelihood calculation in soft decision decoding.

  As described above, in the receiver 51 of FIG. 4, the CSI calculation circuit 66 outputs the CSI fixed value until the calculation of the high-precision CSI sufficiently converges, and the error correction decoder 65 outputs the CSI. Is used to output an MPEG bitstream.

  In this way, until the calculation of high-accuracy CSI converges sufficiently, by substituting with a CSI fixed value, the fluctuation of the transmission line becomes more than a certain level, and some poor environments where the required CNR fluctuates greatly In most environments except for, the viewing start time of the decoded MPEG data can be greatly shortened.

  Next, the detailed operation of the receiver 51 of FIG. 4 will be described with reference to the timing chart of FIG.

  FIG. 7 shows a reset, a synchronization flag, a timer of the RDY signal generation circuit 73, an RDY signal, and a CSI timing chart in order from the top in the figure. The time direction is the direction from the left to the right in the figure.

  As shown in the timing chart of FIG. 7, when the reception of the reception signal is started and the reset is switched from Low to High, the synchronization circuit 64 starts its operation. Thereafter, when synchronization is established by the synchronization circuit 64, the synchronization flag is switched from low to high.

  When the synchronization flag is switched to High, the RDY signal generation circuit 73 starts counting the timer. Thereafter, the RDY signal generation circuit 73 outputs the RDY signal to the selection circuit 74 when the time counted by the timer has exceeded a predetermined time N. That is, as shown in FIG. 7, when the timer becomes N, the RDY signal is switched from Low to High.

  In addition, the CSI output by the selection circuit 74 is output to the error correction decoder 65 as 0 as the initial value from the start of reception of the received signal until the synchronization is established. Subsequently, CSI1 output from the CSI fixed value table 72 is output to the error correction decoder 65 until the RDY signal is output after the synchronization is established, and after the output of the RDY signal, the high-precision CSI calculation circuit The CSI2 calculated by 71 is output to the error correction decoder 65. As shown in FIG. 7, the timing at which the calculation of CSI2, which is a high-precision CSI, is started is the timing at which synchronization is established and the synchronization flag is switched from low to high.

  By the way, in the above-described embodiment, the CSI fixed value table 72 is provided, and CSI1 that is a fixed value is output instead of CSI2 until the calculation of CSI2 that is highly accurate CSI sufficiently converges. However, it is only necessary to substitute another CSI until the calculation of CSI2 converges, and the form is not limited to the above-described example. Therefore, as another embodiment, an example will be described in which CSI1 is used instead of CSI2 by calculating CSI1 at high speed.

  FIG. 8 is a block diagram showing another configuration of the CSI calculation circuit 66.

  In FIG. 8, the same parts as those in FIG. 5 are denoted with the same reference numerals, and the description of the same parts will be omitted as appropriate because the description will be repeated. In this example, a high-speed CSI calculation circuit 91 is provided instead of the CSI fixed value table 72 of FIG.

  The high-speed CSI calculation circuit 91 is supplied with the I and Q components and the synchronization flag from the synchronization circuit 64. The high-speed CSI calculation circuit 91 calculates CSI1 based on the variance of all received symbol points using the information. The high speed CSI calculation circuit 91 outputs the calculated CSI1 to the selection circuit 75.

  That is, since CSI1 is information calculated using not only the known section but also the main signal section, the CSI1 is calculated at high speed in a short time.

  In addition to CSI1 from the high-speed CSI calculation circuit 91, the selection circuit 75 is supplied with a synchronization flag from the synchronization circuit 64. The selection circuit 75 outputs CSI1 from the high-speed CSI calculation circuit 91 when the synchronization flag is 1, and outputs 0 to the selection circuit 74 when the synchronization flag is 0.

  For example, the selection circuit 74 receives an RDY signal generation circuit 73 from the RDY signal generation circuit 73 when a certain period of time elapses after the synchronization of the transmission path is established or when the calculated value of CSI2, which is a high-precision CSI, varies within a certain range. RDY signal is supplied.

  For example, the selection circuit 74 outputs CSI1 calculated by the high-speed CSI calculation circuit 91 to the error correction decoder 65 until the RDY signal is output after the synchronization of the transmission path is established, and thereafter, after the RDY signal is output. Outputs the CSI2 calculated by the high-precision CSI calculation circuit 71 to the error correction decoder 65.

  As described above, the high-accuracy CSI calculation circuit 71 calculates CSI2 using only known sections based on the known symbol information. In contrast, the high-speed CSI calculation circuit 91 calculates CSI1 using the known section and the main signal section. Accordingly, it can be said that CSI1 is a CSI calculated at high speed, and CSI2 is a CSI calculated with high accuracy.

  In other words, until the high-precision CSI calculation is sufficiently converged, the high-speed CSI CSI1 and the high-precision CSI CSI2 are substituted, so that the reception level of radio waves is low and the high-speed CSI calculation accuracy is remarkably high. The viewing start time of the decoded MPEG data can be greatly reduced in almost all environments except some inferior environments that deteriorate.

  When the operation of the CSI calculation circuit 66 in FIG. 8 is represented by a timing chart, it is the same as the operation of the CSI calculation circuit 66 in FIG. 5 described with reference to the timing chart in FIG. . That is, in the timing chart of FIG. 7, in the case of the CSI calculation circuit 66 of FIG. 5, it has been described that CSI1 is a value held in the CSI fixed value table, but in the case of the CSI calculation circuit 66 of FIG. The CSI1 is a value calculated by the high-speed CSI calculation circuit 91.

  As described above, according to the present invention, CSI can be output quickly before calculation of high-precision CSI. As a result, it is possible to shorten the time until the start of broadcast viewing.

  The present invention can be applied to a receiver that receives a modulated signal obtained by digitally modulating a carrier wave, such as a CS (Communication Satellite) broadcast, in addition to a receiver that receives a modulated signal of a BS broadcast.

  In this specification, “CSI” has the same meaning as “channel state information”.

  The series of processes described above can be executed by hardware or can be executed by software. When a series of processing is executed by software, a program constituting the software may execute various functions by installing a computer incorporated in dedicated hardware or various programs. For example, it is installed from a program recording medium in a general-purpose personal computer or the like.

  FIG. 9 is a block diagram showing an example of the configuration of a personal computer that executes the above-described series of processing by a program. A CPU (Central Processing Unit) 111 executes various processes according to a program recorded in a ROM (Read Only Memory) 112 or a recording unit 118. A RAM (Random Access Memory) 113 appropriately stores programs executed by the CPU 111, data, and the like. The CPU 111, the ROM 112, and the RAM 113 are connected to each other by a bus 114.

  An input / output interface 115 is also connected to the CPU 111 via the bus 114. The input / output interface 115 is connected to an input unit 116 made of a microphone or the like and an output unit 117 made of a display, a speaker, or the like. The CPU 111 executes various processes in response to commands input from the input unit 116. Then, the CPU 111 outputs the processing result to the output unit 117.

  The recording unit 118 connected to the input / output interface 115 includes, for example, a hard disk, and records programs executed by the CPU 111 and various data. The communication unit 119 communicates with an external device via a network such as the Internet or a local area network.

  Further, the program may be acquired via the communication unit 119 and recorded in the recording unit 118.

  The drive 120 connected to the input / output interface 115 drives a removable medium 121 such as a magnetic disk, an optical disk, a magneto-optical disk, or a semiconductor memory, and drives programs and data recorded there. Etc. The acquired program and data are transferred to the recording unit 118 and recorded as necessary.

  As shown in FIG. 9, a program recording medium that stores a program that is installed in a computer and can be executed by the computer includes a magnetic disk (including a flexible disk), an optical disk (CD-ROM (Compact Disc-Read Only). Memory), DVD (Digital Versatile Disc), a magneto-optical disk, a removable medium 121 which is a package medium made of a semiconductor memory, or the like, a ROM 112 in which a program is temporarily or permanently stored, or a recording unit 118 It is comprised by the hard disk etc. which comprise. The program is stored in the program recording medium using a wired or wireless communication medium such as a local area network, the Internet, or digital satellite broadcasting via a communication unit 119 that is an interface such as a router or a modem as necessary. Done.

  In the present specification, the step of describing the program stored in the recording medium is not limited to the processing performed in chronological order according to the described order, but is not necessarily performed in chronological order. It also includes processes that are executed individually.

  The embodiments of the present invention are not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present invention.

It is a figure which shows the format of the flame | frame in DVB-S.2 specification. It is a block diagram which shows the structure of the conventional receiver. It is a figure explaining r on IQ plane. It is a block diagram which shows the structure of one Embodiment of the receiver to which this invention is applied. It is a block diagram which shows the detailed structure of a CSI calculation circuit. It is a figure which shows the example of a CSI fixed value table. It is a timing chart explaining operation | movement of a receiver. It is a block diagram which shows the detailed structure of a CSI calculation circuit. And FIG. 11 is a diagram illustrating a configuration of a personal computer.

Explanation of symbols

  51 receiver, 61 tuner, 62 AD converter, 63 channel equalizer, 64 synchronization circuit, 65 error correction decoder, 66 CSI calculation circuit, 71 high-precision CSI calculation circuit, 72 CSI fixed value table, 73 RDY signal generation Circuit, 74 selection circuit, 75 selection circuit, 91 high-speed CSI calculation circuit

Claims (6)

In a receiving apparatus that receives a modulated signal obtained by digitally modulating a carrier wave,
First channel state information used for likelihood calculation in soft decision decoding is calculated using a known section which is a section of a known symbol inserted in a demodulated signal obtained by demodulating the modulated signal. Channel state information calculating means;
Channel state information output means for outputting second channel state information that can be output faster than the first channel state information until the calculation of the first channel state information converges.
When the calculation of the first channel state information converges, the channel state information output means outputs the calculated first channel state information instead of the output second channel state information. Receiver device. Further comprising channel state information holding means for holding transmission information related to transmission of the modulated signal and the predetermined second channel state information in correspondence with each other.
The channel state information output means is a transmission obtained by decoding the known section from the second channel state information held until the calculation of the first channel state information converges. The receiving apparatus according to claim 1, wherein the second channel state information corresponding to the information is output. A second channel state information calculating unit that calculates the second channel state information using a main signal interval that is the known interval and a main signal symbol interval;
The receiving apparatus according to claim 1, wherein the channel state information output unit outputs the calculated second channel state information until calculation of the first channel state information converges. The channel state information output means replaces the output second channel state information with the calculated first channel state information when the variation of the calculated first channel state information falls within a predetermined range. The receiving apparatus according to claim 1, wherein one channel state information is output. The channel state information output means replaces the output second channel state information and outputs the calculated first channel when a predetermined time has elapsed after synchronization of the demodulated signal is established. The receiving device according to claim 1, which outputs status information. In a receiving method of a receiving apparatus that receives a modulated signal obtained by digitally modulating a carrier wave,
First channel state information used for likelihood calculation in soft decision decoding is calculated using a known section that is a section of a known symbol inserted in a demodulated signal obtained by demodulating the modulated signal,
Until the calculation of the first channel state information converges, the second channel state information that can be output faster than the first channel state information is output, and the calculation of the first channel state information is performed. A reception method including a step of outputting the calculated first channel state information in place of the output second channel state information when converged.

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