JP2006005490A - Decoding processor, and digital signal receiver comprising it - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a decoding processor in which the size and power consumption are reduced, and to provide a digital signal receiver comprising the decoding processor. <P>SOLUTION: A TS reproducing section 40 for monitoring the storage amount of data stream DTS being inputted to a data buffer 41 and outputting a predetermined amount of data packet DTP, at a time, from the data buffer 41 to an outer code decoding section 50 holds the data packet DTP stored in the data buffer 41 after the data packet DTP is read in by the outer code decoding section 50 for error detection before it is read in again for error correction. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a decoding processing device and a digital signal receiving device including the decoding processing device, and more particularly to a digital broadcasting receiving device for receiving a digital television broadcast.

  In recent years, digitalization plans for television broadcasting have been rapidly progressing worldwide. In particular, in digital television broadcasting, MPEG2 (Moving Picture Experts Group 2), MPEG4 (Moving Picture Experts Group 4), or H.264, which is an international standard for data compression / decompression, is used. By using H.264, it is possible to transmit a plurality of channels by a single repeater. As a result, the number of channels can be dramatically increased. This is expected to greatly improve user convenience.

  In the digital television broadcast as described above, in a system for transmitting video signals and audio signals, an orthogonal frequency division multiplexing system (hereinafter referred to as OFDM: Orthogonal Frequency Division Multiplexing system) excellent in high-quality transmission and improved frequency utilization efficiency. ) Has been proposed. This OFDM system is characterized by providing a large number of subcarriers in a band of one channel, and is a modulation system excellent in anti-multipath interference.

  In digital television broadcasting, after converting an analog television signal into a digital signal, the MPEG2 standard, MPEG4 standard, or H.264 standard is used. The compression encoding according to the H.264 standard is performed. At the time of this compression encoding, video signals and audio signals corresponding to a plurality of channels are MPEG2 standard or MPEG4 standard or H.264. It is multiplexed as transport stream data (hereinafter also simply referred to as TS data) according to the H.264 standard. TS data is configured as a single data stream by multiplexing encoded data corresponding to a video signal and an audio signal, respectively.

  The encoded data is subjected to an error correction process generally called an outer code and an inner code in order to perform error correction for protecting the data from transmission errors. For example, based on the provisional draft of the digital terrestrial system approved by the Telecommunications Technology Council of the Ministry of Posts and Telecommunications, the Reed-Solomon code, which is a representative example of the block code, is used as the outer code. A convolutional code combined with Viterbi decoding is used as the code.

  For encoded data, it further depends on interleaving processing to disperse the cause of errors in the transmission path such as noise and fading, and modulation schemes such as QPSK (Quadrature Phase Shift Keying) and 16QAM (Quadrature Amplitude Modulation). Mapping processing is performed.

  The encoded data subjected to such processing is subjected to Inverse Fast Fourier Transform (IFFT), and after orthogonal modulation, an RF (Radio Frequency) signal is transmitted as a broadcast radio wave.

  A conventional digital broadcast receiving apparatus (see, for example, Patent Document 1) that receives the digital television broadcast will be described with reference to FIGS.

  FIG. 4 is a schematic block diagram showing a configuration of a general digital broadcast receiving apparatus 500. FIG. 4 shows a portion related to reproduction of a video signal in the digital broadcast receiving apparatus.

  As shown in FIG. 4, a digital broadcast receiving apparatus 500 receives an antenna 1 that receives an RF signal transmitted based on the OFDM scheme, and encodes data corresponding to a desired channel from the RF signal received by the antenna 1. The channel selection unit 2 to extract, the inner code decoding unit 3 that performs inner code decoding of the encoded data from the channel selection unit 2, and the TS data to be transmitted in units of transmission packets in response to the inner code decoded encoded data TS reproduction unit 4, outer code decoding unit 5 that receives the output of TS reproduction unit 4 and performs outer code decoding, inner code decoding from outer code decoding unit 5 and encoded data obtained by outer code decoding in accordance with the MPEG2 standard And an MPEG decoding unit 6 for decoding. Then, the MPEG decoding unit 6 outputs a video signal to the display unit 7.

  FIG. 5 is a block diagram showing a more detailed configuration of a conventional general digital broadcast receiving apparatus 500. FIG. 5 shows a configuration related to the reproduction of a video signal based on the provisional draft of the digital terrestrial system that is typically approved by the “Digital Broadcasting System Committee” of the Telecommunications Technology Council of the Ministry of Posts and Telecommunications.

  As shown in FIG. 5, the digital broadcast receiving apparatus 500 receives an RF signal, which is a broadcast radio wave received by an antenna, and transmits a video signal corresponding to the selected channel to the display unit. The digital broadcast receiving apparatus 500 includes a tuner 11, an analog / digital conversion unit 12, an FFT unit 13, a frequency deinterleaving unit 14, a time deinterleaving unit 15, and a demapping unit 16.

  The digital broadcast receiving apparatus 500 further includes a bit deinterleaving unit 17, a Viterbi decoding unit 18, and a byte deinterleaving unit 19. In addition, the digital broadcast receiving apparatus 500 includes a TS reproduction unit 4, an outer code decoding unit 5, an MPEG decoding unit 6 that decodes encoded data according to the MPEG2 standard, and a digital / analog conversion unit 20.

  The bit deinterleave unit 17 receives the encoded data and cancels bit interleaving. The Viterbi decoding unit 18 performs inner code decoding by error correction using convolutional coding performed on the transmission side. As described above, convolutional coding combined with Viterbi decoding is generally performed for inner coding. The byte deinterleaving unit 19 receives the encoded data that has been subjected to the inner code decoding, and releases the byte interleaving.

  The encoded data subjected to the inner code decoding in this way is sent to the TS reproduction unit 4 as a data stream DTS according to the MPEG2 standard.

  Here, the conventional TS reproducing unit 4 will be described in detail. The TS reproduction unit 4 sends the data stream DTS from the byte deinterleave unit 19 to the outer code (RS) decoding unit 5 as a data packet DTP in units of transmission packets. Also, when the supply of the data stream DTS from the byte deinterleave unit 19 is interrupted and the data packet DTP cannot be transmitted, the TS reproducing unit 4 generates dummy data DMY and directly transmits it to the MPEG decoding unit 6.

  FIG. 6 is a block diagram showing a configuration of a conventional TS reproducing unit 4. As shown in FIG. 6, the conventional TS reproducing unit 4 includes a data buffer 22a for temporarily accumulating the data stream DTS from the byte deinterleaving unit 19, and a dummy data generating unit 22b for generating dummy data DMY. And a data selector 22c for selectively sending either the data packet DTP or the dummy data DMY to the MPEG decoding unit 6. The digital television broadcast signal includes a wider bandwidth than the actual signal bandwidth in order to effectively perform error correction, and samples extra for the guard interval time. For this reason, the digital broadcast signal includes an invalid signal as image data. The portion corresponding to the invalid signal is eliminated by the deinterleaving process for returning the interleaving process. Therefore, the supply of data to the TS playback unit 4 is interrupted during the period corresponding to the invalid signal. On the other hand, in order for the MPEG decoding unit 6 to operate normally, it is necessary to supply encoded data at a predetermined rate. Therefore, during the period when the supply of the data packet DTP is interrupted, dummy data according to the MPEG2 standard is transferred to the MPEG decoding unit 6. Need to supply.

Therefore, the data buffer 22a generates the control signal CSG according to the accumulation amount of the data stream DTS supplied from the byte deinterleave unit 19. When the data storage amount decreases and the data packet DTP cannot be generated, a control signal CSG for switching the connection of the data selector 22c to the dummy data generation unit 22b is sent. Thereby, dummy data DMY according to the MPEG2 standard generated by the dummy data generation unit 22b can be supplied to the MPEG decoding unit 6 during a period when the supply of the data packet DTP based on the broadcast radio wave is interrupted. Therefore, encoded data can be always supplied to the MPEG decoding unit 6 at a predetermined rate. Therefore, the decoding process in the MPEG decoding unit 6 can be executed normally. Further, as described in Patent Document 2, the outer code decoding unit 5 is provided with a buffer 101.
JP 2002-112271 (April 12, 2002) Japanese Patent No. 3178346 (Registered on April 13, 2001)

  The operation of each block in the conventional TS reproduction unit 4 and outer code decoding unit 5 will be described with reference to FIG. FIG. 7 is a chart showing the operation of each block. In FIG. 7, the horizontal axis is the time axis.

  The TS reproducing unit 4 receives data transmitted from the byte deinterleave unit 19 in a period 301 from T = t10 to T = t11. In addition, data is written in the data buffer 22a in the TS reproducing unit 40 in a period 302 from T = t10 to T = t11. When data is sent from the byte deinterleave unit 19, writing to the data buffer 22a is performed, so that the period 301 and the period 302 have the same length and the same timing.

  When the data input from the byte deinterleave unit 19 reaches a predetermined amount (data packet), the TS reproduction unit 4 performs writing to the outer code decoding unit 5 in a period 303 from T = t11 to T = t12. Therefore, the data buffer 22a outputs a data packet to the outer code decoding unit 5 in a period 304 from T = t11 to T = t12. Further, the outer code decoding unit 5 sets an internal register or the like based on a data packet input during a period 305 from T = t11 to T = t12. In the period 306 from T = t11 to T = t12, the buffer 101 in the outer code decoding unit 5 stores the input data packet.

  After inputting a predetermined amount of data packet, the outer code decoding unit 5 calculates an error position and an error value in the data packet during a period 307 from T = t12 to T = t13. During a period 308 from T = t12 to T = t13, the buffer 101 holds the input data packet.

  After the calculation of the error position and value is completed, the outer code decoding unit 5 takes out the data packet stored in the buffer 101 and corrects it in the period 309 from T = t13 to T = t14. In the buffer 101, the data packet is output in a period 310 from T = t13 to T = t14. As a result, in the period 311 from T = t13 to T = t14, the data selector 22c outputs the corrected data packet TSP to the MPEG decoding unit 6.

  After the output of the corrected data, the outer code decoding unit 5 operates until the next data packet is input from the data buffer 22a of the TS reproducing unit 4, that is, in the period 320 from T = t14 to T = t16. To stop.

  During the period from T = t10 to T = t13 in which the outer code decoding unit 5 does not output the data packet to the MPEG decoding unit 6 and the period 312 from T = t14 to the subsequent period, the data buffer 22a The CSG signal changes to L, and the data selector 22c outputs the dummy data DMY generated by the dummy data generating unit 22b to the MPEG decoding unit 6.

  The data in the data buffer 22a of the TS playback unit 4 is discarded after the period 304, that is, during the period 313 from T = t12 to T = t15.

  The data in the buffer 101 of the outer code decoding unit 5 is discarded after the period 310, that is, during the period 314 from T = t14 to T = t16.

  From T = t15, the next data input from the byte deinterleave unit 19 to the TS playback unit 4 starts.

  In the conventional digital broadcast receiving apparatus 500 as described above, as shown in FIG. 6, it is necessary to temporarily store data having a size equal to the data packet in the TS reproduction unit 4. That is, the data buffer 22a requires a memory of one packet size. Also in the outer code decoding unit 5, the buffer 101 corresponding to the size of one packet is used to calculate the error correction position and value after fetching the data of one packet of the data packet DTP output from the data buffer 22 a. Is required.

  As described above, in the conventional digital broadcast receiving apparatus 500, the data buffer 22a in the TS reproduction unit 4 and the buffer 101 in the outer code decoding unit 5 exist independently, and one packet of each transport stream. A storage device (buffer, memory, FIFO (First in First Out), etc.) corresponding to the size of 204 × 8 bits was required. For this reason, the circuit area is increased, which hinders downsizing of the circuit and low power consumption.

  In the above, the digital broadcast receiving apparatus has been described as an example. That is, in the decoding processing apparatus that decodes and outputs the error correction encoded data encoded by the conventional error correction code, the means for monitoring the data speed (above Storage means (corresponding to the data buffer 22a and the buffer 101) for storing data is required for each of the TS reproducing section 4) and the means for decoding error correction (corresponding to the outer code decoding section 5). Met. Therefore, in the conventional decoding processing device and the digital signal receiving device provided with the decoding processing device, the circuit area is increased, which hinders downsizing of the circuit and reduction in power consumption.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a decoding processing device that is reduced in size and consumes power, and a digital signal receiving device including the decoding processing device. It is in.

  As a result of intensive studies, the present inventors have discovered the following and completed the present invention. That is, when the operations of the TS reproduction unit 4 and the outer code decoding unit 5 are observed with reference to the operation chart shown in FIG. 7, during the period 310 during which the data packet after error correction is output from the buffer 101 in the outer code decoding unit 5 It is clear that the data buffer 22a of the TS playback unit 4 is not operating. It is also clear that the buffer 101 of the outer code decoding unit is not operating during the period 302 during which the data buffer 22a receives the DTS. In the period 304 during which the data buffer 22a of the TS reproduction unit 4 sends a predetermined amount of DTP to the outer code decoding unit 5, packet data having the same content is transferred from the data buffer 22a to the buffer 101. Obviously only. It is also clear that after the packet data is transferred from the data buffer 22a to the buffer 101, the contents of the buffer 22a do not change until the next DTS is input. Further, as shown in FIG. 6, by adjusting the operating frequency and the number of processes per clock, it is possible to end the outer code decoding process during the period when the data is not written to the data buffer 22a of the TS reproducing unit 4. It is. From these facts, the present inventors have found that the buffer 101 can be reduced.

  In order to solve the above-described problem, the decoding processing apparatus according to the present invention is a decoding processing apparatus that decodes and outputs error correction encoded data encoded by an error correction code, and the error input to a data storage unit. A stream adjustment unit that monitors the amount of correction encoded data stored and outputs the error correction encoded data by a predetermined amount from the data storage unit; and an error that reads a predetermined amount of the error correction encoded data from the data storage unit And error correction decoding means for detecting and correcting the error by reading the error correction encoded data used for the error detection from the data storage unit again, and decoding the error correction. The stream adjustment means comprises the error correction Until the decoding unit reads the error correction encoded data again, the predetermined amount of the error correction encoded data stored in the data storage unit is held. It is characterized in that.

  According to the above configuration, the stream adjusting unit reads a predetermined amount of corrected encoded data from the data storage unit, detects an error, and then rereads the predetermined amount of correction encoded data read for error detection from the data storage unit. That is, the data storage unit transmits the same data twice.

  Here, in a decoding processing apparatus that decodes and outputs conventional error correction encoded data, means for monitoring the data speed (corresponding to the stream adjustment means of the present invention) and means for decoding error correction (of the present invention) In this case, storage means for accumulating data is required.

  However, in the above configuration, since the error correction decoding means reads data from the data storage unit again, it is not necessary to store data in the error correction decoding means, and a storage device in the error correction decoding means is unnecessary. That is, according to the configuration of the present invention, one data storage unit can also function as a storage unit in the error correction decoding unit without deteriorating a function as a storage unit in the stream adjustment unit, which is an original function. it can. That is, the data storage unit can play the role of both of the two conventional storage means.

  Therefore, the storage device in the error correction decoding means can be reduced. Therefore, the decoding processing device can be reduced in size and weight, and the cost of the decoding processing device can be reduced. Further, power consumption in the decoding processing device can be reduced.

  In the decoding processing device according to the present invention, in addition to the above configuration, the stream adjustment unit receives the dummy data generation unit that generates dummy data, the data that has been decoded by the error correction, and the dummy data, and the data There may be provided data selection means for outputting either one to the data processing means that needs to accept data at a constant speed in accordance with the amount of the error correction encoded data stored in the storage section.

  According to the above configuration, when the amount of error correction coded data stored in the data storage unit is insufficient and the data processing unit cannot supply the decoded data, the dummy data is supplied to the data processing unit. it can. Therefore, the data processing means always receives one of the data, that is, it can receive data at a constant speed and can function normally.

  In addition to the above-described configuration, the decoding processing apparatus according to the present invention, when the error correction decoding unit reads the error correction encoded data again, again outputs a predetermined amount of correction encoded data to the stream adjustment unit. A retransmission request signal requesting output may be transmitted.

  According to the above configuration, the stream adjusting unit that has received the retransmission request signal can retransmit the error correction encoded data that has been sent once at the timing at which the retransmission request signal is received.

  Note that the error correction coded data may be retransmitted without the error correction decoding means making a retransmission request. That is, the timing at which a retransmission request will come within the stream adjustment means is calculated in advance, and at that timing, the stream adjustment means outputs the error correction coded data from the data storage unit to the error correction decoding means. It may be configured. This means that a retransmission request signal is made in the stream adjustment means.

  In order to solve the above problems, a digital signal receiving apparatus according to the present invention is a digital signal receiving apparatus which receives encoded data encoded according to a predetermined standard and further encoded by first and second error correction codes. Any one of the decoding processing devices for decoding the second error correction, and inner code decoding for decoding the first error correction for the received encoded data and transmitting the decoded data to the decoding processing device And encoded data decoding means for decoding the encoded data obtained by decoding the first and second error corrections according to the predetermined standard.

  According to the above configuration, since the decoding processing device that decodes the second error correction can be reduced in size, weight, and power saving, the digital receiving device can also be reduced in size and weight, and the manufacturing cost can be reduced. Can be reduced. Further, power saving can be achieved.

  In addition to the above-described configuration, the digital signal receiving apparatus according to the present invention has MPEG2 or MPEG4 or H.264 as the predetermined standard. It may be H.246 standard.

  In addition to the above configuration, the digital signal receiving apparatus according to the present invention may receive encoded data in which the first and second error corrections are respectively performed by convolutional coding and block coding.

  In addition to the above configuration, the digital signal receiving apparatus according to the present invention may be characterized in that the inner code decoding means decodes the first error correction by a Viterbi decoding process.

  Further, in the digital signal receiving device according to the present invention, in addition to the above configuration, the decoding processing device may decode the second error correction by Reed-Solomon decoding processing.

  According to these structures, this invention can be utilized suitably for the digital broadcast receiver which receives a digital television broadcast.

  As described above, the decoding processing apparatus according to the present invention monitors the storage amount of the error correction encoded data input to the data storage unit, and outputs the error correction encoded data by a predetermined amount from the data storage unit. A stream adjusting unit that reads a predetermined amount of the error correction encoded data from the data storage unit, detects an error, reads the error correction encoded data used for the error detection from the data storage unit again, and corrects the error. Error correction decoding means for decoding error correction, wherein the stream adjusting means stores a predetermined amount of the error correction stored in the data storage section until the error correction decoding means reads the error correction encoded data again. Holds encoded data.

  According to the above configuration, since the error correction decoding means reads data again from the data storage unit, it is not necessary to store data in the error correction decoding means, and a storage device in the error correction decoding means is unnecessary. That is, according to the configuration of the present invention, one data storage unit can also function as a storage unit in the error correction decoding unit without deteriorating a function as a storage unit in the stream adjustment unit, which is an original function. it can. That is, the data storage unit can play the role of both of the two conventional storage means.

  Therefore, the storage device in the error correction decoding means can be reduced. Therefore, the decoding processing device can be reduced in size and weight, and the cost of the decoding processing device can be reduced. Further, power consumption in the decoding processing device can be reduced.

  Hereinafter, an embodiment of the present invention will be described in detail with reference to FIGS. The present invention can be applied to an arbitrary decoding processing device that receives an encoded signal and a digital signal receiving device including the decoding processing device. In the following, as a preferred embodiment, a digital broadcast receiving apparatus (digital signal receiving apparatus) capable of receiving a broadcast signal of a digital broadcast television will be described as an example. The present invention is not limited to this.

  FIG. 2 is a block diagram showing a configuration of the digital broadcast receiving apparatus (digital signal receiving apparatus) 10 of the present embodiment. The digital broadcast receiving apparatus 10 receives an RF signal, which is a broadcast radio wave received by an antenna, and transmits a video signal corresponding to the selected channel to the display unit.

  As shown in FIG. 2, the digital broadcast receiving apparatus 10 includes a tuner 11, an analog / digital conversion unit 12, an FFT unit 13, a frequency deinterleaving unit 14, a time deinterleaving unit 15, and a demapping unit 16. A bit deinterleaving unit 17, a Viterbi decoding unit 18, a byte deinterleaving unit 19, a TS reproduction unit (stream adjustment unit) 40, an outer code (RS) decoding unit (error correction decoding unit) 50, and a decoding unit. 60 and a digital / analog converter 20.

  The tuner 11 receives the received RF signal, down-converts the frequency corresponding to the selected channel, and outputs a baseband signal.

  The analog / digital conversion unit 12 converts the baseband signal from an analog signal to a digital signal, and outputs real axis (I axis) data Bi and imaginary axis (Q axis) data Bq using Hilbert transform or the like.

  The FFT unit 13 receives the I-axis data Bi and the Q-axis data Bq, performs fast Fourier transform, converts the time-axis data into frequency-axis data, and outputs it. The frequency deinterleaving unit 14 cancels the frequency interleaving performed at the time of encoding in order to eliminate a specific frequency signal due to radio wave reflection or the like. The output of the frequency deinterleave unit 14 is transmitted to the time deinterleave unit 15. The time deinterleaving unit 15 cancels the time interleaving performed for anti-fading and the like. The I-axis data Bi and Q-axis data Bq subjected to frequency deinterleaving and time deinterleaving are sent to the demapping unit 16.

  The demapping unit 16 performs demodulation processing according to the modulation scheme. That is, the demapping unit 16 generates n-bit encoded data based on the combination of the I-axis data Bi and the Q-axis data Bq. The number of bits n is determined according to the modulation method. When QPSK, 16QAM and 64QAM modulation are used, 2 bits, 4 bits corresponding to one set of I-axis data Bi and Q-axis data Bq, respectively. Bit and 6-bit digital signals are respectively generated.

  In this way, encoded data corresponding to a desired channel is extracted from the RF signal.

  The bit deinterleaving unit 17 receives the encoded data output from the demapping unit 16 and cancels bit interleaving performed for the purpose of enhancing error resilience.

  The Viterbi decoding unit 18 performs inner code decoding by error correction using convolutional coding performed on the transmission side.

  The byte deinterleave unit 19 receives encoded data that has been Viterbi-decoded, that is, inner-code decoded, and cancels byte interleaving performed for the purpose of enhancing error resilience in the same way as bit interleaving.

  The encoded data subjected to the inner code decoding as described above is MPEG2 standard, MPEG4 standard or H.264. The data stream DTS according to the H.264 standard TS stream is sent to the TS playback unit 40.

  The TS reproduction unit 40 receives the data stream DTS from the byte deinterleaving unit 19, adjusts the TS data transmission packet unit, and transmits the TS data to the outer code decoding unit 5.

  The outer code decoding unit 5 receives the output of the TS reproduction unit 4 and performs outer code decoding.

  The decoding unit (data processing means) 60 is an MPEG2 standard, MPEG4 standard or H.264 standard. In accordance with the H.264 standard, inner code decoding from the outer code decoding unit 5 and encoded data subjected to outer code decoding are decoded.

  The digital / analog conversion unit 20 converts the decoded data sent from the decoding unit 60 from a digital signal to an analog signal and transmits the analog signal to the display unit.

  Next, the TS reproduction unit 40 and the outer code decoding unit 50 of this embodiment will be described with reference to FIG. In the present embodiment, the TS reproduction unit 40 and the outer code decoding unit 50 form a decoding processing device of the present invention. FIG. 1 is a block diagram showing the configuration of the TS playback unit 4 and the outer code decoding unit 50.

  As shown in FIG. 1, the TS reproducing unit 40 temporarily accumulates the data stream DTS that has been subjected to the inner code decoding and deinterleaving processing output from the byte deinterleaving unit 19, and transmits data packets for each transmission packet unit. A data buffer (data storage unit) 41 for outputting as DTP, MPEG2 standard or MPEG4 standard, or H.264 standard. A dummy data generation unit (dummy data generation unit) 42 that generates dummy data DMY according to the H.264 standard and a data selector (data selection unit) 43 are included.

  The data buffer 41 sends the stored data packet DTP to the outer code decoding unit 50.

  The outer code decoding unit 50 performs error correction by Reed-Solomon (RS) decoding of the data packet DTP output from the data buffer 41. Data that has been subjected to error correction by RS decoding in the outer code decoding unit 50 is input to the H side of the data selector 43. On the other hand, the dummy data DMY from the dummy data generation unit 22b is input to the L side of the data selector 43.

  The data buffer 41 stores the data packet DTP that has been sent once, and sends the stored data packet again to the outer code decoding unit 50 in accordance with the input of the retransmission request signal r. Further, the data buffer 41 generates a control signal CSG according to the accumulated data amount.

  The control signal CSG is set to the L level when the encoded data stored in the data buffer 22a is less than a predetermined amount and the data packet DTP cannot be output. On the other hand, when encoded data is accumulated in the data buffer 22a and the data packet DTP can be generated, the control signal CSG is set to the H level.

  The data selector 43 outputs either the output data from the outer code decoding unit 50 or the dummy data DMY to the decoding unit 60 in response to the retransmission request signal r. That is, when the data packet DTP based on the broadcast radio wave is generated, there is a retransmission request signal r, and the data selector 43 sends the encoded data packet TSP that has been error-corrected by the outer code decoding unit 50 to the decoding unit 60. Output. On the other hand, when the data packet DTP based on the broadcast radio wave is not generated corresponding to the period during which the invalid signal is transmitted, there is no retransmission request signal r, and the data selector 43 outputs the dummy data DMY to the decoding unit 60. . Note that there is a retransmission request signal r when the data packet DTP is generated, and there is no retransmission request signal r when the data packet DTP is not generated. Therefore, it can be said that the data selector outputs either one of the output data from the code decoding unit 50 and the dummy data DMY to the decoding unit 60 according to the accumulation amount.

  Thus, the encoded data is input to the decoding unit 60 at a predetermined rate. Therefore, the decoding process in the decoding unit 60 can be executed normally.

  The operation of the outer code decoding unit 50 is controlled in response to the control signal CSG. That is, when the control signal CSG is set to the L level, that is, when the transmission of the data packet DTP from the data buffer 41 is stopped, the operation of the outer code decoding unit 50 is stopped. Further, when the control signal CSG is set to the H level, that is, when the data packet DTP is transmitted from the data buffer 41, the outer code decoding unit 50 operates.

  The outer code decoding unit 50 transmits a retransmission request signal r to the data buffer 41 when error position and value calculation is completed and error correction is performed. The data buffer 41 sends the same data packet once sent to the outer code decoding unit 50 again according to the retransmission request signal r.

  The outer code decoding unit 50 performs error correction on the retransmitted data packet read from the data buffer 41 and sends it to the data selector 43.

  The operation of each block in the TS reproduction unit 40 and the outer code decoding unit 50 of this embodiment will be described with reference to FIG. FIG. 3 is a chart showing the operation of each block. In FIG. 3, the horizontal axis is the time axis.

  As shown in FIG. 3, the TS playback unit 4 receives data sent from the byte deinterleave unit 19 in a period 100 from T = t0 to T = t1. In addition, data is written into the data buffer 41 in the TS reproduction unit 40 in a period 102 from T = t0 to T = t1. When data is sent from the byte deinterleave unit 19, writing to the data buffer 41 is performed, so the period 100 and the period 102 have the same length and the same timing.

  In addition, when the data input from the byte deinterleave unit 19 reaches a predetermined amount (data packet), the TS reproduction unit 40 writes data to the outer code decoding unit 50 in a period 103 from T = t1 to T = t2. Do. Therefore, the data buffer 41 outputs the data packet DTP to the outer code decoding unit 5 during the period 104 from T = t1 to T = t2.

  The outer code decoding unit 5 performs internal register setting based on the data packet input during the period 105 from T = t1 to T = t2. Here, the internal register setting refers to setting of a flag indicating the presence / absence of an error in data, a parameter of a circuit for calculating an error position and a correction value.

  The outer code decoding unit 5 calculates an error position and an error value in the data packet DTP during a period 107 from T = t2 to T = t3 after inputting a predetermined amount of the data packet DTP (error detection). I do. Further, the data buffer 41 of the TS reproducing unit 4 outputs the data packet DTP once output from T = t2 to T = t3, that is, during the period 115 after the output to the outer code decoding unit 50 until the error correction starts. Keep holding.

  The retransmission request signal r is invalid during the period 117 from T = t0 to T = t3 and from T = 4 to T = t6 when the outer code decoding unit 50 does not output the data packet after decoding the error correction. Set to state. That is, no retransmission request signal is transmitted during the period 117.

  The outer code decoding unit 50 decodes error correction for the data packet DTP output from the data buffer 41 during the period 109 from T = t3 to T = t4, and then outputs the decoded data to the decoding unit 60. Therefore, the retransmission request signal r is set to a valid state during the period 110 from T = t3 to T = t4.

  The data buffer 41 receives the retransmission request signal r, and again outputs the held data packet DTP in the period 316 from T = t3 to T = t4. Thus, in the period 111 from T = t3 to T = t4, the data selector 43 outputs the error-corrected data packet TSP from the outer code decoding unit 5 to the decoding unit 60.

  During the period 120 from T = t4 to T = t6 after the correction data is output, the outer code decoding unit 5 operates until the next data packet is input from the data buffer 41 of the TS reproducing unit 40. Stop.

  Then, the data selector 43 transmits the retransmission request signal r during the period 112 from T = t0 to T = t3 and T = t4 to T = t6 when the outer code decoding unit 50 does not output the data packet to the decoding unit 60. Is invalid, the dummy data DMY generated by the dummy data generation unit 42 is output to the decoding unit 60.

  The data packet DTP output twice in the data buffer 41 is discarded in the period 119 from T = t4 to T = t5 after the period 116. Therefore, the next data packet can be input to the data buffer 41. After T = t5, the input of the next data stream from the byte deinterleave unit 19 starts. The above operation is repeated.

  As described above, according to the configuration of the TS reproducing unit 40 and the outer code decoding unit 50 of the present embodiment, the data buffer 41 of the TS reproducing unit 40 does not impair the original function, and the conventional outer code shown in FIG. It can play a role corresponding to the buffer 101 of the decoding unit 5. Therefore, the number of buffers 101 can be reduced, the number of circuits can be reduced, and the LSI size in the digital broadcast receiving apparatus 10 can be reduced. That is, the cost of LSI can be reduced. Further, power consumption can be reduced.

  In this embodiment, the outer code decoding unit 50 transmits the retransmission request signal r. However, the data packet DTP is retransmitted from the data buffer 41 to the outer code decoding unit 50 without transmitting the retransmission request signal r. It may be like this. That is, the TS playback unit 40 may calculate in advance the timing at which a retransmission request will be received, and output the data packet DTP from the data buffer 41 to the outer code decoding unit at that timing. In other words, this configuration makes a retransmission request signal in the TS reproduction unit 40.

  The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope shown in the claims. That is, embodiments obtained by combining technical means appropriately modified within the scope of the claims are also included in the technical scope of the present invention.

  The present invention can be used in the field of signal processing such as information communication, optical pickup, and magneto-optical pickup. For example, the present invention can be used for mobile communication terminals, digital home appliances, space communication, etc. in addition to the above digital broadcast receiving apparatus.

It is a block diagram which shows the structure of TS reproduction | regeneration part and outer code decoding part which concerns on embodiment of this invention. It is a block diagram which shows the structure of the digital broadcast receiver which concerns on embodiment of this invention. It is a figure which shows the chart of operation | movement of each block of the said stream adjustment means and an outer code decoding part. It is a block diagram which shows the structure of the conventional digital broadcast receiver. It is a block diagram which shows the further detailed structure of the conventional digital broadcast receiver. It is a block diagram which shows the structure of TS reproduction | regeneration part and an outer code decoding part in the conventional digital broadcast receiver. It is a figure which shows the chart of operation | movement of each block of the TS reproduction | regeneration part and outer code decoding part in the conventional digital broadcast receiver.

Explanation of symbols

10 Digital broadcast receiver (digital signal receiver)
40 TS playback unit (stream adjustment means)
41 Data buffer (data storage unit)
42 Dummy data generation unit (dummy data generation means)
43 Data selector (data selection means)
50 Outer code decoding unit (error correction decoding means)
60 Decoding unit (data processing unit)
r Retransmission request signal DTS Data stream DTP Data packet DMY Dummy data

Claims (8)

In a decoding processing apparatus for decoding and outputting error correction encoded data encoded by an error correction code,
Stream adjustment means for monitoring the amount of error correction encoded data input to the data storage unit and outputting the error correction encoded data by a predetermined amount from the data storage unit;
A predetermined amount of the error correction encoded data is read from the data storage unit to detect an error, and the error correction encoded data used for the error detection is read from the data storage unit again to correct the error, thereby decoding the error correction. Error correction decoding means,
The stream adjustment unit holds a predetermined amount of the error correction encoded data stored in the data storage unit until the error correction decoding unit reads the error correction encoded data again. . The stream adjusting means includes dummy data generating means for generating dummy data,
Data processing that receives data decoded by the error correction and the dummy data and accepts data at a constant rate according to the amount of the error correction encoded data stored in the data storage unit 2. The decoding processing apparatus according to claim 1, further comprising a data selection means for outputting to the means. The error correction decoding means includes
The retransmission request signal for requesting the stream adjustment unit to output a predetermined amount of the error correction encoded data again when the error correction encoded data is read again. The decoding processing device according to 1 or 2. In a digital signal receiving apparatus for receiving encoded data encoded according to a predetermined standard and further encoded by first and second error correction codes,
The decoding processing apparatus according to any one of claims 1 to 3, which decodes the second error correction;
Inner code decoding means for decoding the first error correction for the received encoded data and transmitting the decoded data to the decoding processing device;
A digital signal receiving apparatus comprising: encoded data decoding means for decoding the encoded data obtained by decoding the first and second error corrections according to the predetermined standard.   The predetermined standard is MPEG2, MPEG4, or H.264. 5. The digital signal receiving apparatus according to claim 4, which is 246 standard.   6. The digital signal receiving apparatus according to claim 4, wherein the first error correction and the second error correction receive encoded data respectively performed by convolutional encoding and block encoding.   The digital signal receiving apparatus according to claim 4, wherein the inner code decoding unit decodes the first error correction by a Viterbi decoding process.   The digital signal receiving apparatus according to claim 4, wherein the decoding processing apparatus decodes the second error correction by a Reed-Solomon decoding process.

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