JP4073863B2 - Decoding circuit and digital broadcast receiving apparatus - Google Patents

Description

  The present invention relates to a digital broadcast receiving apparatus, and more particularly to a digital broadcast receiving apparatus adopting an OFDM (Orthogonal Frequency Division Multiplexing) modulation scheme as a modulation scheme.

  Usually, in digital broadcasting, a packet multiplexing method is adopted as a data transmission method. For example, a transport stream is disclosed as a multiplexed stream of a packet multiplexing system (Non-Patent Document 1).

  In the transport stream (TS), the TS packet shown in FIG. 6A is error-protected by a Reed-Solomon code (RS code) as shown in FIG. It is designed to transmit by cable.

  Normally, TS packets during transmission are divided into layers during digital modulation. For example, when an OFDM (Orthogonal Frequency Division Multiplexing) modulation system is used as a digital modulation system, as shown in FIG. 7, data in one OFDM frame includes a set of a synchronization byte S, information I, and parity P. Are divided into transmission TS packets. At the time of this layer division, the synchronization byte is moved backward, so the receiving side needs to move the synchronization byte at the end of each transmission TS packet to the beginning when combining the received transmission TS packets. There is.

  Such transmission TS packet combining processing is generally performed in a TS reproduction circuit. For example, the TS reproduction circuit shown in FIGS. 10 and 11 is used.

  FIG. 10 is a schematic block diagram showing a part of an OFDM modulation type digital broadcast receiving apparatus, and shows a TS packet layer synthesis unit.

  In the digital broadcast receiving apparatus shown in FIG. 10, first, the energy-spread input packet (transmission TSP) is decoded by the energy despreading block 111 and sent to the TS playback block 112. In the TS reproduction block 112, the synchronization byte at the end of the packet is moved to the beginning to reproduce the packet, and the changed packet is sent to the Reed-Solomon decoding block 113. The packet described here has a structure of 204 words (204 bytes) of 8 bits per word shown in FIG.

  In this TS reproduction block 112, the TS packet sent from the energy despreading block 111 in the format shown in FIG. 8 and at the timing shown in FIG. 9 is moved to the head of the synchronization byte at the end of the packet. After changing to the same packet structure as the MPEG2 TS format as shown in FIG. 12, the packet is sent to the Reed-Solomon decoding block 113 in the next stage. In the Reed-Solomon decoding block 113, error correction of input packet data is performed, and the packet data having the format shown in FIG. 12 is sent to the next stage at the timing shown in FIG.

  FIG. 11 is a schematic block diagram showing a part of an OFDM modulation type digital broadcast receiving apparatus in the case where a device requesting continuous TS packets for input is connected to the subsequent stage because the TS packet valid flag cannot be received. is there. In addition, the same code | symbol is attached | subjected to the member of the same code | symbol as the block diagram shown in FIG. 10, and the description is abbreviate | omitted.

  In the digital broadcast receiving apparatus shown in FIG. 11, the TS reproduction circuit 112 automatically creates a null packet by the null packet generation circuit 114 until the output of the Reed-Solomon decoding block 113 is equal to one packet. Is sent to the next stage at the timing shown in FIG.

  By the way, as described above, in order to synthesize a hierarchically divided transmission TS packet in the Reed-Solomon decoding block 113, it is necessary to move the synchronization byte at the end of the transmission TS packet to the beginning. This is because the Reed-Solomon decoding block 113 is initialized by inputting the leading synchronization byte.

  The TS reproduction block 112 performs this synchronization byte movement operation, and is realized by, for example, the circuit shown in FIG. That is, in the transmission TS packet input to the TS reproduction block 112, when the portion other than the synchronization byte is stored in the recording device 121 and the synchronization byte is detected by the synchronization byte detection block 122, the switching element 123 is only the synchronization byte. After that, the part other than the synchronization byte stored in the recording device 121 is output.

  In the TS packet processed in this way, as shown in FIG. 13B, the portions other than the head synchronization byte (packet data and parity) are moved as they are after the synchronization byte.

  Specifically, in order to move the last byte of the packet arriving at the TS playback block, that is, the synchronization byte attached to the 204th byte to the head, a storage device for 203 bytes as shown in FIG. 121 is prepared, and 203 bytes of data stored in the storage device 121 after the final synchronization byte is output are transmitted.

  In addition to the above, as a method of moving the synchronization byte of the transmission TS packet, for example, as shown in FIG. 14, there is a method of moving the synchronization byte at the end of the immediately preceding TS packet to the beginning of the next TS packet. is there.

Specifically, as shown in FIG. 14, the last byte of the immediately preceding packet is moved to the beginning of the next packet.
Japan Radio Industry Standard ARIB-STD-B24 "Data Broadcast Coding and Transmission Schemes in Digital Broadcasting" Version 3.0 (Published January 2002)

  However, any of the conventional methods for moving the synchronization byte at the end of the transmitted TS packet requires a large-scale storage device such as a shift register or a memory used for moving the synchronization byte, and the cost And the problem of increased power consumption arises.

  The present invention has been made in view of the above-described problems, and its purpose is to appropriately decode a transmission TS packet without moving a synchronization byte at the end of the transmission TS packet. As a result, it is possible to reduce the size of the circuit of the memory device and the size of the entire circuit, and as a result, provide a decoding circuit and a digital broadcast receiving device that can reduce manufacturing costs and power consumption of the entire circuit. There is to do.

  In order to solve the above problems, a decoder according to the present invention includes a decoder that decodes an encoded packet, and the value of the first byte of the packet or the head before the packet is input to the decoder. It is characterized by comprising initialization state setting means for setting the decoder to an initialization state based on a value included from a byte to an arbitrary byte.

  The initialization state setting means may set the values of all registers in the decoder to 0.

  The initialization state setting means may set the values of all registers in the decoder to predetermined values.

  In order to solve the above-described problem, the decoder according to the present invention includes a Reed-Solomon decoder that decodes a multiplexed transport stream packet and a value of the first byte of the transport stream packet or an arbitrary byte from the first byte. An initialization state setting means for setting the Reed-Solomon decoder to an initialization state before the transport packet is input to the Reed-Solomon decoder based on the values included in It is characterized by.

  In order to solve the above problems, a digital broadcast receiving apparatus according to the present invention is a digital broadcast receiving apparatus including a Reed-Solomon decoder that decodes a multiplexed transport stream packet. An initialization that sets the Reed-Solomon decoder to an initialization state before the transport packet is input to the Reed-Solomon decoder based on the value of or the value included from the first byte to an arbitrary byte It is characterized by having state setting means.

  As described above, the decoding circuit according to the present invention decodes the packet based on the value of the first byte of the packet or the value included from the first byte to an arbitrary byte before the packet is input to the decoder. Since the initialization state setting means for setting the device to the initialization state is provided, it is not necessary to separately generate an initialization signal for initializing the decoder. As a result, it is possible to reduce the number of circuits for generating the initialization signal and to reduce the power consumption associated with this circuit, so that the scale of the circuit including the decoder can be reduced and the power can be saved. .

  Also, since the decoder is initialized before the packet is input, as in the conventional case, the packet must be initialized at the same time as the packet is input to the decoder. There is no need to add a sync byte. Accordingly, since a processing circuit for adding the synchronization byte to the head of the packet is not required, the scale of the circuit including the decoder can be reduced, and as a result, the manufacturing cost can be reduced. There is an effect that can be done.

  The value of the first byte of the packet or the value included from the first byte to an arbitrary byte may be a constant value in all packets decoded by the same decoder.

  Here, the initial state of the decoder means a state in which the value of a register (storage unit) inside the decoder is set to 0 or a predetermined value.

  When the decoding circuit is used in a digital broadcast receiving apparatus, for example, it is conceivable to use a transport stream packet as the packet and a Reed-Solomon decoder as the decoder.

  That is, the decoding circuit according to the present invention inputs the transport packet to the Reed-Solomon decoder based on the value of the first byte of the transport stream packet or the value included from the first byte to an arbitrary byte. By providing the initialization state setting means for setting the Reed-Solomon decoder to the initialization state in advance, the circuit can be reduced and the power consumption can be reduced.

  Further, the digital broadcast receiving apparatus according to the present invention may send the transport packet to the Reed-Solomon decoder based on the value of the first byte of the transport stream packet or a value included from the first byte to an arbitrary byte. By providing an initialization state setting means for setting the Reed-Solomon decoder to an initialization state before being input, it is possible to reduce the size of the device and reduce power consumption.

  The embodiment of the present invention will be described as follows.

  The digital broadcast receiving apparatus according to the present embodiment employs an OFDM (Orthogonal Frequency Division Multiplexing) modulation scheme, and employs a transport stream as a multiplexed stream of a packet multiplexing scheme as a data transmission scheme. As shown in FIG. 2, an OFDM demodulator 1 and a baseband processor 2 are provided. The baseband processing unit 2 is the same as a baseband processing circuit provided in a general digital broadcast receiving apparatus, and thus detailed description thereof is omitted.

  First, the transport stream packet (hereinafter referred to as a TS packet) input to the OFDM demodulator 1 will be described, and then the details of the OFDM demodulator 1 will be described.

  As described in the section of the prior art, the TS packet is obtained by layering the transport stream for one frame of OFDM shown in FIG. 7 and has the packet structure shown in FIG.

  That is, as shown in FIG. 8, the TS packet has a packet structure in which a valid packet of 187 bytes is arranged at the beginning, a parity of 16 bytes is arranged next, and a synchronization byte of 1 byte is arranged at the end. ing.

  Normally, a TS packet to be decoded by a Reed-Solomon decoding circuit has a synchronization byte placed at the beginning, followed by a data portion (valid packet), as shown in FIG. 6B, and a parity at the end. It has a packet structure in which parts are arranged.

  By the way, in order to obtain the packet structure of the TS packet shown in FIG. 6B, the synchronization byte must be moved from the packet structure shown in FIG.

  However, in the present embodiment, the Reed-Solomon decoding unit (decoding circuit) 19 included in the OFDM demodulating unit 1 inputs the TS packet having the packet structure shown in FIG. 8 as it is to perform decoding. ing.

  Next, the OFDM demodulator 1 will be described below.

  As shown in FIG. 2, the OFDM demodulator 1 includes a QPSK unit 11, a 16QAM unit 12, a frequency / time deinterleave unit 13, a bit deinterleave unit 14, a depunctured unit 15, a Viterbi decoding unit 16, a byte deinterleave unit. The configuration includes a unit 17, an energy despreading unit 18, and a Reed-Solomon decoding unit 19.

  The QPSK unit 11, the 16QAM unit 12, the frequency / time deinterleaving unit 13, the bit deinterleaving unit 14, the depunctured unit 15, the Viterbi decoding unit 16, the byte deinterleaving unit 17, and the energy despreading unit 18, Since it is the same as a general OFDM demodulation circuit, description of each part is omitted.

  Among the parts of the OFDM demodulator 1, the difference from a general OFDM demodulator is the configuration of a Reed-Solomon decoder 19 that performs Reed-Solomon decoding on a signal (TS packet) output from the energy despreader 18. It is.

  As shown in FIG. 1, the Reed-Solomon decoding unit 19 includes a Reed-Solomon decoder 24 and an initialization device (initialization state setting means) 25 that initializes an internal register of the Reed-Solomon decoder 24. Yes.

  As shown in FIG. 3, the Reed-Solomon decoder 24 has a syndrome calculation unit 20, an error number calculation unit 21, an error position calculation unit 22, and an error correction calculation unit 23.

  That is, in the Reed-Solomon decoding unit 19, the input data is first input to the syndrome calculation unit 20, and information for determining the error position of the data and its value is obtained. Based on this information, the error number calculation unit 21 and the error position calculation unit 22 obtain the data error position and its value. Thereafter, the error correction calculation unit 23 corrects the data error and outputs it as output data. Each of these parts is used for a general Reed-Solomon decoder.

  The Reed-Solomon decoder is provided with an internal register which is a temporary storage area in which the above-described syndrome calculation unit 20, error number calculation unit 21, error position calculation unit 22, and error correction calculation unit 23 perform calculation processing.

  Before the TS packet as the input data is input to the Reed-Solomon decoder 24, the initialization device 25 determines the value based on the value of the first byte of the packet or the value included from the beginning to an arbitrary byte. The Reed-Solomon decoder 24 is set to an initialized state.

  That is, the initialization device 25 generates an initialization signal based on the value of the first byte of the TS packet or the value included from the beginning to an arbitrary byte, and sends this initialization signal to the Reed-Solomon decoder 24. As a result, the internal register is initialized.

  Here, the initialization is to set the value of the internal register to zero. The initialization here includes not only setting the value of the internal register to 0 but also setting it to an arbitrary value calculated in advance. For example, in the case of terrestrial digital broadcasting, the pre-calculated value is 0 × 47h in 8 bits. Note that the above calculation is performed before the Reed-Solomon decoder is mounted on the circuit, and is not performed during the initialization operation.

  Further, the initialization device 25 uses the value of the first byte of the TS packet before being input to the Reed-Solomon decoder 24 or the value included from the first to an arbitrary byte in order to generate the initialization signal. is doing. That is, if the values of these bytes indicate a constant value in each packet, the same initialization signal can always be generated, and the Reed-Solomon decoder 24 can always be initialized at the same timing. .

  The initialization operation of the Reed-Solomon decoding unit 19 by the initialization device 25 will be described below.

  As shown in FIG. 3, initialization circuits 20 a to 23 a are connected to each block of the Reed-Solomon decoding unit 19. These initialization circuits 20a to 23a are adapted to receive an initialization signal from the initialization device 25. Based on this initialization signal, the initialization circuit 20a to 23a sets an initial value for each block of the Reed-Solomon decoding unit 19. The signal to give is output.

  That is, the initialization device 25 calculates the initialization timing of each block in the Reed-Solomon decoding unit 19 from the input data, and sends an initialization signal to the initialization circuits 20a to 23a connected to each block. Upon receiving this initialization signal, each of the initialization circuits 20a to 23a initializes each connection destination block.

  The initialization signal is sent from the initialization device 25 when the leading synchronization byte included in the input data arrives at the Reed-Solomon decoding unit 19 or when the previous packet data processing in the Reed-Solomon decoding unit 19 is completed. Any period during which the operation of each block has been completed after the first synchronization byte of the next packet data reaches the Reed-Solomon decoding unit 19 can be used.

  Here, the decoding operation in the Reed-Solomon decoding unit 19 will be described below.

  First, from the energy despreading unit 18, three types of signals, TS packet data, TS data valid flag, and head data flag, are input to the Reed-Solomon decoding unit 19 in synchronization with the rising edge of the clock CLK.

  The Reed-Solomon decoder 19 calculates synchronization data by the initialization device 25 before receiving the TS head flag, and sets the Reed-Solomon decoder (internal register) 24 to the initialized state. Receiving Solomon decoding is performed by receiving 203-byte TS packet data from the time when the TS valid flag and the TS head flag are input. The decoding results are output in the same order.

  The timing of data output from the Reed-Solomon decoding unit 19 is performed based on the timing chart shown in FIG.

  That is, the Reed-Solomon decoding unit 19 outputs the TS packet, the output valid flag, and the output head flag at the rising edge of the clock CLK. An output head flag is output in synchronization with the output timing of the head data of the TS packet that has been subjected to Reed-Solomon decoding. The output data is valid when the output valid flag is valid. The output valid flag varies depending on the OFDM modulation method.

  Since the TS leading byte flag of the TS packet sent from the energy despreading unit 18 becomes valid before the last synchronization data is moved, the second byte data from the beginning of the TS packet is actually Reed-Solomon decoded. It is sent to the part 19. However, since the Reed-Solomon decoding unit 19 has already calculated the synchronization data of the first byte (initialized state), it is possible to sequentially input a total of 203 bytes of data from the second byte to the 204th byte from the top. It is possible to correctly decode.

  In the decoding method in which the encoded packet is decoded by the decoder, the decoding method includes the value of the first byte of the packet or the first byte to an arbitrary byte before the packet is input to the decoder. Initializing the decoder based on the value being stored.

  The block diagram shown in FIG. 1 is a configuration showing an embodiment in one-segment reception called partial reception. After the energy despreading unit 18, TSs of a plurality of layers essential in the multi-segment reception system are collected. A circuit for forming one TS is omitted.

  That is, in this partial reception-only system, the TS reproduction block only moves the synchronization data that comes after the packet output from the energy despreading unit 18 to the beginning of the packet. Therefore, when the Reed-Solomon decoder of the present invention is incorporated in this system, the output of the energy despread block can be directly input to the Reed-Solomon decoder without going through the TS reproduction block.

  Therefore, in comparison with the block diagram of the prior art shown in FIG. 10, it is possible to delete the TS playback block in the present invention.

  Therefore, since data storage / movement in the TS playback block is not required and a storage device is not required, the circuit can be reduced, the LSI size can be reduced, that is, the cost of the LSI can be reduced, and the power consumption can be reduced. Is possible.

  Further, in the one-segment reception dedicated circuit, the TS reproduction block in the previous stage of the Reed-Solomon decoding unit 19 is not required as seen in the configuration shown in FIG. As a result, the circuit scale can be reduced and the power consumption can be reduced.

  In addition, even when the Reed-Solomon decoding unit 19 of the present invention is used in the configuration of the prior art shown in FIG.

  Furthermore, it goes without saying that the present invention is effective not only in the one-segment partial reception but also in the multi-segment reception, thereby reducing the storage device.

  For example, as a digital broadcast receiving apparatus that performs multi-segment reception, for example, as shown in FIG. 4, a digital signal in which a layer division / combination processing unit 41 is provided before the Viterbi decoding unit 16 of the OFDM demodulation unit 1 shown in FIG. A broadcast receiving apparatus can be considered.

  The hierarchical division / synthesis processing unit 41 includes a hierarchical division circuit 42 that divides input data into an arbitrary number of hierarchies, and a hierarchical synthesis circuit 45 that synthesizes the hierarchically divided data. Between the synthesis circuit 45, depunctured circuits 43a to 43x and hierarchy buffers 44a to 44x corresponding to the number of divided hierarchies are provided.

  As shown in FIG. 5, the hierarchy synthesis circuit 45 includes a switching circuit for outputting data from each hierarchy in time series. As a result, the data of different hierarchies are switched and combined into one and output to the Viterbi decoding unit 16 at the subsequent stage. Note that the switching timing by the switching circuit may be a specific timing according to the broadcast standard.

  The hierarchical synthesis circuit 45 shown in FIG. 5 is an example, and is not particularly limited as long as it is a circuit that can combine hierarchically divided data into one.

  Even with the above configuration, the TS packet input to the Reed-Solomon decoding unit 19 has the packet structure shown in FIG. it can.

  In this embodiment, the initialization signal is generated by the initialization device 25 using the value included in the first byte of the TS packet. However, as described above, not only the first byte of the TS packet is generated. The initialization device 25 may generate an initialization signal with a value included from the first byte to an arbitrary byte.

  Note that when an arbitrary byte is replaced with a byte of the entire packet, the Reed-Solomon decoder itself is not necessary. For example, if the data in the packet is referred to and a calculation result prepared in advance is output for a specific pattern, the Reed-Solomon decoder becomes unnecessary.

  In the present embodiment, the transport stream packet having a fixed packet length is described as the multiplexed packet. However, the present invention is not limited to this, and the decoder is used at the head of the packet. This is effective when it is necessary to set the packet to the initial state, for example, and can be applied to a program stream having a variable packet length as another multiplexed packet.

  In this embodiment, the case where Reed-Solomon coding is applied as an error correction method has been described. However, the present invention is not limited to this, and a packet including a fixed value data at the head is processed. It can be applied in the case of Other error correction methods to which the present invention can be applied include, for example, a cyclic redundancy code (CRC).

  Furthermore, although the present embodiment has been described with respect to the OFDM modulation scheme mainly used in the broadcasting field as the modulation scheme, the present invention is not limited to this and can be applied to other modulation schemes. It is. For example, the present invention can be applied to a modulation method used in optical communication, wireless / wired communication, and can also be applied to a modulation method in reproducing a storage medium such as a magnetic disk.

  In the present embodiment, the terrestrial digital broadcast receiving device is assumed as the digital broadcast receiving device. However, the present invention is not limited to this and can also be applied to a satellite digital broadcast receiving device. It is.

  The present invention is applied to satellite digital broadcast receivers and cable television receivers premised on packet transmission, but besides this, in the same field as error correction applied in digital broadcast receivers, For example, the present invention can also be applied to recording media using magnetism (flexible disk, HDD, magnetic card) and light (CD, MD, DVD) and network communication.

1, showing an embodiment of the present invention, is a block diagram illustrating a main configuration of a decoding circuit. FIG. It is a block diagram which shows the digital broadcast receiver provided with the decoding circuit shown in FIG. FIG. 3 is a block diagram showing a main configuration of a Reed-Solomon decoder in the decoding circuit shown in FIG. 1. FIG. 3 is a block diagram illustrating a main configuration of a layer division / combination processing unit when a transport stream is layered in the digital broadcast receiving apparatus illustrated in FIG. 2. FIG. 5 is a block diagram showing a main configuration of a hierarchical synthesis circuit that constitutes the hierarchical division / synthesis processing unit shown in FIG. 4. (A) is a figure which shows the packet structure of TS packet before error protection, (b) is a figure which shows the packet structure of the state which performed error protection with respect to TS packet shown to (a). It is a figure which shows the state which carries out the hierarchy division | segmentation of the transport stream in an OFDM modulation system. It is a figure which shows the packet structure of the TS packet immediately after the hierarchy division | segmentation shown in FIG. FIG. 9 is a timing chart showing the timing of each signal when the TS packet having the packet structure shown in FIG. 8 is input to the Reed-Solomon decoder. It is a block diagram which shows the principal part structure of TS reproduction | regeneration part vicinity of the conventional OFDM receiving system. It is a block diagram which shows the principal part structure of TS reproduction | regeneration part vicinity of the other conventional OFDM receiving system. It is a figure which shows the packet structure of the TS packet of the state which moved the synchronous byte of TS packet to the head in the TS reproduction | regeneration part shown in FIG. 11 or FIG. (A) is a block diagram showing a circuit for moving the sync byte to the head in the TS playback section, and (b) is a diagram showing a state where the sync byte has been moved to the head by the circuit of (a). It is a figure which shows the other method for moving a synchronous byte to the head in TS reproduction | regeneration part. FIG. 11 is a timing chart of signals sent from the TS playback block to the Reed-Solomon block decoder in the reception system shown in FIG. 10. 12 is a timing chart of signals sent from the TS playback block to the Reed-Solomon block decoder in the reception system shown in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 OFDM demodulation part 2 Baseband process part 11 QPSK part 12 16QAM part 13 Frequency / time deinterleaving 14 Bit deinterleaving part 15 Depunctured part 16 Viterbi decoding part 17 Byte deinterleaving part 18 Energy despreading part 19 Reed-Solomon decoding Part (decoding circuit)
DESCRIPTION OF SYMBOLS 20 Syndrome calculation part 21 Error number calculation part 22 Error position calculation part 23 Error correction calculation part 24 Reed-Solomon decoder (decoder)
25 Initialization device (initialization state setting means)

Claims (5)

A decoder for decoding a packet with a synchronization byte at the end ;
Before the packet is input to the decoder with the synchronization byte placed at the end , based on the value of the first byte of the packet or the value included from the first byte to an arbitrary byte , A decoding circuit comprising: an initialization state setting means for generating an initialization signal for initializing a decoder and outputting the generated initialization signal to the decoder. 2. The decoding circuit according to claim 1, wherein the initialization state setting means sets all register values in the decoder to 0 in response to the initialization signal . 2. The decoding circuit according to claim 1, wherein the initialization state setting means sets values of all registers in the decoder to predetermined values in accordance with the initialization signal . A Reed-Solomon decoder for decoding a transport stream packet in which a packet having a synchronization byte at the end is multiplexed;
Before the transport packet is input to the Reed-Solomon decoder with the synchronization byte placed at the end, it is included in the value of the first byte of the transport stream packet or from the first byte to an arbitrary byte. An initialization state setting means for generating an initialization signal for initializing the Reed-Solomon decoder on the basis of a predetermined value and outputting the generated initialization signal to the Reed-Solomon decoder. A characteristic decoding circuit. In a digital broadcast receiving apparatus including a Reed-Solomon decoder for decoding a transport stream packet in which a packet in which a synchronization byte is arranged at the end is multiplexed,
Before the transport packet is input to the Reed-Solomon decoder with the synchronization byte placed at the end, it is included in the value of the first byte of the transport stream packet or from the first byte to an arbitrary byte. And an initialization state setting means for generating an initialization signal for initializing the Reed-Solomon decoder based on a predetermined value and outputting the generated initialization signal to the Reed-Solomon decoder. Digital broadcast receiver.

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