JP2002204274A - Data receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data receiver in which the scale of a serial-to-parallel conversion circuit for transmitting a Viterbi decode signal to a Leed-Solomon decoding circuit is reduced. SOLUTION: For instance, in a BS(Broadcasting Satellite) digital broadcasting, there are one case where the Viterbi decode signal is outputted with one-bit width and the other case where the Viterbi decode signal is outputted with two-bit width according to a modulation method. When the Viterbi decode output is given with the one-bit width as serial data D0, a data converting part 242 alternately transmits the data to shift registers 256 and 258. The shift registers 256 and 258 then, alternately shift the data. When the Viterbi output signal is given with the two-bit width of D0 and D1, the shift registers 256 and 258 are synchronized with a serial clock and respectively shift the data D1 and D0.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data receiving apparatus, and more particularly, to a digital broadcast receiving apparatus for receiving a digital television broadcast.

[0002]

2. Description of the Related Art In recent years, BS digital broadcasting, which has begun broadcasting, employs two error correction systems, a convolutional code and a block code. Convolutional codes cannot be completely corrected in a low C / N environment (low carrier-to-noise environment), but have an effect of improving errors. On the other hand, the block code has a property that the error can be completely corrected if the error is within the correction capability.

[0003] Due to the nature of both, in order to realize more powerful error correction, concatenated coding, in which an information code is first coded in a block and then convolutionally coded to generate a transmission code, is often used. Can be Since the residual error of the convolutional code becomes a burst, an RS (Reed-Solomon) code is generally used as the block code.

[0004] In the block diagram of the entire system including the transmitting side and the receiving side of the BS digital broadcast, the block coding section and the decoding section are located outside and the convolutional coding section and the decoding section are located inside. Therefore, the convolutional code may be called an inner code, and the block code may be called an outer code.

[0005] The combination of the inner code error correction system and the modulation system of BS digital broadcasting will be described. In the case of modulation by 8PSK, error correction by trellis coding is performed. In this case, the coding rate is 2/3. This combination is hereinafter referred to as TC8PSK. The coding rate 2/3 indicates that conversion is performed from 2 bits to 3 bits.

On the other hand, in the case of modulation by QPSK or BPSK, convolutional coding is used as an error correction method. The coding rate in this case is 1/2, 2/3, 3/4, 5
/ 6, 7/8. When the coding rate is 2/3 to 7/8, the coding rate is さ ら に, the constraint length is 7, and the generator polynomial 1
Encoding to a punctured code is performed using a code of 71, 133 (octal) as a source signal.

A coded signal of an inner code is obtained by inputting a 1-bit bit string to an encoder and outputting a 2-bit signal.
Convolutional encoding uses this 2-bit output to map to QPSK or BPSK. In trellis coding, 3-bit coding is further performed using 1 bit, and mapping is performed on 8PSK.

The Viterbi decoding output is a decoding of the inner code, and is a 2-bit serial output in the case of TC8PSK and a 1-bit serial output in other modes.

On the other hand, the outer code error correction system uses a shortened RS
(Reed-Solomon) (204,188) code and 8-bit parallel signal.

[0010] In the signal flow in the receiver, RS decoding (outer code error correction) is performed after Viterbi decoding (inner code error correction). Since the bit width of signal processing is different between Viterbi decoding and RS decoding, a 1-bit or 2-bit serial output of Viterbi decoding is converted into an 8-bit parallel signal.
It is necessary to perform parallel conversion and perform signal processing. Also, the circuit after the parallel conversion must perform the parallel signal processing without interrupting the signal.

FIG. 10 is a block diagram showing a serial converter for converting a Viterbi decoded output used in a conventional digital broadcast receiving apparatus.
FIG. 3 is a block diagram illustrating a configuration of a parallel conversion circuit 502.

Referring to FIG. 10, serial-to-parallel conversion circuit 502 provides serial data D0,
It includes a data conversion unit 504 that converts D1 into parallel data POUT0 to POUT7, and a clock generation unit 506 that receives the serial clock SCLK and outputs the parallel clock PCLK.

The clock generator 506 includes an octal counter 518 for receiving the serial clock SCLK, a clock generator 520 for outputting a clock signal CLK0 according to the count value of the octal counter 518, and a count operation according to the serial clock SCLK. Quaternary counter 5 that performs
14 and a clock generation circuit 516 that outputs a clock signal CLK1 according to the count value of the quaternary counter 514.
And a clock signal CL according to the operation mode signal MODE.
Either K0 or CLK1 is converted to the parallel clock PCLK
And a selector 522 that outputs a

Clock generation circuit 520 outputs an H level when the count value of oscillation counter 518 is 0 to 3, and outputs an L level when the count value is 4 to 7. The clock generation circuit 516 has a quaternary counter 5
When the count value of 14 is 0 or 1, the H level is output, and when the count value is 2 or 3, the L level is output.

The serial-parallel conversion circuit 502
A and B have two operation modes. Operation mode A
Corresponds to the case where the output of the Viterbi decoding circuit is given by 2 bits, and the operation mode B is that the output of the Viterbi decoding circuit is 1
Corresponds to the case given by bits.

The operation mode of the selector 522 is mode A.
In this case, the clock signal CLK1 is
CLK and outputs the clock signal CLK0 as the parallel clock PCLK when the operation mode is mode B.

The data converter 504 receives the clock signal CL
Serial-parallel conversion circuit 510 for converting serial data D0 into 8-bit parallel data according to K0
And the serial data D according to the clock signal CLK1.
A serial-parallel conversion circuit 508 for converting 2-bit data of 0 and D1 into 8-bit parallel data, and an output of one of the serial-parallel conversion circuits 508 and 510 according to a mode signal MODE.
And a selector 512 that outputs the signals as UT0 to POUT7.

The operation mode of the selector 512 is mode A.
In the case of, the output of the serial-parallel conversion circuit 508 is output as parallel data POUT0 to POUT7,
When the operation mode is mode B, the output of the serial-parallel conversion circuit 510 is output to the parallel data POUT0 to POOUT.
Output as UT7.

That is, in the configuration shown in FIG.
A serial-parallel converter 510 is provided for 8PSK, and a serial-parallel converter 5 is provided for other modes.
08, the serial-to-parallel conversion is performed independently, and the output of any one of the serial-to-parallel conversion circuits is selected by the selector 512, and the parallel data
ＰPOUT7.

Further, regarding the generation of the clock, TC8
An octal counter 518 and a clock generation circuit 520 are provided for PSK, and a quaternary counter 5 is provided for other modes.
14 and a clock generation circuit 516, one of which is provided by the selector
K was output.

FIG. 11 is a circuit diagram showing a configuration of a data conversion section 532 used in place of the data conversion section 504 in another example of a conventional serial-parallel conversion circuit.

Referring to FIG. 11, data conversion section 532
Are flip-flops 540-547 and selector 550
To 556.

Flip-flop 540 receives serial data D0 and receives the B input of selector 550 and selector 5
Data is output to the A input 51. Selector 55
Serial data D1 is given to the A input of 0. Flip-flop 541 takes in the output of selector 550 and outputs the data taken in the B input of selector 551 and the A input of selector 552. Flip-flop 542
Receives the output of the selector 551 and outputs the received data to the B input of the selector 552 and the A input of the selector 553. Flip-flop 543 receives the output of selector 552, and outputs the received data to the B input of selector 553 and the A input of selector 554.

The flip-flop 544 is connected to the selector 55
3 and outputs the received data to the selector 554 B
Input and output to A input of selector 555. The flip-flop 545 receives the output of the selector 554 and outputs the received data to the B input of the selector 555 and the A input of the selector 556. Flip-flop 5
46 receives the output of the selector 555 and outputs the received data to the B input of the selector 556. Flip-flop 547 receives the output of selector 556.

When the operation mode is mode A, selectors 550 to 556 output a signal given to the A input. On the other hand, when the operation mode is B, the selectors 550-5
56 outputs the signal given to the B input.

The flip-flops 540 to 547 respectively control the parallel data POUT0 at a predetermined timing.
To POUT7.

That is, the serial-parallel conversion circuit 5
At 32, a selector is used before the flip-flop of the shift register that outputs each parallel data bit. If the Viterbi output is a 1-bit serial output, the mode B is selected and the data input as the serial data D0 is The data is sequentially shifted to flip-flops 540-547. Then, when data is accumulated in all flip-flops 540 to 547, the accumulated data is latched as parallel data POUT0 to POUT7 in the next stage circuit.

On the other hand, when the Viterbi output is 2-bit serial data D0 and D1, the mode is set to A, and the data input to flip-flop 540 is sequentially shifted to flip-flops 542, 544 and 546. Data input to flip-flop 541 receiving serial data D1 is flip-flop 543, 545,
547. And flip-flop 5
When the data is accumulated in all of 40 to 547, the parallel data POUT0 to POUT7 are latched in the next stage circuit.

[0029]

As described above,
The configuration of the digital broadcast receiver shown in FIG. 10 includes two systems each of a serial-parallel conversion circuit and a clock generation circuit that generates a parallel clock, and the circuit scale is large.

When the configuration shown in FIG. 11 is employed, the number of selectors is one more than the number of bits of parallel data.
A smaller number is required, and the larger the number of bits of parallel data, the larger the circuit scale.
Therefore, there has been a problem that the digital broadcast receiving apparatus becomes expensive.

An object of the present invention is to provide a digital broadcast receiving apparatus having a reduced circuit scale.

[0032]

According to the present invention, there is provided a data receiving apparatus for decoding a convolutional code and, in a first operation mode, a serial decoded signal having a 2-bit width in accordance with a modulation scheme of a received signal. And a first decoding means for outputting a 1-bit width serial decoded signal in the second operation mode, and a second decoding means for receiving data according to the output of the first decoding means and decoding a block code. And decoding means for receiving the serial data corresponding to the output of the first decoding means, provided on a path through which data is transmitted from the first decoding means to the second decoding means. A serial-parallel conversion circuit that outputs parallel data having a bit width wider than the output, wherein the serial data is 2 bits wide in the first operation mode and 1 bit in the second operation mode. And a serial - parallel converter circuit, in a first mode of operation, and outputs the serial data as a signal as 2-bit wide, in the second mode of operation, by distributing the serial data alternately 2
A data converter that outputs a bit width signal; and a first and a second that receive and shift the first and second bits of the output of the data converter, respectively, and collectively output parallel data when predetermined data is accumulated. A second shift register.

Preferably, the serial-parallel conversion circuit performs a counting operation in response to a serial clock supplied in synchronization with the serial data, and outputs parallel data in the first mode according to the count value of the counter. First clock generation means for generating a parallel clock synchronized with the timing, and second clock generation means for generating a parallel clock synchronized with the timing for outputting the parallel data in the second mode in accordance with the count value of the counter. Selecting means for selecting and outputting any one of the outputs of the first and second clock generating means.

Preferably, the serial-parallel conversion circuit includes a counter for performing a counting operation in response to a serial clock provided in synchronization with serial data, and an internal circuit having a cycle twice as long as the serial clock in accordance with the count value of the counter. A clock generation circuit for outputting a clock;
In the second mode, a first shift clock which outputs a serial clock as a first shift clock indicating a shift operation timing of a first shift register, and outputs a first shift clock in accordance with an internal clock in a second mode Clock selecting means, and in the first mode, outputting the serial clock as a second shift clock indicating the shift operation timing of the second shift register, and in the second mode, outputting the second shift clock in accordance with the internal clock. And second shift clock selecting means for outputting

More preferably, the first and second shift clocks are two serial clocks in the second mode.
The clocks have double periods and are complementary to each other.

Preferably, the first shift register includes a plurality of first flip-flops outputting data corresponding to even-numbered bits of parallel data, and the second shift register corresponds to odd-numbered bits of parallel data. Including a plurality of second flip-flops for outputting data.

Preferably, the first decoding means includes a Viterbi decoding means for decoding a convolutional code by a maximum likelihood decoding method,
The second decoding means includes Reed-Solomon decoding means for decoding a Reed-Solomon code.

[0038]

Embodiments of the present invention will be described below in detail with reference to the drawings. In the drawings, the same reference numerals indicate the same or corresponding parts.

FIG. 1 is a schematic block diagram showing a main part extracted from the configuration of data receiving apparatus 1000 according to the embodiment of the present invention.

Referring to FIG. 1, data receiving apparatus 1000
In, an RF signal received from an antenna (not shown) is tuned by tuners 100.1 and 100.2, and supplied to 8PSK demodulators 102.1 and 102.2, respectively.

8PSK demodulators 102.1 and 102.
2 are transport stream decoders (hereinafter referred to as TS decoders) 104.1 and 104.1.
4.2, and to the MPEG decoding unit 110 via the changeover switch 106. That is, from the TS decoders 104.1 and 104.2,
The baseband signal is extracted from the selected channel.

The MPEG decoding unit 110 receives a data stream provided from the changeover switch 106, and uses a random access memory (hereinafter, referred to as a RAM) 112 as a buffer for temporarily storing data, thereby providing a video signal and an audio signal. Convert to

Data receiving apparatus 1000 further receives, via data bus BS1, signals from TS decoders 104.1 and 104.2, and a built-in storage device 148 for storing, and a data bus BS1. An arithmetic processing unit 144 for performing predetermined processing on data stored in the built-in storage device 148 and outputting the processed data;
ROM 140 for recording a program in the arithmetic processing of arithmetic processing section 144, RAM 142 for providing a memory area for operation of arithmetic processing section 144, and data input / output between data bus BS1 and the outside. A high-speed digital interface 146. Although not particularly limited, the built-in storage device 148 and the ROM 1
As 40, for example, a flash memory capable of electrically writing and reading data can be used.

The data after the arithmetic processing unit 144 has processed the data stored in the built-in storage device 148 according to an instruction given from the outside is synthesized from an on-screen display processing unit 130. Unit 160.2.

The synthesizer 160.2 synthesizes the output from the MPEG decoding unit 110 and the output from the on-screen display processing unit 130,
Give to 4. The output from the video output terminal 164 is provided to the display unit 1004.

The data receiving apparatus 1000 further receives data and the like as a result of processing by the arithmetic processing section 144 based on the data stored in the built-in storage device 148, and receives a sound effect or the like for a video output on the display section. And an additional sound generator 1 for generating the
20 that receives data processed by the arithmetic processing unit 144 based on the data stored in the built-in storage device 148 and the like, generates an audio signal, and supplies the generated audio signal to the synthesizer 160.1.
An M decoder 122 is provided.

The synthesizer 160.1 outputs the output from the MPEG decoder 110, the additional sound generator 120 and the PCM
In response to the output from the decoder 122, the synthesis result is provided to the audio output terminal 162. The audio signal provided to the audio output terminal 162 is output from the audio output unit 1002 as an audio signal.

The data receiving apparatus 1000 may be provided with a modem 150 for exchanging data with the outside and an IC card interface 152 for receiving information from an IC card, if necessary. .

Via the high-speed digital interface 146, for example, an external storage device 180 such as an HDD for a home server and a remote controller (or a keyboard or the like) 182 as an external input device are connected to the data bus BS1.
Is connected to

The data receiving apparatus 1000 has a configuration integrated with a display section 1004 for receiving a video output and displaying it on a display and an audio output section 1002 such as a speaker for receiving an audio output signal and outputting audio. Is also good.

FIG. 2 shows the TS decoder 10 shown in FIG.
It is a block diagram which shows the structure of 4.1. Note that the TS decoder 104.2 has the same configuration as the TS decoder 104.1.

Referring to FIG. 2, TS decoder 104.1
Are a Viterbi decoding circuit 202 that receives the output of the 8PSK demodulator 102.1 and performs Viterbi decoding, and a Viterbi decoding circuit 2
02 and the parallel data POUT0 to POU
A serial-to-parallel conversion circuit 204 that outputs T7 and generates a parallel clock PCLK; a deinterleave circuit 206 that receives the output of the serial-to-parallel conversion circuit 204 and rearranges the data; And a Reed-Solomon decoding circuit 208 for decoding a Reed-Solomon code, which is one of the block coding methods. The TS decoder 104.1 further includes a synchronization processing unit (not shown). FIG.
In the embodiment, the serial-parallel conversion circuit 204 is disposed between the Viterbi decoding circuit 202 and the deinterleave circuit 206, but may be disposed in the deinterleave circuit 206 and the Reed-Solomon decoding circuit 208.

The output of the 8PSK demodulator 102.1 is a convolutional code that has been convolutionally processed on the transmission side so that error correction can be performed. Viterbi decoding is generally used to decode this convolutional code.

Viterbi decoding is widely used as a method for efficiently realizing maximum likelihood decoding of convolutional codes and as an error correction method for digital signals in satellite communication systems and mobile communication systems due to its strong error correction capability. ing. Viterbi decoding is one of the maximum likelihood decoding methods for estimating a transmission sequence closest to a received reception sequence and decoding the original information sequence.

The modulation method in BS digital broadcasting is as follows.
8PSK, QPSK, BP according to the content of information to be transmitted
SK is used as appropriate.

When the modulation method is 8PSK, trellis coding (coding rate 2/3) is used as the error correction method.
Hereinafter, this combination is referred to as TC8PSK. In this case, the Viterbi decoding circuit 202 outputs a 2-bit signal of D0 and D1. Hereinafter, the mode in which the serial-parallel conversion operation is performed in response to this output is referred to as operation mode A.

On the other hand, when the modulation method is QPSK or BPSK, the error correction method uses convolutional coding (coding rate 1 /
2, 2/3, 3/4, 5/6, 7/8).
When the coding rate is 2/3 to 7/8, the coding rate is 1
/ 2, constraint length 7, generator polynomials 171 and 133 (Octa
l) as a source signal using a punctured code (punctu
Red convolutional code). In this case, the Viterbi decoding circuit 202 outputs a 1-bit signal consisting of only D0. Hereinafter, the mode in which the serial-parallel conversion operation is performed in response to this output is referred to as operation mode B.

FIG. 3 is a circuit diagram showing a configuration of serial-parallel conversion circuit 204 shown in FIG.

Referring to FIG. 3, serial-to-parallel conversion circuit 204 receives serial data output from Viterbi decoding circuit 202 in one bit (D0) or two bits (D0, D1) depending on the modulation method. Converted and parallel signals POUT0-PO suitable for Reed-Solomon decoding
It includes a data conversion unit 212 that outputs the UT 7 and a clock generation unit 214 that receives the serial clock SCLK and outputs a parallel clock PCLK. The parallel clock PCLK is a clock signal synchronized with the parallel signals POUT0 to POUT7, and is used for processing the parallel signals POUT0 to POUT7 in the deinterleave circuit 206, the Reed-Solomon decoding circuit 208, and the like at the subsequent stage.

FIG. 4 shows the clock generator 21 shown in FIG.
4 is a circuit diagram showing a configuration of FIG. Referring to FIG. 4, clock generation unit 214 includes an octal counter 216 that performs a counting operation according to serial clock SCLK, and a parallel clock PC according to a count value of octal counter 216.
LK output parallel clock generator 220, and data conversion clocks FCLK1 and FCLK1 according to the count value of octal counter 216 and serial clock SCLK.
And a conversion clock generator 218 that outputs CLK2 and SCLK2.

The conversion clock generator 218 receives the clock SCLK2 and inverts the clock SCLK2 when the count value of the octal counter 216 is 0, 2, 4, and 6, and the clock generation circuit 220 sets the clock SCLK2 to the H level. An inverting circuit 222, a selector 226 that outputs the serial clock SCLK as the clock FCLK1 when the operation mode is A, and receives and outputs the clock SCLK2 as the clock FCLK1 when the operation mode is B; , The serial clock SCLK is output as the clock FCLK2. When the operation mode is mode B, the output of the inversion circuit 222 is
And a selector 224 that outputs the data as 2.

The parallel clock generator 220 includes selectors 228 and 234 and clock generators 230 and 232
And

Selector 228 supplies the count value of octal counter 216 to clock generation circuit 230 when the operation mode is mode A, and to clock generation circuit 232 when the operation mode is mode B.

The selector 234 operates in mode A.
In this case, the clock generated by the clock generation circuit 230 is output as the parallel clock PCLK. On the other hand, when the operation mode is mode B, selector 234 outputs the clock generated by clock generation circuit 232 as parallel clock PCLK.

When the count value of the octal counter 216 is 0, 1, 4, or 5, the clock generation circuit 230 sets the output clock to the H level, and when the count value of the octal counter 216 is 2, 3, 6, 7 In this case, the output clock is set to L level. The clock generation circuit 232 sets the output clock to H level when the count value of the octal counter 216 is 0, 1, 2, 3, and when the count value of the octal counter 216 is 4, 5, 6, 7, Sets the output clock to L level.

FIG. 5 shows the data converter 212 shown in FIG.
FIG. 3 is a circuit diagram showing the configuration of FIG. Referring to FIG. 5, data conversion section 212 receives serial data D0 and D1, converts data in accordance with mode signal MODE and conversion clock SCLK2, and receives internal data DI0 and DI1. Clock FCLK1, FC
And a data holding unit 244 for taking in and holding data according to LK2.

The data conversion unit 242 includes a selector 246,
248 and a signal switching circuit 250. The signal switching circuit 250 includes selectors 252 and 254.

Selector 246 receives serial data D0 as input and transmits serial data D0 to A input of selector 254 when the operation mode is mode A. On the other hand, when the operation mode is mode B, selector 246 outputs serial data D0 to selector 248. The selector 248 outputs the data conversion clock SCLK.
The data received from the selector 246 is alternately output to the B input of the selector 252 and the B input of the selector 254 in response to (2).

When the operation mode is A, selectors 252 and 254 output the data given to the A input as respective bits of 2-bit internal data DI1 and DI0. On the other hand, when the operation mode is mode B, selectors 252 and 254 output the data received at the B input as respective bits of internal data DI1 and DI0.

The data holding section 244 is provided with the shift register 2
56,258. The shift register 256 includes flip-flops FF1, FF3, and FF that sequentially shift the internal data DI1 in accordance with the data conversion clock FCLK1.
5, FF7.

The shift register 258 stores the internal data DI
Flip-flops FF0, FF2, FF4, FF for sequentially shifting 0 according to the data conversion clock FCLK2
6 inclusive. Note that the flip-flops FF0 to FF7 are
The parallel data POUT0 to POUT7 are respectively output. Therefore, the flip-flop FF0 outputs the least significant bit (LSL) of the parallel data POUT0 to POUT7.
B) POUT0 is output. Flip-flop F
F7 outputs POUT7 which is the most significant bit (MSB) of the parallel data POUT0 to POUT7.

FIG. 6 is a diagram for explaining an operation example of the serial-parallel conversion circuit when the Viterbi decoding output is 2 bits.

Referring to FIG. 6, first, the 0th and 1st data are simultaneously supplied to the parallel / serial conversion circuit. After one serial clock, the flip-flops FF0 and FF1 hold the first and zeroth data, respectively. Subsequently, after two serial clocks, the flip-flops FF0, FF1, FF2, and FF3 hold the third, second, first, and zeroth data, respectively.

After three serial clocks, flip-flops FF0 and FF1 hold fifth and fourth data, respectively, and flip-flops FF2 and FF3
Hold third and second data, respectively, and flip-flops FF4 and FF5 hold first and zeroth data, respectively.

Subsequently, after four serial clocks, flip-flops FF0, FF1, FF2, FF3
Holds the seventh, sixth, fifth, and fourth data, respectively. Also, flip-flops FF4, FF5,
FF6, FF7 have 3rd, 2nd, 1st,
The 0th data is retained.

That is, after four serial clocks, the 0th to 7th data are held in all flip-flops, and these eight data are output collectively to the next stage circuit as parallel data.

FIG. 7 is an operation waveform diagram for describing the operation when the Viterbi decoding output is 2 bits in more detail.

Referring to FIGS. 5 and 7, in mode A where the Viterbi decoding output is 2 bits, serial data D0 is converted to internal data DI by data conversion section 242.
0, and the serial data D1 is the internal data D
Output as I1. Also, the shift register 256,
Data conversion clocks FCLK1,
A serial clock SCLK is used for both FCLK2.

At time t1, internal data DI0 and DI1 are taken into flip-flops FF0 and FF1, respectively, in synchronization with the rise of the clock signal. Therefore, between times t1 and t2, flip-flop FF1
Holds data DATA0 and flip-flop FF0
Holds data DATA1.

At time t2, data DATA0 held by flip-flop FF1 is shifted to flip-flop FF3. The data DATA1 held by the flip-flop FF0 is shifted to the flip-flop FF2. The flip-flop 1 is connected to the data DATA given as the internal data DI1.
2 and the flip-flop FF0 stores the internal data DI
The data DATA3 given as 0 is held.

Therefore, from time t2 to time t3, flip-flop FF1 holds data DATA2, and flip-flop FF3 holds data DATA0. The flip-flop FF0 holds data DATA3, and the flip-flop FF2 holds data DATA1.

Similarly, as a result of sequentially shifting data, flip-flops FF1 and FF1 are turned on between times t4 and t5.
FF3, FF5, FF7 are data DATA6, respectively.
DATA4, DATA2, and DATA0 are held. The flip-flops FF0, FF2, FF4, and FF6 store data DATA7, DATA5, DATA3, and D, respectively.
Hold ATA1. Therefore, since data has been stored in all flip-flops, parallel data is latched by the next-stage circuit at the subsequent time t5 in accordance with the rise of parallel clock PCLK.

Thereafter, the same operation is repeated from time t5 to t9. FIG. 8 is a diagram illustrating a state of the flip-flop when the Viterbi decoding output is 1 bit.

Referring to FIG. 8, when the Viterbi decoding output is 1 bit, the 0th to 7th data are sequentially supplied to the serial-parallel conversion circuit as serial data D0 bit by bit. First, after one serial clock, the flip-flop FF1 holds the 0th data. After two subsequent serial clocks, the flip-flop FF0 holds the first data, and the flip-flop FF1 holds the 0th data. I do.

After three subsequent serial clocks, flip-flop FF0 holds the first data, and flip-flop FF1 holds the second data. Then, the flip-flop FF3 holds the 0th data.

Subsequently, after four serial clocks, flip-flops FF0, FF1, FF2, FF3
Hold the third, second, first, and zeroth data, respectively. After 5 serial clocks, the flip-flops FF0, FF1, FF2, and FF3 are 3
The fourth, fourth, first, and second data are held, and the flip-flop FF5 holds the zeroth data.

After 6 serial clocks, the flip-flops FF0, FF1, FF2, and FF3 hold the fifth, fourth, third, and second data, respectively, and the flip-flops FF4 and FF5 hold the first and zero data, respectively.
Hold the th data.

After the subsequent seven serial clocks, the flip-flops FF0, FF1, FF2, and FF3 hold the fifth, sixth, third, and fourth data, respectively. The flip-flops FF4 and FF5 hold the first and second data, respectively. Then, the flip-flop FF7 holds the 0th data.

After eight serial clocks, flip-flops FF0, FF1, FF2, and FF3 hold the seventh, sixth, fifth, and fourth data, respectively, and flip-flops FF4, FF5, FF6, and FF7 each hold three. The second, first, and 0th data are held. At this time, flip-flops FF0 to FF7
Are in a state where all the data are stored, and these eight data are transmitted to the next stage as parallel data.

FIG. 9 is an operation waveform diagram for explaining the operation when the Viterbi decoding output is 1 bit.

Referring to FIGS. 5 and 9, in mode B where the Viterbi decoding output is 2 bits, the Viterbi decoding output is applied only to serial data D0. The clocks SCLK2 are included in the conversion clocks FCLK1 and FCLK2.
Are provided. Selector 2
48, the data DATA0 to DATA7 given as serial data D0 are internal data DI1,
DI0 alternately.

At time t1, data DATA0 is applied to flip-flop F in synchronization with the rising edge of the clock.
It is taken in F1. Subsequently, at time t2, the data DA
TA1 is taken into flip-flop FF0. Time t
In 3, the data DATA0 held by the flip-flop FF1 is output to the flip-flop FF3, and the flip-flop FF1 takes in the data DATA2. At time t4, data DATA1 held by flip-flop FF0 is shifted, and flip-flop FF0 takes in data DATA3.

At time t5, flip-flop FF
1, Data DATA2, DATA held by FF3
0 is shifted to flip-flops FF3 and FF5, respectively, and flip-flop FF1 takes in data DATA4. At time t6, flip-flops FF0, FF
2 is shifted to flip-flops FF2 and FF4, respectively, and flip-flop FF0 newly takes in data DATA5. At time t7, flip-flops FF1, F
Data DATA4 and DAT held by F3 and FF5
A2 and DATA0 are shifted to the next stage, and flip-flop FF1 newly takes in data DATA6. Time t8
, The data DATA5, DATA3, and D held by the flip-flops FF0, FF2, and FF4, respectively.
ATA1 is shifted to the next stage and flip-flop FF0
Fetches new data DATA7. As a result of the shift operation being performed alternately in shift registers 256 and 258, flip-flop FF is turned on from time t8 to t9.
The state is such that eight data are held in 0 to FF7.

At time t9, the parallel clock P
A circuit connected to the next stage latches the data held by flip-flops FF0 to FF7 as parallel data in response to the rise of CLK.

As described above, according to the present invention, the flip-flop of the serial-parallel conversion circuit is configured as a two-system shift register, and the data is appropriately distributed according to the number of bits of the Viterbi decoding output. Serial mode with multiple circuits with a small circuit scale
A parallel conversion operation can be realized.

In this embodiment, 8-bit parallel data has been described.
The present invention is also applicable to serial-parallel conversion of other bits such as bits. Furthermore, in the present embodiment, a BS digital broadcast receiver has been described as an example of a data receiving device, but the present invention is not limited to this, and the present invention provides a concatenated code using a combination of a plurality of codings. Any data receiving apparatus that receives and decodes a transmission code in which error correction is enhanced by the conversion can be suitably used.

The embodiments disclosed this time are to be considered in all respects as illustrative and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

[0098]

According to the present invention, the flip-flops of the serial-parallel conversion circuit constitute two shift registers, and the data is appropriately distributed according to the number of bits of the Viterbi decoding output. A plurality of modes of serial-parallel conversion operation can be realized with a circuit scale.

[Brief description of the drawings]

FIG. 1 shows a data receiving apparatus 1 according to an embodiment of the present invention.
000 is a schematic block diagram showing a main part extracted from FIG.

FIG. 2 is a block diagram showing a configuration of a TS decoder 104.1 shown in FIG.

3 is a serial-parallel conversion circuit 2 shown in FIG. 2;
FIG. 4 is a circuit diagram showing a configuration of a fourth embodiment.

FIG. 4 is a circuit diagram showing a configuration of a clock generator 214 shown in FIG.

FIG. 5 is a circuit diagram showing a configuration of a data conversion unit 212 shown in FIG.

FIG. 6 is a diagram for explaining an operation example of the serial-parallel conversion circuit when the Viterbi decoding output is 2 bits.

FIG. 7 is an operation waveform diagram for describing the operation when the Viterbi decoding output is 2 bits in more detail.

FIG. 8 is a diagram illustrating a state of a flip-flop when a Viterbi decoding output is 1 bit.

FIG. 9 is an operation waveform diagram for explaining an operation when the Viterbi decoding output is 1 bit.

FIG. 10 is a block diagram showing a configuration of a serial-parallel conversion circuit 502 for converting a Viterbi decoding output used in a conventional digital broadcast receiving apparatus.

FIG. 11 is a circuit diagram showing a configuration of a data conversion unit 532 used in place of the data conversion unit 504 in another example of a conventional serial-parallel conversion circuit.

[Explanation of symbols]

100 tuner, 102 8PSK demodulator, 104
TS decoder, 106 changeover switch, 110 MPEG
Decoder, 120 additional sound generator, 122 PCM decoder, 130 on-screen display processor, 1
44 arithmetic processing unit, 146 high-speed digital interface, 148 built-in storage device, 150 modem, 1
52 card interface, 160 synthesizer, 16
2 audio output terminal, 164 video output terminal, 180 external storage device, 202 Viterbi decoding circuit, 204 serial-parallel conversion circuit, 206 deinterleave circuit, 208 Reed-Solomon decoding circuit, 212 data conversion unit, 214 clock generation unit, 2168 Counter, 218 conversion clock generator, 220, 230,
232 clock generation circuit, 220 parallel clock generation unit, 222 inversion circuit, 224, 226, 228, 2
34, 246, 248, 252, 254 selector, 2
42 data conversion unit, 504 data conversion unit, 244
Data holding unit, 250 signal switching circuit, 256, 258
Shift register, 1000 data receiving device, 1002
Audio output unit, 1004 display unit, BS1 data bus, FF0 to FF7 flip-flop.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H04N 7/00 H04N 7/00 Z 7/24 7/13 A F term (Reference) 5C059 MA00 RF04 SS02 UA05 UA09 UA24 5C063 AB03 CA12 CA31 CA40 5J065 AB03 AC02 AD10 AD11 AF03 AG05 AH08 AH23 5K004 AA05 FA03 FA05 FA06 FD05

Claims (6)

[Claims] 1. A method for decoding a convolutional code, outputting a 2-bit-width serial decoded signal in a first operation mode, and outputting a 1-bit serial decoded signal in a second operation mode in accordance with a modulation scheme of a received signal.
A first decoding unit that outputs a serial decoded signal having a bit width; a second decoding unit that receives data corresponding to an output of the first decoding unit and decodes a block code; and a first decoding unit. Means on a path through which data is transmitted from the means to the second decoding means, receives serial data corresponding to the output of the first decoding means, and has a bit width smaller than that of the output of the first decoding means. A serial-parallel conversion circuit that outputs wide parallel data, wherein the serial data has a 2-bit width in the first operation mode, a 1-bit width in the second operation mode, The parallel conversion circuit outputs the serial data as it is as a 2-bit width signal in the first operation mode, and outputs the serial data in the second operation mode. A data converter for alternately distributing real data and outputting a 2-bit signal; and receiving and shifting the first and second bits of the output of the data converter, respectively. A data receiving device, comprising: first and second shift registers that output data collectively. 2. The serial-parallel conversion circuit, comprising: a counter for performing a counting operation in response to a serial clock provided in synchronization with the serial data; and the parallel mode in the first mode according to a count value of the counter. First clock generation means for generating a parallel clock synchronized with the data output timing; and generating a parallel clock synchronized with the parallel data output timing in the second mode in accordance with the count value of the counter. 2. The data receiving apparatus according to claim 1, further comprising: a second clock generation unit; and a selection unit that selects and outputs one of the outputs of the first and second clock generation units. 3. The serial-parallel conversion circuit includes: a counter that performs a counting operation in response to a serial clock supplied in synchronization with the serial data; and a cycle twice as long as the serial clock according to a count value of the counter. And a clock generation circuit that outputs an internal clock having the following. In the first mode, the serial clock is output as a first shift clock indicating a shift operation timing of the first shift register, and in the second mode, First shift clock selecting means for outputting the first shift clock in accordance with the internal clock; and, in the first mode, a second shift clock indicating a shift operation timing of the second shift register in the second mode. In the second mode. Further comprising a second shift clock selecting means for outputting said second shift clock in accordance with the internal clock, the data receiving apparatus according to claim 1. 4. The first and second shift clocks have a period twice as long as the serial clock in the second mode, and are mutually complementary clocks.
A data receiving device according to claim 1. 5. The first shift register includes a plurality of first flip-flops that output data corresponding to even bits of the parallel data, and the second shift register includes an odd bit of the parallel data. And a plurality of second flip-flops for outputting data corresponding to the first and second flip-flops.
A data receiving device according to claim 1. 6. The first decoding means includes a Viterbi decoding means for decoding a convolutional code by a maximum likelihood decoding method, and the second decoding means includes a Reed-Solomon decoding means for decoding a Reed-Solomon code. The data receiving apparatus according to claim 1.