TWI451430B - System and method for correcting errors in non-volatile memory using product codes - Google Patents

Description

System and method for correcting errors in non-volatile memory using product codes

This invention relates to memory systems and, more particularly, to error correction of memory systems.

The background description given herein is for the purpose of providing a general description of the present disclosure. The prior art of the present disclosure is not explicitly or implicitly admitted to the work of the inventor of the present invention as described in the background section and the various aspects that are not described as prior art.

Referring now to FIG. 1, the non-volatile semiconductor memory 10 may include a flash memory, a static random access memory (SRAM), a nitride read only memory (NROM), a magnetic RAM, a phase change memory (PRAM), and the like. . The memory controller 12 can write data to or read from the NV memory 10 via the write and read paths 14, 16. Data corruption or errors in the NV memory 10 may occur in the form of interference, such as intersymbol interference, and/or noise "n".

Referring now to Figures 1 and 2, the encoder 18 of the write path 14 can receive the data flow U and can apply an error correction code (ECC) to the data to produce the encoded signal Y. The NV memory 10 can store encoded data. The decoder 24 of the read path 16 can use ECC to detect and correct errors in the read signal Y' to generate a data flow U'. U’ may be similar to U.

Encoder 18 may encode U in a one-dimensional (1D) array 30. Array 30 can include a series of rows 31-1, 31-2, ..., and 31-M of length N (collectively, row 31). Each row may contain a user profile area 32 of length K and an overhead data area 34 of length N-K, which may contain ECC encoded material. K and N-K may be based on the number of bits stored in the respective regions 32,34.

The decoder 24 may analyze the ECC encoded data during a read operation to determine if there is an error and/or whether to correct such an error. The ECC can include common coefficients for specialized polynomials. When reading data from the NV memory 10, the integrity of the data can be checked by regenerating these coefficients from the read data. If the regenerated ECC does not "match" the stored ECC, an error is detected.

Exemplary ECCs include Hamming, Reed-Solomon (RS) codes, and Bose-Chaudhuri-Hochquenghem (BCH) binary codes. Other ECCs include Loop Redundancy Code (CRC), Golay code, Reed-Moore code, Goppa code, Low Density Parity Check (LDPC) code, turbo code, convolutional code, trellis coded modulation (TCM), Block code modulation (BCM), etc.

The decoder 24 can recover the data, but there may be some error recovery that accepts a small probability. However, as the error data increases, the probability of reliable data recovery may decrease rapidly. Once an error in the read data is detected, decoder 24 can attempt to correct and/or erase the error.

Hamming distance is a measure of the error detection and correction capabilities of the code. The Hamming distance between two data words is the number of different positions of the corresponding bits. In other words, the Hamming distance measurement changes the number of substitutions required to change one word to another, or the number of errors in which one word is transformed into another. For example, the Hamming distance between 1111 and 1001 is 2. The Hamming distance between 1111 and 0001 is 3.

In order to detect the E digits in the error, a code with a minimum Hamming distance of (E+1) may be required. In order to correct E errors, the code must display the minimum Hamming distance of (2E+1). The minimum distance indicates the amount of noise that the system can tolerate before erroneously decoding the stored codeword.

A product code encoder for non-volatile (NV) memory includes a first encoder that encodes data in a codeword stored in a first dimension in the NV memory. The product code encoder further includes a second encoder that encodes data in a codeword stored in the second dimension in the NV memory. The product code codeword is based on the codeword in the first dimension and the codeword in the second dimension.

In other features, at least one of the first and second dimensional codewords is based on a code selected from the group consisting of: Hamming code, Reed-Solomon (RS) code, Bose-Chaudhuri- Hochquenghem (BCH) binary code, loop redundancy code, Golay code, Reed-Moore code, Goppa code, low density parity check (LDPC) code, turbo code, convolutional code, trellis coded modulation (TCM) ), block code modulation (BCM).

In other features, at least one of the first and second encoders comprises a product code encoder. The product code codeword is based on the product of the codeword in the first dimension and the codeword in the second dimension. The first dimension includes rows and the second dimension includes columns.

Among other features, an NV memory system includes a product code encoder and a product code decoder. The product code decoder decodes the first dimensional codeword and the second dimensional codeword from the NV memory. The NV memory includes at least one of the following memories: a flash memory memory, a static random access memory (SRAM), a nitride read only memory (NROM), a magnetic RAM, and a phase change memory (PRAM). ). The burst code decoder operates in parallel with the product code decoder. The burst code decoder decodes at least one of the first dimension codeword and the second dimension codeword.

In other features, the NV memory system includes a modulator that modulates a signal from a product code encoder during a write operation. The demodulator demodulates the data stored in the NV memory during a read operation. The product code decoder includes a row decoder that decodes the first dimensional codeword and a column decoder that decodes the second dimensional codeword.

In other features, when the row decoder detects an error in one of the first dimensional codewords, the one of the first dimensional codewords is marked as erased. The column decoder detects another error in one of the second dimensional codewords based on the erasure. A product code decoder repeats at the row and column decoders to determine other errors in the first and second dimensional codewords. The row decoder determines that one of the first dimensional codewords is miscorrected based on the number of errors in the first dimensional codeword and erases the first dimensional codeword.

In other features, the product code decoder erases the plurality of least reliable first dimensional codewords when the one of the second dimensional codewords is not successfully decoded, and repeats said in the second dimensional codeword One is for decoding. When the product code decoder decodes one of the second dimensional codewords but changes the symbols in one of the first dimensional codewords, the product code decoder erases the plurality of least reliable first dimensional codewords. The product code decoder then repeats decoding of the one of the second dimensional code words. The product code encoder also includes N encoders that encode data in code words stored in N dimensions in the NV memory. The product code codeword is based on the product of the codewords in the N dimensions, where N is an integer greater than or equal to three.

In other features, a product code decoder includes a first decoder that decodes a first dimensional codeword stored in non-volatile (NV) memory. The product code decoder also includes a second decoder that decodes the second dimensional codeword stored in the NV memory. The product code codeword is based on the first dimension codeword and the second dimension codeword.

In other features, the first dimension includes rows and the second dimension includes columns. The product code codeword is based on the product of the first dimension codeword and the second dimension codeword. At least one of the first and second decoders includes a product code decoder. When the first decoder detects an error in one of the first dimensional codewords, the one of the first dimensional codewords is marked as erased. The second decoder detects another error in one of the second dimensional codewords based on the erasure.

In other features, the first and second decoders repeat to determine other errors in the first and second dimensional codewords. The first decoder determines that one of the first dimensional codewords is miscorrected based on the number of errors in the first dimensional codeword and erases the first dimensional codeword. When the second decoder fails to successfully decode one of the second dimensional codewords, one of the first and second decoders erases the plurality of least reliable first dimensional codewords. The second decoder then repeats decoding of the one of the second dimensional codewords.

In other features, when the second decoder decodes one of the second dimensional codewords but changes the symbols in one of the first dimensional codewords, one of the first and second decoders erases multiple The least reliable first dimension codeword. The second decoder then repeats decoding of the one of the second dimensional codewords.

In other features, at least one of the first and second dimensional codewords is based on a code selected from the group consisting of: Hamming code, Reed-Solomon (RS) code, Bose-Chaudhuri- Hochquenghem (BCH) binary code, loop redundancy code, Golay code, Reed-Moore code, Goppa code, low density parity check (LDPC) code, turbo code, convolutional code, trellis coded modulation (TCM) ), block code modulation (BCM).

Among other features, an NV memory system includes a product code decoder. The NV memory includes at least one of the following memories: flash memory memory, static random access memory (SRAM), nitride read only memory (NROM), magnetic RAM, and phase change memory (PRAM). . The memory system also includes a product code encoder including a row encoder that encodes the first dimensional codeword and a column encoder that encodes the second dimensional codeword. The product code decoder includes N decoders that decode data in code words stored in N dimensions in NV memory. The product code codeword is based on the product of the codewords in the N dimensions, where N is an integer greater than or equal to 3.

In other features, a method for encoding a product code includes encoding data in a codeword stored in a first dimension in NV memory. The method also includes encoding the data in the codewords stored in the second dimension in the NV memory. The product code codeword is based on the codeword in the first dimension and the codeword in the second dimension. The product code codeword is based on the product of the codeword in the first dimension and the codeword in the second dimension. The first dimension includes rows and the second dimension includes columns.

In other features, the method includes encoding data in codewords stored in N dimensions in NV memory. The product code codeword is based on the product of the codewords in the N dimensions, where N is an integer greater than or equal to 3.

In other features, a method for decoding a product code includes decoding a first dimensional codeword stored in non-volatile (NV) memory. The method also includes decoding the second dimensional codeword stored in the NV memory. The product code codeword is based on the first dimension codeword and the second dimension codeword. The first dimension includes rows and the second dimension includes columns. The product code codeword is based on the product of the first dimension codeword and the second dimension codeword.

In other features, the method includes detecting an error in one of the first dimensional codewords and marking the one of the first dimensional codewords as an erase. The method also includes detecting another error in one of the second dimensional codewords based on the erasing. The method also includes determining that one of the first dimensional codewords was miscorrected based on the number of errors in the first dimensional codeword. The method also includes erasing the first dimension codeword.

In other features, the method includes erasing the plurality of least reliable first dimensional codewords in response to failing to successfully decode one of the second dimensional codewords. The method also includes repeatedly decoding the one of the second dimensional codewords. The method also includes erasing the plurality of least reliable first dimensional codewords when one of the second dimensional codewords is decoded but the symbols in one of the first dimensional codewords are changed. The method also includes repeatedly decoding the one of the second dimensional codewords.

In other features, at least one of the first and second dimensional codewords is based on a code selected from the group consisting of: Hamming code, Reed-Solomon (RS) code, Bose-Chaudhuri- Hochquenghem (BCH) binary code, loop redundancy code, Golay code, Reed-Moore code, Goppa code, low density parity check (LDPC) code, turbo code, convolutional code, trellis coded modulation (TCM) ), block code modulation (BCM).

In other features, a product code encoder for an NV device for storing data includes a first encoding device that encodes data in a codeword stored in a first dimension in NV memory. The product code encoder further includes second encoding means for encoding data in a codeword stored in the second dimension in the NV memory. The product code codeword is based on the codeword in the first dimension and the codeword in the second dimension.

In other features, at least one of the first and second dimensional codewords is based on a code selected from the group consisting of: Hamming code, Reed-Solomon (RS) code, Bose-Chaudhuri- Hochquenghem (BCH) binary code, loop redundancy code, Golay code, Reed-Moore code, Goppa code, low density parity check (LDPC) code, turbo code, convolutional code, trellis coded modulation (TCM) ), block code modulation (BCM).

In other features, at least one of the first and second encoding means includes encoding means for encoding the product code. The product code codeword is based on the codeword in the first dimension and the codeword in the second dimension. The first dimension includes rows and the second dimension includes columns.

In other features, the product code decoder includes a first decoding device for decoding a first dimensional codeword stored in an NV device for storing material. The product code decoder also includes a second decoding device that decodes the second dimensional codeword stored in the NV memory device. The product code codeword is based on the first dimension codeword and the second dimension codeword. The first dimension includes rows and the second dimension includes columns. The product code codeword is based on the product of the first dimension codeword and the second dimension codeword.

In other features, at least one of the first and second decoding devices includes a product code means for decoding. When the first decoding device detects an error in one of the first dimensional codewords, the first dimensional codeword is marked as erased. The second decoding device detects another error in one of the second dimensional code words based on the erasing. The first and second decoding means are iterative to determine other errors in the first and second dimensional codewords. The first decoding device determines that one of the first dimensional codewords is miscorrected based on the number of errors in the first dimensional codeword and erases the first dimensional codeword.

In other features, one of the first and second decoding devices erases the plurality of least reliable first dimensional codewords when the second decoding device fails to successfully decode one of the second dimensional codewords. The second decoding device then repeats decoding of the one of the second dimensional codewords. When the second decoding device decodes one of the second dimensional codewords but changes the symbols in one of the first dimensional codewords, one of the first and second decoding devices erases the plurality of least reliable One-dimensional codeword. Then, the second decoding means repeats decoding of the one of the second dimensional code words.

In other features, at least one of the first and second dimensional codewords is based on a code selected from the group consisting of: Hamming code, Reed-Solomon (RS) code, Bose-Chaudhuri- Hochquenghem (BCH) binary code, loop redundancy code, Golay code, Reed-Moore code, Goppa code, low density parity check (LDPC) code, turbo code, convolutional code, trellis coded modulation (TCM) ), block code modulation (BCM).

In other features, a computer program stored by a processor for operating a product code encoder of an NV memory includes encoding data in a codeword stored in a first dimension in NV memory. The computer program also includes encoding the data in the codewords stored in the second dimension in the NV memory. The product code codeword is based on the codeword in the first dimension and the codeword in the second dimension. The product code codeword is based on the product of the codeword in the first dimension and the codeword in the second dimension. The first dimension includes rows and the second dimension includes columns.

In other features, the computer program includes encoding data in codewords stored in N dimensions in NV memory. The product code codeword is based on the product of the codewords in the N dimensions, where N is an integer greater than or equal to 3.

In other features, a computer program for decoding a product code includes decoding a first dimensional codeword stored in NV memory. The computer program also includes decoding the second dimensional codeword stored in the NV memory. The product code codeword is based on the first dimension codeword and the second dimension codeword. The first dimension includes rows and the second dimension includes columns. The product code codeword is based on the product of the first dimension codeword and the second dimension codeword.

In other features, the computer program includes detecting an error in one of the first dimension codewords and marking the one of the first dimension codewords as being erased. The computer program also includes detecting another error in one of the second dimension codewords based on the erasure. The computer program also includes determining that one of the first dimensional codewords was miscorrected based on the number of errors in the first dimensional codeword. The computer program also includes erasing the first dimension codeword.

In other features, the computer program includes erasing a plurality of least reliable first dimensional codewords in response to failure to successfully decode one of the second dimensional codewords. The computer program also includes repeatedly decoding the one of the second dimension codewords. The computer program also includes erasing the plurality of least reliable first dimensional codewords when one of the second dimensional codewords is decoded but the symbols in one of the first dimensional codewords are changed. The computer program also includes repeatedly decoding the one of the second dimension codewords.

In other features, at least one of the first and second dimensional codewords is based on a code selected from the group consisting of: Hamming code, Reed-Solomon (RS) code, Bose-Chaudhuri- Hochquenghem (BCH) binary code, loop redundancy code, Golay code, Reed-Moore code, Goppa code, low density parity check (LDPC) code, turbo code, convolutional code, trellis coded modulation (TCM) ), block code modulation (BCM).

In other features, the systems and methods described above are implemented in a computer program executed by one or more processors. The computer program can reside on a computer readable medium such as but not limited to a memory, a non-volatile data storage device, and/or other suitable tangible storage medium.

Further areas of applicability of the present invention will become apparent from the detailed description provided below. The detailed description and specific examples of the invention are intended to

The following description is merely exemplary in nature and is in no way intended to limit For the sake of clarity, the same reference numbers will be used in the drawings. As used herein, the term "module" refers to a dedicated integrated circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or group) that executes one or more software or firmware programs, and a memory. Combining logic circuits, and/or other enabled components that provide the functionality. As used herein, the phrase "at least one of A, B, and C" should be interpreted to mean the logic (A or B or C) that utilizes a non-exclusive logic or. It should be understood that steps of the method may be performed in a different order without changing the principles of the disclosure.

The present disclosure relates to the use of product codes to store data in non-volatile (NV) memory.

Referring now to FIG. 3, memory storage system 50 includes a write path 54 and a read path 56. The write path 54 has a product code encoder 58, and the product code encoder 58 receives the information material flow U from the memory controller 59 and generates a product code data flow X. The product code data stream X is received by the modulator 60, which modulates the data stream X into a signal suitable for NV memory storage. The data flow X is then written to a single level unit (SLC) or multi-level unit (MLC) NV memory 62.

The signal "n" represents the noise or distortion experienced by the modulated signal in the NV memory 62 and thus added to the modulated signal in effect. The combination of the noise n and the modulated signal is received by the demodulator 70 of the read path 56. The demodulator 70 generates a received signal X' and causes the signal X' to be received by the product code decoder 72. The demodulator 70 may first quantize the readback voltage (or current) from the NV memory cell and convert the reading to binary data X', but the binary data X' may include errors due to n.

If no error occurs during readback processing/demodulation, X' may be the same as X. If there is an error, product code decoder 72 can detect and/or clear the error in X' such that U' is always equal to U.

Referring now to Figures 4 and 5, the material of the product code can be written and/or read row by column and/or row by row. Product code encoder 58 may include a row encoder 74 and a column encoder 76 that encode the rows and columns of material to be written to NV memory 62. The product code decoder 72 may include a row decoder 78, a column decoder 80, and an error correction module 82. The row and column decoders 78, 80 decode the rows and columns of the material read from the NV memory 62 and can detect data errors. The error correction module 82 can correct data errors.

Referring now to Figure 6A, a product code encoder 58 may be a product code (C _p) 86 in the form of data encoded in an exemplary two-dimensional (2D) during a write operation. C _p = C ₁ × C ₂ , where C ₁ may represent a (N ₁ , K ₁ ) code, and in a direction in which the code length N ₁ and the data length K _{1 are} perpendicular, the (N ₁ , K ₁ ) code may be Binary linear code. C ₂ may represent a (N ₂ , K ₂ ) code, and in the direction in which the code length N ₂ and the information length K _{2 are} perpendicular, the (N ₂ , K ₂ ) code may also be a binary linear code. The product code 86 can represent a (N ₁ N ₂ , K ₁ K ₂ ) linear code.

That is, C ₁ and C ₂ may have K ₁ and K ₂ data bits, respectively, and become N ₁ and N ₂ encoded bits, respectively, after encoding. The product code can be constructed by first storing K ₁ × K ₂ data bits in a 2D array of blocks 1 having K ₁ rows and K ₂ columns. Block 1 can be expressed as: Where D represents data and i and j represent rows and columns of the matrix. D _i,j (i=1, 2, . . . , K ₁ ; j=1, 2, . . . , K ₂ ) may be 0 or 1. Block 2 can be constructed by providing a (N ₁ -K ₁ ) bit check of the C ₁ code to each column of the first through K ₂ columns. Block 2 can be represented as a N ₁ -K ₁ row and K ₂ 2D array columns. Blocks 3 and 4 may be constructed by subsequently provided to the respective line C from the first to N ₁ row ₂ codes (N ₂ -K ₂₎ test bit.

Block 1 specifies the original data bit K ₁ × K ₂ , and blocks 2 and 3 each specify a check on the original data bit. Block 4 can specify a redundancy check for block 2-3. Block 4 may thus comprise (N ₁ -K ₁ )×(N ₂ -K ₂ ) test data.

Referring now to Figure 6B, this figure further illustrates the exemplary product code 86 of Figure 6A. Line encoder 74 may each row of data 88-1,88-2, ..., 88-P, and encoded, and each row can represent the code word C _2. Column encoder 76 may encode each of the columns 90-1, 90-2, ..., and 90-Q, and each column can be a C ₁ in the codeword. One or both of C ₁ and C ₂ may include a Reed-Solomon (RS) code, a Bose-Chaudhuri-Hochquenghem (BCH) binary code, a Hamming code, and the like. C ₁ and C ₂ may also include loop redundancy code (CRC), Golay code, Reed-Moore code, Goppa code, low density parity check (LDPC) code, turbo code, convolutional code, trellis coding. Modulation (TCM), block code modulation (BCM), and the like.

The total code rate of the product code may be (K ₁ *K ₂ )/(N ₁ *N ₂ ). If C ₁ has a minimum Hamming distance d ₁ and C ₂ has a minimum Hamming distance d ₂ , the product code may have a minimum Hamming distance d ₁ ×d ₂ .

Referring again to Figures 4 and 5, the product code encoder 58 can encode the product code dimension by dimension. For example, for the 2D product code in Figures 6A and 6B, each row can be encoded first using row encoder 74. The encoded bits can be converted to a matrix format. Product code encoder 58 may then encode each column using column encoder 76. Alternatively, the column can be encoded before the line.

Product code decoder 72 may first decode each row using row decoder 78 and then decode each column using column decoder 80 (or vice versa). The product code decoder 72 receives the stored material line by line or column by column from the demodulator 70. The decoder 72 may first decode line by line, which may allow for the correction of burst errors when receiving data column by column, and vice versa. Subsequent column (or row) decoding can clean up the error correction caused by row (or column) decoding.

In an alternate embodiment, decoder 72 may perform error detection based on decoding for only one dimension. When row decoder 78 detects an error on the line, row decoder (or error correction module 82) marks the row as erased. Column decoder 80 and error correction module 82 then perform error and erasure decoding using the erases flagged by row decoder 78.

Product code decoder 72 may be repeated between row and column decoders 78,80. First, row decoder 78 can be used to correct each line. For each row, the row decoder 78 may store several bits m _P, the digit is the row number of symbols in the 88-P corrected. Larger m _P values may correspond to rows that are more likely to have been incorrectly corrected. Uncorrectable row may be assigned to m _{P =} "infinity", and the error correction module 82 may erase all symbols in this row.

Column decoder 80 can then be used to sequentially correct the columns using error and erase correction methods. For example, if the decoding fails because the column is uncorrectable, or if the correction is successful, but the decoding changes the symbols in the unerased rows, then some row decoding may be incorrect. In this case, the error correction module 82 can be erased two most unreliable unerased rows (row having the maximum value m _P) and the repetitive decoding of the column.

Referring now to Figure 7, the product code may allow decoding burst errors and random errors to occur simultaneously. Therefore, the burst error decoder 84 can operate in parallel with the iterative product code decoder 72 in the decoder module 89. If the decoder 72, 84 determines a valid codeword, then the decoding can be considered successful.

Referring now to Figure 8, which illustrates an exemplary performance curves 2D product code 150, wherein C ₁ and C ₂ comprise a BCH code. Curve 150 shows the word error rate (WER) at the output of the product code decoder. The raw bit error rate (BER) 156 and the original WER 158 are also shown based on the error rate and signal to noise ratio (SNR). In one example of the present disclosure, both C ₁ and C ₂ include (511, 466) binary BCH codes. The parameters of C ₁ and C ₂ may include N ₁ = N ₂ = 511, k ₁ = K ₂ = 466, and d ₁ = d ₂ = 11, that is, each code can correct up to 5 bit errors. The product code can have a minimum Hamming distance _dmin = 121 and can correct up to 60 bit errors. The code rate is 0.83. The resulting product code performance is shown as curve 150. The coding gain can be greater than 6.5 dB at WER of 10 ^-10 , which is a considerable improvement over unencoded system performance.

The larger coding gain from the product code allows for an increase in the capacity and/or reliability of the non-volatile memory system. If the number of stages in each memory cell is increased from 4 to 8, the noise margin can be reduced, and thus the original BER is increased. The final WER from the product code decoder may be less than 10 ^-13 when the original BER is approximately 10 ^-4 .

Referring now to Figure 9, a block diagram 200 illustrates a method for encoding and decoding NV memory. The method begins in step 204 when data is received from a memory controller. In step 206, the data is encoded by the product code encoder into rows and columns of codewords. In step 208, the modulator modulates the encoded data. In step 210, the modulated material is stored into the NV memory by a write operation. In step 212, the stored material is read from the NV memory and demodulated. In step 214, the demodulated data is decoded and the error corrected.

Referring now to FIG. 10, although the above examples illustrate 2D product codes, the present disclosure may also include 3D or higher dimensions. For example, FIG. 10 shows a 3-dimensional (3D) product code 220. The product code 220 is based on the product of the codewords in 3 dimensions such that C _p = C ₁ × C ₂ × C ₃ , where C ₁ × C ₂ × C ₃ represents the codes in the first, second, and third dimensions, respectively. / Codewords 222, 224 and 226. Moreover, each dimension may or may not be in the form of a "rectangular". If the encoder input is X ₀ , X ₁ , ... X _N-1 , where N = N ₁ * N ₂ , the dimension in the rectangular form can be mathematically represented by the first (row) dimension (X _i ), such that i=mN ₂ +z, where 0 m<N ₁ , m is the row index. 0 z N ₂ ,z lists all the bits in the same row. Furthermore, the dimension can be represented by the second (column) dimension (X _j ) such that j=sN ₁ +t, where 0 s N ₂ , s is the column index; and 0 t<N ₁ ,t lists all the bits in the same column.

Other methods can also be used to qualify each dimension. For example, a row can be used for the first dimension and a diagonal for the second dimension. For this arrangement, bits X ₀ through X _{N-1 are} first arranged in a matrix, where each bit can be indexed by X _i,j . The dimension is then mathematically defined as the first (row) dimension (X _i,j ), where i is the row index and j enumerates all the bits in the same row. Furthermore, the second (diagonal) dimension (X _i,j ) is defined such that i-j=m, where m is the diagonal index. All combinations of (i, j) satisfying i-j=m can enumerate all bits in the same diagonal.

Product codes or other combination codes can also be used as component codes for one or more dimensions. For example, in Figure 6A, code 1 in the column dimension can be a product code. Using the product code as a component code simplifies the decoding of the corresponding dimensions and achieves a higher coding gain.

Referring now to Figures 11A-11G, these figures illustrate various exemplary implementations incorporating the teachings of the present disclosure. Referring now to FIG. 11A, the teachings of the present disclosure can be used to encode, decode, and correct data for NV memory 312 of a hard disk drive (HDD) 300. The HDD 300 includes a hard disk component (HDA) 301 and an HDD PCB 302. The HDA 301 can include a magnetic medium 303 (eg, one or more discs that store material) and a read/write device 304. The read/write device 304 can be disposed on the execution arm 305 and can read material on the magnetic medium 303 and write data onto the magnetic medium 303. In addition, the HDA 301 includes a spindle motor 306 that rotates the magnetic medium 303 and a voice coil motor (VCM) 307 that drives the actuator arm 305. Preamplifier component 308 amplifies the signal generated by read/write device 304 during a read operation and provides a signal to read/write device 304 during a write operation.

The HDD PCB 302 includes a read/write channel module (hereinafter referred to as "read channel") 309, a hard disk controller (HDC) module 310, a buffer 311, an NV memory 312, a processor 313, and a spindle/VCM driver module. Group 314. Read channel 309 processes the data received and transmitted to preamplifier 308. The HDC module 310 controls the elements of the HDA 301 and communicates with external devices (not shown) via the I/O interface 315. External devices may include computers, multimedia devices, mobile computing devices, and the like. The I/O interface 315 can include wired and/or wireless communication links.

The HDC module 310 can receive data from the HDA 301, the read channel 309, the buffer 311, the non-volatile memory 312, the processor 313, the spindle/VCM driver module 314, and/or the I/O interface 315. The processor 313 can process the data, including encoding, decoding, filtering, and/or formatting. The processed data can be output to HDA 301, read channel 309, buffer 311, non-volatile memory 312, processor 313, spindle/VCM driver module 314, and/or I/O interface 315.

The HDC module 310 can utilize the buffer 311 and/or the non-volatile memory 312 to store data related to the control and operation of the HDD 300. The buffer 311 may include a DRAM, an SDRAM, or the like. Non-volatile memory 312 may include flash memory memory (including NAND and NOR flash memory), phase change memory, magnetic RAM or multi-state memory (where each memory cell has more than two Status). Spindle/VCM driver module 314 controls spindle motor 306 and VCM 307. The HDD PCB 302 includes a power source 316 that provides power to components of the HDD 300.

Referring now to FIG. 11B, the teachings of the present disclosure can be used to encode, decode, and correct data for the NV memory 323 of a DVD drive 318 or a CD drive (not shown). The DVD drive 318 includes a DVD PCB 319 and a DVD component (DVDA) 320. The DVD PCB 319 includes a DVD control module 321, a buffer 322, an NV memory 323, a processor 324, a spindle/FM (feed motor) driver module 325, an analog front end module 326, a write strategy module 327, and a DSP module. Group 328.

The DVD control module 321 controls the elements of the DVDA 320 and communicates with an external device (not shown) via the I/O interface 329. External devices may include computers, multimedia devices, mobile computing devices, and the like. I/O interface 329 can include wired and/or wireless communication links.

The DVD control module 321 can receive from the buffer 322, the non-volatile memory 323, the processor 324, the spindle/FM driver module 325, the analog front end module 326, the write strategy module 327, the DSP module 328, and/or Information on the I/O interface 329. Processor 324 can process the data, including encoding, decoding, filtering, and/or formatting. The DSP module 328 performs signal processing, such as video and/or audio encoding/decoding. The processed data can be output to buffer 322, non-volatile memory 323, processor 324, spindle/FM driver module 325, analog front end module 326, write strategy module 327, DSP module 328, and/or I/O interface 329.

The DVD control module 321 can utilize the buffer 322 and/or the non-volatile memory 323 to store data related to the control and operation of the DVD drive 318. Buffer 322 can include DRAM, SDRAM, and the like. The non-volatile memory 323 may include flash memory memory (including NAND and NOR flash memory), phase change memory, magnetic RAM, or multi-state memory (where each memory cell has more than two Status). The DVD PCB 319 includes a power source 330 that provides power to components of the DVD drive 318.

The DVDA 320 can include a preamplifier 331, a laser driver 332, and an optical device 333, which can be an optical read/write (ORW) device or an optical read only (OR) device. Spindle motor 334 rotates optical storage medium 335 and feed motor 336 drives optical device 333 relative to optical storage medium 335.

Upon reading data from the optical storage medium 335, the laser driver provides read power to the optical device 333. The optical device 333 detects material from the optical storage medium 335 and transmits the data to the preamplifier 331. The analog front end module 326 receives the material from the preamplifier 331 and performs functions such as filtering and A/D conversion. In order to write to the optical storage medium 335, the write strategy module 327 sends the power level and timing data to the laser driver 332. The laser driver 332 controls the optical device 333 to write material to the optical storage medium 335.

Referring now to FIG. 11C, the teachings of the present disclosure can be used to encode, decode, and correct data for memory 341 in high definition television (HDTV) 337. The HDTV 337 includes an HDTV control module 338, a display 339, a power source 340, a memory 341, a storage device 342, a network interface 343, and an external interface 345. If the network interface 343 includes a wireless local area network interface, an antenna (not shown) may be included.

The HDTV 337 can receive input signals from a network interface 343 and/or an external interface 345 that transmit and receive data via cable, broadband Internet, and/or satellite. The HDTV control module 338 can process the input signal, including encoding, decoding, filtering, and/or formatting, and generate an output signal. The output signal can be transmitted to one or more of display 339, memory 341, storage device 342, network interface 343, and external interface 345.

The memory 341 may include random access memory (RAM) and/or non-volatile memory, such as a flash memory, a phase change memory, or a multi-state memory (each of which memories) The body unit has more than two states). The storage device 342 can include an optical storage drive (eg, a DVD drive) and/or a hard disk drive (HDD). The HDTV control module 338 communicates with the outside via the network interface 343 and/or the external interface 345. Power source 340 provides power to the components of HDTV 337.

Referring now to FIG. 11D, the teachings of the present disclosure can be used to encode, decode, and correct data for the vehicle 346. Vehicle 346 may include vehicle control system 347, power source 348, NV memory 349, storage device 350, and network interface 352. If the network interface 352 includes a wireless local area network interface, an antenna (not shown) may be included. The vehicle control system 347 can be a powertrain control system, a main body control system, an entertainment control system, an anti-lock braking system (ABS), a navigation system, a remote information processing system, a lane departure system, an adaptive cruise control system, and the like.

Vehicle control system 347 can communicate with one or more sensors 354 and generate one or more output signals 356. The sensor 354 can include a temperature sensor, an acceleration sensor, a pressure sensor, a rotational sensor, a gas flu detector, and the like. The output signal 356 can control engine operating parameters, transmission operating parameters, suspension parameters, and the like.

Power source 348 provides power to the components of vehicle 346. The vehicle control system 347 can store the data in the memory 349 and/or the storage device 350. The memory 349 may include random access memory (RAM) and/or non-volatile memory, such as flash memory, phase change memory or multi-state memory (where each memory) The body unit has more than two states). The storage device 350 can include an optical storage drive (eg, a DVD drive) and/or a hard disk drive (HDD). Vehicle control system 347 can communicate with the outside using network interface 352.

Referring now to FIG. 11E, the teachings of the present disclosure can be used to encode, decode, and correct data for NV memory 364 in cellular telephone 358. The cellular telephone 358 includes a telephone control module 360, a power source 362, an NV memory 364, a storage device 366, and a cellular network interface 367. Cellular phone 358 can include a network interface 368, a microphone 370, an audio output 372 (eg, a speaker and/or output jack), a display screen 374, and a user input device 376 (eg, a keyboard and/or pointing device). If the network interface 368 includes a wireless local area network interface, an antenna (not shown) may be included.

The telephony control module 360 can receive input signals from the cellular network interface 367, the network interface 368, the microphone 370, and/or the user input device 376. The telephony control module 360 can process the signals (including encoding, decoding, filtering, and/or formatting) and generate an output signal. The output signal can be transmitted to one or more of memory 364, storage device 366, cellular network interface 367, network interface 368, and audio output 372.

The memory 364 may include random access memory (RAM) and/or non-volatile memory, such as flash memory, phase change memory or multi-state memory (where each memory) The body unit has more than two states). The storage device 366 can include an optical storage drive (eg, a DVD drive) and/or a hard disk drive (HDD). Power source 362 provides power to the components of cellular telephone 358.

Referring now to FIG. 11F, the teachings of the present disclosure can be used to encode, decode, and correct data for memory 383 in set top box 378. The set top box 378 includes a set top box control module 380, a display 381, a power source 382, a memory 383, a storage device 384, and a network interface 385. If the network interface 385 includes a wireless local area network interface, an antenna (not shown) may be included.

The set top box control module 380 can receive input signals from a network interface 385 and an external interface 387 that can transmit and receive signals via cable, broadband Internet, and/or satellite. The set top box control module 380 can process the signals (including encoding, decoding, filtering, and/or formatting) and generate an output signal. The output signals may include audio and/or video signals in standard and/or high definition formats. The output signal can be transmitted to network interface 385 and/or display 381. Display 381 can include a television, a projector, and/or a monitor.

Power source 382 provides power to the components of set top box 378. The memory 383 may include random access memory (RAM) and/or non-volatile memory, such as flash memory, phase change memory or multi-state memory (where each memory) The body unit has more than two states). The storage device 384 can include an optical storage drive (eg, a DVD drive) and/or a hard disk drive (HDD).

Referring now to FIG. 11G, the teachings of the present disclosure can be used to encode, decode, and correct data in NV memory 392 of a mobile device. The mobile device 389 can include a mobile device control module 390, a power source 391, an NV memory 392, a storage device 393, a WLAN interface 394, and an external interface 399. If the network interface 394 includes a wireless local area network interface, an antenna (not shown) may be included.

Mobile device control module 390 can receive input signals from network interface 394 and/or external interface 399. External interface 399 can include USB, infrared, and/or Ethernet. The input signal can include compressed audio and/or video and can follow the MP3 format. Additionally, the mobile device control module 390 can receive input from a user input 396 such as a keyboard, touch screen, or a single button. The mobile device control module 390 can process the input signal (including encoding, decoding, filtering, and/or formatting) and generate an output signal.

The mobile device control module 390 can output an audio signal to the audio output 397 and output the video signal to the display screen 398. Audio output 397 can include a speaker and/or an output jack. Display 398 may present a graphical user interface, which may include a menu, icons, and the like. Power source 391 provides power to the components of media player 389. The memory 392 may include random access memory (RAM) and/or non-volatile memory, such as flash memory, phase change memory or multi-state memory (each memory) The body unit has more than two states). The storage device 393 can include an optical storage drive (eg, a DVD drive) and/or a hard disk drive (HDD). Mobile devices may include personal digital assistants, media players, laptops, game consoles, or other mobile computing devices.

Those skilled in the art can now appreciate from the foregoing description that the broad teachings of the invention can be implemented in various forms. Accordingly, the present invention is intended to be limited by the scope of the inventions

10. . . Memory

12. . . Memory controller

14. . . Write path

16. . . Reading path

18. . . Encoder

20. . . decoder

30. . . Array

31, 31-1, 31-2, ..., and 31-M. . . Row

32. . . User profile area

34. . . Overhead data area

50. . . Memory storage system

54. . . Write path

56. . . Reading path

58. . . Product code encoder

59. . . Memory controller

60. . . Modulator

62. . . NV memory

70. . . Demodulator

72. . . Product code decoder

74. . . Line encoder

76. . . Column encoder

78. . . Row decoder

80. . . Column decoder

82. . . Error correction module

84. . . Burst error decoder

86. . . Product code (C _p )

88-1, 88-2, ..., and 88-P. . . Row

89. . . Decoder module

90-1, 90-2, ..., and 90-Q. . . Column

220. . . Product code

222, 224 and 226. . . Code/codeword

300. . . Hard disk drive

301. . . Hard disk component (HDA) module

302. . . Hard disk component (HDA) printed circuit board

303. . . Magnetic medium

304. . . Read/write device

305. . . Drive actuator arm

306. . . Spindle motor

307. . . Voice coil motor (VCM)

308. . . Preamplifier

309. . . Read/write channel module

310. . . HDC module

311. . . Buffer module

313. . . processor

314. . . Spindle/VCM driver module

315. . . I/O interface

316. . . power supply

318. . . DVD drive

319. . . DVD PCB

320. . . DVD component (DVDA)

321. . . DVD control module

322. . . buffer

323. . . NV memory

324. . . processor

325. . . Spindle/FM (feed motor) driver module

326. . . Analog front end module

327. . . Write strategy module

328. . . DSP module

329. . . I/O interface

330. . . power supply

331. . . Preamplifier

332. . . Laser driver

333. . . Optical device

334. . . Spindle motor

335. . . Optical storage medium

336. . . motor

337. . . High definition television (HDTV)

338. . . HDTV control module

339. . . monitor

340. . . power supply

341. . . Memory

342. . . Storage device

343. . . Network interface

345. . . External interface

346. . . vehicle

347. . . Vehicle control system

348. . . power supply

349. . . NV memory

350. . . Storage device

352. . . Network interface

354. . . Sensor

356. . . signal

358. . . Cellular phone

360. . . Telephone control module

362. . . power supply

364. . . NV memory

366. . . Storage device

367. . . Cellular network interface

368. . . Network interface

370. . . microphone

372. . . Audio output

374. . . Display screen

376. . . User input device

378. . . Set top box

380. . . Control module

381. . . monitor

382. . . power supply

383. . . Memory

384. . . Storage device

385. . . Network interface

389. . . Mobile devices

390. . . Mobile device control module

391. . . power supply

392. . . NV memory

393. . . Storage device

394. . . WLAN interface

396. . . User input

397. . . Audio output

398. . . Display screen

399. . . External interface

1 is a functional block diagram of a memory system according to the prior art; FIG. 2 is a schematic diagram of a memory array according to the prior art; FIG. 3 is a functional block diagram of a memory system according to the present disclosure; Functional block diagram of a product code encoder; FIG. 5 is a functional block diagram of a product code decoder in accordance with the present disclosure; FIGS. 6A-6B are schematic diagrams of a memory array in accordance with the present disclosure; FIG. 7 is a product code decoding in accordance with the present disclosure. Functional block diagram of the device; FIG. 8 is a diagram showing exemplary performance of a non-volatile memory system; FIG. 9 is a block diagram showing a method for encoding and decoding non-volatile memory according to the present disclosure. Figure 10 is a schematic diagram of a three-dimensional (3D) product code in accordance with the present disclosure; Figure 11A is a functional block diagram of a hard disk drive; Figure 11B is a functional block diagram of a DVD drive; Figure 11C is a functional block diagram of a high definition television; 11D is a functional block diagram of the vehicle control system; FIG. 11E is a functional block diagram of the cellular phone; FIG. 11F is a functional block diagram of the set top box; and FIG. 11G is a functional block diagram of the mobile device.

50. . . Memory storage system

54. . . Write path

56. . . Reading path

58. . . Product code encoder

59. . . Memory controller

60. . . Modulator

62. . . NV memory

70. . . Demodulator

72. . . Product code decoder

Claims (13)

A memory storage system comprising: a non-volatile semiconductor memory; a product code encoder comprising: a first encoder configured to encode data in a codeword in a first dimension; and a first a second encoder configured to encode data in a codeword in a second dimension, wherein the product code encoder is configured to provide a product codeword for storage in the non-volatile semiconductor memory, The product code codeword is based on the codewords in the first dimension and the codewords in the second dimension; a modulator configured to map bits of the product code codeword to the non-volatile semiconductor a corresponding voltage level in the cells of the memory; a demodulator configured to read the voltage levels in the cells and convert the voltage levels into bits corresponding to the product codeword; And a decoder comprising: a product code decoder configured to perform iterative decoding on the product code codeword; and a burst code decoder configured to perform the product codeword word in parallel with the iterative decoding Burst error decoding. The memory storage system of claim 1, further comprising: a write path including the product code encoder and the modulator; and a read path including the demodulator and the decoder. The memory storage system of claim 1, wherein the non-volatile semiconductor memory comprises a single-level cell non-volatile semiconductor memory or a multi-level cell non-volatile semiconductor memory. The memory storage system of claim 1, wherein the first encoder and the second encoder are configured to be encoded according to Bose-Chaudhuri-Hochquenghem (BCH) encoding. The memory storage system of claim 1, wherein the product code encoder is configured to be iterated between the codewords in the first dimension and the codewords in the second dimension. . The memory storage system of claim 1, wherein the decoder is configured to store an indication of a symbol number of the codewords in the first dimension corrected during decoding. The memory storage system of claim 6, wherein the decoder is configured to selectively erase the codewords in the first dimension based on the indication. A memory storage method includes: encoding data in a codeword in a first dimension; encoding data in a codeword in a second dimension; providing for storage in a non-volatile semiconductor memory a product codeword in which the codeword is based on the codewords in the first dimension and the codewords in the second dimension; mapping the bits of the product codeword to the non-volatile Corresponding voltage levels in the cells of the semiconductor memory; reading the voltage levels in the cells; converting the voltage levels into bits corresponding to the product codeword; the product code The word performs iterative decoding; and performs burst error decoding on the product code codeword in parallel with the iterative decoding. The memory storage method of claim 8, wherein the non-volatile semiconductor memory comprises a single-level cell non-volatile semiconductor memory or a multi-level cell non-volatile semiconductor memory. The memory storage method of claim 8, wherein the data in the codewords in the first dimension is encoded and the codes in the second dimension are The encoding of the material in the word includes encoding according to the Bose-Chaudhuri-Hochquenghem (BCH) encoding. The memory storage method of claim 8, wherein the data in the codewords in the first dimension is encoded and the data in the codewords in the second dimension is performed. Encoding the codewords included in the first dimension and the iterations between the codewords in the second dimension. The memory storage method of claim 8, further comprising storing an indication of a symbol number of the codewords in the first dimension corrected during decoding. The memory storage method of claim 12, further comprising selectively erasing the codewords in the first dimension based on the indication.