JP2009271963A - Decoding method, hard disk controller, and hard disk device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce decoding time without propagating the error of LDPC, in a method for decoding a dual code by using an RS code as an external code and a LDPC code as an internal code. <P>SOLUTION: A decoding device is provided with: an LDPC decoder 84 for supplying likelihood of reproduced data output from a magnetic head, adjusting the likelihood according to an RS decoding result, and performing LDPC decoding for hard determination result of the reproduced data based on the adjusted likelihood; and an RS decoder 86 for performing RS decoding for the decoding result of the LDPC decoder. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an error correction code decoding method, and more particularly, a code that is double-encoded using an LDPC (Low Density Parity Check) code as an inner code using a code capable of limit distance decoding as an outer code. It relates to the decoding method.

  When digital data (encoded data) is communicated or recorded, an error may occur in the digital data due to external noise or the like. Therefore, an error correction code is used to detect and correct such an error. In the error correction code, redundant data is added to data at the time of encoding, and data error is corrected based on this redundant data at the time of decoding.

  As this error correction code, there are a Reed Solomon code and an LDPC code. The Reed-Solomon code is a block code capable of limit distance decoding that can correct errors in a plurality of consecutive bit units (symbols). Specifically, the Reed-Solomon code correction process includes a step of generating a syndrome and detecting an error position, a step of calculating and correcting an error value, checking a correction result, and a step of outputting the correction result. . Another example of a block code that can be decoded by a limit distance is a BCH code.

  However, the information amount of data recorded on recent recording media has been extremely increased, and there has been a problem that the error correction capability of the Reed-Solomon code is not always sufficient. Therefore, it has been considered to combine a Reed-Solomon code and an LDPC code (see Patent Document 1). In encoding, RS encoding is first performed, and then LDPC encoding is performed. In decoding, LDPC decoding is first performed, and then RS decoding is performed.

An LDPC code is a block code defined by a sparse check matrix, and is decoded by an iterative decoding process. The advantages of the LDPC code include, for example, excellent decoding performance close to the Shannon limit, and a parallel processing structure suitable for high-speed decoding by hardware. However, in the LDPC code, when the number of generated errors is equal to or greater than the number of correctable errors, the errors may propagate and conversely increase the errors. In such a case, correction is not possible unless the RS code is made very powerful (error correction capability is enhanced). In order to reduce the effect of increasing the error, it is conceivable to deliberately suppress the code length of the LPDPC code. However, this causes a decrease in the performance of the LDPC code itself, which is not preferable. In addition, LDPC decoding repeats the decoding process until the number of errors becomes a certain number or less, but RS decoding is not started even if the number of errors becomes equal to or less than the number that can be corrected by the next stage RS decoding. Throughput tends to be low and the total decoding time tends to be long.
JP 2007-336529 A

  As described above, in the conventional decoding method, it is necessary to reduce the performance of the LDPC code itself in order to suppress the influence of error propagation of the LDPC code, and even if the error is within the range that can be decoded by the RS code. In addition, since decoding of LDPC is continued, there is a disadvantage that decoding time becomes long.

  An object of the present invention is to provide a decoding method capable of suppressing the influence of LDPC code error propagation without increasing the decoding time.

A decoding method according to an aspect of the present invention is a decoding method for decoding a double-encoded code using an LDPC code as an inner code, using a code capable of limit distance decoding as an outer code,
Adjust the likelihood according to the outer decoding result,
An inner decoding process is performed based on the adjusted likelihood, and an outer decoding process is performed according to the inner decoding result.

A hard disk controller according to an aspect of the present invention includes:
An outer encoder that performs an encoding process capable of limit distance decoding on recorded data;
An inner encoder that interleaves an outer codeword sequence output from the outer encoder, LDPC-encodes the interleaved outer codeword sequence, and supplies double-encoded recording data to the magnetic head;
An inner decoder which is supplied with the likelihood of the reproduction data output from the magnetic head, adjusts the likelihood according to the outer decoding result, and performs an inner decoding process on the reproduction data based on the adjusted likelihood;
An outer decoder that performs outer decoding processing on the reproduction data;
It is characterized by comprising.

A hard disk device according to an aspect of the present invention includes:
A head disk assembly including a magnetic disk, a magnetic head, a first motor for rotating the magnetic head, and a second motor for moving the magnetic head;
A hard disk device comprising: a motor driver connected to the first motor and the second motor; and a hard disk controller including a signal processing unit connected to the magnetic head.
The hard disk controller is
An outer encoder that performs an encoding process capable of limit distance decoding on recorded data;
An inner encoder that interleaves an outer codeword sequence output from the outer encoder, LDPC-encodes the interleaved outer codeword sequence, and supplies double-encoded recording data to the magnetic head;
An inner decoder which is supplied with the likelihood of the reproduction data output from the magnetic head, adjusts the likelihood according to the outer decoding result, and performs an inner decoding process on the reproduction data based on the adjusted likelihood;
An outer decoder that performs outer decoding processing on the reproduction data;
It is characterized by comprising.

  As described above, according to the present invention, the likelihood is adjusted according to the outer decoding result, the inner decoding process is performed based on the adjusted likelihood, and the outer decoding process is performed according to the inner decoding result. Therefore, when the number of errors is small, the outer decoding result is trusted, so that the inner decoding and outer decoding processes can be shared, the outer decoding and inner decoding processes do not overlap, and the inner code (LDPC code) ) Error propagation and processing time can be shortened.

  Embodiments of a decoding method according to the present invention will be described below with reference to the drawings.

First Embodiment FIG. 1 is a block diagram showing a configuration of a hard disk device which is an example of an application example of a decoding method according to a first embodiment of the present invention. The hard disk device performs error correction coding on recorded information and records the information on a magnetic disk, and reproduces the recorded information by error correction decoding data reproduced from the magnetic disk.

  The hard disk device includes a head disk assembly (HDA) 12 and a signal processing board 14, and the signal processing board 14 is connected to a host system 18 such as a personal computer via a general-purpose bus, for example, an ATA (IDE) bus 16. The hard disk device may be either a built-in type disposed in a housing of a personal computer as the host system 18 or an external type disposed outside the housing.

  The CPU 20 controls each part in the signal processing board 14 and the head IC 54 in a time-sharing manner.

  The head disk assembly 12 includes a magnetic disk 24. For example, the upper surface of the magnetic disk 24 forms a recording surface on which data is magnetically recorded. A magnetic head 26 is disposed corresponding to the recording surface of the magnetic disk 24. The magnetic head 26 is used for data writing (data recording) to the magnetic disk 24 and data reading (data reproduction) from the disk. Although not shown, the lower surface of the magnetic disk 24 also forms a recording surface, and a head similar to the head 26 is disposed corresponding to the recording surface. In the configuration of FIG. 1, a hard disk device including a single disk 24 is assumed, but a hard disk device in which a plurality of disks 24 are stacked may be used.

  The motor driver 22 drives a spindle motor (SPM) 28 for rotating the magnetic disk 24 and a voice coil motor (VCM) 30 for moving the magnetic head 26 to a target track position under the control of the CPU 20. Current is passed through the spindle motor 28 and the voice coil motor 30.

  A CPU bus 34 connected to the CPU 20 includes a ROM 36 in which a program to be executed by the CPU 20 is recorded, a RAM 38 for use in storing variables, a hard disk controller (HDC) 40, and various signals necessary for control. A gate array 42 is connected.

  The control registers of the hard disk controller (HDC) 40 and the gate array 42 are respectively allocated to a part of the memory space of the CPU 20, and the hard disk controller 40 and the gate array 42 are read and written by the CPU 20 with respect to this area. Control.

  The hard disk controller 40 mainly includes a servo block 46 that performs signal processing necessary for positioning processing of the magnetic head 26, a read / write channel 48 that performs signal processing for data read / write, an error correction circuit 50, a host It is roughly divided into a host block 52 that performs interface control with the system 18. A buffer RAM 56 is also connected to the hard disk controller 40.

  On the magnetic disk 24, areas (servo areas) where servo data signals for positioning are recorded and areas (data areas) for recording data transferred from the host system 18 are alternately arranged. . When the positioning process of the magnetic head 26 is performed, the analog signal read from the magnetic head 26 and amplified by the head IC 54 is sent to the hard disk controller 48, and servo data is extracted by the servo block 46. Servo data is supplied to the gate array 42 and processed. The CPU 20 controls the motor driver 22 based on the processing result of the gate array 42, and passes a current for positioning the magnetic head 26 to the voice coil motor 30.

  At the time of reading, an analog signal is read from the magnetic disk 24 by the magnetic head 26 and amplified by the head IC 54. The amplified analog signal is decoded by the read / write channel 48 in the hard disk controller 40 and error-corrected by the error correction circuit 50. The decoded signal after error correction is processed in accordance with each control signal from the gate array 42 to generate data to be transferred to the host system 18.

  At the time of writing, the data transferred from the host system 18 to the hard disk controller 40 is temporarily stored in the buffer RAM 56, and then an error is caused by the read / write channel 48 and the error correction circuit 50 in accordance with each control signal from the gate array 42. Correction encoded. The encoded data is written to the magnetic disk 24 by the magnetic head 26 via the head IC 54.

  FIG. 2 is a block diagram showing details of error correction encoding / decoding processing of the error correction circuit 50.

  The recording data is supplied to an RLL (Run Length Limited) encoder 72 and converted into an RLL sequence.

  The output of the RLL encoder 72 is supplied to an RS (Reed-Solomon) encoder 74 and subjected to Reed-Solomon (RS) encoding. Since Reed-Solomon encoding is the first encoding in double encoding, the Reed-Solomon code is referred to as an outer code, and the RS encoder 74 is referred to as an outer encoder. The outer code needs to be a code capable of limit distance decoding, and a BCH code may be used instead of the Reed-Solomon code.

  The output of the RS encoder 74 is supplied to the LDPC encoder 76, the RS codeword is interleaved, and each interleaved sequence is LDPC encoded. Since LDPC encoding is the second encoding in double encoding, the LDPC code is referred to as an inner code, and the LDPC encoder 76 is referred to as an inner encoder.

  The output of the LDPC encoder 76 is recorded on the magnetic disk 24 by a magnetic recording channel 78 (consisting of a part of the read / write channel 48 and the head IC 54).

  Noise may occur during recording and reproduction, and an error may occur in the data. This state is shown as noise input to the adder 80.

  The signal reproduced from the magnetic disk 24 by the detection channel 82 (consisting of a part of the read / write channel 48 and the head IC 54) is waveform-equivalent to a target PR (Partial Response) sequence and decoded by the APP detector. The Typical APP detectors include a SOVA (Soft-Output Viterbi Algorithm) decoder and a Max-Log-Map decoder. This detector outputs a numerical value (soft decision result) called likelihood indicating the certainty of the hard decision result together with 0 and 1 decoding results (hard decision result). Since this likelihood is output on a log scale in order to simplify the hardware implementation, it is called LLR (Log-Likelihood-Ratio).

  The likelihood is input to an LDPC decoder 84 as an inner decoder, and the hard decision result is input to an LDPC decoder 84 and an RS decoder 86 as an outer decoder. The RS decoder 86 performs RS decoding based on the hard decision result (decoding result of 0, 1). The RS decoder 86 supplies an adjustment signal having a likelihood corresponding to the number of errors detected by the RS decoding to the LDPC decoder 84.

  The LDPC decoder 84 increases or decreases the likelihood supplied from the detection channel 82 according to the adjustment signal supplied from the RS decoder 86 (there may be invariable). The LDPC decoder 84 performs LDPC decoding on the hard decision result supplied from the detection channel 82 based on the likelihood corrected by such increase / decrease processing. The LDPC decoding result is supplied to the RS decoder 84, and RS decoding is performed.

  The decoding operation of the LDPC decoder 84, the decoding operation of the RS decoder 86 (and the adjustment of the likelihood) until the result of the decoding processing of the LDPC decoder 84 indicates the normal end of the decoding and the result of the decoding processing of the RS decoder 86 is no error. ) Is repeated. The output of the RS decoder 84 becomes reproduction data.

  FIG. 3 is a flowchart for explaining the encoding operation of FIG.

  In block # 12, the recording data is converted into an RLL sequence by the RLL encoder 72. For example, 512-byte recording data is converted into a 4120-bit RLL sequence (see FIGS. 5A and 5B).

  In block # 14, the output of the RLL encoder 72 is supplied to an RS (Reed Solomon) encoder 74, and a 4120-bit RLL sequence is divided into 10 parts, and each is Reed-Solomon (RS) encoded. Here, the RS code has error correction capability at three locations, and has 6 symbols (42 bits) of redundant symbols per information word (412 bits). The 42-bit redundant symbols are distributed (interleaved) in the information word of the RS code (see (c) and (d) in FIG. 5).

  In block # 16, the output of the RS encoder 74 is supplied to the LDPC encoder 76, and as shown in FIG. 5, each RS codeword (one RS codeword in which one rectangle in FIG. 4 is 454 bits) is interleaved into four, In each interleave sequence, 10 RS codewords are connected to create 4 sequences (vertical sequence in FIG. 4). Each of these sequences is LDPC encoded. Redundant symbols of the LDPC code are P1, P2, P3, and P4 in FIG. These redundant symbols are also dispersed in the information word of the LDPC code in the same manner as the RS code.

  In block # 18, the output of the LDPC encoder 76 is recorded on the magnetic disk 24 by the magnetic recording channel 78.

  FIG. 6 is a flowchart for explaining the decoding operation of FIG.

  The signal reproduced from the magnetic disk 24 by the detection channel 82 in block # 32 is waveform-equivalent to a target PR (Partial Response) sequence.

  In block # 34, decoding by the APP detector in the detection channel 82 is performed, and likelihood (LLR value) is output together with decoding results (hard decision results) of 0 and 1.

  In block # 36, the RS decoder 86 is operated, and 10 RS codewords are decoded based on the hard decision result. There is a possibility that a data error has occurred during recording and reproduction. If an error has occurred, the error is detected by RS decoding. As described above, since the RS code has error correction capability at three locations, errors up to three locations can be corrected.

  In block # 38, processing according to the presence or absence of an error is performed. For example, if there is no error, the likelihood is maximized while keeping the hard decision results of 0 and 1 as they are. If one error is detected, one error correction is performed and the likelihood is increased by 50%. If two errors are detected, two error corrections are performed and the likelihood is increased by 10%. If three errors are detected, three error corrections are performed, but the likelihood is reduced by 10%. If four or more errors (uncorrectable) are detected, error correction processing is not performed and the likelihood is reduced by 30%. An adjustment signal for increasing or decreasing the likelihood is supplied from the RS decoder 86 to the LDPC decoder 84.

  In block # 40, the LDPC decoder 84 increases or decreases (may be unchanged) the likelihood supplied from the detection channel 82 in accordance with the adjustment signal supplied from the RS decoder 86, and then detects based on the corrected likelihood. LDPC decoding is performed a predetermined number of times on the hard decision result supplied from the channel 82.

  When LDPC iterative decoding is performed a predetermined number of times, the presence or absence of an error is determined in block # 42. If there is an error, as shown in block # 36, the RS decoder 86 is operated and RS decoding is performed again.

  If it is determined in block # 42 that there is no error, it is determined in block # 44 whether or not the error is zero in the RS decoding result. If there is an error, as shown in block # 36, the RS decoder 86 is operated and RS decoding is performed again.

  If it is determined that there is no error in block # 44, there is no error in both RS decoding and LDPC decoding, so that RLL decoding is performed in block # 46 and reproduction data is obtained.

  As described above, according to the present embodiment, error correction is performed according to the number of errors (symbols) detected by RS decoding (the hard decision result is changed), and the likelihood is increased according to the number of corrected errors. LDPC decoding is started after changing the value. LDPC decoding is performed only for a predetermined number of iterations. If there is an error, RS decoding is performed again. Therefore, since there is no LDPC decoding even though there are more errors than the number of correctable errors, no error is propagated in the LDPC decoding. In other words, LDPC decoding is not performed until errors are eliminated, and if errors are reduced to the number that can be corrected by the next stage RS decoding, LDPC decoding is terminated and RS decoding is started. High and total decoding time is shortened. Furthermore, it is not necessary to make the RS code very strong (those with improved error correction capability).

In order to maximize the merit of the present embodiment, it is desirable to make the code length of the LDPC code as long as possible, and the code length of the RS code should be as short as possible within a range where the error correction probability is low. Is desirable. This is desirable in terms of strengthening the LDPC code and shortening the decoding time of the RS code.
Modifications The present invention is not limited to the above-described embodiments, and can be implemented with various modifications. For example, in the above description, the hard disk device has been described as an application example of the decoding method. However, a recording / reproducing device using another storage medium such as a floppy disk device, a DVD device, or a semiconductor memory may be used, and encoded data is transmitted. It may be a device that does.

  The number of RLL bits, RS codeword length, number of redundant bits and capability (number of correctable errors), number of RS code interleaves, LDPC code length and number of redundant bits are examples, and can be changed arbitrarily Is possible. Further, the ratio of increasing or decreasing the likelihood according to the number of errors corrected by the RS decoder is such that the smaller the number of errors, the larger the likelihood (LLR value), and the smaller the number of errors, the smaller the likelihood. Any change is possible. In short, in order to suppress the adverse effects of erroneous correction, the smaller the number of errors, the more reliable the correction result.

  Further, in the RS decoder, it is not necessary to correct the error by maximizing the capability of the RS code. For example, if three errors are detected, the likelihood may be reduced by 20% without performing error correction.

  The likelihood adjustment signal output from the RS decoder may be fed back to the APP detector, and the decoding may be performed again from the APP detector.

  First, the RS decoder performs decoding processing, adjusts the likelihood of LDPC decoding according to the number of errors, performs LDPC iterative decoding processing a predetermined number of times, and if there is an error, RS decoding is performed again. First, the LDPC decoding process may be performed a predetermined number of times with the likelihood output from the APP detector, then the RS decoding process may be performed, the likelihood may be adjusted according to the number of errors, and the LDPC iterative decoding process may be performed a predetermined number of times. . In short, since LDPC decoding and RS decoding are alternately and repeatedly performed in the above-described embodiment, the order of LDPC decoding and RS decoding is not limited to FIG. 6, and the likelihood of LDPC decoding according to the RS decoding result. Should be adjusted. Note that RS decoding may not be performed after the error becomes 0 in LDPC decoding. For example, an LDPC decoder may be configured to have a CRC circuit, and the error correction probability may be reduced there.

1 is a diagram showing a schematic configuration of a hard disk device according to an embodiment of the present invention. The block diagram which shows the structure of the principal part of the read / write channel of FIG. The flowchart which shows encoding operation | movement. The figure explaining the outline | summary of RS encoding. The figure explaining the outline | summary of LDPC encoding. The flowchart which shows decoding operation | movement.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 12 ... Head disk assembly, 14 ... Signal processing board, 40 ... Hard disk controller, 48 ... Read / write channel, 50 ... Error correction circuit, 72 ... RLL encoder, 74 ... RS encoder, 76 ... LDPC encoder, 84 ... LDPC decoder , 86... RS decoder, 88... RLL decoder.

Claims (23)

In a decoding method for decoding a double-encoded code using a code capable of limit distance decoding as an outer code and using an LDPC code as an inner code,
Adjust the likelihood according to the outer decoding result,
A decoding method characterized by performing an inner decoding process based on the adjusted likelihood and performing an outer decoding process according to the inner decoding result. 2. The decoding method according to claim 1, wherein an outer decoding process is first performed, and a likelihood of the inner decoding process is adjusted according to a decoding result of the outer decoding process. 2. The decoding method according to claim 1, wherein the inner decoding process is performed once, and then the outer decoding process is performed, and the likelihood of the inner decoding process is adjusted according to the decoding result of the outer decoding process. 2. The decoding method according to claim 1, wherein the inner decoding process and the outer decoding process are repeated until the result of the inner decoding process indicates a normal end of decoding and the result of the outer decoding process is no error. 2. The outer decoding process corrects m errors that are positive integers less than n when the outer code is a code that can correct n errors that are arbitrary positive integers. Decoding method as described. 2. The decoding method according to claim 1, wherein the numerical value representing the likelihood is increased as the number of errors corrected by the outer decoding process is smaller. 2. The decoding method according to claim 1, wherein when the correction is impossible by the outer decoding process, the numerical value indicating the likelihood is decreased. An outer encoder that performs an encoding process capable of limit distance decoding on recorded data;
An inner encoder that interleaves an outer codeword sequence output from the outer encoder, LDPC-encodes the interleaved outer codeword sequence, and supplies double-encoded recording data to the magnetic head;
An inner decoder which is supplied with the likelihood of the reproduction data output from the magnetic head, adjusts the likelihood according to the outer decoding result, and performs an inner decoding process on the reproduction data based on the adjusted likelihood;
An outer decoder that performs outer decoding processing on the reproduction data;
A hard disk controller comprising: The reproduction data output from the magnetic head is supplied to the outer decoder, the outer decoder is first operated, and the likelihood of the reproduction data is adjusted according to the decoding result of the outer decoder, and the inner decoder 9. The hard disk controller according to claim 8, wherein the hard disk controller is operated. First, the inner decoder is operated once, the reproduction data output from the inner decoder is supplied to the outer decoder, the outer decoder is operated, and the reproduction data according to the decoding result of the outer decoder. 9. The hard disk controller according to claim 8, wherein the inner decoder is operated by adjusting the likelihood of. The inner decoder and the outer decoder are alternately and repeatedly operated until the decoding result of the inner decoder indicates a normal end of decoding and the decoding result of the outer decoder becomes error-free. The hard disk controller according to claim 8. The outer encoder generates a code capable of correcting n errors which are arbitrary positive integers;
9. The hard disk controller according to claim 8, wherein the outer decoder corrects m errors that are positive integers less than n. 9. The hard disk controller according to claim 8, wherein the inner decoder increases a numerical value indicating the likelihood of reproduced data as the number of errors corrected by the outer decoder is smaller. 9. The hard disk controller according to claim 8, wherein the inner decoder decreases a numerical value indicating the likelihood of reproduced data when the outer decoder cannot correct the data. 9. The hard disk controller according to claim 8, wherein the inner encoder encodes an outer codeword having a number larger than m as one inner codeword, where m is an interleave number of outer codewords. A head disk assembly including a magnetic disk, a magnetic head, a first motor for rotating the magnetic head, and a second motor for moving the magnetic head;
A hard disk device comprising: a motor driver connected to the first motor and the second motor; and a hard disk controller including a signal processing unit connected to the magnetic head.
The hard disk controller is
An outer encoder that performs an encoding process capable of limit distance decoding on recorded data;
An inner encoder that interleaves an outer codeword sequence output from the outer encoder, LDPC-encodes the interleaved outer codeword sequence, and supplies double-encoded recording data to the magnetic head;
An inner decoder which is supplied with the likelihood of the reproduction data output from the magnetic head, adjusts the likelihood according to the outer decoding result, and performs an inner decoding process on the reproduction data based on the adjusted likelihood;
An outer decoder that performs outer decoding processing on the reproduction data;
A hard disk device comprising: The reproduction data output from the magnetic head is supplied to the outer decoder, the outer decoder is first operated, and the likelihood of the reproduction data is adjusted according to the decoding result of the outer decoder, and the inner decoder The hard disk device according to claim 16, wherein the hard disk device is operated. First, the inner decoder is operated once, the reproduction data output from the inner decoder is supplied to the outer decoder, the outer decoder is operated, and the reproduction data according to the decoding result of the outer decoder. 17. The hard disk drive according to claim 16, wherein the inner decoder is operated by adjusting the likelihood of. The inner decoder and the outer decoder are alternately and repeatedly operated until the decoding result of the inner decoder indicates a normal end of decoding and the decoding result of the outer decoder becomes error-free. The hard disk device according to claim 16. 17. The outer decoding process corrects m errors that are positive integers less than n when the outer code is a code that can correct n errors that are arbitrary positive integers. The hard disk device described. 17. The hard disk drive according to claim 16, wherein the inner decoder increases a numerical value indicating the likelihood of reproduced data as the number of errors corrected by the outer decoder is smaller. 17. The hard disk device according to claim 16, wherein the inner decoder decreases a numerical value indicating the likelihood of the reproduction data when the outer decoder cannot correct it. 17. The hard disk drive according to claim 16, wherein the inner encoder encodes an outer codeword having a number larger than m as one inner codeword, where m is an interleave number of outer codewords.

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