CN103309766A - Error correction method of cyclic hamming code based on parallel coding and decoding - Google Patents

Abstract

The invention relates to the technical field of error correction codes, and discloses an error correction method of a cyclic hamming code based on parallel coding and decoding. The method comprises the steps that a structure of the traditional serial cyclic redundancy check (CRC) coding circuit is analyzed; a recurrence relation among data in five registers of the serial CRC coding circuit is obtained; the recurrence relation is expanded; a relational expression between a check bit and an information bit in the parallel coding is obtained; the parallel coding is performed according to the relational expression between the check bit and the information bit in the parallel coding; a relational expression between a new check bit and a new coded character code in the parallel decoding is obtained; the parallel decoding is performed; a code word is obtained; and finally, the code word obtained through the parallel decoding is subjected to error correction. The method adopts a parallel mode to perform coding and decoding on input data, so that the coding speed and the decoding speed of an input signal are increased, the error correction of the input signal is realized, and the added check bits are minimum.

Description

Error correction method based on the circulation Hamming code of parallel encoding decoding

Technical field

The present invention relates to the error-correcting code technique field, particularly a kind of error correction method of the circulation Hamming code based on parallel encoding decoding.

Background technology

CRC(Cyclic Redundancy Check, cyclic redundancy check (CRC) code) be a kind of efficient error correcting code, its loop coding makes it communicate by letter in raising, automatically control with the decoding characteristics and the aspects such as reliability of storer are widely used.Common CRC coding and decoding adopts serial mode to realize, the required circuit of the coding and decoding of this scheme is very little, but the coding and decoding time but depend on clock period and code word size, therefore requiring high occasion seeming inapplicable to circuit speed.

(22,16) Hsiao code is a kind of linear block codes commonly used, can remedy a mistake and detect the error correcting code (SECDED) of two mistakes.By its corresponding generator matrix and check matrix, can design corresponding the parallel combined decoding scheme, thereby greatly shorten the coding and decoding time.(but 22,16) Hsiao code needs 6 redundancy check bits, has increased the area of the peripheral EDAC circuit of SRAM and register.

Summary of the invention

In view of this, the object of the present invention is to provide a kind of error correction method of the circulation Hamming code based on parallel encoding decoding, be used for improving coding and decoding efficient.

The invention provides a kind of error correction method of the circulation Hamming code based on parallel encoding decoding, comprising:

Obtain the Recurrence Relation between the data in five registers of serial cyclic redundancy check (CRC) code CRC coding circuit:

$\left\{\begin{array}{c}{s}_4^{i+1}=s_3^i\\ s_3^{i+1}=s_2^i\\ s_2^{i+1}=s_4^i+u_{i+1}+s_1^i\\ s_1^{i+1}=s_0^i\\ s_0^{i+1}=s_4^i+u_{i+1}\end{array}\right.$

Wherein, s0i+1 represents to input the value of i+1 data late register s0 the inside, s1i+1 represents to input the value of i+1 data late register s1 the inside, s2i+1 represents to input the value of i+1 data late register s2 the inside, s3i+1 represents to input the value of i+1 data late register s3 the inside, and s4i+1 represents to input the value of i+1 data late register s4 the inside; S0i represents to input the value of i data late register s0 the inside, s1i represents to input the value of i data late register s1 the inside, s2i represents to input the value of i data late register s2 the inside, s3i represents to input the value of i data late register s3 the inside, and s4i represents to input the value of i data late register s4 the inside; Ui+1 represents i+1 information bit inputting;

Described Recurrence Relation is launched to obtain the relational expression between the check bit sum information bit in the parallel encoding:

$\left\{\begin{array}{c}{\mathrm{<figure-callout\; id="4"\; label="S"\; filenames="HDA00003380993900012.png,HDA00003380993900022.png"\; state="\{\{state\}\}">S</figure-callout>}}_4^{16}=u_{12}\&CirclePlus;u_{11}\&CirclePlus;u_{10}\&CirclePlus;u_9\&CirclePlus;u_8\&CirclePlus;u_5\&CirclePlus;u_4\&CirclePlus;u_2\\ S_3^{16}=u_{15}\&CirclePlus;u_{11}{\&CirclePlus;u}_{10}\&CirclePlus;u_9\&CirclePlus;u_8\&CirclePlus;u_7\&CirclePlus;u_4\&CirclePlus;u_3\&CirclePlus;u_1\\ {\mathrm{<figure-callout\; id="2"\; label="S"\; filenames="HDA00003380993900012.png"\; state="\{\{state\}\}">S</figure-callout>}}_2^{16}=u_{15}\&CirclePlus;u_{14}\&CirclePlus;u_{10}\&CirclePlus;u_9\&CirclePlus;u_8\&CirclePlus;u_7\&CirclePlus;u_6\&CirclePlus;u_3\&CirclePlus;u_2\&CirclePlus;u_0\\ S_1^{16}=u_{14}\&CirclePlus;u_{13}\&CirclePlus;u_{12}\&CirclePlus;u_{11}\&CirclePlus;u_{10}\&CirclePlus;u_7\&CirclePlus;u_6\&CirclePlus;u_4\&CirclePlus;u_1\\ S_0^{16}=u_{13}\&CirclePlus;u_{12}\&CirclePlus;u_{11}\&CirclePlus;u_{10}\&CirclePlus;u_9\&CirclePlus;u_6\&CirclePlus;u_5\&CirclePlus;u_3\&CirclePlus;u_0\end{array}\right.$

Carry out parallel encoding according to described relational expression;

Obtain the relational expression between the new coding character code of check bit sum new in the parallel decoding, and carry out parallel decoding and obtain code word;

The code word that obtains by described parallel decoding is carried out error correction.

The error correction method of the circulation Hamming code based on parallel encoding decoding provided by the invention adopts parallel mode that the input data are carried out coding and decoding, not only improved the coding and decoding speed of input signal, and realized error correction to input signal, and the check bit of adding is minimum, only need five check bit, compare few one of (22,16) Hsiao code.

Description of drawings

The error correction method process flow diagram of a kind of circulation Hamming code based on parallel encoding decoding that Fig. 1 provides for the embodiment of the invention;

Fig. 2 is the digital circuit figure of conventional serial CRC coding circuit;

The digital circuit figure of the part parallel coding circuit that the error correction method based on the circulation Hamming code of parallel encoding decoding that Fig. 3 provides for the embodiment of the invention makes up;

The digital circuit figure of the part parallel decoding scheme that the error correction method based on the circulation Hamming code of parallel encoding decoding that Fig. 4 provides for the embodiment of the invention makes up;

The digital circuit figure of the part error correction circuit that the error correction method based on the circulation Hamming code of parallel encoding decoding that Fig. 5 provides for the embodiment of the invention makes up.

Embodiment

For making the purpose, technical solutions and advantages of the present invention clearer, the present invention is described in further detail below in conjunction with accompanying drawing.

The error correction method process flow diagram of a kind of circulation Hamming code based on parallel encoding decoding that Fig. 1 provides for the embodiment of the invention may further comprise the steps:

Step 101, obtain the Recurrence Relation between the data in five registers of serial CRC coding circuit.That is:

$\left\{\begin{array}{c}{s}_4^{i+1}=s_3^i\\ s_3^{i+1}=s_2^i\\ s_2^{i+1}=s_4^i+u_{i+1}+s_1^i\\ s_1^{i+1}=s_0^i\\ s_0^{i+1}=s_4^i+u_{i+1}\end{array}\right.$

Wherein, s ₀ ^I+1I+1 data late register s of expression input ₀The value of the inside, s ₁ ^I+1I+1 data late register s of expression input ₁The value of the inside, s ₂ ^I+1I+1 data late register s of expression input ₂The value of the inside, s ₃ ^I+1I+1 data late register s of expression input ₃The value of the inside, s ₄ ^I+1I+1 data late register s of expression input ₄The value of the inside; s ₀ ⁱI data late register s of expression input ₀The value of the inside, s ₁ ⁱI data late register s of expression input ₁The value of the inside, s ₂ ⁱI data late register s of expression input ₂The value of the inside, s ₃ ⁱI data late register s of expression input ₃The value of the inside, s ₄ ⁱI data late register s of expression input ₄The value of the inside; u _I+1I+1 information bit of expression input.

Concrete, as shown in Figure 2, clock signal clk controls five registers, is respectively register s ₀, register s ₁, register s ₂, register s ₃With register s ₄When the clock rising edge arrived, next stage was sent in the output of register, register s ₄The output signal of coming in an input send into XOR gate 1, and then deliver to register s ₀, register s ₁Output send into XOR gate 2 with XOR gate 1; XOR gate 2 is sent to data register s again ₂, the rest may be inferred.After information bit input was finished, the value of preserving in five registers was exactly the value of five bit check positions.Five interior data of preserving of register are with external world's input, ring shift.Understand according to algebraic method, five bit check positions are exactly the information bit polynomial expression that information bit consists of, and then multiply by X ⁵(output of input message and rightmost register together computing is equivalent to multiply by X ⁵), again divided by generator polynomial p corresponding to CPC (X)=1+X ²+ X ⁵The coefficient of the residue that obtains.Thereby obtain the Recurrence Relation between the data in the register.

Step 102, Recurrence Relation is launched to obtain the relational expression between the check bit sum information bit in the parallel encoding.Namely

$\left\{\begin{array}{c}{\mathrm{<figure-callout\; id="4"\; label="s"\; filenames="HDA00003380993900012.png,HDA00003380993900022.png"\; state="\{\{state\}\}">s</figure-callout>}}_4^{16}=u_{12}\&CirclePlus;u_{11}\&CirclePlus;u_{10}\&CirclePlus;u_9\&CirclePlus;u_8\&CirclePlus;u_5\&CirclePlus;u_4\&CirclePlus;u_2\\ s_3^{16}=u_{15}\&CirclePlus;u_{11}{\&CirclePlus;u}_{10}\&CirclePlus;u_9\&CirclePlus;u_8\&CirclePlus;u_7\&CirclePlus;u_4\&CirclePlus;u_3\&CirclePlus;u_1\\ {\mathrm{<figure-callout\; id="2"\; label="s"\; filenames="HDA00003380993900012.png"\; state="\{\{state\}\}">s</figure-callout>}}_2^{16}=u_{15}\&CirclePlus;u_{14}\&CirclePlus;u_{10}\&CirclePlus;u_9\&CirclePlus;u_8\&CirclePlus;u_7\&CirclePlus;u_6\&CirclePlus;u_3\&CirclePlus;u_2\&CirclePlus;u_0\\ s_1^{16}=u_{14}\&CirclePlus;u_{13}\&CirclePlus;u_{12}\&CirclePlus;u_{11}\&CirclePlus;u_{10}\&CirclePlus;u_7\&CirclePlus;u_6\&CirclePlus;u_4\&CirclePlus;u_1\\ s_0^{16}=u_{13}\&CirclePlus;u_{12}\&CirclePlus;u_{11}\&CirclePlus;u_{10}\&CirclePlus;u_9\&CirclePlus;u_6\&CirclePlus;u_5\&CirclePlus;u_3\&CirclePlus;u_0\end{array}\right.$

Concrete grammar comprises:

Introduce first matrix F:

$F=\left[\begin{array}{cccc}{p}_{m-1}& & & \\ p_{m-2}& & & I_{m-1,m-1}\\ \&CenterDot;& & & \\ \&CenterDot;& & & \\ \&CenterDot;& & & \\ p_0& 0& 0& 0\end{array}\right]=\left[\begin{array}{ccccc}0& 1& 0& 0& 0\\ 0& 0& 1& 0& 0\\ 1& 0& 0& 1& 0\\ 0& 0& 0& 0& 1\\ 1& 0& 0& 0& 0\end{array}\right]$

P wherein ₀Be 0 power coefficient of generator polynomial corresponding to (31,26) CRC, P _M-1Be m-1 power coefficient of generator polynomial corresponding to (31,26) CRC, P _M-2Be m-2 power coefficient of generator polynomial corresponding to (31,26) CRC, I _{M-1, m-1}It is the square formation of (m-1) * (m-1).

Establish again: A=[1,0,0,0,0] ^T, U=[u ₁₅, u ₁₄..., u ₀], wherein U is the set of information bit code, then:

Again the Recurrence Relation between the data in five registers in the serial CRC coding circuit is simplified and is obtained:

$S^{i+1}=F[S^i\&CirclePlus;G_{,i+1}]$ （1）

Wherein, S ^I+1Syndrome vector in i+1 data late register of expression input, S ⁱSyndrome vector in i data late register of expression input, G _{, i+1}The i+1 row of expression G matrix, and 0≤i≤15.

Again (1) formula is launched, obtained

$\&DoubleRightArrow;S^{i+1}=F^{i+1}{S}^0\&CirclePlus;F^{i+1}{G}_{,1}\&CirclePlus;F^i{G}_{,2}\&CirclePlus;\&CenterDot;\&CenterDot;\&CenterDot;{\&CirclePlus;\mathrm{FG}}_{,i+1}$ （2）

Because the data in register initial value satisfies: S ⁰=0; Then can be with (2) formula abbreviation

$\&DoubleRightArrow;S^{i+1}=F^{i+1}{G}_{,1}\&CirclePlus;F^i{G}_{,2}\&CirclePlus;\&CenterDot;\&CenterDot;\&CenterDot;\&CirclePlus;{\mathrm{FG}}_{,i+1}$ （3）

By Matlab (3) formula is calculated:

$S^{16}=u_{15}\left[01100\right]\&CirclePlus;u_{14}\left[00110\right]\&CirclePlus;\&CenterDot;\&CenterDot;\&CenterDot;\&CirclePlus;u_0\left[00101\right]$ （4）

(4) formula is launched release to be obtained:

$\left\{\begin{array}{c}{\mathrm{<figure-callout\; id="4"\; label="s"\; filenames="HDA00003380993900012.png,HDA00003380993900022.png"\; state="\{\{state\}\}">s</figure-callout>}}_4^{16}=u_{12}\&CirclePlus;u_{11}\&CirclePlus;u_{10}\&CirclePlus;u_9\&CirclePlus;u_8\&CirclePlus;u_5\&CirclePlus;u_4\&CirclePlus;u_2\\ s_3^{16}=u_{15}\&CirclePlus;u_{11}{\&CirclePlus;u}_{10}\&CirclePlus;u_9\&CirclePlus;u_8\&CirclePlus;u_7\&CirclePlus;u_4\&CirclePlus;u_3\&CirclePlus;u_1\\ {\mathrm{<figure-callout\; id="2"\; label="s"\; filenames="HDA00003380993900012.png"\; state="\{\{state\}\}">s</figure-callout>}}_2^{16}=u_{15}\&CirclePlus;u_{14}\&CirclePlus;u_{10}\&CirclePlus;u_9\&CirclePlus;u_8\&CirclePlus;u_7\&CirclePlus;u_6\&CirclePlus;u_3\&CirclePlus;u_2\&CirclePlus;u_0\\ s_1^{16}=u_{14}\&CirclePlus;u_{13}\&CirclePlus;u_{12}\&CirclePlus;u_{11}\&CirclePlus;u_{10}\&CirclePlus;u_7\&CirclePlus;u_6\&CirclePlus;u_4\&CirclePlus;u_1\\ s_0^{16}=u_{13}\&CirclePlus;u_{12}\&CirclePlus;u_{11}\&CirclePlus;u_{10}\&CirclePlus;u_9\&CirclePlus;u_6\&CirclePlus;u_5\&CirclePlus;u_3\&CirclePlus;u_0\end{array}\right.$

Step 103, make up the parallel encoding circuit according to the relational expression between the check bit sum information bit in the parallel encoding, by the parallel encoding circuit input signal is carried out parallel encoding again.

Step 104, obtain the relational expression between the new coding character code of check bit sum new in the parallel decoding, and carry out parallel decoding and obtain code word.Concrete grammar is:

Introduce first matrix F:

$F=\left[\begin{array}{cccc}{p}_{m-1}& & & \\ p_{m-2}& & & I_{m-1,m-1}\\ \&CenterDot;& & & \\ \&CenterDot;& & & \\ \&CenterDot;& & & \\ p_0& 0& 0& 0\end{array}\right]=\left[\begin{array}{ccccc}0& 1& 0& 0& 0\\ 0& 0& 1& 0& 0\\ 1& 0& 0& 1& 0\\ 0& 0& 0& 0& 1\\ 1& 0& 0& 0& 0\end{array}\right]$

P wherein ₀Be 0 power coefficient of generator polynomial corresponding to (31,26) CRC, P _M-1Be m-1 power coefficient of generator polynomial corresponding to (31,26) CRC, P _M-2Be m-2 power coefficient of generator polynomial corresponding to (31,26) CRC, I _{M-1, m-1}It is the square formation of (m-1) * (m-1).

Establish again A=[1,0,0,0,0] ^T, V=[v ₂₀, v ₁₉, v ₁₈..., v ₀], wherein V is the set of coding character code, then

Wherein, H is information bit matrix to be encoded.

Because traditional serial decoding is actually a polynomial division circuit, according to recurrence relation, therefore final five bit check subvector S and the relational expression between the information bit matrix H to be encoded are in parallel decoding:

Wherein, S ²¹After the input of 21 bit word is finished, the syndrome vector S in the register, and S=(s ₀, s ₁, s ₂, s ₃, s ₄), H ₁Be the first row of H matrix, H ₂Be the secondary series of H matrix, H21 is the 21 row of H matrix.

Again five final in parallel decoding bit check subvector S and the relationship expression between the information bit matrix H to be encoded are launched to obtain the relational expression between the new coding character code of check bit sum new in the parallel decoding, and the relational expression between the new coding character code of the new check bit sum in the parallel decoding that launches to obtain is:

$\left\{\begin{array}{c}{\mathrm{<figure-callout\; id="4"\; label="s"\; filenames="HDA00003380993900012.png,HDA00003380993900022.png"\; state="\{\{state\}\}">s</figure-callout>}}_4^{21}=v_{20}\&CirclePlus;v_{19}\&CirclePlus;v_{17}\&CirclePlus;v_{16}\&CirclePlus;v_{12}\&CirclePlus;v_{11}\&CirclePlus;v_{10}{\&CirclePlus;v}_9\&CirclePlus;v_8\&CirclePlus;v_5\&CirclePlus;v_4{\&CirclePlus;v}_2\\ s_3^{21}=v_{20}{\&CirclePlus;v}_{19}\&CirclePlus;v_{18}\&CirclePlus;v_{16}\&CirclePlus;v_{15}\&CirclePlus;v_{11}\&CirclePlus;v_{10}\&CirclePlus;v_9\&CirclePlus;v_8\&CirclePlus;v_7\&CirclePlus;v_4\&CirclePlus;v_3\&CirclePlus;v_1\\ {\mathrm{<figure-callout\; id="2"\; label="s"\; filenames="HDA00003380993900012.png"\; state="\{\{state\}\}">s</figure-callout>}}_2^{21}=v_{19}\&CirclePlus;v_{18}\&CirclePlus;v_{17}\&CirclePlus;v_{15}\&CirclePlus;v_{14}\&CirclePlus;v_{10}\&CirclePlus;v_9\&CirclePlus;v_8\&CirclePlus;v_7\&CirclePlus;v_6\&CirclePlus;v_3\&CirclePlus;v_2\&CirclePlus;v_0\\ s_1^{21}=v_{19}\&CirclePlus;v_{18}\&CirclePlus;v_{14}\&CirclePlus;v_{13}{\&CirclePlus;v}_{12}\&CirclePlus;v_{11}\&CirclePlus;v_{10}{\&CirclePlus;v}_7{\&CirclePlus;v}_6\&CirclePlus;v_4\&CirclePlus;v_1\\ s_0^{21}=v_{20}\&CirclePlus;v_{18}\&CirclePlus;v_{17}\&CirclePlus;v_{13}\&CirclePlus;v_{12}\&CirclePlus;v_{11}\&CirclePlus;v_{10}\&CirclePlus;v_9\&CirclePlus;v_6\&CirclePlus;v_5{\&CirclePlus;v}_3{\&CirclePlus;v}_0\end{array}\right.$

Step 105, make up the parallel decoding circuit according to the relational expression between the new coding character code of check bit sum new in the parallel decoding, by the parallel decoding circuit coding character code is carried out parallel decoding again and obtain code word.

Step 106, the code word that obtains by parallel decoding is carried out error correction.Concrete grammar is:

To multiply by X through power corresponding to the code word that parallel decoding obtains first ⁵, again divided by generator polynomial p corresponding to CRC (X)=1+X ²+ X ⁵, and determine whether according to the operation result that obtains code word is carried out error correction.

If operation result is 0, illustrate that then the code word that obtains through parallel decoding can be divided exactly by generator polynomial corresponding to CRC, namely saltus step does not occur in code word, does not need error correction; If operation result is not 0, illustrate that then the code word that obtains through parallel decoding can not be divided exactly by generator polynomial corresponding to CRC, be that saltus step has occured code word, then make up error correction circuit, and the coefficient that operation result is corresponding is done and the door computing, and will do XOR with result and the code word of door computing, realize error correction.

Based on the error correction method of the circulation Hamming code of parallel encoding decoding 16 SRAM is carried out error correction based on what the embodiment of the invention provided, because to be processed is 16 information bit, must shorten 10 by (31,26) CRC, consist of (21,16) and shorten the circulation Hamming code.Establishing first five redundancy check bit polynomial expressions is:

s(X)=s ₀+s ₁X+s ₂X ²+s ₃X ³+s ₄X ⁴

If 16 information bit polynomial expressions are:

u(X)=u ₀+u ₁X+u ₂X ²+…+u ₁₅X ¹⁵

If 21 bit code polynomial expressions are:

v(X)=v ₀+v ₁X+v ₂X ²+…+v ₂₀X ²⁰

Wherein, v ₀To v ₄The sub-s of corresponding redundancy check ₀To s ₄, v ₅To v ₂₀Corresponding informance position u ₀To u ₁₅

The generator polynomial that (31,26) CRC is corresponding is:

p(X)=p ₀+p ₁X+…+p ₅X ⁵=1+X ²+X ⁵

Obtain in the serial CRC coding circuit Recurrence Relation between the data in five registers by traditional CRC coding circuit again, Recurrence Relation is launched to obtain the relational expression between the check bit sum information bit in the parallel encoding, namely

$\left\{\begin{array}{c}{\mathrm{<figure-callout\; id="4"\; label="s"\; filenames="HDA00003380993900012.png,HDA00003380993900022.png"\; state="\{\{state\}\}">s</figure-callout>}}_4^{16}=u_{12}\&CirclePlus;u_{11}\&CirclePlus;u_{10}\&CirclePlus;u_9\&CirclePlus;u_8\&CirclePlus;{\mathrm{<figure-callout\; id="5"\; label="u"\; filenames="HDA00003380993900023.png"\; state="\{\{state\}\}">u</figure-callout>}}_5\&CirclePlus;{\mathrm{<figure-callout\; id="4"\; label="u"\; filenames="HDA00003380993900012.png,HDA00003380993900022.png"\; state="\{\{state\}\}">u</figure-callout>}}_4\&CirclePlus;u_2\\ s_3^{16}=u_{15}\&CirclePlus;u_{11}{\&CirclePlus;u}_{10}\&CirclePlus;u_9\&CirclePlus;u_8\&CirclePlus;u_7\&CirclePlus;{\mathrm{<figure-callout\; id="4"\; label="u"\; filenames="HDA00003380993900012.png,HDA00003380993900022.png"\; state="\{\{state\}\}">u</figure-callout>}}_4\&CirclePlus;u_3\&CirclePlus;u_1\\ {\mathrm{<figure-callout\; id="2"\; label="s"\; filenames="HDA00003380993900012.png"\; state="\{\{state\}\}">s</figure-callout>}}_2^{16}=u_{15}\&CirclePlus;u_{14}\&CirclePlus;u_{10}\&CirclePlus;u_9\&CirclePlus;u_8\&CirclePlus;u_7\&CirclePlus;u_6\&CirclePlus;u_3\&CirclePlus;{\mathrm{<figure-callout\; id="2"\; label="u"\; filenames="HDA00003380993900012.png"\; state="\{\{state\}\}">u</figure-callout>}}_2\&CirclePlus;u_0\\ s_1^{16}=u_{14}\&CirclePlus;u_{13}\&CirclePlus;u_{12}\&CirclePlus;u_{11}\&CirclePlus;u_{10}\&CirclePlus;u_7\&CirclePlus;u_6\&CirclePlus;{\mathrm{<figure-callout\; id="4"\; label="u"\; filenames="HDA00003380993900012.png,HDA00003380993900022.png"\; state="\{\{state\}\}">u</figure-callout>}}_4\&CirclePlus;u_1\\ s_0^{16}=u_{13}\&CirclePlus;u_{12}\&CirclePlus;u_{11}\&CirclePlus;u_{10}\&CirclePlus;u_9\&CirclePlus;u_6\&CirclePlus;{\mathrm{<figure-callout\; id="5"\; label="u"\; filenames="HDA00003380993900023.png"\; state="\{\{state\}\}">u</figure-callout>}}_5\&CirclePlus;u_3\&CirclePlus;u_0\end{array}\right.$ （5）

Then make up the parallel encoding circuit according to the relational expression between the check bit sum information bit in the parallel encoding, by the parallel encoding circuit input signal is carried out parallel encoding again, Fig. 3 is the digital circuit figure by the part parallel coding circuit of the present embodiment structure; Then obtain the relational expression between the new coding character code of check bit sum new in the parallel decoding, namely

$\left\{\begin{array}{c}{s}_4^{21}=v_{20}\&CirclePlus;v_{19}\&CirclePlus;v_{17}\&CirclePlus;v_{16}\&CirclePlus;v_{12}\&CirclePlus;v_{11}\&CirclePlus;v_{10}{\&CirclePlus;v}_9\&CirclePlus;v_8\&CirclePlus;v_5\&CirclePlus;v_4{\&CirclePlus;v}_2\\ s_3^{21}=v_{20}{\&CirclePlus;v}_{19}\&CirclePlus;v_{18}\&CirclePlus;v_{16}\&CirclePlus;v_{15}\&CirclePlus;v_{11}\&CirclePlus;v_{10}\&CirclePlus;v_9\&CirclePlus;v_8\&CirclePlus;v_7\&CirclePlus;v_4\&CirclePlus;v_3\&CirclePlus;v_1\\ s_2^{21}=v_{19}\&CirclePlus;v_{18}\&CirclePlus;v_{17}\&CirclePlus;v_{15}\&CirclePlus;v_{14}\&CirclePlus;v_{10}\&CirclePlus;v_9\&CirclePlus;v_8\&CirclePlus;v_7\&CirclePlus;v_6\&CirclePlus;v_3\&CirclePlus;v_2\&CirclePlus;v_0\\ s_1^{21}=v_{19}\&CirclePlus;v_{18}\&CirclePlus;v_{14}\&CirclePlus;v_{13}{\&CirclePlus;v}_{12}\&CirclePlus;v_{11}\&CirclePlus;v_{10}{\&CirclePlus;v}_7{\&CirclePlus;v}_6\&CirclePlus;v_4\&CirclePlus;v_1\\ s_0^{21}=v_{20}\&CirclePlus;v_{18}\&CirclePlus;v_{17}\&CirclePlus;v_{13}\&CirclePlus;v_{12}\&CirclePlus;v_{11}\&CirclePlus;v_{10}\&CirclePlus;v_9\&CirclePlus;v_6\&CirclePlus;v_5{\&CirclePlus;v}_3{\&CirclePlus;v}_0\end{array}\right.$ （6）

Make up the parallel decoding circuit according to the relational expression between the new coding character code of check bit sum new in the parallel decoding again, by the parallel decoding circuit coding character code is carried out parallel decoding and obtain code word, Fig. 4 is the digital circuit figure by the part parallel decoding scheme of the present invention's structure.To multiply by X through power corresponding to the code word that parallel decoding obtains again ⁵, again divided by generator polynomial p corresponding to CRC (X)=1+X ²+ X ⁵, and determine whether according to the operation result that obtains code word is carried out error correction.

For example: if code word v ₂₀Saltus step occurs, and the redundancy check vector that then calculates must equal X ²⁰* X ⁵=X ²⁵(v ₂₀Corresponding power is X ²⁰, because from the input of circuit right-hand member, therefore multiply by X ⁵), divided by generator polynomial p (X)=1+X ²+ X ⁵The residue that obtains is 1+X ³+ X ⁴Corresponding syndrome vector is: S=10011 (s ₀s ₁s ₂s ₃s ₄), logical operation s is satisfied in design ₀﹠amp; (! s ₁) ﹠amp; (! s ₂) ﹠amp; s ₃﹠amp; s ₄With door, if the result is 1, then by with v ₂₀Carry out XOR the value on this is overturn, thereby information bit is corrected, Fig. 5 is the v that is made up by the present embodiment ₂₀The digital circuit figure (all the other are similar) of corresponding error correction circuit.

And for example: U=[u ₀u ₁u ₂U ₁₅]=[110 ... 0], obtain code word by formula (5) coding:

[s ₀s ₁…s ₄,u ₀u ₁…u ₁₅]=[11110,110…0]

Wherein, the first five is the redundancy check bit that generates; Rear sixteen bit is information bit.If u ₀Saltus step occurs, and becomes:

[s ₀s ₁…s ₄,u ₀u ₁…u ₁₅]=[11110,010…0]

Generate five new bit check positions by formula (6), obtain check bit [s ₀s ₁S ₄]=[10100], inevitable corresponding to X ⁵Divided by generator polynomial p (X)=1+X ²+ X ⁵Residue 1+X ²Because u ₀Corresponding X own ⁰, be equivalent to multiply by X from the right-hand member input ⁵, as long as error correction circuit is so that residue 1+X so ²Coefficient [10100] be 1, again with u ₀(v ₅) XOR gets final product.

The error correction method of the circulation Hamming code based on parallel encoding decoding provided by the invention adopts parallel mode that the input data are carried out coding and decoding, not only improved the coding and decoding speed of input signal, and realized error correction to input signal, and the check bit of adding is minimum.

In a word, the above is preferred embodiment of the present invention only, is not for limiting protection scope of the present invention.

Claims (5)

1. the error correction method based on the circulation Hamming code of parallel encoding decoding is characterized in that, comprising:

Obtain the Recurrence Relation between the data in five registers of serial cyclic redundancy check (CRC) code CRC coding circuit:

Wherein, s ₀ ^I+1I+1 data late register s of expression input ₀The value of the inside, s ₁ ^I+1I+1 data late register s of expression input ₁The value of the inside, s ₂ ^I+1I+1 data late register s of expression input ₂The value of the inside, s ₃ ^I+1I+1 data late register s of expression input ₃The value of the inside, s ₄ ^I+1I+1 data late register s of expression input ₄The value of the inside; s ₀ ⁱI data late register s of expression input ₀The value of the inside, s ₁ ⁱI data late register s of expression input ₁The value of the inside, s ₂ ⁱI data late register s of expression input ₂The value of the inside, s ₃ ⁱI data late register s of expression input ₃The value of the inside, s ₄ ⁱI data late register s of expression input ₄The value of the inside; u _I+1I+1 information bit of expression input;

Described Recurrence Relation is launched to obtain the relational expression between the check bit sum information bit in the parallel encoding:

Carry out parallel encoding according to described relational expression;

Obtain the relational expression between the new coding character code of check bit sum new in the parallel decoding, and carry out parallel decoding and obtain code word;

The code word that obtains by described parallel decoding is carried out error correction.

2. the error correction method of the circulation Hamming code based on parallel encoding decoding according to claim 1 is characterized in that, the described step that Recurrence Relation is launched to obtain the relational expression between the check bit sum information bit in the parallel encoding specifically comprises:

If A=[1,0,0,0,0] ^T, U=[u ₁₅, u ₁₄..., u ₀], wherein U is the set of information bit code, then:

Recurrence Relation between the data in five registers in the described serial CRC coding circuit simplified obtains:

（1）

Wherein, S ^I+1Syndrome vector in i+1 data late register of expression input, S ⁱSyndrome vector in i data late register of expression input, G _{, i+1}The i+1 row of expression G matrix, and 0≤i≤20;

(1) formula is launched, obtained

(2)

Because the data in register initial value satisfies: S ⁰=0, then with (2) formula abbreviation be

（3）

(3) formula is calculated:

（4）

(4) formula is launched to obtain:

。

3. the error correction method of the circulation Hamming code based on parallel encoding decoding according to claim 2 is characterized in that, described step of carrying out parallel encoding according to relational expression specifically comprises:

Make up the parallel encoding circuit according to the relational expression between the check bit sum information bit in the described parallel encoding, by described parallel encoding circuit input signal is carried out parallel encoding again.

4. the error correction method of the circulation Hamming code based on parallel encoding decoding according to claim 2, it is characterized in that, the described relational expression that obtains between the new coding character code of check bit sum new in the parallel decoding, and carry out the step that parallel decoding obtains code word and specifically comprise:

Introduce matrix F:

P wherein ₀Be 0 power coefficient of generator polynomial corresponding to (31,26) CRC, P _M-1Be m-1 power coefficient of generator polynomial corresponding to (31,26) CRC, P _M-2Be m-2 power coefficient of generator polynomial corresponding to (31,26) CRC, I _{M-1, m-1}It is the square formation of (m-1) * (m-1);

If A=[1,0,0,0,0] ^T, V=[v ₂₀, v ₁₉..., v ₂, v ₁, v ₀], wherein V is the set of coding character code, then

Wherein, H is codeword information bit matrix;

Final five bit check subvector S and the relational expression between the information bit matrix H to be encoded are in the parallel decoding:

Wherein, S ₂₁After the input of 21 bit word is finished, the syndrome vector S in the register, and S=(s ₀, s ₁, s ₂, s ₃, s ₄), H ₁Be the first row of H matrix, H ₂Be the secondary series of H matrix, H ₂₁The 21 row for the H matrix;

Five final in described parallel decoding bit check subvector S and the relational expression between the code word H are launched to obtain relational expression between the new coding character code of check bit sum new in the parallel decoding:

Make up the parallel decoding circuit according to the relational expression between the new coding character code of check bit sum new in the described parallel decoding, by described parallel decoding circuit the coding character code is carried out parallel decoding again and obtain code word.

5. the error correction method of the described circulation Hamming code based on parallel encoding decoding of any one in 4 according to claim 1 is characterized in that, the described step that the code word that obtains by parallel decoding is carried out error correction specifically comprises:

Described power corresponding to code word that obtains through parallel decoding be multiply by X ⁵, again divided by generator polynomial p corresponding to CRC (X)=1+X ²+ X ⁵, and determine whether according to the operation result that obtains code word is carried out error correction;

If described operation result is not 0, the code word that then obtains through parallel decoding can not be divided exactly by generator polynomial corresponding to CRC, saltus step has occured in code word, then make up error correction circuit, and the coefficient that operation result is corresponding is done and the door computing, and will do XOR with result and the code word of door computing, realize error correction.

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