CN104506201B - （15,5）The coding circuit design method of BCH code - Google Patents
（15,5）The coding circuit design method of BCH code Download PDFInfo
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Abstract
The present invention provides a kind of coding circuit design method of (15,5) BCH code, which includes：According to the generator polynomial of (15, the 5) BCH code, serial encoding circuitry is constructed；Each register respectively in serial encoding circuitry obtains it is stored after inputting i+1 position information bit redundancy check bit and input the first relational expression after i-th bit information bit between the redundancy check bit of each register memory storage, the i+1 position information bit of input；Each register respectively in serial encoding circuitry obtains the redundancy check bit that it is stored after inputting all 5 information bits and the second relational expression for not inputting the redundancy check bit of each register memory storage when any information bit, whole 5 information bits；According to the second relational expression, parallel encoding circuit is constructed.The present invention replaces traditional tandem coding solution using parallel circuit, greatly shortens the scramble time.
Description
Technical field
The present invention relates to error-correcting code technique field, more particularly to a kind of coding circuit design method of (15,5) BCH code.
Background technology
BCH (BoSe Ray-Chaudhuri Hocque5ghe15) is a kind of efficient error correcting code, loop coding and is translated
Code feature makes it be widely used with the reliability of memory etc. improving communication, automatically control.
Usual Bose-Chaudhuri-Hocquenghem Code is decoded to be realized using serial mode, circuit very little needed for the coding and decoding of this scheme,
But the coding and decoding time with dependence in clock cycle and code word size, therefore requiring high occasion to seem circuit speed
It is not applicable.
(15,5) BCH code can correct 3 mistakes, need 10 redundancy check bits in total, in the GF (2 of m=44)
Three wrong BCH codes can be corrected by being constructed on domain, therefore t=3.In GF (24) on, basis α and α3=α2t-1Corresponding multinomial
Respectively：
φ1(X)=1+X+X4,
φ3(X)=1+X+X2+X3+X4,
φ5(X)=1+X+X2,
The generator polynomial for obtaining (15,5) BCH code is：
G (X)=φ1(X)·φ3(X)·φ5(X)=1+X+X2+X4+X5+X8+X10
According to the expression-form of generator polynomial g (X), coding and decoding circuit is can be designed that as shown in Figure 1, wherein square table
Show register, expression modular two addition device of the circle the inside with plus sige, i.e. XOR gate.As can be seen that traditional BCH code coding needs
By 10 registers, therefore in the synchronous digital circuit of clock control, need 5 clock cycle could be by 5 data bit
It is all sent into shift register and completes coding, speed is slower.It is not particularly suited for high speed Bose-Chaudhuri-Hocquenghem Code circuit.
Invention content
The present invention provides a kind of coding circuit design methods of (15,5) BCH code, can greatly shorten the scramble time,
It is not limited by the clock cycle, coding rate greatly improves.
According to one embodiment of present invention, a kind of coding circuit design method of (15,5) BCH code, the coding are provided
Circuit design method includes：According to the generator polynomial of (15, the 5) BCH code, construct serial with 10 concatenated registers
Coding circuit；According to the serial encoding circuitry, each register respectively in serial encoding circuitry obtains input i+1 position
The redundancy check bit that it is stored after information bit and the redundancy check bit of each register memory storage, input after input i-th bit information bit
I+1 position information bit between the first relational expression, i≤4 and be nonnegative integer；It is respectively serial to compile according to the first relational expression
Each register in code circuit obtains it is stored after inputting all 5 information bits redundancy check bit and do not input any letter
Cease the second relational expression of each register memory stores up when position redundancy check bit, whole 5 information bits；According to the second relational expression, structure
It is input, the parallel encoding circuit that 10 redundancy check bits are output to make with 5 information bits.
Optionally, the redundancy check bit of each register memory storage is both configured to 0 when not inputting any information bit.
Optionally, include according to the step of the first relational expression the second relational expression of acquisition：To be each in serial encoding circuitry
The first relational expression vectorization that register obtains, to obtain indicate input i+1 position information bit after 10 registers storages
The vector for the redundancy check bit that the vector of redundancy check bit is stored with 10 registers after input i-th bit information bit, the of input
The primary vector relational expression of relationship between i+1 information bits；According to primary vector relational expression, obtains and indicate input all 5
The vector for the redundancy check bit that 10 registers store after information bit is stored with 10 registers when not inputting any information bit
The secondary vector relational expression of the vector of redundancy check bit, all relationship between 5 information bits；From secondary vector relational expression,
Obtain the second relational expression for corresponding to each register in serial encoding circuitry.
The present invention redundancy check that each register stores after first obtaining input i+1 position information bit in serial encoding circuitry
Pass behind position and input i-th bit information bit between the redundancy check bit of each register memory storage, the i+1 position information bit of input
System, so obtain input all after 5 information bits the redundancy check bit of each register storage with it is each when not inputting any information bit
The relationship of the redundancy check bit of register memory storage, all 5 information bits, the relationship are exactly 10 redundancy check bits and 5 letters
Cease position relationship, so as to construct with 5 information bits be input, 10 redundancy check bits be output parallel encoding circuit.
Compared with the serial encoding circuitry of the prior art, traditional tandem coding solution is replaced using parallel circuit, it can not be by clock
The limitation in period, greatly shortens the scramble time, and coding rate greatly improves.
Description of the drawings
By reading a detailed description of non-restrictive embodiments in the light of the attached drawings below, of the invention other
Feature, objects and advantages will become more apparent upon.
Fig. 1 is the coding circuit of (15,5) BCH code of the prior art；
Fig. 2 is the structure first as (15,5) BCH code of an example of the coding circuit of (15,5) BCH code of the invention
The serial encoding circuitry made；
Fig. 3 is the last structure as (15,5) BCH code of an example of the coding circuit of (15,5) BCH code of the invention
The parallel encoding circuit produced；
Fig. 4 is the flow chart of the coding circuit design method of (15,5) BCH code according to an embodiment of the invention.
Specific implementation mode
The embodiment of the present invention is described below in detail.
Examples of the embodiments are shown in the accompanying drawings, and in which the same or similar labels are throughly indicated identical or classes
As element or element with the same or similar functions.The embodiments described below with reference to the accompanying drawings are exemplary, only
For explaining the present invention, and it is not construed as limiting the claims.Following disclosure provide many different embodiments or
Example is used for realizing the different structure of the present invention.In order to simplify disclosure of the invention, hereinafter to the component of specific examples and setting
It sets and is described.Certainly, they are merely examples, and is not intended to limit the present invention.
The present invention provides a kind of coding circuit design methods of (15,5) BCH code, and the wherein digit of information bit is 5, is compiled
Total bit after code is 15, and the digit of redundancy check bit is 10.As shown in figure 4, this method includes：
In step S1, according to the generator polynomial of (15, the 5) BCH code, construct serial with 10 concatenated registers
Coding circuit.
By taking (15,5) BCH code as an example, the serial code with 10 concatenated registers that is constructed Fig. 2 shows one
Circuit can construct in the way of the prior art.Generator polynomial with (15,5) BCH code as described above is：
G (X)=φ1(X)·φ3(X)·φ5(X)=1+X+X2+X4+X5+X8+X10
In case of, construct serial encoding circuitry shown in Fig. 2.In fact, Fig. 2 is the connection of the materialization of Fig. 1
Figure.The circuit includes S0~S9Ten registers.
Specifically, when circuit works, clock signal c1k controls ten register S0~S9.When rising edge clock arrives,
The output of ten registers is respectively fed to next stage, while generating the output of next stage.After information bit, which inputs, to be completed, 10
The value preserved in register is exactly the value of 10 bit check positions.The data preserved in 10 registers together, are recycled with external world's input
Displacement.Understood according to algebraic method, ten bit check positions are exactly the information bit multinomial that information bit is constituted, and are then multiplied by X10It is (defeated
Enter information operation together with the output of the register of rightmost and be equivalent to be multiplied by X10), then divided by the corresponding generator polynomial g of BCH
(X) coefficient of the residue obtained.
In step S2, according to the serial encoding circuitry, each register respectively in serial encoding circuitry is inputted
The redundancy check of the redundancy check bit that it is stored after the information bit of i+1 position and each register memory storage after input i-th bit information bit
Position, input i+1 position information bit between the first relational expression, i≤4 and be nonnegative integer.
Still by taking the example of Fig. 2 as an example, it can be each register in 10 registers of Fig. 2, obtain the first relational expression
It is as follows：
Wherein,The redundancy school stored in each register S0~S9 after expression input i-th bit information bit
Position is tested,Each register S after the information bit of input i+1 position0~S9The redundancy check bit of interior storage,
ui+1Indicate the i+1 position information bit of input.As shown in Fig. 2, register S9Its storage value is after the information bit of input i+1 position
Previous register S8It passes over, previous register S should be equal to8The storage value after inputting i-th bit information bit, thereforeRegister S8Its storage value is previous register S after the information bit of input i+1 position7The value passed over is added and is posted
Storage S9The sum of the value fed back, thereforeAdding here all refers to that mould two adds.
In step s3, according to the first relational expression (1), each register respectively in serial encoding circuitry obtains defeated
Enter the redundancy check bit and the redundancy school for not inputting each register memory storage when any information bit that all it is stored after 5 information bits
Test position, all 5 information bits the second relational expression (2).Specifically：
In sub-step S31, the first relational expression vectorization that will be obtained for each register in serial encoding circuitry, to
Obtain the vector and input i-th bit information bit of the redundancy check bit that 10 registers store after indicating input i+1 position information bit
The primary vector of the relationship between the vector of redundancy check bit of 10 registers storage, the i+1 position information bit of input closes afterwards
It is formula.
Still for for above-mentioned (15,5) BCH code, the first relational expression (1) is rewritten into primary vector relationship formula (I)：
SiThe vector for the redundancy check bit that 10 registers store after expression input i-th bit information bit, Si+1Indicate input
The vector for the redundancy check bit that 10 registers store after the information bit of i+1 position.Still with aforementioned (15,5) BCH code for：
Matrix A is the coefficient matrix obtained by each coefficient in above formula (1).Matrix A is：
Gi+1It is the vector of the i+1 position information bit of reflection input.It is a column vector, and the first row is the i+1 of input
The vector of position information bit, remaining behavior 0.If U be all group of information bits at vectorial U=[u0, u1..., u4],
Wherein G, i+1The i+1 of representing matrix arranges.
In sub-step S32, according to primary vector relationship formula (I), posted for 10 after whole 5 information bits of acquisition expression input
Storage storage redundancy check bit vector with do not input any information bit when 10 registers storage redundancy check bit to
The secondary vector relational expression of amount, all relationship between 5 information bits.
By taking above-mentioned (15,5) BCH code as an example, by primary vector relationship formula (I), secondary vector relationship formula (II) is obtained：
S5For the vector for the redundancy check bit that 10 registers after expression input all 5 information bits store, S0Not input
The vector for the redundancy check bit that 10 registers store when any information bit.It will can not input each register when any information bit
The redundancy check bit of interior storage is both configured to 0, at this time S0It is 0, upper formula (II) becomes：
In step S33, from secondary vector relational expression, obtains and correspond to each register in serial encoding circuitry
Second relational expression.
By taking above-mentioned (15,5) BCH code as an example, above formula (II-1) expansion can be obtained into following expression, that is, corresponded to serial
Second relational expression of each register in coding circuit：
Step S3 can not also be executed in the way of above-mentioned S31-S33.For example, directly from the first relational expression (1), i.e.,
, will by derivingIt is expressed as u0-u4Function to get to (2), only process is slightly multiple
It is miscellaneous.
Herein, plus sige all indicates the addition on mould two, that is, is equal to binary exclusive or
In step S4, according to the second relational expression, it is input to construct with 5 information bits, 10 redundancy check bits are output
Parallel encoding circuit.
By taking above-mentioned (15,5) BCH code as an example, according to above-mentioned (2), parallel encoding circuit as shown in Figure 3 is constructed.
Assuming that information bit to be encoded is (11000), corresponding multinomial is U (X)=1+X, X10U (X) divided by generation are multinomial
Formula g (X)=1+X+X2+X4+X5+X8+X10Obtain residue：
B (X)=1+X3+X4+X6+X8+X9
Therefore coding obtains (1001101011 | 11000), 10, the left side is redundancy check bit, and 5, the right is information bit,
It is correct derivation result can be verified according to formula (2).
Although front is with the generator polynomial of (15,5) BCH code：
G (X)=φ1(X)·φ3(X)·φ5(X)=1+X+X2+X4+X5+X8+X10
For describe the design process of coding circuit of the present invention, but skilled person will appreciate that, if g (X) is it
It, the present invention is equally applicable.
The present invention proposes a kind of coding circuit design method of (15,5) BCH code, and traditional string is replaced using parallel circuit
Row encoding scheme can not be limited by the clock cycle, greatly shorten the scramble time, and coding rate greatly improves.
Claims (1)
1. a kind of coding circuit design method of (15,5) BCH code, the coding circuit design method include：
According to the generator polynomial of (15, the 5) BCH code, the serial encoding circuitry with 10 concatenated registers is constructed；
According to the serial encoding circuitry, each register respectively in serial encoding circuitry obtains input i+1 position information bit
The i+1 of the redundancy check bit of its storage is stored up with each register memory after input i-th bit information bit afterwards redundancy check bit, input
Position information bit between the first relational expression, i≤4 and be nonnegative integer；
According to the first relational expression, each register respectively in serial encoding circuitry, obtain input all after 5 information bits its
The redundancy check bit of storage and the redundancy check bit of each register memory storage, all 5 information bits when any information bit are not inputted
The second relational expression；
According to the second relational expression, construction is input, the parallel encoding circuit that 10 redundancy check bits are output with 5 information bits：
Wherein include according to the step of the first relational expression the second relational expression of acquisition：
The the first relational expression vectorization that will be obtained for each register in serial encoding circuitry indicates input i+1 to obtain
The vector for the redundancy check bit that 10 registers store after the information bit of position and 10 registers storage after input i-th bit information bit
The primary vector relational expression of relationship between the vector of redundancy check bit, the i+1 position information bit of input；
According to primary vector relational expression, the redundancy check bit that 10 registers store after indicating whole 5 information bits of input is obtained
Vector and the vector of the redundancy check bit of 10 registers storage when not inputting any information bit, all between 5 information bits
Relationship secondary vector relational expression；
From secondary vector relational expression, the second relational expression for corresponding to each register in serial encoding circuitry is obtained；
First relational expression is as follows：
In formulaEach register S after expression input i-th bit information bit0~S9The redundancy check of interior storage
Position,Each register S after the information bit of expression input i+1 position0~S9Interior storage it is superfluous
Remaining check bit, ui+1Indicate the i+1 position information bit of input；Adding in the first relational expression is all that mould two adds：
It is as follows that first relational expression is rewritten into primary vector relational expression：
S in formulaiThe vector for the redundancy check bit that 10 registers store after expression input i-th bit information bit, Si+1Indicate input i-th
The vector for the redundancy check bit that 10 registers store after+1 information bit, matrix A are by each system in first relational expression
The coefficient matrix that number obtains；G, i+1It is vector matrix Gi+1I+1 row, Gi+1Be reflection input i+1 position information bit to
Moment matrix；
It is as follows that secondary vector relational expression is obtained by primary vector relational expression：
S in formula5The vector for the redundancy check bit that 10 registers store after whole 5 information bits of expression input, S0Appoint not input
The vector of the redundancy check bit of 10 registers storage when what information bit；
The redundancy check bit that setting does not input each register memory storage when any information bit is all 0, at this time S0Be 0, then secondary vector
Relational expression is deformed into：
Deformed secondary vector relational expression is unfolded to obtain the corresponding to each register in serial encoding circuitry as a result,
Two relational expressions：
In formulaRegister S is indicated respectively0~S9The second relational expression；U is set as all group of information bits
At vector, then U=[u0, u1..., u4]。
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| JP2000013241A (en) * | 1998-04-22 | 2000-01-14 | Oki Electric Ind Co Ltd | Convolutional coder and viterbi decoder |
| US7124064B1 (en) * | 2001-03-30 | 2006-10-17 | Cisco Technology, Inc. | Automatic generation of hardware description language code for complex polynomial functions |
| CN101227194A (en) * | 2008-01-22 | 2008-07-23 | 炬力集成电路设计有限公司 | Circuit, encoder and method for encoding parallel BCH |
| CN102761340A (en) * | 2012-08-10 | 2012-10-31 | 济南微晶电子技术有限公司 | Broadcast channel (BCH) parallel coding circuit |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000013241A (en) * | 1998-04-22 | 2000-01-14 | Oki Electric Ind Co Ltd | Convolutional coder and viterbi decoder |
| US7124064B1 (en) * | 2001-03-30 | 2006-10-17 | Cisco Technology, Inc. | Automatic generation of hardware description language code for complex polynomial functions |
| CN101227194A (en) * | 2008-01-22 | 2008-07-23 | 炬力集成电路设计有限公司 | Circuit, encoder and method for encoding parallel BCH |
| CN102761340A (en) * | 2012-08-10 | 2012-10-31 | 济南微晶电子技术有限公司 | Broadcast channel (BCH) parallel coding circuit |
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