CN107239362A - A kind of computational methods and system of CRC parallel computing code - Google Patents
A kind of computational methods and system of CRC parallel computing code Download PDFInfo
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- CN107239362A CN107239362A CN201710128854.1A CN201710128854A CN107239362A CN 107239362 A CN107239362 A CN 107239362A CN 201710128854 A CN201710128854 A CN 201710128854A CN 107239362 A CN107239362 A CN 107239362A
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- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
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Abstract
This application discloses the computational methods and system of a kind of CRC parallel computing code, wherein, the method that the computational methods of the CRC parallel computing code employ parametrization, realize and change degree of parallelism and generator polynomial as needed, so as to improve the portable purpose of the computational methods of the CRC parallel computing code, and the CRC parallel computing code refer to the solution of matrix high math power in Traditional parallel CRC check code computational methods using shifting function and XOR, operand is reduced, reduces for about 75% calculating time than directly calculating on algorithm layer.
Description
This application claims Patent Office of the People's Republic of China, Application No. 201710089849.4, invention were submitted on 2 20th, 2017
The priority of the Chinese patent application of entitled " a kind of computational methods and system of CRC parallel computing code ", entire contents are led to
Reference is crossed to be incorporated in the present application.
Technical field
The application is related to communication technical field, more specifically to a kind of CRC parallel computing code computational methods and
System.
Background technology
In data communication process, in order to solve the erroneous detection problem in data communication, typically in the letter that will be transmitted
Add the check code of certain digit to realize detection process after breath code.In numerous methods of calibration, Cyclical Redundancy Check
(Cyclic Redundancy Check, CRC) is verified due to its outstanding error detection capability, is widely used in data and is led to
Believe technical field.
The basic thought of CRC check is the CRC check that a binary sequence is added after the information code to be sent
Code, one new information code of generation is sent to receiving terminal.Wherein, CRC check code is required to enable the new information code of generation
Some certain number selected jointly with transmitting terminal and receiving terminal divides exactly, and this certain number is multinomial by the generation of generation CRC check code
Formula is determined, after new information code reaches receiving terminal, receiving terminal to the new information code that receives using " module-2 division " divided by
This certain number, if result does not have remainder, illustrates that mistake does not occur in new information code, if as a result there is remainder, says
The bright information code occurs in that mistake in transmitting procedure.
The calculating of CRC check code is divided into serial and concurrent two ways, and the computational methods of serial CRC check code are each only
A data to be generated can be calculated；, every time can be with and the computational methods of CRC parallel computing code have the parameter of degree of parallelism
Calculate the data to be generated of degree of parallelism digit.In actual application process, in order to improve computational efficiency generally using parallel
The computational methods of CRC check code carry out the calculating of CRC check code.But in the prior art, the calculating side of CRC parallel computing code
Method is usually look-up table, i.e., generate specific check code form to carry out acquisition of tabling look-up, this method according to specific degree of parallelism
When degree of parallelism changes, needing to generate new check code again, it is portable low, it is impossible to change degree of parallelism and life as needed
Into multinomial.
The content of the invention
In order to solve the above technical problems, the invention provides a kind of CRC parallel computing code computational methods and system, with
Realize the portable purpose for the computational methods for improving CRC parallel computing code.
To realize above-mentioned technical purpose, the embodiments of the invention provide following technical scheme：
A kind of computational methods of CRC parallel computing code, for calculating data data=[d to be generatedk-1dk-2dk-3…d0]
CRC check code, the computational methods of CRC parallel computing code include：
S101：Obtain generator polynomial poly=[pn-1pn-2pn-3…p0] and degree of parallelism w；
S102：The first provisional matrix temp is generated using the generator polynomial；Wherein,
S103：The second provisional matrix is generated using the generator polynomial
S104：Utilize preceding w generation middle coefficient vectors of untreatment data in the data to be generated
S105：Vectorial pressed with first provisional matrix of the middle coefficient is arranged into work and computing, the first middle square is obtained
Battle array
S106：The column vector of first intermediary matrix is subjected to reduction XOR by leu time, obtained in the middle of second
Matrix factor=[fn-1fn-2fn-3…f0]；
S107：The second intermediary matrix step-by-step is made and computing with the column vector in second provisional matrix successively,
Obtain the 3rd intermediary matrix
S108：All row of 3rd intermediary matrix are made into step-by-step XOR, verification vector is obtainedJudge whether untreatment data is zero in the data to be generated, if it is, by the school
Vector is tested as the CRC check code of the data to be generated；If it is not, then updating system in the middle of described using the verification vector
The preceding n rows of number vector, the rear w of the middle coefficient vector is updated using preceding w of untreatment data in the data to be generated
OK, and return and make the middle coefficient is vectorial and computing by row with first provisional matrix, obtain the first intermediary matrix
Step.
Optionally, step S108 includes：
All row of 3rd intermediary matrix are made into step-by-step XOR, verification vector is obtainedJudge whether untreatment data is zero in the data to be generated, if it is, by the school
Vector is tested as the CRC check code of the data to be generated；If it is not, then judging untreatment data in the data to be generated
Digit whether be less than or equal to the degree of parallelism, if it is not, then returning the middle coefficient is vectorial with the described first interim square
Battle array is made and computing by row, the step of obtaining the first intermediary matrix, if so, then utilizing untreatment data in the data to be generated
The middle coefficient vector is modified with the verification vector, and returned the middle coefficient is vectorial with described first
Provisional matrix is made and computing by row, the step of obtaining the first intermediary matrix.
Optionally, it is described vectorial to the middle system using untreatment data in the data to be generated and the verification
Number vector be modified including：
Untreatment data inverted order in the data to be generated is assigned to the last M rows of the middle coefficient vector, M's takes
Value is identical with the digit of untreatment data in the data to be generated；
The vectorial M+1 reciprocal of the middle coefficient is assigned to M+n rows reciprocal by the data in the verification vector；
By the preceding w-M rows zero padding of middle coefficient vector.
Optionally, the acquisition generator polynomial poly=[pn-1pn-2pn-3…p0] and degree of parallelism w after, it is described utilize
The generator polynomial also includes before generating the first provisional matrix temp：
S1012：Judge whether the degree of parallelism obtained is more than the data bits to be generated and the generator polynomial digit
Sum, if it is, using the data bits to be generated and the generator polynomial digit and be used as the degree of parallelism；Such as
It is really no, then judge whether the degree of parallelism obtained is less than 1, if so, being then used as the degree of parallelism using 1.
A kind of computing system of CRC parallel computing code, for calculating data data=[d to be generatedk-1dk-2dk-3…d0]
CRC check code, the computing system of CRC parallel computing code includes：
Acquisition module, for obtaining generator polynomial poly=[pn-1pn-2pn-3…p0] and degree of parallelism w；
First provisional matrix generation module, for generating the first provisional matrix temp using the generator polynomial；Wherein,
Second provisional matrix generation module, for generating the second provisional matrix using the generator polynomial
Middle coefficient vector generation module, in the preceding w generations using untreatment data in the data to be generated
Between coefficient vector
First intermediary matrix generation module, for vectorial pressed with first provisional matrix of the middle coefficient to be arranged into work
With computing, the first intermediary matrix is obtained
Second intermediary matrix generation module, for the column vector of first intermediary matrix to be reduced by leu
XOR, obtains the second intermediary matrix factor=[fn-1fn-2fn-3…f0]；
3rd intermediary matrix generation module, for by the second intermediary matrix step-by-step successively with the described second interim square
Column vector in battle array is made and computing, obtains the 3rd intermediary matrix
Vector generation module is verified, for all row of the 3rd intermediary matrix to be made into step-by-step XOR, school is obtained
Test vectorJudge whether untreatment data is zero in the data to be generated, if it is, will
The vectorial CRC check code as the data to be generated of the verification；If it is not, then updating described using the verification vector
The preceding n rows of middle coefficient vector, using preceding w of the untreatment data renewal middle coefficients in the data to be generated to
The rear w rows of amount, and return to the first intermediary matrix generation module.
Optionally, the verification vector generation module by all row of the 3rd intermediary matrix specifically for making step-by-step
XOR, obtains verification vectorJudge in the data to be generated whether is untreatment data
It is zero, if it is, using the vector that verifies as the CRC check codes of the data to be generated；If it is not, then judging described
Whether the digit of untreatment data is less than or equal to the degree of parallelism in data to be generated, if it is not, then returning in the middle of described first
Matrix generation module, if so, then using untreatment data in the data to be generated and verification vector to the middle system
Number vector is modified, and returns to the first intermediary matrix generation module.
Optionally, the verification vector generation module utilizes untreatment data and the verification in the data to be generated
Vector is modified to the middle coefficient vector specifically for assigning institute by untreatment data inverted order in the data to be generated
The last M rows of middle coefficient vector are stated, M value is identical with the digit of untreatment data in the data to be generated；
The vectorial M+1 reciprocal of the middle coefficient is assigned to M+n rows reciprocal by the data in the verification vector；
By the preceding w-M rows zero padding of middle coefficient vector.
Optionally, in addition to：
Degree of parallelism correcting module, for judge obtain degree of parallelism whether be more than the data bits to be generated with it is described
The sum of generator polynomial digit, if it is, using the data bits to be generated and the generator polynomial digit and as
The degree of parallelism；If it is not, then judging whether the degree of parallelism obtained is less than 1, if so, being then used as the degree of parallelism using 1.
It can be seen from the above technical proposal that the embodiments of the invention provide a kind of computational methods of CRC parallel computing code
And system, wherein, the method that the computational methods of CRC parallel computing code employ parametrization realizes change as needed
Degree of parallelism and generator polynomial, so that the portable purpose of the computational methods of the CRC parallel computing code is improved, and
The CRC parallel computing code refer to matrix in Traditional parallel CRC check code computational methods using shifting function and XOR
The solution of high math power, reduces operand, reduces for about 75% calculating time than directly calculating on algorithm layer.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will to embodiment or
The accompanying drawing used required in description of the prior art is briefly described, it should be apparent that, drawings in the following description are only
Embodiments of the invention, for those of ordinary skill in the art, on the premise of not paying creative work, can be with
Other accompanying drawings are obtained according to the accompanying drawing of offer.
A kind of flow signal of the computational methods for CRC parallel computing code that Fig. 1 provides for one embodiment of the application
Figure；
A kind of structural representation of the computing system for CRC parallel computing code that Fig. 2 provides for one embodiment of the application
Figure；
A kind of structural representation of the computing system for CRC parallel computing code that Fig. 3 provides for another embodiment of the application
Figure.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation is described, it is clear that described embodiment is only a part of embodiment of the invention, rather than whole embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art obtained under the premise of creative work is not made it is all its
His embodiment, belongs to the scope of protection of the invention.
The embodiment of the present application provides a kind of computational methods of CRC parallel computing code, as shown in figure 1, for calculating to be generated
Into data data=[dk-1dk-2dk-3…d0] CRC check code, the computational methods of CRC parallel computing code include：
S101：Obtain generator polynomial poly=[pn-1pn-2pn-3…p0] and degree of parallelism w；
S102：The first provisional matrix temp is generated using the generator polynomial；Wherein,
Specifically, the first provisional matrix generation method, should for last column first left numerical value is set into 1
Numerical value after row is polynomial high (n-1) position (i.e. the binary representation of the preceding n-1 coefficient of generator polynomial) of generation；
The generation method of other rows of first provisional matrix is：Will a line be (for example thereafter：For row second from the bottom, its is latter
Behavior row last) the digit of the left side first and height (n-1) the position step-by-step work of generator polynomial and computing, by this result with
Thereafter a line removes the primary n-1 data in the left side and makees step-by-step XOR, and obtained result is exactly the row from n-1 from left to right
The data of position, a data of the row rightmost is the leftmost a data of data line after the row.
S103：The second provisional matrix is generated using the generator polynomial
S104：Utilize preceding w generation middle coefficient vectors of untreatment data in the data to be generated
S105：Vectorial pressed with first provisional matrix of the middle coefficient is arranged into work and computing, the first middle square is obtained
Battle array
It should be noted that in first intermediary matrix,
S106：The column vector of first intermediary matrix is subjected to reduction XOR by leu time, obtained in the middle of second
Matrix factor=[fn-1fn-2fn-3…f0]；
It should be noted that in second intermediary matrix,
S107：The second intermediary matrix step-by-step is made and computing with the column vector in second provisional matrix successively,
Obtain the 3rd intermediary matrix
S108：All row of 3rd intermediary matrix are made into step-by-step XOR, verification vector is obtainedJudge whether untreatment data is zero in the data to be generated, if it is, by the school
Vector is tested as the CRC check code of the data to be generated；If it is not, then updating system in the middle of described using the verification vector
The preceding n rows of number vector, the rear w of the middle coefficient vector is updated using preceding w of untreatment data in the data to be generated
OK, and return and make the middle coefficient is vectorial and computing by row with first provisional matrix, obtain the first intermediary matrix
Step.
In the verification vector,
On the basis of above-described embodiment, in one embodiment of the application, the acquisition generator polynomial poly=
[pn-1pn-2pn-3…p0] and degree of parallelism w after, it is described using the generator polynomial generate the first provisional matrix temp before
Also include：
S1012：Judge whether the degree of parallelism obtained is more than the data bits to be generated and the generator polynomial digit
Sum, if it is, using the data bits to be generated and the generator polynomial digit and be used as the degree of parallelism；Such as
It is really no, then judge whether the degree of parallelism obtained is less than 1, if so, being then used as the degree of parallelism using 1.
In the present embodiment, increase step S1012 purpose is that the abnormal degree of parallelism of input is modified, to avoid
The mistake that the degree of parallelism of acquisition is abnormal and is likely to result in.
On the basis of above-described embodiment, in the preferred embodiment of the application, step S108 includes：
All row of 3rd intermediary matrix are made into step-by-step XOR, verification vector is obtainedJudge whether untreatment data is zero in the data to be generated, if it is, by the school
Vector is tested as the CRC check code of the data to be generated；If it is not, then judging untreatment data in the data to be generated
Digit whether be less than or equal to the degree of parallelism, if it is not, then returning the middle coefficient is vectorial with the described first interim square
Battle array is made and computing by row, the step of obtaining the first intermediary matrix, if so, then utilizing untreatment data in the data to be generated
The middle coefficient vector is modified with the verification vector, and returned the middle coefficient is vectorial with described first
Provisional matrix is made and computing by row, the step of obtaining the first intermediary matrix.
Specifically, it is described vectorial to the middle system using untreatment data in the data to be generated and the verification
Number vector be modified including：
Untreatment data inverted order in the data to be generated is assigned to the last M rows of the middle coefficient vector, M's takes
Value is identical with the digit of untreatment data in the data to be generated；
The vectorial M+1 reciprocal of the middle coefficient is assigned to M+n rows reciprocal by the data in the verification vector；
By the preceding w-M rows zero padding of middle coefficient vector.
It should be noted that the form of revised middle coefficient vector is shown below：
The 3rd intermediary matrix obtained in last time calculating process is shown below：
The verification vector obtained in last time calculating process is shown below：
Wherein,
On the basis of above-described embodiment, in the specific embodiment of the application, using a bit length as 7 it is to be generated
Into exemplified by data 1011001, the computational methods to CRC parallel computing code are tested, it is assumed that generator polynomial is, its
Corresponding binary code is 1001 (dispensing highest order 1), really to be calculated is 10110010000 (data to be generated it
Generator polynomial digit is mended afterwards 0).To embody the characteristic of this method, the degree of parallelism 7 that selection one can not be divided evenly, therefore need
Calculate twice that (data bit 7 to be generated, generator polynomial 4, their sums divided by degree of parallelism 7, as a result round up
2)。
The high 7 of data 10110010000 (generator polynomial digit 0 is mended after 1011001) is calculated for the first time：
(1) generation the first provisional matrix temp this matrix last column be generator polynomial correspondence code 1001 it is overall to
Extreme higher position 1 after one is moved to right, is as a result 1100.The highest order of behavior 1100 second from the bottom and generator polynomial make with as a result
For 1001, XOR is made in the front three step-by-steps of this result and 1100 results 1001 that circulation moves one to the left, obtains 0001.
The highest order of behavior 0001 third from the bottom is made with being as a result 0000, this result moves one with 0001 circulation to the left with generator polynomial
XOR is made in the front three step-by-step of the result 0010 of position, obtains 0010.The like, the square until obtaining 11 rows 4 row
Battle array：
(2) the second provisional matrix is built
(3) build middle coefficient vector h, during starting before 4 behaviors 0,7 behaviors data to be generated is high 7 afterwards：
(4) h and temp is made and computing by row, produces qand：
(5) qand column vector is subjected to reduction XOR successively, has obtained 4 end values, obtain factor=
[1011]。
(6) factor each and F each column are made and computing successively, obtained
(7) by sand all row step-by-step XORs, a column vector is obtainedBe exactly data 10110010000 (
Preceding 7 CRC of generator polynomial digit 0) result of calculation is mended after 1011001.
The low 4 of data 10110010000 (generator polynomial digit 0 is mended after 1011001) is calculated for the second time：
(8) h is changed, the remaining data that will calculate CRC code in data to be generated are assigned to the last several of column vector
OK, the intermediate CRC-results then calculated step beforeIt is added to row thereon, the row zero padding finally started.
(9) h and temp is made and computing by row, produces qand.
(10) qand column vector is subjected to reduction XOR successively, has obtained 4 end values, obtained：Factor=
[0101]
(11) by factor, each makees and computing successively with F each columns, obtains
(12) by all row step-by-step XORs of sand, it is exactly data 10110010000 (1011001 to obtain a column vector
The final CRC of generator polynomial digit 0) result of calculation is mended afterwards：
So last result of calculation is 1010, the CRC check code of data 1011001 as to be generated replaces this value
Change data 10110010000 (generator polynomial digit 0 is mended after 1011001) latter 40, obtain 10110011010,
The first seven position is information code, and latter four are CRC check codes.
Accordingly, the embodiment of the present application additionally provides a kind of computing system of CRC parallel computing code, as shown in Fig. 2 with
In calculating data data=[d to be generatedk-1dk-2dk-3…d0] CRC check code, the computing system of CRC parallel computing code
Including：
Acquisition module 100, for obtaining generator polynomial poly=[pn-1pn-2pn-3…p0] and degree of parallelism w；
First provisional matrix generation module 200, for generating the first provisional matrix temp using the generator polynomial；Wherein,
Second provisional matrix generation module 300, for generating the second provisional matrix using the generator polynomial
Middle coefficient vector generation module 400, for the preceding w lifes using untreatment data in the data to be generated
Into middle coefficient vector
First intermediary matrix generation module 500, for vectorial pressed with first provisional matrix of the middle coefficient to be arranged
Make and computing, obtain the first intermediary matrix
Second intermediary matrix generation module 600, for the column vector of first intermediary matrix to be contracted by leu
Subtract XOR, obtain the second intermediary matrix factor=[fn-1fn-2fn-3…f0]；
3rd intermediary matrix generation module 700, for the second intermediary matrix step-by-step is interim with described second successively
Column vector in matrix is made and computing, obtains the 3rd intermediary matrix
Vector generation module 800 is verified, for all row of the 3rd intermediary matrix to be made into step-by-step XOR, is obtained
Vector must be verifiedJudge whether untreatment data is zero in the data to be generated, if it is,
Then using the vectorial CRC check code as the data to be generated of the verification；If it is not, then being updated using the verification vector
The preceding n rows of the middle coefficient vector, system in the middle of described is updated using preceding w of untreatment data in the data to be generated
The rear w rows of number vector, and return to the first intermediary matrix generation module 500.
It should be noted that the first provisional matrix generation method is to set last column first left numerical value
For 1, numerical value after the row is generates polynomial high (n-1) position (i.e. binary system of the preceding n-1 coefficient of generator polynomial
Represent)；The generation method of other rows of first provisional matrix is：Will a line be (for example thereafter：For row second from the bottom,
Thereafter behavior row last) the digit of the left side first and height (n-1) the position step-by-step work of generator polynomial and computing, by this
As a result the primary n-1 data in the left side are removed with a line thereafter and makees step-by-step XOR, obtained result is exactly the row from a left side
The data of n-1 are played, a data of the row rightmost is the leftmost a data of data line after the row.
In first intermediary matrix,
In second intermediary matrix,
In the verification vector,
On the basis of above-described embodiment, in one embodiment of the application, as shown in figure 3, the CRC check codes
Computing system also include：
Whether degree of parallelism correcting module 900, the degree of parallelism for judging to obtain is more than the data bits to be generated and institute
State the sum of generator polynomial digit, if it is, by the data bits to be generated and the generator polynomial digit and make
For the degree of parallelism；If it is not, then judging whether the degree of parallelism obtained is less than 1, if so, being then used as the degree of parallelism using 1.
In the present embodiment, the purpose for increasing the degree of parallelism correcting module 900 is that the abnormal degree of parallelism of input is carried out
Amendment, with the mistake for avoiding the degree of parallelism obtained abnormal and being likely to result in.
On the basis of above-described embodiment, in the preferred embodiment of the application, the verification vector generation module
800, specifically for all row of the 3rd intermediary matrix are made into step-by-step XOR, obtain verification vectorJudge whether untreatment data is zero in the data to be generated, if it is, by the school
Vector is tested as the CRC check code of the data to be generated；If it is not, then judging untreatment data in the data to be generated
Digit whether be less than or equal to the degree of parallelism, if it is not, then return to the first intermediary matrix generation module 500, if so,
Then the middle coefficient vector is modified using untreatment data in the data to be generated and verification vector, and
Return to the first intermediary matrix generation module 500.
Specifically, the verification vector generation module 800 utilizes untreatment data and the school in the data to be generated
Vector is tested to be modified the middle coefficient vector specifically for untreatment data inverted order in the data to be generated is assigned
The last M rows of the middle coefficient vector, M value is identical with the digit of untreatment data in the data to be generated；
The vectorial M+1 reciprocal of the middle coefficient is assigned to M+n rows reciprocal by the data in the verification vector；
By the preceding w-M rows zero padding of middle coefficient vector.
It should be noted that the form of revised middle coefficient vector is shown below：
The 3rd intermediary matrix obtained in last time calculating process is shown below：
The verification vector obtained in last time calculating process is shown below：
Wherein,
On the basis of above-described embodiment, in the specific embodiment of the application, using a bit length as 7 it is to be generated
Into exemplified by data 1011001, the computing system to CRC parallel computing code is tested, it is assumed that generator polynomial is, its
Corresponding binary code is 1001 (dispensing highest order 1), really to be calculated is 10110010000 (data to be generated it
Generator polynomial digit is mended afterwards 0).To embody the characteristic of this method, the degree of parallelism 7 that selection one can not be divided evenly, therefore need
Calculate twice that (data bit 7 to be generated, generator polynomial 4, their sums divided by degree of parallelism 7, as a result round up
2)。
The high 7 of data 10110010000 (generator polynomial digit 0 is mended after 1011001) is calculated for the first time：
(1) generation the first provisional matrix temp this matrix last column be generator polynomial correspondence code 1001 it is overall to
Extreme higher position 1 after one is moved to right, is as a result 1100.The highest order of behavior 1100 second from the bottom and generator polynomial make with as a result
For 1001, XOR is made in the front three step-by-steps of this result and 1100 results 1001 that circulation moves one to the left, obtains 0001.
The highest order of behavior 0001 third from the bottom is made with being as a result 0000, this result moves one with 0001 circulation to the left with generator polynomial
XOR is made in the front three step-by-step of the result 0010 of position, obtains 0010.The like, the square until obtaining 11 rows 4 row
Battle array：
(2) the second provisional matrix is built
(3) build middle coefficient vector h, during starting before 4 behaviors 0,7 behaviors data to be generated is high 7 afterwards：
(4) h and temp is made and computing by row, produces qand：
(5) qand column vector is subjected to reduction XOR successively, has obtained 4 end values, obtain factor=
[1011]。
(6) factor each and F each column are made and computing successively, obtained
(7) by sand all row step-by-step XORs, a column vector is obtainedBe exactly data 10110010000 (
Preceding 7 CRC of generator polynomial digit 0) result of calculation is mended after 1011001.
The low 4 of data 10110010000 (generator polynomial digit 0 is mended after 1011001) is calculated for the second time：
(8) h is changed, the remaining data that will calculate CRC code in data to be generated are assigned to the last several of column vector
OK, the intermediate CRC-results then calculated step beforeIt is added to row thereon, the row zero padding finally started.
(9) h and temp is made and computing by row, produces qand.
(10) qand column vector is subjected to reduction XOR successively, has obtained 4 end values, obtained：Factor=
[0101]
(11) by factor, each makees and computing successively with F each columns, obtains
(12) by all row step-by-step XORs of sand, it is exactly data 10110010000 (1011001 to obtain a column vector
The final CRC of generator polynomial digit 0) result of calculation is mended afterwards：
So last result of calculation is 1010, the CRC check code of data 1011001 as to be generated replaces this value
Change data 10110010000 (generator polynomial digit 0 is mended after 1011001) latter 40, obtain 10110011010,
The first seven position is information code, and latter four are CRC check codes.
In summary, the embodiment of the present application provides the computational methods and system of a kind of CRC parallel computing code, wherein, institute
The method that the computational methods of CRC parallel computing code employ parametrization is stated, is realized and is changed degree of parallelism as needed and generate many
Item formula, so that the portable purpose of the computational methods of the CRC parallel computing code is improved, and the CRC parallel computing
Code refer to the solution of matrix high math power in Traditional parallel CRC check code computational methods using shifting function and XOR, subtract
Operand is lacked, has reduced for about 75% calculating time than directly calculating on algorithm layer.
Further, the computational methods for the CRC parallel computing code that the embodiment of the present application is provided can realize any degree of parallelism
CRC check code generation and inspection, eliminate the specific limitation of degree of parallelism.
The embodiment of each in this specification is described by the way of progressive, and what each embodiment was stressed is and it
Between the difference of his embodiment, each embodiment identical similar portion mutually referring to.
The foregoing description of the disclosed embodiments, enables professional and technical personnel in the field to realize or using the present invention.
A variety of modifications to these embodiments will be apparent for those skilled in the art, defined herein
General Principle can realize in other embodiments without departing from the spirit or scope of the present invention.Therefore, originally
Invention is not intended to be limited to the embodiments shown herein, and is to fit to special with principles disclosed herein and novelty
The consistent most wide scope of point.
Claims (8)
1. a kind of computational methods of CRC parallel computing code, it is characterised in that for calculating data data=[d to be generatedk-1 dk-2
dk-3 … d0] CRC check code, the computational methods of CRC parallel computing code include：
S101：Obtain generator polynomial poly=[pn-1 pn-2 pn-3 … p0] and degree of parallelism w；
S102：The first provisional matrix temp is generated using the generator polynomial；Wherein,
S103：The second provisional matrix is generated using the generator polynomial
S104：Utilize preceding w generation middle coefficient vectors of untreatment data in the data to be generated
S105：Vectorial pressed with first provisional matrix of the middle coefficient is arranged into work and computing, the first intermediary matrix is obtained
S106：The column vector of first intermediary matrix is subjected to reduction XOR by leu time, the second intermediary matrix is obtained
Factor=[fn-1 fn-2 fn-3 … f0]；
S107：The second intermediary matrix step-by-step is made and computing with the column vector in second provisional matrix successively, obtained
3rd intermediary matrix
S108：All row of 3rd intermediary matrix are made into step-by-step XOR, verification vector is obtainedJudge whether untreatment data is zero in the data to be generated, if it is, by the verification
The vectorial CRC check code as the data to be generated；If it is not, then using the verification vector update the middle coefficient to
The preceding n rows of amount, the rear w rows of the middle coefficient vector are updated using preceding w of untreatment data in the data to be generated, and
Return and vectorial pressed with first provisional matrix of the middle coefficient is arranged into work and computing, the step of obtaining the first intermediary matrix.
2. according to the method described in claim 1, it is characterised in that step S108 includes：
All row of 3rd intermediary matrix are made into step-by-step XOR, verification vector is obtained
Judge whether untreatment data is zero in the data to be generated, if it is, the verification is vectorial as described to be generated
The CRC check code of data；If it is not, then judging whether the digit of untreatment data in the data to be generated is less than or equal to institute
Degree of parallelism is stated, makees the middle coefficient is vectorial and computing by row with first provisional matrix if it is not, then returning, obtains first
The step of intermediary matrix, if so, then utilizing untreatment data and the verification in the data to be generated vectorial to the centre
Coefficient vector is modified, and vectorial pressed with first provisional matrix of the middle coefficient is arranged work and computing by return, acquisition
The step of first intermediary matrix.
3. method according to claim 2, it is characterised in that it is described using untreatment data in the data to be generated and
It is described verification vector the middle coefficient vector is modified including：
Untreatment data inverted order in the data to be generated is assigned to the last M rows of the middle coefficient vector, M value and institute
The digit for stating untreatment data in data to be generated is identical；
The vectorial M+1 reciprocal of the middle coefficient is assigned to M+n rows reciprocal by the data in the verification vector；
By the preceding w-M rows zero padding of middle coefficient vector.
4. according to the method described in claim 1, it is characterised in that the acquisition generator polynomial poly=[pn-1 pn-2 pn-3
… p0] and degree of parallelism w after, it is described using the generator polynomial generate the first provisional matrix temp before also include：
S1012：Judge the degree of parallelism obtained whether be more than the data bits to be generated and the generator polynomial digit and,
If it is, using the data bits to be generated and the generator polynomial digit and be used as the degree of parallelism；If it is not, then
Judge whether the degree of parallelism obtained is less than 1, if so, being then used as the degree of parallelism using 1.
5. a kind of computing system of CRC parallel computing code, it is characterised in that for calculating data data=[d to be generatedk-1 dk-2
dk-3 … d0] CRC check code, the computing system of CRC parallel computing code includes：
Acquisition module, for obtaining generator polynomial poly=[pn-1 pn-2 pn-3 … p0] and degree of parallelism w；
First provisional matrix generation module, for generating the first provisional matrix temp using the generator polynomial；Wherein,
Second provisional matrix generation module, for generating the second provisional matrix using the generator polynomial
Middle coefficient vector generation module, for being in the middle of the preceding w generations using untreatment data in the data to be generated
Number vector
First intermediary matrix generation module, for vectorial pressed with first provisional matrix of the middle coefficient to be arranged into work and fortune
Calculate, obtain the first intermediary matrix
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Second intermediary matrix generation module, for the column vector of first intermediary matrix to be carried out into reduction XOR fortune by leu time
Calculate, obtain the second intermediary matrix factor=[fn-1 fn-2 fn-3 … f0]；
3rd intermediary matrix generation module, for by the second intermediary matrix step-by-step successively with second provisional matrix
Column vector is made and computing, obtains the 3rd intermediary matrix
Verify vector generation module, for all row of the 3rd intermediary matrix to be made into step-by-step XOR, obtain verification to
AmountJudge whether untreatment data is zero in the data to be generated, if it is, by the school
Vector is tested as the CRC check code of the data to be generated；If it is not, then updating the middle coefficient using the verification vector
The preceding n rows of vector, the rear w rows of the middle coefficient vector are updated using preceding w of untreatment data in the data to be generated,
And return to the first intermediary matrix generation module.
6. system according to claim 5, it is characterised in that the verification vector generation module is specifically for by described
All row of three intermediary matrixs make step-by-step XOR, obtain verification vectorJudge described to be generated
Whether untreatment data is zero into data, if it is, using the vector that verifies as the CRC check of the data to be generated
Code；If it is not, then judge whether the digit of untreatment data in the data to be generated is less than or equal to the degree of parallelism, if
It is no, then the first intermediary matrix generation module is returned to, if so, then utilizing untreatment data and described in the data to be generated
Verification vector is modified to the middle coefficient vector, and returns to the first intermediary matrix generation module.
7. system according to claim 6, it is characterised in that the verification vector generation module utilizes the number to be generated
The middle coefficient vector is modified specifically for by the number to be generated according to middle untreatment data and verification vector
The last M rows of the middle coefficient vector are assigned according to middle untreatment data inverted order, M value in the data to be generated with not locating
The digit for managing data is identical；
The vectorial M+1 reciprocal of the middle coefficient is assigned to M+n rows reciprocal by the data in the verification vector；
By the preceding w-M rows zero padding of middle coefficient vector.
8. system according to claim 5, it is characterised in that also include：
Degree of parallelism correcting module, it is many with the generation whether the degree of parallelism for judging to obtain is more than the data bits to be generated
Sum of formula digit, if it is, using the data bits to be generated and the generator polynomial digit and described in simultaneously
Row degree；If it is not, then judging whether the degree of parallelism obtained is less than 1, if so, being then used as the degree of parallelism using 1.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2019214265A1 (en) * | 2018-05-08 | 2019-11-14 | 华为技术有限公司 | Method and apparatus for calculating cyclic redundancy check (crc) code |
| CN110995394A (en) * | 2019-11-30 | 2020-04-10 | 国网辽宁省电力有限公司锦州供电公司 | Two-dimensional CRC (Cyclic redundancy check) method for data information |
| CN113110954A (en) * | 2021-04-23 | 2021-07-13 | 合肥恒烁半导体有限公司 | CRC (Cyclic redundancy check) code parallel computing method and device and application thereof |
| CN116566399A (en) * | 2023-05-19 | 2023-08-08 | 合芯科技有限公司 | CRC32C data error detection method, system, terminal and medium based on vector polynomial multiplication instruction |
| CN116861493A (en) * | 2023-08-31 | 2023-10-10 | 上海芯联芯智能科技有限公司 | Verification code generation method, processor and electronic equipment |
| CN117097440A (en) * | 2023-10-18 | 2023-11-21 | 苏州联讯仪器股份有限公司 | CRC (cyclic redundancy check) method for Ethernet packet |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080065958A1 (en) * | 2006-08-15 | 2008-03-13 | Samsung Electronics Co., Ltd. | Efficient parallel cyclic redundancy check calculation using modulo-2 multiplications |
| CN101795175A (en) * | 2010-02-23 | 2010-08-04 | 中兴通讯股份有限公司 | Data verifying method and device |
| CN101847999A (en) * | 2010-05-28 | 2010-09-29 | 清华大学 | Method for performing parallel check by using cyclic redundancy check codes |
| CN101902228A (en) * | 2009-05-25 | 2010-12-01 | 中兴通讯股份有限公司 | Rapid cyclic redundancy check encoding method and device |
| CN102891685A (en) * | 2012-09-18 | 2013-01-23 | 国核自仪系统工程有限公司 | Parallel cyclic redundancy check (CRC) operation circuit based on field programmable gate array (FPGA) |
| CN103731239A (en) * | 2013-12-31 | 2014-04-16 | 中国科学院自动化研究所 | Universal CRC parallel calculation component suitable for being used for vector processor and method |
-
2017
- 2017-03-06 CN CN201710128854.1A patent/CN107239362B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080065958A1 (en) * | 2006-08-15 | 2008-03-13 | Samsung Electronics Co., Ltd. | Efficient parallel cyclic redundancy check calculation using modulo-2 multiplications |
| CN101902228A (en) * | 2009-05-25 | 2010-12-01 | 中兴通讯股份有限公司 | Rapid cyclic redundancy check encoding method and device |
| CN101795175A (en) * | 2010-02-23 | 2010-08-04 | 中兴通讯股份有限公司 | Data verifying method and device |
| CN101847999A (en) * | 2010-05-28 | 2010-09-29 | 清华大学 | Method for performing parallel check by using cyclic redundancy check codes |
| CN102891685A (en) * | 2012-09-18 | 2013-01-23 | 国核自仪系统工程有限公司 | Parallel cyclic redundancy check (CRC) operation circuit based on field programmable gate array (FPGA) |
| CN103731239A (en) * | 2013-12-31 | 2014-04-16 | 中国科学院自动化研究所 | Universal CRC parallel calculation component suitable for being used for vector processor and method |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2019214265A1 (en) * | 2018-05-08 | 2019-11-14 | 华为技术有限公司 | Method and apparatus for calculating cyclic redundancy check (crc) code |
| CN110995394A (en) * | 2019-11-30 | 2020-04-10 | 国网辽宁省电力有限公司锦州供电公司 | Two-dimensional CRC (Cyclic redundancy check) method for data information |
| CN113110954A (en) * | 2021-04-23 | 2021-07-13 | 合肥恒烁半导体有限公司 | CRC (Cyclic redundancy check) code parallel computing method and device and application thereof |
| CN113110954B (en) * | 2021-04-23 | 2023-10-24 | 恒烁半导体(合肥)股份有限公司 | CRC (cyclic redundancy check) code parallel computing method, CRC code parallel computing device and application of CRC code parallel computing device |
| CN116566399A (en) * | 2023-05-19 | 2023-08-08 | 合芯科技有限公司 | CRC32C data error detection method, system, terminal and medium based on vector polynomial multiplication instruction |
| CN116566399B (en) * | 2023-05-19 | 2023-11-07 | 合芯科技有限公司 | CRC32C data error detection method, system, terminal and medium based on vector polynomial multiplication instruction |
| CN116861493A (en) * | 2023-08-31 | 2023-10-10 | 上海芯联芯智能科技有限公司 | Verification code generation method, processor and electronic equipment |
| CN116861493B (en) * | 2023-08-31 | 2024-03-29 | 上海芯联芯智能科技有限公司 | Verification code generation method, processor and electronic equipment |
| CN117097440A (en) * | 2023-10-18 | 2023-11-21 | 苏州联讯仪器股份有限公司 | CRC (cyclic redundancy check) method for Ethernet packet |
| CN117097440B (en) * | 2023-10-18 | 2024-03-15 | 苏州联讯仪器股份有限公司 | CRC (cyclic redundancy check) method for Ethernet packet |
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