WO2019214265A1 - Method and apparatus for calculating cyclic redundancy check (crc) code - Google Patents

Abstract

A solution for calculating a cyclic redundancy check (CRC) code. In the solution, an information sequence is processed based on multiples of a source polynomial, and a CRC code is calculated from the processed information sequence based on the source polynomial.

Description

Method and device for calculating cyclic redundancy check CRC coding Technical field

The present invention relates to the field of information technology, and in particular, to a method and apparatus for calculating a cyclic redundancy check CRC coding.

Background technique

In the storage system, Cyclic Redundancy Check (CRC) coding is a cyclic code. The CRC coding in the storage system usually uses a native polynomial based on the Galois field GF(2) to design a CRC coding scheme. CRC coding principle: Assume an L-bit information sequence (information value is 0 or 1), aL-1, aL-2, ..., a0, where the information sequence can be data to be processed, such as data to be stored or transmitted. The L-bit information sequence is represented as a polynomial:

C(x)=a _L-1 x^(L-1)+a _L-2 x^(L-2)+a _L-3 x^(L-3)+...+a ₀ . Where a _l-1 is the Most Significant Bit (MSB) of the information sequence, a ₀ is the Least Significant Bit (LSB) of the information sequence, and x^(L-1) is the L-1 of X. The power or the L-1 power of X.

In addition, the m-th order primitive polynomial G(m) is:

G(x)=g _m x^m+g _m-1 x^(m-1)+g _m-2 x^(m-2)+...+g ₀

then,

The code for calculating C(x) can be expressed as: CRC(C(x))=C(x)*x^m mod G(x)

As can be seen from the above equation, the CRC code represents the remainder after C(x)*x^m divided by another fixed number G(x), where "*" represents the "multiplication" in the mathematical operation symbol. .

In the storage system, in order to perform error detection on valid data, the storage system CRC-encodes the data, so that after the data is stored or transmitted, the storage system can quickly perform data consistency check, so the CRC code is Common features in storage systems.

In the prior art, a pipeline is used in combination with a table lookup method to CRC code data, as shown in FIG. 1:

a) Divide the data into segments, such as segment0 to SegmentN, where N is a natural number not less than one.

b) Perform CRC encoding on each segment separately, and get crc0 to crcN respectively.

c) Perform the carry-less multiplication (CLMUL) of the crc obtained by encoding each segment and the specific constant coefficient (Constant). For example, CrcUL is performed by crc0 and Constant0, CLMUL is performed by crc1 and Constant1, and CLMUL is performed by crcN and ConstantN.

d) CRC coding the CLMUL results of each segment to obtain C0, C1, C2, ..., CN, respectively.

e) Exclusive OR (XOR) of C0, C1, C2, ..., CN to obtain the final CRC coded CRCF.

However, the CRC encoding operation in steps b and d of the prior art CRC encoding method requires a large amount of shift and XOR operation, which increases the computational complexity and consumes a large amount of computing resources, thereby affecting the efficiency of CRC encoding. performance.

Summary of the invention

A first aspect of the embodiments of the present invention provides a solution for calculating a cyclic redundancy check CRC coding, including: acquiring first data; shifting the first data to the left by N bits to obtain second data, where N is a cyclic redundancy check CRC. a number of coded bits; processing the second data based on the one or more first source polynomials to obtain third data; wherein an exponent X of the highest term of each of the one or more first source polynomials valid for the first source polynomial is valid The difference between the index Y of the next highest item is greater than 1; the length of the third data is less than the length of the second data; X and Y are positive integers, and X is greater than Y; processing the third data based on the second source polynomial to obtain the first data N-bit CRC code; wherein each of the one or more first source polynomials is a multiple of the second source polynomial, each of the one or more first source polynomials The exponent X of the highest term of the polynomial effective is greater than the exponent R of the highest highest term of the second native polynomial. Specifically, the foregoing solution may be implemented by a controller, a server, or the like of the storage array, where the first source polynomial and the second source polynomial are stored. This scheme reduces the shift and XOR operation and improves the efficiency and performance of calculating CRC coding.

With reference to the first aspect, in a first possible implementation, the number of items that are valid for each of the one or more first source polynomials is less than the number of items that are valid by the second source polynomial, thereby Reduced shift operations and XOR operations.

With reference to the first aspect or the first possible implementation manner of the first aspect, in a second possible implementation, the first source polynomial is the least number of valid items in the multiple of the second native polynomial In the doubling mode, the shift operation and the exclusive-OR operation can be further reduced by using a multiple of the number of valid items.

With reference to the first aspect or the first or second possible implementation of the first aspect, in a third possible implementation, the processing the second data based on the one or more first source polynomials Three data, including:

Step 1: dividing the second data from the highest bit and dividing the data segment by the X bit size;

Step 2: Perform a shift operation on the first data segment of the second data based on the first source polynomial, and XOR the data segment obtained by the shift operation to obtain a third data segment; the first data segment is The first data segment obtained from the highest bit of the second data in the step 1;

Step 3: XOR the third data segment and the second data segment to obtain a fourth data segment; the second data segment is the second one obtained by dividing the X-bit size from the highest bit in step 1. Data segment

Step 4: replacing the first data segment and the second data segment of the second data in step 1 with the fourth data segment to form the second data, and performing steps 1 to 4 until The length of the second data is less than 2*X bits, where "*" indicates multiplication. This implementation can reduce the number of data segments for shifting and XOR operations, thereby improving the efficiency and performance of computational data CRC encoding.

With reference to the first aspect or the first or second possible implementation of the first aspect, in a fourth possible implementation, the processing the second data based on the one or more first source polynomials Three data, including:

Step 1: dividing the second data from the highest bit and dividing the data segment by the X bit size;

Step 2: Perform a shift operation on the first data segment of the second data based on the first source polynomial, and XOR the data segment obtained by the shift operation to obtain a third data segment; the first data segment is a first data segment obtained from the highest bit of the second data in the step 1; wherein the length of the third data segment is M bits;

Step 3: XORing the lower X bits of the third data segment with the second data segment to obtain a fourth data segment; the second data segment is divided into X bits according to the highest bit in step 1. The second data segment obtained;

Step 4: Perform a shift operation on the high (M-X) bit of the third data segment based on the Q(x) to obtain a fifth data segment;

Step 5: XOR the fourth data segment and the fifth data segment to obtain a sixth data segment;

Step 6: replacing the first data segment and the second data segment of the second data in step 1 with the sixth data segment to form the second data, and performing steps 1 to 6 until The length of the second data is less than 2*X bits, where "*" indicates multiplication. This implementation can reduce the number of data segments for shifting and XOR operations, thereby improving the efficiency and performance of computational data CRC encoding.

In conjunction with the first aspect or the first or second possible implementation of the first aspect, in a fifth possible implementation, the one or more first source polynomials comprise a first native polynomial Q1(x) And Q2(x), wherein an index of a highest item valid for Q1(x) is greater than an index of a highest item valid for Q2(x); said processing the second data based on one or more first source polynomials to obtain a third Data, including:

Processing the second data based on Q1(x) to obtain fourth data;

The fourth data is processed based on Q2(x) to obtain the third data. This implementation can further reduce the number of data segments for shifting and XOR operations, thereby improving the efficiency and performance of computational data CRC encoding.

With reference to the fifth possible implementation manner of the first aspect, in a sixth possible implementation, the processing, by using the second data, to obtain the fourth data, based on Q1(x), includes:

Step 1: dividing the second data from the highest bit and dividing the data segment by the exponent bit size of the highest item valid by Q1(x);

Step 2: Perform a shift operation on the first data segment of the second data based on the Q1 (x), and XOR the data segment obtained by the shift operation to obtain a third data segment; the first data segment is The first data segment obtained from the highest bit of the second data in the step 1;

Step 3: XOR the third data segment and the second data segment to obtain a fourth data segment; the second data segment is the highest item in the step 1 that is valid from the highest bit and is valid with Q1(x) The second data segment obtained by dividing the index bit size;

Step 4: replacing the first data segment and the second data segment of the second data in step 1 with the fourth data segment to form the second data, and performing steps 1 to 4 until The length of the second data is less than 2 times the exponent bit of the highest term in which Q1(x) is valid.

With reference to the fifth or sixth possible implementation of the first aspect, in a seventh possible implementation, the fourth data is processed based on Q2(x) to obtain the third data, including:

Step 21: Divide the fourth data from the highest bit to divide the data segment by the exponent bit size of the highest item valid by Q2(x);

Step 22: Perform a shift operation on the first data segment of the fourth data based on the Q2 (x), and XOR the data segment obtained by the shift operation to obtain a fifth data segment; a data segment is the first data segment obtained from the highest bit of the fourth data in the step 21;

Step 23: XORing the fifth data segment and the second data segment of the fourth data to obtain a sixth data segment; the second data segment of the fourth data is from the The second data segment obtained by dividing the highest bit of the fourth data;

Step 24: replacing the first data segment and the second data segment of the fourth data in step 21 with the sixth data segment to form the fourth data, and performing steps 21 to 24 until the fourth data The length is less than 2 times the length of the exponent bit of the highest term valid for Q2(x).

With reference to the fifth or the sixth possible implementation of the first aspect, in an eighth possible implementation, the fourth data is processed based on Q2(x) to obtain the third data, including:

Step 21: Divide the fourth data from the highest bit to divide the data segment by the K bit size; wherein K represents an index of the highest item valid for Q2(x);

Step 22: Perform a shift operation on the first data segment of the fourth data based on the Q2 (x), and XOR the data segment obtained by the shift operation to obtain a fifth data segment; a data segment is the first data segment obtained from the highest bit of the fourth data in the step 21;

Step 23: XOR the lower R bit of the fifth data segment and the second data segment of the fourth data to obtain a sixth data segment; the second data segment of the fourth data is the a second data segment obtained by dividing a highest bit of the fourth data; the length of the fifth data segment is M bits;

Step 24: Perform a shift operation on the high (M-K) bit of the fifth data segment based on the Q (2x) to obtain a seventh data segment;

Step 25: XOR the sixth data segment and the seventh data segment to obtain an eighth data segment;

Step 26: replacing the first data segment and the second data segment of the fourth data in step 21 with the eighth data segment to form the fourth data, and performing steps 22 to 26 until the fourth data The length of the segment is less than 2*K, where "*" indicates multiplication.

With reference to the first aspect, or any one of the first to the eighth possible implementations of the first aspect, in the ninth possible implementation, the processing the third data based on the second source polynomial to obtain the An N-bit CRC encoding of a data, including:

Dividing the third data by the second source polynomial yields an N-bit remainder as the N-bit CRC encoding of the first data.

With reference to the first aspect, or any one of the first to the ninth possible implementation manners of the first aspect, in the tenth possible implementation, the method further includes:

And storing the first data and the N-bit CRC code. This case can improve the reliability of data storage and prevent errors in stored data. Further, the method further includes reading the first data and the N-bit CRC code, calculating an N-bit CRC code of the first data, and comparing whether the calculated N-bit CRC code and the read N are compared. The bit CRC code is consistent to determine whether the first data has an error during the storage process.

With reference to the first aspect, or any one of the first to the tenth possible implementation manners of the first aspect, in an eleventh possible implementation manner, the method further includes:

Transmitting the first data and the N-bit CRC code.

A second aspect of the embodiments of the present invention provides an apparatus for calculating a cyclic redundancy check CRC code, which includes various units for implementing various possible implementation manners of the first aspect of the embodiments of the present invention.

A third aspect of the embodiments of the present invention provides an apparatus for calculating a cyclic redundancy check CRC code, including an interface and a processor, where the interface is in communication with a processor, and the processor is configured to perform various possible aspects of the first aspect of the embodiments of the present invention. Method to realize.

A fourth aspect of the embodiments of the present invention provides an apparatus for calculating a cyclic redundancy check CRC code, including an interface and a processor, where the interface communicates with a processor, and the interface is used to perform various possible aspects of the first aspect of the embodiments of the present invention. Method to realize.

Correspondingly, the fifth aspect of the embodiments of the present invention further provides a computer readable storage medium and a computer program product, where the computer readable storage medium and the computer program product comprise computer instructions for implementing various possibilities of the first aspect of the embodiments of the present invention. Method to realize.

A sixth aspect of the present invention provides a chip, including various units, for performing various possible implementations of the first aspect of the embodiments of the present invention.

DRAWINGS

1 is a schematic diagram of a prior art CRC coding.

2 is a schematic diagram of a memory array architecture in accordance with an embodiment of the present invention.

3 is a schematic diagram of a controller of a memory array in accordance with an embodiment of the present invention.

4 is a schematic diagram of a distributed block storage system in accordance with an embodiment of the present invention.

FIG. 5 is a schematic structural block diagram of a server of a distributed block storage system.

FIG. 6 is a schematic flowchart of CRC coding according to an embodiment of the present invention.

FIG. 7 is a schematic diagram of a sequence of divided information according to an embodiment of the present invention.

FIG. 8 is a schematic flowchart of CRC coding according to an embodiment of the present invention.

FIG. 9 is a schematic flowchart of CRC coding according to an embodiment of the present invention.

FIG. 10 is a schematic diagram of a sequence of divided information according to an embodiment of the present invention.

11 is a schematic view showing the structure of a chip according to an embodiment of the present invention.

detailed description

The technical solutions in the embodiments of the present invention will be described below with reference to the accompanying drawings.

As shown in FIG. 2, the storage system in the embodiment of the present invention may be a storage array (such as

of

series,

series). The storage array includes a storage controller 201 and a plurality of hard disks, wherein the hard disks include solid state disks (SSDs), disks, or hybrid hard disks. As shown in FIG. 3, the controller 201 includes a central processing unit (CPU) 301, a memory 302 and an interface 303. The memory 302 stores computer instructions, and the CPU 301 executes computer instructions in the memory 302 to manage and store the storage system. Access operation. In addition, in order to save the computing resources of the CPU 301, a Field Programmable Gate Array (FPGA) or other hardware may also be used to perform all operations of the CPU 301 in the embodiment of the present invention; or, an FPGA or other hardware and the CPU 301 are used respectively. Part of the operation of the CPU 301 of the embodiment of the present invention is performed. For convenience of description, the embodiment of the present invention uniformly refers to a combination of a CPU 301 and a memory 302, and various implementations described above, and the processor communicates with the interface 303. The interface 303 can be a Network Interface Card (NIC), a Host Bus Adaptor (HBA), an antenna, or the like.

As shown in FIG. 2 and FIG. 3, the controller 201 is configured to acquire data, such as receiving data sent by the host or the client, and calculate a CRC code of the data by using a method for calculating CRC encoding provided by the embodiment of the present invention.

Further, the storage system of the embodiment of the present invention may also be a distributed file storage system (such as

of

Series), distributed block storage systems (eg

of

Series) and so on. Take

of

series. Illustratively, as shown in FIG. 4, the distributed block storage system includes a plurality of servers, such as server 1, server 2, server 3, ..., server 6, and the servers communicate with each other through InfiniBand or Ethernet. In an actual application, the number of servers in the distributed block storage system may be increased or decreased according to actual requirements, which is not limited by the embodiment of the present invention.

The server of the distributed block storage system includes the structure as shown in FIG. As shown in FIG. 5, each server in the distributed block storage system includes a central processing unit (CPU) 501, a memory 502, an interface 503, a hard disk 1, a hard disk 2, and a hard disk 3. The computer 502 stores computer instructions. The CPU 501 executes the program instructions in the memory 502 to perform the corresponding operations. The interface 503 can be a hardware interface, such as a network interface card (NIC) or a host bus adapter (HBA), or a program interface module. The hard disk contains a Solid State Disk (SSD), a disk, or a hybrid hard disk. . In addition, in order to save the computing resources of the CPU 401, a Field Programmable Gate Array (FPGA) or other hardware may perform the above-mentioned corresponding operations instead of the CPU 501, or the FPGA or other hardware may perform the above-mentioned corresponding operations together with the CPU 501. For convenience of description, the embodiment of the present invention collectively refers to the combination of CPU 501 and memory 502, FPGA and other hardware or FPGA replacing CPU 501 and other hardware replacing CPU 501 and CPU 501 as a processor. The interface 303 can be a Network Interface Card (NIC), a Host Bus Adaptor (HBA), an antenna, or the like.

As shown in FIG. 4 and FIG. 5, the processor of the server is configured to acquire data, such as receiving data sent by the host or the client, and calculate the CRC code of the data by using the method for calculating CRC encoding provided by the embodiment of the present invention. .

In addition to the scenarios shown in FIG. 2 to FIG. 5, the embodiment of the present invention can also be applied to a data transmission scenario. In order to ensure the reliability of data transmission, for example, a computer network or various communication networks use data according to an embodiment of the present invention. A method of calculating the CRC encoding of the data provided. For example, a computer acquires data, such as data generated by an application on a computer, and calculates a CRC code of the data.

For a better understanding of the embodiments of the present invention, firstly, the basic principle of the CRC coding is introduced in the embodiment of the present invention in conjunction with the storage system shown in FIG. 2: after the controller 201 receives the data (the following is an example of receiving K-bit data), The K-bit data is used as the information sequence, and the N-bit check code is spliced after the K-bit information sequence, and the entire code length is K+N=R bits. Therefore, this encoding is also called the (R, K) code. For a given (R, K) code, it can be proved that there is a polynomial G(x) with the highest power RK=N. According to G(x), the CRC encoding of the K-bit sequence can be generated, and G(x) is called The generator polynomial of this CRC code. The specific generation process of the N-bit check code is as follows: assuming that the data to be stored is called an information sequence, an information sequence can be represented by a polynomial C(X), and C(x) is shifted to the left by N bits (which can be expressed as C(x) *X^N), so that the right side of C(x) will be N bits, which is the position where the CRC code is placed. The embodiment of the present invention is based on obtaining a check code by using C(x)*X^N and a generator polynomial G(x), that is, a remainder obtained by dividing C(x)*X^N by G(x) as an N-bit CRC code. . Among them, any one of the data consisting of binary bit strings can be in one-to-one correspondence with a polynomial whose coefficients are only '0' and '1'. Among them, the item with a coefficient of 1 is called a valid item. For example, the polynomial corresponding to the data 1010111 is X^6+X^4+X^2+X+1, where X^6 represents the 6th power of X or the 6th power of x, x is a pseudo variable, and the power index (also called index) is used to indicate the position of the arrangement between the powers, the power exponent is a non-negative integer, and "+" means an exclusive OR. The data corresponding to the polynomial X^5+X^3+X^2+X+1 is 101111. The original polynomial of CRC16 developed by the T10 Technical Committee of INCITS (InterNational Committee on Information Technology Standards) is 0x18BB7, written as binary 0001 1000 1011 1011 0111, and the corresponding polynomial is X^16+X^15+X^11+X^ 9+X^8+X^7+X^5+X^4+X^2+X^1+1. According to the existing CRC16 coding method, the information sequence needs to be divided into data segments of size 16 bits, and the data segments divided by the information sequence are the first data segment and the second data segment from the highest bit (from left to right). ..., the Nth data segment. Where N is a natural number not less than 2. First, the first data segment should be shifted to the left by 15 bits, left to 11 bits, left to 9 bits, left to 8 bits, left to 7 bits, left to 5 bits, left to 4 bits, and left to 2 bits. , shifting 1 bit to the left and 0 bit to the left, XORing the data segment obtained by shifting the first data segment, and XORing the XOR result with the second data segment, and then The third data segment and the Nth data segment are reconstructed into a data sequence. If the length of the reconstructed new data sequence is greater than 16 bits, the above operation is repeated for the new data sequence (that is, the new data sequence is divided into 16 bits. The new data segment performs the above shift and XOR operation on the new data segment again to form the updated data sequence. The number of repetitions may be one or more times until the last information sequence length is equal to 16 bits.

Therefore, the following formula (1) is obtained: CRC(C(x))=(x ^deg(G(x)) C(x))(mod(G(x)); where CRC(C(x)) represents information The CRC code of the sequence C(x), G(x) represents the source polynomial, such as the original polynomial of CRC16 of T10 is X^16+X^15+X^11+X^9+X^8+X^7+X ^5+X^4+X^2+X^1+1; deg(G(x)) represents the index of the highest term of the source polynomial, such as the index of the highest term of the original polynomial of CRC16 of T10 is 16, that is, the highest The exponent of the bit; x ^deg(G(x)) C(x) denotes the exponent bit that shifts the information sequence C(x) to the left of the highest term of the source polynomial, and mod denotes the modulo.

Combining equation (1), let Q(x)=G(x)T(x), then CRC(C(x))=R(x)(mod(G(x))); where R(x) =(x ^deg(G(x)) C(x))(mod(Q(x)), Q(x) represents a multiple of G(x), and T(x) represents a polynomial used to represent Q (x) is a multiple of G(x), and R(x) represents the remainder of the polynomial obtained by shifting the information sequence C(x) by 16 bits to the left by Q(x), where the valid highest term contained in Q(x) The difference between the index of the index and the effective second highest term is greater than 1, so that the number of cyclic shift operations can be reduced relative to G(x). Further, Q(x) with a small number of valid terms can be selected to be further reduced. The number of exclusive OR operations, thereby greatly reducing the complexity of the CRC encoding, for example, selecting the least efficient multiple of the number of terms. In the embodiment of the present invention, the effective term of the polynomial refers to the term of the coefficient 1, for example, the CRC16 of T10 The coefficients of X^16, X^15, X^11, X^9, X^8, X^7, X^5, X^4, X^2, X^1, and 1 in the source polynomial are all 1, As an effective item.

In the embodiment of the present invention, G(X)=X^16+X^15+X^11+X^9+X^8+X^7+X^5+X^4+X^2+X^1+ 1 For example, a computer can calculate a multiplier of G(x), for example, using the following procedure to find a ploid of G(x), usually defining a search range, and defining an index of the highest term of the multiplier, for example, 524287. The multiplet Q(x) of G(x) is expressed as x^i+x^j. The calculation of the doubling method in the embodiment of the present invention may be calculated by an independent computer, or may be calculated by the device provided by the embodiment of the present invention, such as a storage system, and is not limited herein. Taking an independent computer calculation as an example, the computer performs the following operations:

The first step: traversing i and j, where i and j are assigned, and 0 <= j < i <= 524287.

Step 2: Initialize the information sequence C(x) with a length of 524288 bits to all zeros. Because if the index of the highest term of the octave is 524287, the information sequence C(x) has 524288 bits.

The third step: setting the value of the i-th bit and the j-th bit of the information sequence C(x) to 1.

The fourth step: the CRC16 encoding method is performed on the information sequence C(x) of length 524288 to obtain the CRC encoding. If the CRC encoding is 0, it means that one G(x) multiple is found.

Repeat steps 1 through 4 until you have traversed all i and j.

In the embodiment of the present invention, a multiple of Q(x)=X^369+X^31+1 of G(x) is taken as an example. From this doubling, it can be seen that, except for the index 369 of the highest term, the polynomial has only two coefficients. It is 1, that is, except for the highest item, there are only two valid items, so the number of cyclic shift operations and XOR operations is only 2 times.

In the embodiment of the present invention, G(x)=X^16+X^15+X^11+X^9+X^8+X^7+X^5+X^4+X^2+X^1+ 1,Q(x)=X^369+X^31+1, and C(x) is an information sequence of 4096 bits as an example, and the CRC16 encoding of the information sequence is calculated. In the embodiment of the present invention, the controller 201 needs to store Q(x) and G(x) for calculating the CRC encoding of the data. The embodiment of the present invention is as shown in FIG. 6, and includes:

Step 601: Shift C(x) to the left by 16 bits.

That is, 16 zeros are added after 4096 bits, and the shifted information sequence is used as a new information sequence with a length of 4096+16=4112 bits.

Step 602: Divide the new information sequence from the highest bit of the new information sequence into a data segment of length 369 bits.

The new information sequence is divided from the highest bit to the left of the new information, and the first bit on the left is the highest bit. Step 602 divides the shifted information sequence into 11 data segments of length 369 bits and a data segment of length 53. As shown in FIG. 7, the data segments having a length of 369 bits are represented as the first data segment, the second data segment, the third data segment, ..., the 11th data segment, and the data segment having the length of 53 bits is recorded as the 12th segment. Data segment. The information sequence of the first data segment is represented as A, and the information sequence of the second data segment is represented as B. Dividing a new sequence of information from the highest bit of the new information sequence into a data segment of length 369 bits is also referred to as dividing the new information sequence from the highest bit of the new information sequence by 369 bits, ie Q (x) ) The exponent bit size of the highest valid item divides the data segment.

Step 603: Move the first data segment to the left by 31 bits and 0 bits respectively (in other words: generate a data segment by shifting the first data segment by 31 bits to the left, and shifting the first data segment by 0 bits to generate the second data. Segment), XORed by 31 bits left and 0 bits shifted left by 0.

According to the previous operation of calculating the CRC16 encoding, the first data segment starts shifting to the left according to the next highest index of the octave.

Step 604: The XOR result of shifting the left data by 31 bits and shifting the left bit by 0 bits is further XORed with the second data segment.

Step 605: The result of step 604 is formed into a new information sequence as the first data segment and the remaining data segments.

The new sequence of information generated in step 605 is executed in steps 602-605, and is cycled until the final length of the new information sequence obtained according to step 605 is 394 bits, that is, the length of the new information sequence is less than 2*369.

In the embodiment of the present invention, after step 605, when the length of the new information sequence is greater than 2*369, step 602 is performed; when the length of the new information sequence is less than 2*369, step 606 is performed.

In the above embodiment, the data segment needs to be shifted to the left by 31 bits according to Q(x), but each time the steps 602-605 are performed, one data segment is reduced, so even if the data segment is shifted to the left by 31 bits, it is still reduced. The length of the (369-31) bit is reduced by 338 bits. Therefore, the number of shift operations is reduced relative to the prior art. The length of the new information sequence in step 601 is 4112 bits, that is, (12*338+56) bits. Therefore, when the length of the new information sequence obtained in step 605 is 394 bits, the operations of steps 2-4 cannot be performed. When the new information sequence length obtained in step 605 is 394 bits, 606 is performed.

Step 606: Calculate the CRC16 encoding based on G(x) with the new information sequence. That is, the CRC16 coding is obtained by processing a new information sequence based on G(x). In the actual implementation, the new information sequence is divided by the remainder of G(x) as the CRC16 coding.

In the embodiment shown in FIG. 6, the number of shift operations and the number of XOR operations are reduced relative to the prior art, thereby saving computational resources and improving the efficiency and performance of calculating CRC coding.

In another embodiment of the present invention, as shown in FIG. 8, in the embodiment of the present invention, steps 801-803 refer to steps 601-603 shown in FIG. 6, respectively.

Step 804: The lower 369 bits of the XOR result of the 1st data segment shifted to the left by 31 bits and the left shift of 0 bits are XORed with the 2nd data segment.

The XOR of the first data segment of the left shift of 31 bits and the left shift of 0 bits has a total of 400 bits, and the left side of the XOR of the first data segment of the left shift of 31 bits and the left shift of 0 bits is defined as a high bit (conversely defined as Low), for example, the first 31 bits from the left are called the high 31 bits, and the 369 bits from the right are called the lower 369 bits.

Step 805: After shifting the upper 31 bits of the XOR data of the 1st data segment shifted left 31 bits and the left shift 0 bit to the left by 31 bits and 0 bits respectively, the two are XORed.

Step 806: XOR the results of step 804 and step 805 to obtain a new data segment, and form a new information sequence with the new data segment and the remaining data segments.

Steps 802-806 are repeated for the new information sequence until the new information sequence length obtained according to step 805 is (369+53) bits, ie 422 bits.

In the embodiment of the present invention, after step 806, when the length of the new information sequence is greater than 2*369, step 802 is performed; when the length of the new information sequence is less than 2*369, step 807 is performed.

In the above embodiment, the data segment needs to be shifted to the left by 31 bits according to Q(x) each time, but each time through the steps 802-804, even if the data segment is shifted to the left by 31 bits, the length of 369 bits is reduced. Therefore, the shift operation data is greatly reduced as compared with the prior art. The length of the new information sequence in step 1 is 4112 bits, that is, (11*369+56) bits. Therefore, when the length of the new information sequence obtained in step 806 is 422 bits, the operations of steps 802-805 cannot be performed. That is, the new information sequence length is less than 2*369. When the new information sequence length obtained in step 806 is 422 bits, step 807 is performed.

Step 807: Calculate the CRC16 encoding based on G(x) with the new information sequence. That is, the CRC16 coding is obtained by processing a new information sequence based on G(x). In the actual implementation, the new information sequence is divided by the remainder of G(x) as the CRC16 code.

In the embodiment shown in FIG. 8, the number of shift operations and the number of exclusive OR operations are reduced relative to the prior art, thereby saving computational resources and improving the efficiency and performance of calculating CRC coding.

In another embodiment of the present invention,

G(x)=X^16+X^15+X^11+X^9+X^8+X^7+X^5+X^4+X^2+X^1+1,Q(x For example, the information sequence of 512 KB is 512 KB, and the number of bits of the information sequence of 512 KB is 512*1024*8=4194304 bits, which can be used in the embodiment of the present invention. The doubling formula performs CRC16 calculation, such as the multiple equation Q1(x)=x^65535+1, and the multiple equation Q2(x)=x^369+x^31+1. The implementation of the present invention is as shown in FIG. 9, and includes:

Step 901: Shift C(x) to the left by 16 bits.

That is, 16 zeros are added after the 4194304 bits, and the shifted information sequence is used as a new information sequence with a length of 4194304+16=4194320 bits.

Step 902: The new information sequence is divided from the highest bit into a data segment having a length of 65535 bits.

The new information sequence is divided from the highest bit to indicate the division from the left of the new information. Step 902 divides the shifted information sequence into 64 data segments of length 65535 bits and a data segment of length 80 bits. As shown in FIG. 10, the data segments having a length of 65535 bits are respectively represented as the first data segment, the second data segment, the third data segment, ..., the 64th data segment, and the data segment having the length of 80 bits is recorded as the 65th. Data segment. The information sequence of the first data segment is represented as A, and the information sequence of the second data segment is represented as B.

Step 903: XOR the first data segment and the second data segment.

According to the previous operation of calculating the CRC16 check data, the first data segment starts shifting to the left according to the next highest index of the multiple. In the embodiment of the present invention, the next highest index of Q1(x)=x^65535+1 is 0, and 0 bit is shifted to the left.

Step 904: The result of the exclusive OR of step 903 is formed into a new information sequence as the first data segment and the remaining data segments.

The new information sequence is executed in steps 902-904 until the new information sequence length obtained according to step 904 is (65536+80) bits, that is, the new information sequence length is less than 2*65535.

In the embodiment of the present invention, after the step 904, when the length of the new information sequence is greater than 2*65535, step 902 is performed until the length of the new information sequence is less than 2*65535.

In the above embodiment, the data segment needs to be shifted to the left by 0 bits each time according to Q1(x), but each time through steps 902-904, the data sequence is reduced by 65535 bits. Therefore, the shift operation data is greatly reduced as compared with the prior art. Therefore, when the new information sequence length obtained in step 904 is 65,615 bits, the operations of steps 902-904 can no longer be performed. When the new information sequence length obtained in step 904 is 65615 bits, steps 602-606 of the embodiment shown in FIG. 6 or steps 802-807 of the embodiment shown in FIG. 8 are performed according to Q2(x).

In the embodiment shown in FIG. 9, multiple multiples are used, which can effectively reduce the number of shift operations and XOR calculations when calculating a CRC code for a long information sequence, thereby saving computational resources and improving computational CRC. The efficiency and performance of the coding.

In the embodiment of the present invention, in order to reduce data processing delay, a central processing unit (CPU) may be used to calculate a CRC check code, for example,

of

Different sizes of CPUs have different register sizes, such as 64-bit registers, 128-bit registers, 256-bit registers, and 512-bit registers. The size of the CPU's registers can be considered when determining Q(x) to take full advantage of the hardware resources of the CPU. For example, in

In a CPU that supports Streaming Single Instruction Single Instruction Multiple Data Extensions (SSE), the register size is 128 bits. Therefore, Q(x)=x^384+x^46+x can be used. ^15, this can divide the information sequence into data segments according to 384-bit size, then three 128-bit registers are needed, which can make full use of CPU hardware resources.

The above embodiments are applied to a storage system, which stores CRC codes of data, stores CRC codes of data and data, and ensures accuracy and consistency of data storage. When the storage system reads the data, the CRC code of the data is simultaneously read, and the storage system calculates the CRC code of the read data, and compares whether the CRC code of the read data is the same as the CRC code calculated by the read data. If they are the same, it means that the data did not have an error during the storage process; if it is not the same, it indicates that the data has an error during the storage process.

The technical solution provided by the embodiment of the present invention can also be used for the CRC check of the data link layer. In the communication system, the data unit of the network layer protocol is an Internet Protocol (IP) data packet, and the work of the data link layer is to encapsulate the IP data packet delivered by the network layer into a frame and send it to the link. And, the data packet in the received frame is taken out and handed over to the network layer. To achieve this, the data link must have a series of corresponding functions, mainly:

Encapsulating a data packet into a frame, which is a transmission unit of the data link layer;

Controlling the transmission of the frame, including processing the transmission error, adjusting the transmission rate to match the receiver;

Management of the establishment, maintenance, and release of data link pathways between two network entities.

The data link layer needs to have the following functions in the transmission of control frames:

Error control:

The communication system must have the ability to detect errors and take measures to correct it so that the error is within the smallest possible range. This is the error control process and one of the main functions of the data link layer.

Feedback resend:

By checking the CRC code, the receiver can determine whether a frame has an error during transmission. Once an error is found, it can generally be corrected by feedback retransmission. This requires the recipient to feed back to the sender a message that the reception is correct, so that the sender can make a decision on whether to resend accordingly. The sender can only consider that the frame has been correctly transmitted after receiving the feedback signal that the receiver has correctly received. Otherwise, it needs to be resent until it is correct. The receiving party, that is, the receiving device receives the frame, acquires the data in the frame and the CRC code, and the receiving device calculates the CRC code of the data in the same manner as the sending device, and compares whether the CRC code calculated by the receiving device and the CRC code in the frame are The same, if the same, proves that the frame did not make an error during the transmission, otherwise an error occurred.

Therefore, the embodiment of the present invention can also be applied to the operation of CRC encoding performed in a switch and a physical network card. The embodiment of the invention can also be applied to an FPGA chip,

The processor or an application-specific integrated circuit (ASIC) or the like calculates the CRC code. Physical network cards, FPGA chips, ARM or ASICs can be applied to servers, user terminals, in-vehicle devices, wireless base stations, routers, switches, gateways, and the like. In a specific implementation, the source polynomial G(x) and one or more primitive polynomials Q(x) may be generated according to the length of the CRC encoding, such as 16-bit CRC encoding, for convenient calculation of CRC encoding, G(x) And Q(x) may be preset in the chip or device to query or invoke G(x) and Q(x) when the various devices of the embodiments of the present invention calculate the CRC code. G(x) and Q(x) may be presented in binary, hexadecimal, etc., which is not limited by the implementation of the present invention.

The embodiments of the present invention provide a storage device, a server, a user terminal, an in-vehicle device, a wireless base station, a router, a switch, a gateway, and the like, including an interface and a processor, where the processor is used to execute various embodiments of the embodiments of the present invention, or an interface card of the foregoing device. The various embodiments of the embodiments of the present invention are implemented. In another implementation, the above device includes various units, as shown in FIG. 11, including an obtaining unit 111, a shifting unit 112, and a processing unit 113. The obtaining unit 111 is configured to acquire first data, and the shifting unit 112 is configured to shift the first data to the left by N bits to obtain second data, where N is a cyclic redundancy check CRC coded number of bits; 113. The method is configured to process the second data based on one or more first source polynomials to obtain third data, and process the third data based on the second native polynomial to obtain an N-bit CRC encoding of the first data. a difference between an index X of a highest item in which the first source polynomial is valid for each of the first source polynomial and an index Y of the effective second highest item is greater than 1; a length of the third data is less than the second The length of the data; X and Y are positive integers, X is greater than Y; each of the one or more first source polynomials is a multiple of the second source polynomial, the one or more first source polynomials An index X of the highest item valid for each of the first source polynomials is greater than an index R of the highest highest item of the second source polynomial. Further, the processing unit 113 is specifically configured to perform the following steps:

Step 1: dividing the second data from the highest bit and dividing the data segment by the X bit size;

Step 2: Perform a shift operation on the first data segment of the second data based on the first source polynomial, and XOR the data segment obtained by the shift operation to obtain a third data segment; the first data segment is The first data segment obtained from the highest bit of the second data in the step 1;

Step 3: XOR the third data segment and the second data segment to obtain a fourth data segment; the second data segment is the second one obtained by dividing the X-bit size from the highest bit in step 1. Data segment

Step 4: replacing the first data segment and the second data segment of the second data in step 1 with the fourth data segment to form the second data, and performing steps 1 to 4 until The length of the second data is less than 2*X bits, where "*" indicates multiplication.

Further, the processing unit 113 is specifically configured to perform the following steps:

Step 1: dividing the second data from the highest bit and dividing the data segment by the X bit size;

Step 2: Perform a shift operation on the first data segment of the second data based on the first source polynomial, and XOR the data segment obtained by the shift operation to obtain a third data segment; the first data segment is a first data segment obtained from the highest bit of the second data in the step 1; wherein the length of the third data segment is M bits;

Step 3: XORing the lower X bits of the third data segment with the second data segment to obtain a fourth data segment; the second data segment is divided into X bits according to the highest bit in step 1. The second data segment obtained;

Step 4: Perform a shift operation on the high (M-X) bit of the third data segment based on the Q(x) to obtain a fifth data segment;

Step 5: XOR the fourth data segment and the fifth data segment to obtain a sixth data segment;

Step 6: replacing the first data segment and the second data segment of the second data in step 1 with the sixth data segment to form the second data, and performing steps 1 to 6 until The length of the second data is less than 2*X bits, where "*" indicates multiplication.

Further, the one or more first source polynomials comprise first source polynomials Q1(x) and Q2(x), wherein the index of the highest item valid for Q1(x) is greater than the highest item of Q2(x) effective The index, processing unit 113 is specifically configured to perform the following steps:

Processing the second data based on Q1(x) to obtain fourth data;

The fourth data is processed based on Q2(x) to obtain the third data.

Further, the processing unit 113 is specifically configured to perform the following steps:

Step 1: dividing the second data from the highest bit and dividing the data segment by the exponent bit size of the highest item valid by Q1(x);

Step 2: Perform a shift operation on the first data segment of the second data based on the Q1 (x), and XOR the data segment obtained by the shift operation to obtain a third data segment; the first data segment is The first data segment obtained from the highest bit of the second data in the step 1;

Step 3: XOR the third data segment and the second data segment to obtain a fourth data segment; the second data segment is the highest item in the step 1 that is valid from the highest bit and is valid with Q1(x) The second data segment obtained by dividing the index bit size;

Step 4: replacing the first data segment and the second data segment of the second data in step 1 with the fourth data segment to form the second data, and performing steps 1 to 4 until The length of the second data is less than 2 times the exponent bit of the highest term in which Q1(x) is valid.

Further, the processing unit 113 is specifically configured to perform the following steps:

Step 21: Divide the fourth data from the highest bit to divide the data segment by the exponent bit size of the highest item valid by Q2(x);

Step 22: Perform a shift operation on the first data segment of the fourth data based on the Q2 (x), and XOR the data segment obtained by the shift operation to obtain a fifth data segment; a data segment is the first data segment obtained from the highest bit of the fourth data in the step 21;

Step 23: XORing the fifth data segment and the second data segment of the fourth data to obtain a sixth data segment; the second data segment of the fourth data is from the The second data segment obtained by dividing the highest bit of the fourth data;

Step 24: replacing the first data segment and the second data segment of the fourth data in step 21 with the sixth data segment to form the fourth data, and performing steps 21 to 24 until the fourth data The length is less than 2 times the length of the exponent bit of the highest term valid for Q2(x).

Further, the processing unit 113 is specifically configured to perform the following steps:

Step 21: Divide the fourth data from the highest bit to divide the data segment by the K bit size; wherein K represents an index of the highest item valid for Q2(x);

Step 22: Perform a shift operation on the first data segment of the fourth data based on the Q2 (x), and XOR the data segment obtained by the shift operation to obtain a fifth data segment; a data segment is the first data segment obtained from the highest bit of the fourth data in the step 21;

Step 23: XOR the lower K bit of the fifth data segment and the second data segment of the fourth data to obtain a sixth data segment; the second data segment of the fourth data is the a second data segment obtained by dividing a highest bit of the fourth data; the length of the fifth data segment is M bits;

Step 24: Perform a shift operation on the high (M-K) bit of the fifth data segment based on the Q (2x) to obtain a seventh data segment;

Step 25: XOR the sixth data segment and the seventh data segment to obtain an eighth data segment;

Step 26: replacing the first data segment and the second data segment of the fourth data in step 21 with the eighth data segment to form the fourth data, and performing steps 22 to 26 until the fourth data The length of the segment is less than 2*K, where "*" indicates multiplication.

Further, the processing unit 113 is specifically configured to:

Dividing the third data by the second source polynomial yields an N-bit remainder as the N-bit CRC encoding of the first data.

Further, a storage unit is further included, configured to store the first data and the N-bit CRC code.

Further, the method further includes a sending unit, configured to send the first data and the N-bit CRC code.

Further, the storage unit is further configured to store the source polynomial and the multiple. The above-mentioned units are respectively used to implement the corresponding implementations of the embodiments of the embodiments of the present invention. The specific implementations of the various units may be the device structure of the embodiment of the present invention, or may be a software module, which may be run on a server, thereby enabling the device to complete the present invention. Various implementations described in the embodiments. The various units may also be hardware devices, for example each unit may be implemented as a processor or interface. For the implementation of the foregoing device, including the various unit implementations, reference may be made to the foregoing method embodiments, and details are not described herein.

The embodiment of the present invention further provides a chip, as shown in FIG. 11, comprising: an obtaining unit 111, a shifting unit 112, and a processing unit 113. Further, the above chip may further include a storage unit 114 for storing the original polynomial and the multiple. Each of the above units is used to implement the corresponding implementation of each solution in the embodiment of the present invention. Each unit shown in FIG. 11 may be a hardware logic module of the chip, an ASCI, a network card, or the like.

Yet another aspect of the present application provides a computer readable storage medium having instructions stored therein that, when executed on a computer, cause the computer to perform the various embodiments described above.

Yet another aspect of the present application provides a computer program product comprising instructions that, when executed on a computer, cause the computer to perform the various embodiments described above.

Those of ordinary skill in the art will appreciate that the elements and algorithm steps of the various examples described in connection with the embodiments disclosed herein can be implemented in electronic hardware or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the solution. A person skilled in the art can use different methods to implement the described functions for each particular application, but such implementation should not be considered to be beyond the scope of the present application.

A person skilled in the art can clearly understand that for the convenience and brevity of the description, the specific working process of the system, the device and the unit described above can refer to the corresponding process in the foregoing method embodiment, and details are not described herein again.

In the several embodiments provided herein, it should be understood that the disclosed systems, devices, and methods may be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the unit is only a logical function division. In actual implementation, there may be another division manner, for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be in an electrical, mechanical or other form.

The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

The functions may be stored in a computer readable storage medium if implemented in the form of a software functional unit and sold or used as a standalone product. Based on such understanding, the technical solution of the present application, which is essential or contributes to the prior art, or a part of the technical solution, may be embodied in the form of a software product, which is stored in a storage medium, including The instructions are used to cause a computer device (which may be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present application. The foregoing computer readable storage medium includes: a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and the like. The medium of the program code.

Claims (48)

1. A method for calculating a cyclic redundancy check CRC coding, the method comprising:

   Obtain the first data;

   Transmitting the first data to the left by N bits to obtain second data, where N is a cyclic redundancy check CRC coded number of bits;

   Processing the second data based on the one or more first native polynomials to obtain third data; wherein an exponent X of the highest term of each of the one or more first native polynomials is valid and a valid number of times The difference between the highest index Y is greater than 1; the length of the third data is less than the length of the second data; X and Y are positive integers, and X is greater than Y;

   Processing the third data based on the second native polynomial to obtain an N-bit CRC encoding of the first data; wherein each of the one or more first source polynomials is a multiple of the second native polynomial, An index X of the highest item valid for each of the one or more first source polynomials is greater than an index R of the highest highest item of the second source polynomial.
2. The method of claim 1 wherein the number of items valid for each of the one or more first source polynomials is less than the number of items valid for the second source polynomial.
3. The method according to claim 1 or 2, wherein the first source polynomial is a finite formula having the least number of terms valid in a multiple of the second native polynomial.
4. The method according to any one of claims 1-3, wherein the processing the second data based on the one or more first source polynomials to obtain the third data comprises:

   Step 1: dividing the second data from the highest bit and dividing the data segment by the X bit size;

   Step 2: Perform a shift operation on the first data segment of the second data based on the first source polynomial, and XOR the data segment obtained by the shift operation to obtain a third data segment; the first data segment is The first data segment obtained from the highest bit of the second data in the step 1;

   Step 3: XOR the third data segment and the second data segment to obtain a fourth data segment; the second data segment is the second one obtained by dividing the X-bit size from the highest bit in step 1. Data segment

   Step 4: replacing the first data segment and the second data segment of the second data in step 1 with the fourth data segment to form the second data, and performing steps 1 to 4 until The length of the second data is less than 2*X bits, where "*" indicates multiplication.
5. The method according to any one of claims 1-3, wherein the processing the second data based on the one or more first source polynomials to obtain the third data comprises:

   Step 1: dividing the second data from the highest bit and dividing the data segment by the X bit size;

   Step 2: Perform a shift operation on the first data segment of the second data based on the first source polynomial, and XOR the data segment obtained by the shift operation to obtain a third data segment; the first data segment is a first data segment obtained from the highest bit of the second data in the step 1; wherein the length of the third data segment is M bits;

   Step 3: XORing the lower X bits of the third data segment with the second data segment to obtain a fourth data segment; the second data segment is divided into X bits according to the highest bit in step 1. The second data segment obtained;

   Step 4: Perform a shift operation on the high (M-X) bit of the third data segment based on the Q(x) to obtain a fifth data segment;

   Step 5: XOR the fourth data segment and the fifth data segment to obtain a sixth data segment;

   Step 6: replacing the first data segment and the second data segment of the second data in step 1 with the sixth data segment to form the second data, and performing steps 1 to 6 until The length of the second data is less than 2*X bits, where "*" indicates multiplication.
6. A method according to any of claims 1-3, wherein said one or more first source polynomials comprise first source polynomials Q1(x) and Q2(x), wherein Q1(x) is valid The index of the highest item is greater than the index of the highest item valid for Q2(x); the processing the second data based on the one or more first source polynomials to obtain the third data, including:

   Processing the second data based on Q1(x) to obtain fourth data;

   The fourth data is processed based on Q2(x) to obtain the third data.
7. The method according to claim 6, wherein the processing the second data based on Q1(x) to obtain fourth data comprises:

   Step 1: dividing the second data from the highest bit and dividing the data segment by the exponent bit size of the highest item valid by Q1(x);

   Step 2: Perform a shift operation on the first data segment of the second data based on the Q1 (x), and XOR the data segment obtained by the shift operation to obtain a third data segment; the first data segment is The first data segment obtained from the highest bit of the second data in the step 1;

   Step 3: XOR the third data segment and the second data segment to obtain a fourth data segment; the second data segment is the highest item in the step 1 that is valid from the highest bit and is valid with Q1(x) The second data segment obtained by dividing the index bit size;

   Step 4: replacing the first data segment and the second data segment of the second data in step 1 with the fourth data segment to form the second data, and performing steps 1 to 4 until The length of the second data is less than 2 times the exponent bit of the highest term in which Q1(x) is valid.
8. The method according to claim 7, wherein the processing the fourth data based on Q2(x) to obtain the third data comprises:

   Step 21: Divide the fourth data from the highest bit to divide the data segment by the exponent bit size of the highest item valid by Q2(x);

   Step 22: Perform a shift operation on the first data segment of the fourth data based on the Q2 (x), and XOR the data segment obtained by the shift operation to obtain a fifth data segment; a data segment is the first data segment obtained from the highest bit of the fourth data in the step 21;

   Step 23: XORing the fifth data segment and the second data segment of the fourth data to obtain a sixth data segment; the second data segment of the fourth data is from the The second data segment obtained by dividing the highest bit of the fourth data;

   Step 24: replacing the first data segment and the second data segment of the fourth data in step 21 with the sixth data segment to form the fourth data, and performing steps 21 to 24 until the fourth data The length is less than 2 times the length of the exponent bit of the highest term valid for Q2(x).
9. The method according to claim 7, wherein the processing the fourth data based on Q2(x) to obtain the third data comprises:

   Step 21: Divide the fourth data from the highest bit to divide the data segment by the K bit size; wherein K represents an index of the highest item valid for Q2(x);

   Step 22: Perform a shift operation on the first data segment of the fourth data based on the Q2 (x), and XOR the data segment obtained by the shift operation to obtain a fifth data segment; a data segment is the first data segment obtained from the highest bit of the fourth data in the step 21;

   Step 23: XOR the lower K bit of the fifth data segment and the second data segment of the fourth data to obtain a sixth data segment; the second data segment of the fourth data is the a second data segment obtained by dividing a highest bit of the fourth data; the length of the fifth data segment is M bits;

   Step 24: Perform a shift operation on the high (M-K) bit of the fifth data segment based on the Q (2x) to obtain a seventh data segment;

   Step 25: XOR the sixth data segment and the seventh data segment to obtain an eighth data segment;

   Step 26: replacing the first data segment and the second data segment of the fourth data in step 21 with the eighth data segment to form the fourth data, and performing steps 22 to 26 until the fourth data The length of the segment is less than 2*K, where "*" indicates multiplication.
10. The method according to any one of claims 1-9, wherein the processing the third data based on the second native polynomial to obtain the N-bit CRC encoding of the first data comprises:

    Dividing the third data by the second source polynomial yields an N-bit remainder as the N-bit CRC encoding of the first data.
11. The method according to any one of claims 1 to 10, wherein the method further comprises:

    And storing the first data and the N-bit CRC code.
12. The method according to any one of claims 1 to 10, wherein the method further comprises:

    Transmitting the first data and the N-bit CRC code.
13. An apparatus for calculating a cyclic redundancy check CRC code, comprising:

    An obtaining unit, configured to acquire first data;

    a shifting unit, configured to shift the first data to the left by N bits to obtain second data, where N is a cyclic redundancy check CRC coded number of bits;

    a processing unit, configured to process the second data based on the one or more first native polynomials to obtain third data, and process the third data based on the second native polynomial to obtain an N-bit CRC encoding of the first data; a difference between an index X of a highest item in which the first source polynomial is valid of each of the one or more first source polynomials and an index Y of a valid second highest item is greater than 1; a length of the third data is less than the number The length of the two data; X and Y are positive integers, X is greater than Y; each of the one or more first source polynomials is a multiple of the second native polynomial, the one or more first sources An exponent X of the highest item valid for each of the first original polynomial of the polynomial is greater than an exponent R of the highest highest item of the second native polynomial.
14. The apparatus of claim 13 wherein the number of terms for which each of the one or more first source polynomials is valid for the first source polynomial is less than the number of terms for which the second source polynomial is valid.
15. The apparatus according to claim 13 or 14, wherein said first source polynomial is a multiple of a number of terms valid in a multiple of said second native polynomial.
16. The device according to any one of claims 11-15, wherein the processing unit is specifically configured to perform the following steps:

    Step 1: dividing the second data from the highest bit and dividing the data segment by the X bit size;

    Step 2: Perform a shift operation on the first data segment of the second data based on the first source polynomial, and XOR the data segment obtained by the shift operation to obtain a third data segment; the first data segment is The first data segment obtained from the highest bit of the second data in the step 1;

    Step 3: XOR the third data segment and the second data segment to obtain a fourth data segment; the second data segment is the second one obtained by dividing the X-bit size from the highest bit in step 1. Data segment

    Step 4: replacing the first data segment and the second data segment of the second data in step 1 with the fourth data segment to form the second data, and performing steps 1 to 4 until The length of the second data is less than 2*X bits, where "*" indicates multiplication.
17. The device according to any one of claims 11-15, wherein the processing unit is specifically configured to perform the following steps:

    Step 1: dividing the second data from the highest bit and dividing the data segment by the X bit size;

    Step 2: Perform a shift operation on the first data segment of the second data based on the first source polynomial, and XOR the data segment obtained by the shift operation to obtain a third data segment; the first data segment is a first data segment obtained from the highest bit of the second data in the step 1; wherein the length of the third data segment is M bits;

    Step 3: XORing the lower X bits of the third data segment with the second data segment to obtain a fourth data segment; the second data segment is divided into X bits according to the highest bit in step 1. The second data segment obtained;

    Step 4: Perform a shift operation on the high (M-X) bit of the third data segment based on the Q(x) to obtain a fifth data segment;

    Step 5: XOR the fourth data segment and the fifth data segment to obtain a sixth data segment;

    Step 6: replacing the first data segment and the second data segment of the second data in step 1 with the sixth data segment to form the second data, and performing steps 1 to 6 until The length of the second data is less than 2*X bits, where "*" indicates multiplication.
18. The apparatus according to any one of claims 11-15, wherein said one or more first source polynomials comprise first source polynomials Q1(x) and Q2(x), wherein Q1(x) is valid The index of the highest item is greater than the index of the highest item that is valid for Q2(x); the processing unit is specifically configured to perform the following steps:

    Processing the second data based on Q1(x) to obtain fourth data;

    The fourth data is processed based on Q2(x) to obtain the third data.
19. The device according to claim 18, wherein the processing device is specifically configured to perform the following steps:

    Step 1: dividing the second data from the highest bit and dividing the data segment by the exponent bit size of the highest item valid by Q1(x);

    Step 2: Perform a shift operation on the first data segment of the second data based on the Q1 (x), and XOR the data segment obtained by the shift operation to obtain a third data segment; the first data segment is The first data segment obtained from the highest bit of the second data in the step 1;

    Step 3: XOR the third data segment and the second data segment to obtain a fourth data segment; the second data segment is the highest item in the step 1 that is valid from the highest bit and is valid with Q1(x) The second data segment obtained by dividing the index bit size;

    Step 4: replacing the first data segment and the second data segment of the second data in step 1 with the fourth data segment to form the second data, and performing steps 1 to 4 until The length of the second data is less than 2 times the exponent bit of the highest term in which Q1(x) is valid.
20. The device according to claim 18, wherein the processing unit is specifically configured to perform the following steps:

    Step 21: Divide the fourth data from the highest bit to divide the data segment by the exponent bit size of the highest item valid by Q2(x);

    Step 22: Perform a shift operation on the first data segment of the fourth data based on the Q2 (x), and XOR the data segment obtained by the shift operation to obtain a fifth data segment; a data segment is the first data segment obtained from the highest bit of the fourth data in the step 21;

    Step 23: XORing the fifth data segment and the second data segment of the fourth data to obtain a sixth data segment; the second data segment of the fourth data is from the The second data segment obtained by dividing the highest bit of the fourth data;

    Step 24: replacing the first data segment and the second data segment of the fourth data in step 21 with the sixth data segment to form the fourth data, and performing steps 21 to 24 until the fourth data The length is less than 2 times the length of the exponent bit of the highest term valid for Q2(x).
21. The device according to claim 18, wherein the processing unit is specifically configured to perform the following steps:

    Step 21: Divide the fourth data from the highest bit to divide the data segment by the K bit size; wherein K represents an index of the highest item valid for Q2(x);

    Step 22: Perform a shift operation on the first data segment of the fourth data based on the Q2 (x), and XOR the data segment obtained by the shift operation to obtain a fifth data segment; a data segment is the first data segment obtained from the highest bit of the fourth data in the step 21;

    Step 23: XOR the lower K bit of the fifth data segment and the second data segment of the fourth data to obtain a sixth data segment; the second data segment of the fourth data is the a second data segment obtained by dividing a highest bit of the fourth data; the length of the fifth data segment is M bits;

    Step 24: Perform a shift operation on the high (M-K) bit of the fifth data segment based on the Q (2x) to obtain a seventh data segment;

    Step 25: XOR the sixth data segment and the seventh data segment to obtain an eighth data segment;

    Step 26: replacing the first data segment and the second data segment of the fourth data in step 21 with the eighth data segment to form the fourth data, and performing steps 22 to 26 until the fourth data The length of the segment is less than 2*K, where "*" indicates multiplication.
22. The device according to any one of claims 13 to 21, wherein the processing unit is specifically configured to:

    Dividing the third data by the second source polynomial yields an N-bit remainder as the N-bit CRC encoding of the first data.
23. The apparatus according to any one of claims 13-22, further comprising a storage unit for storing said first data and said N-bit CRC code.
24. The apparatus according to any one of claims 13-22, further comprising a transmitting unit configured to transmit the first data and the N-bit CRC code.
25. An apparatus for calculating a cyclic redundancy check CRC code, the apparatus comprising an interface and a processor, the processor is configured to:

    Obtain the first data;

    Transmitting the first data to the left by N bits to obtain second data, where N is a cyclic redundancy check CRC coded number of bits;

    Processing the second data based on one or more first source polynomials to obtain third data;

    Processing the third data based on the second native polynomial to obtain an N-bit CRC encoding of the first data; wherein an index X of a highest term of each of the one or more first native polynomials valid for the first native polynomial The difference from the index Y of the effective next highest item is greater than 1; the length of the third data is less than the length of the second data; X and Y are positive integers, and X is greater than Y; the one or more first sources Each of the polynomials is a multiple of the second native polynomial, an exponent X of the highest term of each of the one or more first native polynomials valid for the first native polynomial being greater than the validity of the second native polynomial The highest index of the index R.
26. The apparatus of claim 25 wherein the number of terms for which each of the one or more first source polynomials is valid for the first source polynomial is less than the number of terms for which the second source polynomial is valid.
27. The apparatus according to claim 25 or 26, wherein said first source polynomial is a finite formula having the least number of terms valid in a multiple of said second native polynomial.
28. The device according to any one of claims 25-27, wherein the processor is specifically configured to:

    Step 1: dividing the second data from the highest bit and dividing the data segment by the X bit size;

    Step 2: Perform a shift operation on the first data segment of the second data based on the first source polynomial, and XOR the data segment obtained by the shift operation to obtain a third data segment; the first data segment is The first data segment obtained from the highest bit of the second data in the step 1;

    Step 3: XOR the third data segment and the second data segment to obtain a fourth data segment; the second data segment is the second one obtained by dividing the X-bit size from the highest bit in step 1. Data segment

    Step 4: replacing the first data segment and the second data segment of the second data in step 1 with the fourth data segment to form the second data, and performing steps 1 to 4 until The length of the second data is less than 2*X bits, where "*" indicates multiplication.
29. The device according to any one of claims 25-27, wherein the processor is specifically configured to:

    Step 1: dividing the second data from the highest bit and dividing the data segment by the X bit size;

    Step 2: Perform a shift operation on the first data segment of the second data based on the first source polynomial, and XOR the data segment obtained by the shift operation to obtain a third data segment; the first data segment is a first data segment obtained from the highest bit of the second data in the step 1; wherein the length of the third data segment is M bits;

    Step 3: XORing the lower X bits of the third data segment with the second data segment to obtain a fourth data segment; the second data segment is divided into X bits according to the highest bit in step 1. The second data segment obtained;

    Step 4: Perform a shift operation on the high (M-X) bit of the third data segment based on the Q(x) to obtain a fifth data segment;

    Step 5: XOR the fourth data segment and the fifth data segment to obtain a sixth data segment;

    Step 6: replacing the first data segment and the second data segment of the second data in step 1 with the sixth data segment to form the second data, and performing steps 1 to 6 until The length of the second data is less than 2*X bits, where "*" indicates multiplication.
30. The apparatus according to any one of claims 25-27, wherein said one or more first source polynomials comprise first source polynomials Q1(x) and Q2(x), wherein Q1(x) is valid The index of the highest item is greater than the index of the highest item valid for Q2(x); the processor is specifically used to:

    Processing the second data based on Q1(x) to obtain fourth data;

    The fourth data is processed based on Q2(x) to obtain the third data.
31. The device according to claim 30, wherein the processor is specifically configured to:

    Step 1: dividing the second data from the highest bit and dividing the data segment by the exponent bit size of the highest item valid by Q1(x);

    Step 2: Perform a shift operation on the first data segment of the second data based on the Q1 (x), and XOR the data segment obtained by the shift operation to obtain a third data segment; the first data segment is The first data segment obtained from the highest bit of the second data in the step 1;

    Step 3: XOR the third data segment and the second data segment to obtain a fourth data segment; the second data segment is the highest item in the step 1 that is valid from the highest bit and is valid with Q1(x) The second data segment obtained by dividing the index bit size;

    Step 4: replacing the first data segment and the second data segment of the second data in step 1 with the fourth data segment to form the second data, and performing steps 1 to 4 until The length of the second data is less than 2 times the exponent bit of the highest term in which Q1(x) is valid.
32. The device according to claim 30, wherein the processor is specifically configured to:

    Step 21: Divide the fourth data from the highest bit to divide the data segment by the exponent bit size of the highest item valid by Q2(x);

    Step 22: Perform a shift operation on the first data segment of the fourth data based on the Q2 (x), and XOR the data segment obtained by the shift operation to obtain a fifth data segment; a data segment is the first data segment obtained from the highest bit of the fourth data in the step 21;

    Step 23: XORing the fifth data segment and the second data segment of the fourth data to obtain a sixth data segment; the second data segment of the fourth data is from the The second data segment obtained by dividing the highest bit of the fourth data;

    Step 24: replacing the first data segment and the second data segment of the fourth data in step 21 with the sixth data segment to form the fourth data, and performing steps 21 to 24 until the fourth data The length is less than 2 times the length of the exponent bit of the highest term valid for Q2(x).
33. The apparatus according to claim 30, wherein said processor is specifically configured to: step 21: divide said fourth data from a highest bit by a K bit size; wherein K indicates that Q2(x) is valid The highest index of the item;

    Step 22: Perform a shift operation on the first data segment of the fourth data based on the Q2 (x), and XOR the data segment obtained by the shift operation to obtain a fifth data segment; a data segment is the first data segment obtained from the highest bit of the fourth data in the step 21;

    Step 23: XOR the lower K bit of the fifth data segment and the second data segment of the fourth data to obtain a sixth data segment; the second data segment of the fourth data is the a second data segment obtained by dividing a highest bit of the fourth data; the length of the fifth data segment is M bits;

    Step 24: Perform a shift operation on the high (M-K) bit of the fifth data segment based on the Q (2x) to obtain a seventh data segment;

    Step 25: XOR the sixth data segment and the seventh data segment to obtain an eighth data segment;

    Step 26: replacing the first data segment and the second data segment of the fourth data in step 21 with the eighth data segment to form the fourth data, and performing steps 22 to 26 until the fourth data The length of the segment is less than 2*K, where "*" indicates multiplication.
34. The device according to any one of claims 25-33, wherein the processor is specifically configured to:

    Dividing the third data by the second source polynomial yields an N-bit remainder as the N-bit CRC encoding of the first data.
35. The device according to any one of claims 25-34, wherein the processor is further configured to:

    And storing the first data and the N-bit CRC code.
36. The device according to any one of claims 25-34, wherein the processor is further configured to:

    Transmitting the first data and the N-bit CRC code.
37. A computer program product, comprising: computer program product, the processor executing the computer instruction for:

    Obtain the first data;

    Transmitting the first data to the left by N bits to obtain second data, where N is a cyclic redundancy check CRC coded number of bits;

    Processing the second data based on one or more first source polynomials to obtain third data;

    Processing the third data based on the second native polynomial to obtain an N-bit CRC encoding of the first data; wherein an index X of a highest term of each of the one or more first native polynomials valid for the first native polynomial The difference from the index Y of the effective next highest item is greater than 1; the length of the third data is less than the length of the second data; X and Y are positive integers, and X is greater than Y; the one or more first sources Each of the polynomials is a multiple of the second native polynomial, an exponent X of the highest term of each of the one or more first native polynomials valid for the first native polynomial being greater than the validity of the second native polynomial The highest index of the index R.
38. The computer program product of claim 37, wherein the number of items valid for each of the one or more first source polynomials is less than the number of items valid for the second source polynomial.
39. A computer program product according to claim 37 or claim 38, wherein said first source polynomial is a least significant multiple of the number of terms in the multiple of said second native polynomial.
40. A computer program product according to any of claims 37-39, wherein said processor executes said computer program product specifically for:

    Step 1: dividing the second data from the highest bit and dividing the data segment by the X bit size;

    Step 2: Perform a shift operation on the first data segment of the second data based on the first source polynomial, and XOR the data segment obtained by the shift operation to obtain a third data segment; the first data segment is The first data segment obtained from the highest bit of the second data in the step 1;

    Step 3: XOR the third data segment and the second data segment to obtain a fourth data segment; the second data segment is the second one obtained by dividing the X-bit size from the highest bit in step 1. Data segment

    Step 4: replacing the first data segment and the second data segment of the second data in step 1 with the fourth data segment to form the second data, and performing steps 1 to 4 until The length of the second data is less than 2*X bits, where "*" indicates multiplication.
41. A computer program product according to any of claims 37-39, wherein said processor executes said computer program product specifically for:

    Step 1: dividing the second data from the highest bit and dividing the data segment by the X bit size;

    Step 2: Perform a shift operation on the first data segment of the second data based on the first source polynomial, and XOR the data segment obtained by the shift operation to obtain a third data segment; the first data segment is a first data segment obtained from the highest bit of the second data in the step 1; wherein the length of the third data segment is M bits;

    Step 3: XORing the lower X bits of the third data segment with the second data segment to obtain a fourth data segment; the second data segment is divided into X bits according to the highest bit in step 1. The second data segment obtained;

    Step 4: Perform a shift operation on the high (M-X) bit of the third data segment based on the Q(x) to obtain a fifth data segment;

    Step 5: XOR the fourth data segment and the fifth data segment to obtain a sixth data segment;

    Step 6: replacing the first data segment and the second data segment of the second data in step 1 with the sixth data segment to form the second data, and performing steps 1 to 6 until The length of the second data is less than 2*X bits, where "*" indicates multiplication.
42. A computer program product according to any of claims 37-39, wherein said one or more first source polynomials comprise first source polynomials Q1(x) and Q2(x), wherein Q1(x) The index of the valid highest item is greater than the index of the highest item valid for Q2(x); the processor executes the computer program product specifically for:

    Processing the second data based on Q1(x) to obtain fourth data;

    The fourth data is processed based on Q2(x) to obtain the third data.
43. The computer program product of claim 42, wherein the processor executes the computer program product specifically for:

    Step 1: dividing the second data from the highest bit and dividing the data segment by the exponent bit size of the highest item valid by Q1(x);

    Step 2: Perform a shift operation on the first data segment of the second data based on the Q1 (x), and XOR the data segment obtained by the shift operation to obtain a third data segment; the first data segment is The first data segment obtained from the highest bit of the second data in the step 1;

    Step 3: XOR the third data segment and the second data segment to obtain a fourth data segment; the second data segment is the highest item in the step 1 that is valid from the highest bit and is valid with Q1(x) The second data segment obtained by dividing the index bit size;

    Step 4: replacing the first data segment and the second data segment of the second data in step 1 with the fourth data segment to form the second data, and performing steps 1 to 4 until The length of the second data is less than 2 times the exponent bit of the highest term in which Q1(x) is valid.
44. The computer program product of claim 42, wherein the processor executes the computer program product specifically for:

    Step 21: Divide the fourth data from the highest bit to divide the data segment by the exponent bit size of the highest item valid by Q2(x);

    Step 22: Perform a shift operation on the first data segment of the fourth data based on the Q2 (x), and XOR the data segment obtained by the shift operation to obtain a fifth data segment; a data segment is the first data segment obtained from the highest bit of the fourth data in the step 21;

    Step 23: XORing the fifth data segment and the second data segment of the fourth data to obtain a sixth data segment; the second data segment of the fourth data is from the The second data segment obtained by dividing the highest bit of the fourth data;

    Step 24: replacing the first data segment and the second data segment of the fourth data in step 21 with the sixth data segment to form the fourth data, and performing steps 21 to 24 until the fourth data The length is less than 2 times the length of the exponent bit of the highest term valid for Q2(x).
45. The computer program product of claim 42, wherein the processor executes the computer program product specifically for:

    Step 21: Divide the fourth data from the highest bit to divide the data segment by the K bit size; wherein K represents an index of the highest item valid for Q2(x);

    Step 22: Perform a shift operation on the first data segment of the fourth data based on the Q2 (x), and XOR the data segment obtained by the shift operation to obtain a fifth data segment; a data segment is the first data segment obtained from the highest bit of the fourth data in the step 21;

    Step 23: XOR the lower R bit of the fifth data segment and the second data segment of the fourth data to obtain a sixth data segment; the second data segment of the fourth data is the a second data segment obtained by dividing a highest bit of the fourth data; the length of the fifth data segment is M bits;

    Step 24: Perform a shift operation on the high (M-K) bit of the fifth data segment based on the Q (2x) to obtain a seventh data segment;

    Step 25: XOR the sixth data segment and the seventh data segment to obtain an eighth data segment;

    Step 26: replacing the first data segment and the second data segment of the fourth data in step 21 with the eighth data segment to form the fourth data, and performing steps 22 to 26 until the fourth data The length of the segment is less than 2*K, where "*" indicates multiplication.
46. A computer program product according to any of claims 37-45, wherein said processor executes said computer program product specifically for:

    Dividing the third data by the second source polynomial yields an N-bit remainder as the N-bit CRC encoding of the first data.
47. A computer program product according to any of claims 37-46, wherein said processor executing said computer instructions is further for:

    And storing the first data and the N-bit CRC code.
48. A computer program product according to any of claims 37-46, wherein said processor executing said computer instructions is further for:

    Transmitting the first data and the N-bit CRC code.

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