CN105790773A - Novel 10 gigabit Ethernet parallel CRC encoding and decoding method - Google Patents
Novel 10 gigabit Ethernet parallel CRC encoding and decoding method Download PDFInfo
- Publication number
- CN105790773A CN105790773A CN201610218491.6A CN201610218491A CN105790773A CN 105790773 A CN105790773 A CN 105790773A CN 201610218491 A CN201610218491 A CN 201610218491A CN 105790773 A CN105790773 A CN 105790773A
- Authority
- CN
- China
- Prior art keywords
- data
- crc
- byte
- input
- frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
Landscapes
- Physics & Mathematics (AREA)
- Probability & Statistics with Applications (AREA)
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Error Detection And Correction (AREA)
Abstract
The present invention provides a novel 10 gigabit Ethernet parallel CRC encoding and decoding method. Compared with a traditional 10 gigabit Ethernet parallel CRC encoder and decoder which cannot combine calculation speed and occupancy of resources, the novel 10 gigabit Ethernet parallel CRC encoding and decoding method is able to simply solve the problem of the CRC encoding caused by variable-length bytes through encoding preprocessing at encoding so as to simplify the design of a CRC encoding circuit, and separate the FCS region of an Ethernet frame through decoding preprocessing and recover the data output by an encoding preprocessing module at decoding so as to simplify the design of the CRC verification circuit. The CRC encoder and decoder are compatible to the current method through switching work modes, speed up the calculation through the designed work modes, and are small in calculation circuit time relay and small in consume resources so as to be compatible to the calculation speed and the occupancy of resources.
Description
Technical field
The present invention relates to the quick braiding decoding technique field of ethernet communication, particularly to a kind of ten thousand novel mbit ethernet Parallel CRC coding and decoding methods.
Background technology
Ethernet is the most general communication protocol standard that current existing LAN adopts, and needs the Error Control using CRC (CyclicRedundancyCheck, CRC) to realize data in ethernet communication.The internal data width that ten thousand mbit ethernets adopt is up to 64bit, all much bigger compared to internal data width 8bit or 4bit of gigabit and following bandwidth Ethernet.
Ten thousand traditional mbit ethernet Parallel CRC coders mainly have following 3 kinds of methods to realize: 1, cross-current water law, the method uses 8 CRC-32 circuit and 64 CRC-32 circuit that data are carried out pipeline computing respectively, the data meeting 64 alignment are used the CRC-32 circuit of 64 parallel-by-bit inputs, the data being unsatisfactory for 64 alignment are used 8 CRC-32 circuit.2, cascade structure method, the CRC-32 circuit that the method constitutes 64 parallel-by-bits inputs by the CRC-32 circuit that cascade 8 parallel-by-bit inputs realizes the CRC to data and calculates.3, repeating CRC logic method, the method one has the CRC-32 module of 8 different input bit wides, calculates by selecting in these 8 CRC-32 modules to realize the CRC to data effective bit wide of input data.But, above-mentioned three kinds of methods all can not take into account calculating speed and resource occupation simultaneously, and the flowing water that intersects sends out maximum possible the output time delay of 7 clock cycle, and the computing circuit time delay of cascade structure method is very big, and it is many that repetition CRC logic method takies logical resource.
In view of variety of problems of the prior art, a kind of computing circuit by less resource occupation and relatively low delay is urgently proposed at present, can quickly calculate simultaneously crc value and can be compatible with existing Ethernet ten thousand mbit ethernet CRC coding and decoding methods.
Summary of the invention
It is an object of the invention to the shortcoming overcoming prior art with not enough, a kind of ten thousand novel mbit ethernet Parallel CRC coding and decoding methods are provided, the method, based on the generation of fast parallel CRC and verification, has the advantages that resource occupation is few, computing circuit gate delay is low, can quickly export in real time.
The purpose of the present invention is achieved through the following technical solutions:
A kind of ten thousand novel mbit ethernet Parallel CRC coding and decoding methods, including CRC coded method and CRC interpretation method:
(1) CRC encoder coding modes selects step as follows:
S1, CRC encoder starts to input the initial data that a frame is new；
S2, before the crc value calculating the new initial data of a frame, it is judged that whether receiving terminal did not verify the data that a frame is complete；
If so, step S4 is entered；
If it is not, enter step S3；
S3, judge whether CRC decoder correctly verified at least one frame data；
If so, the pattern then making CRC encoder is corresponding with the pattern of CRC decoder.Namely CRC decoder uses decoding mode 1 to verify correctly, then CRC encoder uses and be locked as coding mode 1, if CRC decoder uses decoding mode 2 to verify correctly, then CRC encoder uses and be locked as coding mode 2；
If it is not, enter step S4；
S4, use coding mode 2 are calculated return step S1 after the crc value of previous frame data.
Further, in described step S1, input the initial data that a frame is new, refer to the starting position needing to be calculated the crc value of frame data, be i.e. destination address in a frame Ethernet data.
Further, in described step S3, the step of coding mode 1 is as follows:
S3-1-1, judge whether physical layer auto negotiation result is 10G；
If so, step S3-1-2 is entered；
If it is not, namely physical layer auto negotiation result is 10/100/1000M, then interior data width is 4 or 8, enters step S3-1-4；
S3-1-2, judging that 8 data input channel are whether all effective, namely whether data 64 are effective；
If so, then adopt 64 parallel-by-bit CRC-32 to calculate, enter step S3-1-3；
If it is not, enter step S3-1-5；
S3-1-3, judged whether these frame data crc value calculate；
If so, step S3-1-6 is entered；
If it is not, return step S3-1-2；
S3-1-4, adopt 8 parallel-by-bits input CRC-32 to calculate the crc value of present input datas, then judge that the data being currently entered whether this frame finally needs to calculate the data of crc value；
If so, step S3-1-6 is entered；
If it is not, continue executing with step S3-1-4；
S3-1-5, adopt 8 parallel-by-bits input CRC-32 calculate present input datas crc value, calculated after enter step S3-1-6；
S3-1-6, output crc value；
Further, in described step S3-1-5, present input data refers in the data of input it may is 8,16,24,32,40,48,56 valid data, and when using 8 parallel-by-bit input CRC-32 to calculate CRC, output result there will be corresponding 1,2,3,4,5,6,7 clock cycle time delays.
Further, in described step S3, the step of coding mode 2 is as follows:
S3-2-1, judge that current 8 data input channel are whether all effective, namely whether input data 64 effective；
If so, step S3-2-2 is entered；
If it is not, non-64 bit data of input are carried out zero padding pretreatment by coding pretreatment module to become 64 bit data, subsequently into step S3-2-2；
Whether this frame finally needs to calculate the data of crc value to the data that S3-2-2, judgement are currently entered；
If so, crc value is exported；
If it is not, the CRC continuing next group data calculates, return step S3-2-1；
Further, in described step S3-2-1, its preprocessing process is as shown in Figure 7, the data inputted each time are all 8 data channel, i.e. 8 byte datas, and being located in the input of last data, only N byte data are effective, value possible for N is the random integers of 1≤N≤8, coding pretreatment module makes the data of N byte be output as 8 bytes by filling " 0 " at data end, and does not deal with during N=8, it is known that 8 byte datas finally exported have 8-N byte " 0 ".Being now 8 byte-aligned owing to encoding pretreated data, therefore CRC encoder only needs the CRC-32 circuit that 64 bit data input parallel.
(2) CRC decoder for decoding mode selecting step is as follows:
R1, CRC decoder starts to input the data that a frame is new；
R2, CRC decoder uses checking mode 2, it is judged that whether correctly verify these frame data under current checking mode；
If so, then locking CRC decoder is checking mode 2, enters step R4；
If it is not, conversion checking mode, enter step R3；
R3, CRC decoder uses checking mode 1, it is judged that whether correctly verify these frame data under current checking mode；
If so, then locking CRC decoder is checking mode 1, enters step R4；
If it is not, use checking mode 1 or the equal check errors of checking mode 2, the error in data received is described, check errors mark is put 1；
R4, output verification complete and check errors mark；
Further, in described step R2, the step of checking mode 2 is as follows:
R2-1-1, carry out decoding pretreatment operation, be first easily separated operation, from the frame data being currently received, remove PRE territory and the SFD territory of ethernet frame, remaining data are isolated FCS territory, data are divided into non-FCS territory and FCS territory two parts；Then operation it is filled with, the data making the non-FCS territory part after filling in " 0 " of the data minimum byte of filling of non-FCS territory part are 8 byte-aligned, and the data that FCS territory is owing to being 4 bytes, then filling " 0 " of 4 bytes after FCS territory makes the data of the FCS territory part after filling be 8 bytes, now filling two parts data after " 0 " is all 8 byte-aligned, enters step R2-1-2；
R2-1-2, adopt 64 bit data to input CRC-32 parallel to verify, enter step R2-1-3；
R2-1-3, judge pretreated data whether complete verification；
If so, CRC check result is then exported；
If it is not, continue executing with step R2-1-2；
Further, in described step R2-1-1, in decoding pretreatment operation, FCS territory is isolated from the data behind removing ethernet frame PRE territory and SFD territory, and the position according to FCS territory can be divided into 3 class situations to process: (1) FCS territory is present in the 8+K byte data finally received, as shown in Figure 8, if finally receiving the byte number K=1 of data, 2, 3, now FCS territory is not only present in last received K byte data, some is present in 8 byte datas that penultimate receives, it is thus desirable to the 8+K byte data in the end received is separately separated out the FCS territory of 4 bytes, then two 8 byte datas of " 0 " composition are filled respectively.(2) FCS territory is precisely the K byte data finally received, as shown in Figure 9, if finally receiving the byte number K=4 of data, now FCS territory is exactly the K byte data received for the last time, and only these data need to be filled 4 bytes " 0 " forms 8 byte datas.(3) FCS territory exists only in the K byte data finally received, as shown in Figure 10, if finally receiving byte number K=5,6,7,8 of data, now FCS territory exists only in the K byte data finally received, and this K byte data also has the part in non-FCS territory, therefore going out non-FCS territory and FCS territory from this data separating, size is K-4 byte and 4 bytes respectively, then fills two 8 byte datas of " 0 " composition respectively.
Further, in described step R3, the step of checking mode 1 is as follows:
R3-1-1,64 effectively to judge the data of input；
If so, step R3-1-2 is entered；
If it is not, the data of this input i.e. must be the decline of these frame data, data are mended " 0 " pretreatment and are become 64 bit data, enter step R3-1-2；
R3-1-2, adopt 64 bit data to input CRC-32 circuit checks data parallel after, it is judged that whether these frame data complete；
If so, output CRC check result；
If it is not, return step R3-1-1.
The present invention has such advantages as relative to prior art and effect:
1) the ten thousand a kind of novel mbit ethernet Parallel CRC coding and decoding methods that the present invention proposes, the method, based on the generation of fast parallel CRC and verification, has that resource occupation is few, computing circuit gate delay is low, it is fast to calculate speed, can realize real-time output.
2) present invention proposes a kind of ten thousand mbit ethernets based on coding checkout model selection and inputs CRC coding and decoding method parallel, during coding, simply solves, by encoding pretreatment, the CRC encoded question that random length byte is brought, simplifies the design of CRC coding circuit；During decoding, isolate the FCS territory of ethernet frame by decoding pretreatment, and recover the data that coding pretreatment module exports, simplify the design of CRC check circuit.
3) this CRC coder allows hand over the next compatible existing method of mode of operation, and the mode of operation designed by the present invention makes to calculate speed, and computing circuit time delay is less, takies resource less, therefore can take into account calculating speed simultaneously and take resource.
Accompanying drawing explanation
Fig. 1 is that CRC encoder coding modes selects flow chart；
Fig. 2 is the coding flow chart of CRC coding mode 1；
Fig. 3 is the coding flow chart of CRC coding mode 2；
Fig. 4 is CRC decoder for decoding model selection flow chart；
Fig. 5 is the decoding flow chart of CRC decoding mode 2；
Fig. 6 is the decoding flow chart of CRC decoding mode 1；
Fig. 7 is for sending process of data preprocessing schematic diagram；
Process of data preprocessing schematic diagram is received when Fig. 8 is K=1,2,3；
Process of data preprocessing schematic diagram is received when Fig. 9 is K=4；
Process of data preprocessing schematic diagram is received when Figure 10 is K=5,6,7,8.
Detailed description of the invention
For making the purpose of the present invention, technical scheme and advantage clearly, clearly, developing simultaneously referring to accompanying drawing, the present invention is described in more detail for embodiment.Should be appreciated that specific embodiment described herein is only in order to explain the present invention, is not intended to limit the present invention.
Embodiment
Present embodiment discloses a kind of CRC coding and decoding workflow under ten thousand mbit ethernet bandwidth.
Referring to Fig. 1, Fig. 1 is that in the present embodiment, a kind of ten thousand mbit ethernet CRC coding modes select flow chart.As it is shown in figure 1, the selection of this CRC coding mode can select different coding modes according to different decoding results, one has CRC coding mode two kinds different: CRC coding mode 1 and CRC coding mode 2.Wherein the flow process of CRC coding mode 1 is as in figure 2 it is shown, this coding mode is broadly divided into two encoders, encoder that 8 bit data input parallel and the encoder that 64 bit data input parallel, selects corresponding encoder according to the significance bit of input data.Wherein the flow process of CRC coding mode 2 is as it is shown on figure 3, this coding mode mainly has two flow processs, preprocessing process and cataloged procedure before coding.
In the present embodiment, in order to highlight the emphasis of the present invention, it is assumed that the data of input be sized to 8M+N byte, wherein M is positive integer, the random integers of 1≤N≤8, in order to advantages of the present invention is described, the present embodiment sets N=4, and namely needing the data length calculating crc value is 8M+4 byte.Concrete coding flow process is as follows:
S1, CRC encoder starts to input the initial data that a frame is new, and these data input according to 8 byte parallels, and each clock cycle inputs once, and total 8M+N byte data in the present embodiment, it is therefore desirable to M+1 clock cycle could input；
S2, calculate these data crc value before, first determine whether whether receiving terminal did not verify the data that a frame is complete；
If so, step S4 is entered；
If it is not, enter step S3；
S3, judging whether CRC decoder correctly verified at least one frame data, namely whether CRC decoder verified data before CRC encodes these data；
If so, the pattern then making CRC encoder is corresponding with the pattern of CRC decoder.Namely CRC decoder uses decoding mode 1 to verify correctly, then CRC encoder uses and be locked as coding mode 1, if CRC decoder uses decoding mode 2 to verify correctly, then CRC encoder uses and be locked as coding mode 2；
If it is not, enter step S4；
S4, use coding mode 2 are calculated return step S1 after the crc value of previous frame data；
The coding flow chart of the coding mode 1 in described step S3 is as in figure 2 it is shown, specifically comprise the following steps that
S3-1-1, judge whether physical layer auto negotiation result is 10G；
If so, step S3-1-2 is entered；
If it is not, namely physical layer auto negotiation result is 10/100/1000M, then interior data width is 4 or 8, enters step S3-1-4；
S3-1-2, judging that 8 data input channel are whether all effective, namely whether data 64 are effective；
If so, then adopt 64 bit data to input parallel and calculate crc value, in the present embodiment, have 8M byte data to be inputted parallel by 64 bit data and calculate crc value, subsequently enter step S3-1-3；
If it is not, enter step S3-1-5；
S3-1-3, judged whether these frame data crc value calculate；
If so, step S3-1-6 is entered；
If it is not, return step S3-1-2；
S3-1-4, adopting 8 parallel-by-bits input CRC-32 to calculate the crc value of present input datas, the data namely inputted all use 8 bit data to input calculating crc value parallel, then the clock periodicity that calculating crc value needs is 8M+N.And be judged as the data that are currently entered whether this frame after often having calculated 1 byte data and finally need to calculate the data of crc value；
If so, step S3-1-6 is entered；
If it is not, continue executing with step S3-1-4；
S3-1-5, adopt 8 parallel-by-bits input CRC-32 calculate present input datas crc value.Present input data refers in the data of input it may is 8,16,24,32,40,48,56 valid data, and when using 8 parallel-by-bit input CRC-32 to calculate CRC, output result there will be corresponding 1,2,3,4,5,6,7 clock cycle time delays.In the present embodiment, what now calculate is last N byte data, and completing this calculating needs N number of clock cycle time delay, enters step S3-1-6 after having calculated；
S3-1-6, output crc value；
The coding flow chart of the coding mode 2 in described step S3 is as it is shown on figure 3, specifically comprise the following steps that
S3-2-1, input data and judge that current 8 data input channel are whether all effective, namely whether inputting data 64 effective.In the present embodiment, it is effective that the front 8M byte of input is 64 bit data, and the N byte recently entered is that 4 byte datas are effective；
If so, step S3-2-2 is entered；
If it is not, non-64 bit data of input are carried out zero padding pretreatment by coding preprocessing process to become 64 bit data.In the present embodiment, front 8M byte data is made without operation, and 8-N byte data is required supplementation with for last N byte data, after N byte data, namely add 4 bytes " 0 " data again make 8 byte datas.What obtain after the encoded pretreatment of data of input is all 8 bytes, and the data therefore finally entering CRC encoder are 8 byte-aligned, are so conducive to the design of CRC encoder.Subsequently into step S3-2-2；
S3-2-2, use 64 bit data to input parallel to carry out CRC coding, then judge whether the data being currently entered are the data finally needing to calculate crc value；
If so, exporting crc value, CRC calculates and terminates；
If it is not, return step S3-2-1；
Referring to Fig. 4, Fig. 4 is that in the present embodiment, a kind of ten thousand mbit ethernet CRC decoder checking modes select flow chart.As shown in Figure 4, the selection of this CRC check pattern can select different checking modes according to the correctness of check results, including two kinds of CRC check patterns: CRC check pattern 1 and CRC check pattern 2.The flow process of wherein CRC check pattern 1 is as it is shown in figure 5, the CRC decoder that this checking mode is mainly inputted parallel by 64 bit data forms.As shown in Figure 6, this checking mode mainly has two flow processs to the flow process of wherein CRC check pattern 2, preprocessing process and checking procedure before data check.
In the present embodiment, in order to the emphasis of the present invention is described, and be mapped with CRC coding module, again owing to crc value is 4 byte-sized, then set the size of data that is input to CRC decoder as 8 (M+1) byte, the wherein last FCS territory that 4 bytes are ethernet frame, the i.e. radix-minus-one complement of the crc value of CRC encoder output.Wherein the setup parameter of M and N and CRC encoder is the same.Concrete decoding flow process is as follows:
R1, CRC decoder starts to input the data that a frame is new；
R2, CRC decoder is first by checking mode 2, it is judged that whether correctly verify these frame data under current checking mode；
If so, then locking CRC decoder is checking mode 2, enters step R4；
If it is not, conversion checking mode, enter step R3；
R3, CRC decoder uses checking mode 1 to carry out checking data, and judges whether correctly verify these frame data under current checking mode；
If so, then locking CRC decoder is checking mode 1, enters step R4；
If it is not, use checking mode 1 or the equal check errors of checking mode 2, the error in data received is described, check errors mark is put 1；
R4, output verification complete and check errors mark, terminate；
The checking process figure of the checking mode 2 in described step R2 is as it is shown in figure 5, specifically comprise the following steps that
R2-1-1, first carry out preprocessing process before data check, the Frame of input is easily separated operation, PRE territory and the SFD territory of ethernet frame is removed from the frame data being currently received, remaining 8 (M+1) byte after performing this operation in the present embodiment, then in remaining 8 (M+1) byte data, isolate the FCS territory of 4 bytes, data are divided into the non-FCS territory of 8M+N byte and FCS territory two parts of 4 bytes；Then respectively non-FCS territory and FCS territory are filled with operation, data in non-FCS territory part are filled " 0 " of minimum byte and are made the data of non-FCS territory part after filling be 8 byte-aligned, the non-FCS territory after namely filling be sized to 8 (M+1) byte；And the data that FCS territory is owing to being 4 bytes, then filling " 0 " of 4 bytes after FCS territory makes the data of the FCS territory part after filling be 8 bytes, namely the FCS territory after blank map be sized to 8 bytes.Preprocessing process before data above verifies, the size of data obtaining output is 8 (M+2) byte, and the data after filling are 8 byte-aligned, subsequently into step R2-1-2；
R2-1-2, adopting 64 bit data to input CRC-32 parallel to verify, be 64 for alignment owing to the data in R2-1-1 export, therefore 64 bit data are only inputted effectively by this step parallel, subsequently into step R2-1-3；
R2-1-3, judge pretreated data whether complete verification；
If so, then output CRC check result, end；
If it is not, continue executing with step R2-1-2；
The checking process figure of the checking mode 1 in described step R2 as shown in Figure 6, specifically comprises the following steps that
R3-1-1, judge the data of input whether 64 effectively, in the present embodiment, input is the data of 64 alignment；
If so, step R3-1-2 is entered；
If it is not, the data of this input i.e. must be the decline of these frame data, data are mended " 0 " pretreatment and are become 64 bit data, enter step R3-1-2；
R3-1-2, adopt 64 bit data to input CRC-32 circuit checks data parallel after, it is judged that whether these frame data complete；
If so, output CRC check result；
If it is not, return step R3-1-1；
It should be noted that in above-mentioned CRC coder embodiment, the size of data of input simply illustrates the process that realizes of the present invention according to some particular case, but is not limited to the size of data.
The result that the present invention realizes obtaining after comprehensively can be taken into account less logical resource compared with other technologies scheme simultaneously and calculate speed faster, meets the eyeball of real-time output.
After the design of the present invention is comprehensive compared with other schemes, the logical block taken is as shown in table 1.Context of methods is compared to repeating CRC logic method, and on logical block LE takies, encoder and decoder decrease 43.1% and 52.5% respectively, always take LE and decrease 47.8%, nearly half.Context of methods is compared to cross-current water law and cascade structure method, and logical block makes to account for and is more or less the same.
The design of the present invention is compared with other schemes, and it is more as shown in table 2 that CRC module calculates velocity ratio.The present invention and repetition CRC logic method and cascade structure method can realize next clock cycle output crc value, and cross-current water law can bring the time delay of maximum 7 clock cycle, is primarily due to what the input of random length byte caused.On the gate delay of computing circuit, context of methods is all 6 grades of XOR gate time delays with repetition CRC logic method and cross-current water law, input parallel calculate crc value because these three method all realizes 64 bit data by recurrence method, now maximum in XOR gate computing circuit computing items is 52 inputs, and the total gate delay of computing circuit is 6 grades of XOR gate time delays.And cascade structure method is to realize 8 bit data by recurrence method to input first order calculation crc value parallel, then pass through 8 grades of cascades to realize 64 bit data and input calculating crc value parallel, in the XOR gate computing circuit of every one-level, maximum computing items are 14 inputs, one-level computing circuit gate delay is 4 grades of XOR gate time delays, the gate delay that after 8 grades of cascades, computing circuit is total is 8 times of one-level computing circuit gate delay, i.e. 32 grades of XOR gate time delays.Compared with the 6 of this programme grades of XOR gate time delays, time delay is bigger.
By above resource occupation with calculate that velocity contrast is analysis integrated obtains, it is many that repetition CRC logic method takies resource, cross-current water law has output time delay, cascade structure method computing circuit gate delay is big, and resource that context of methods does not only take up is few, and key operation gate time delay is little, calculate speed fast, real-time output can be realized.
Table 1CRC module logic resource occupation results contrast
| Method | The LE that encoder takies | The LE that decoder takies | The LE always taken |
| Repeat CRC logic method | 1311 | 1322 | 2633 |
| Cross-current water law | 583 | 597 | 1180 |
| Cascade structure method | 684 | 695 | 1379 |
| Context of methods | 746 | 628 | 1374 |
Table 2CRC module calculates velocity ratio relatively
It should be noted that in said system embodiment, each included device and unit are carry out dividing according to function logic, but are not limited to above-mentioned division, as long as being capable of corresponding function；It addition, the concrete title of each device and unit is also only to facilitate mutually distinguish, it is not limited to protection scope of the present invention.
Above-described embodiment is the present invention preferably embodiment; but embodiments of the present invention are also not restricted to the described embodiments; the change made under other any spirit without departing from the present invention and principle, modification, replacement, combination, simplification; all should be the substitute mode of equivalence, be included within protection scope of the present invention.
Claims (9)
1. ten thousand novel mbit ethernet Parallel CRC coding and decoding methods, including CRC coded method and CRC interpretation method, it is characterised in that
Described CRC encoder coded method comprises the steps:
S1, CRC encoder starts to input the initial data that a frame is new；
S2, before the crc value calculating the new initial data of a frame, it is judged that whether receiving terminal did not verify the data that a frame is complete；
If so, step S4 is entered；
If it is not, enter step S3；
S3, judge whether CRC decoder correctly verified at least one frame data；
If so, the pattern then making CRC encoder is corresponding with the pattern of CRC decoder.Namely CRC decoder uses decoding mode 1 to verify correctly, then CRC encoder uses and be locked as coding mode 1, if CRC decoder uses decoding mode 2 to verify correctly, then CRC encoder uses and be locked as coding mode 2；
If it is not, enter step S4；
S4, use coding mode 2 are calculated return step S1 after the crc value of previous frame data.
Described CRC decoder for decoding method comprises the steps:
R1, CRC decoder starts to input the data that a frame is new；
R2, CRC decoder uses checking mode 2, it is judged that whether correctly verify these frame data under current checking mode；
If so, then locking CRC decoder is checking mode 2, enters step R4；
If it is not, conversion checking mode, enter step R3；
R3, CRC decoder uses checking mode 1, it is judged that whether correctly verify these frame data under current checking mode；
If so, then locking CRC decoder is checking mode 1, enters step R4；
If it is not, use checking mode 1 or the equal check errors of checking mode 2, the error in data received is described, check errors mark is put 1；
R4, output verification complete and check errors mark.
2. a kind of ten thousand novel mbit ethernet Parallel CRC coding and decoding methods according to claim 1, it is characterised in that
In described step S3, the step of coding mode 1 is as follows:
S3-1-1, judge whether physical layer auto negotiation result is 10G；
If so, step S3-1-2 is entered；
If it is not, namely physical layer auto negotiation result is 10/100/1000M, then interior data width is 4 or 8, enters step S3-1-4；
S3-1-2, judging that 8 data input channel are whether all effective, namely whether data 64 are effective；
If so, then adopt 64 parallel-by-bit CRC-32 to calculate, enter step S3-1-3；
If it is not, enter step S3-1-5；
S3-1-3, judged whether these frame data crc value calculate；
If so, step S3-1-6 is entered；
If it is not, return step S3-1-2；
S3-1-4, adopt 8 parallel-by-bits input CRC-32 to calculate the crc value of present input datas, then judge that the data being currently entered whether this frame finally needs to calculate the data of crc value；
If so, step S3-1-6 is entered；
If it is not, continue executing with step S3-1-4；
S3-1-5, adopt 8 parallel-by-bits input CRC-32 calculate present input datas crc value, calculated after enter step S3-1-6；
S3-1-6, output crc value.
3. a kind of ten thousand novel mbit ethernet Parallel CRC coding and decoding methods according to claim 2, it is characterised in that
Present input data in described step S3-1-5 refers in the data of input it is 8,16,24,32,40,48 or 56 valid data, and when using 8 parallel-by-bit input CRC-32 to calculate CRC, output result there will be corresponding 1,2,3,4,5,6,7 clock cycle time delays.
4. a kind of ten thousand novel mbit ethernet Parallel CRC coding and decoding methods according to claim 1, it is characterised in that
In described step S3, the step of coding mode 2 is as follows:
S3-2-1, judge that current 8 data input channel are whether all effective, namely whether input data 64 effective；
If so, step S3-2-2 is entered；
If it is not, non-64 bit data of input are carried out zero padding pretreatment by coding pretreatment module to become 64 bit data, subsequently into step S3-2-2；
Whether this frame finally needs to calculate the data of crc value to the data that S3-2-2, judgement are currently entered；
If so, crc value is exported；
If it is not, the CRC continuing next group data calculates, return step S3-2-1.
5. a kind of ten thousand novel mbit ethernet Parallel CRC coding and decoding methods according to claim 4, it is characterised in that
CRC encoder under described coding mode 2 is the CRC-32 circuit that 64 bit data input parallel.
6. a kind of ten thousand novel mbit ethernet Parallel CRC coding and decoding methods according to claim 1, it is characterised in that
The initial data inputting a frame new in described step S1 refers to the starting position needing to be calculated the crc value of frame data, i.e. destination address in a frame Ethernet data.
7. a kind of ten thousand novel mbit ethernet Parallel CRC coding and decoding methods according to claim 1, it is characterised in that
In described step R2, the step of checking mode 2 is as follows:
R2-1-1, carry out decoding pretreatment operation, be first easily separated operation, from the frame data being currently received, remove PRE territory and the SFD territory of ethernet frame, remaining data are isolated FCS territory, data are divided into non-FCS territory and FCS territory two parts；Then operation it is filled with, the data making the non-FCS territory part after filling in " 0 " of the data minimum byte of filling of non-FCS territory part are 8 byte-aligned, and the data that FCS territory is owing to being 4 bytes, then filling " 0 " of 4 bytes after FCS territory makes the data of the FCS territory part after filling be 8 bytes, now filling two parts data after " 0 " is all 8 byte-aligned, enters step R2-1-2；
R2-1-2, adopt 64 bit data to input CRC-32 parallel to verify, enter step R2-1-3；
R2-1-3, judge pretreated data whether complete verification；
If so, CRC check result is then exported；
If it is not, continue executing with step R2-1-2.
8. a kind of ten thousand novel mbit ethernet Parallel CRC coding and decoding methods according to claim 7, it is characterised in that
In decoding pretreatment operation in described step R2-1-1, from the data behind removing ethernet frame PRE territory and SFD territory, isolate FCS territory, and the position according to FCS territory can be divided into 3 class situations to process:
(1) FCS territory is present in the 8+K byte data finally received, if finally receiving byte number K=1,2,3 of data, now FCS territory is not only present in last received K byte data, some is present in 8 byte datas that penultimate receives, therefore the 8+K byte data in the end received is separately separated out the FCS territory of 4 bytes, then fills two 8 byte datas of " 0 " composition respectively；
(2) FCS territory is present in the K byte data finally received, and finally receives the byte number K=4 of data, and now FCS territory is exactly the K byte data received for the last time, these data is filled 4 bytes " 0 " and forms 8 byte datas；
(3) FCS territory is present in the K byte data finally received, and finally receive byte number K=5,6,7,8 of data, now FCS territory exists only in the K byte data finally received, and this K byte data also has the part in non-FCS territory, non-FCS territory and FCS territory is gone out from this data separating, size is K-4 byte and 4 bytes respectively, then fills two 8 byte datas of " 0 " composition respectively.
9. a kind of ten thousand novel mbit ethernet Parallel CRC coding and decoding methods according to claim 6, it is characterised in that
In described step R3, the step of checking mode 1 is as follows:
R3-1-1,64 effectively to judge the data of input；
If so, step R3-1-2 is entered；
If it is not, the data of this input i.e. must be the decline of these frame data, data are mended " 0 " pretreatment and are become 64 bit data, enter step R3-1-2；
R3-1-2, adopt 64 bit data to input CRC-32 circuit checks data parallel after, it is judged that whether these frame data complete；
If so, output CRC check result；
If it is not, return step R3-1-1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610218491.6A CN105790773A (en) | 2016-04-08 | 2016-04-08 | Novel 10 gigabit Ethernet parallel CRC encoding and decoding method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610218491.6A CN105790773A (en) | 2016-04-08 | 2016-04-08 | Novel 10 gigabit Ethernet parallel CRC encoding and decoding method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105790773A true CN105790773A (en) | 2016-07-20 |
Family
ID=56395988
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610218491.6A Pending CN105790773A (en) | 2016-04-08 | 2016-04-08 | Novel 10 gigabit Ethernet parallel CRC encoding and decoding method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105790773A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108574490A (en) * | 2018-05-08 | 2018-09-25 | 华为技术有限公司 | Calculate the method and device of cyclic redundancy check (CRC) coding |
| CN110504975A (en) * | 2019-09-29 | 2019-11-26 | 中国科学院微电子研究所 | A kind of parallel decoding method of CRC and the codec based on it |
| CN113190376A (en) * | 2021-05-10 | 2021-07-30 | 天津光电通信技术有限公司 | Method for checking FCS value of 100GE data packet |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102223228A (en) * | 2011-05-11 | 2011-10-19 | 北京航空航天大学 | Method for designing AES (Advanced Encryption Standard) encryption chip based on FPGA (Field Programmable Gate Array) and embedded encryption system |
| CN104035832A (en) * | 2013-03-04 | 2014-09-10 | 联想(北京)有限公司 | Electronic device and data verification method |
| CN104424434A (en) * | 2013-08-29 | 2015-03-18 | 腾讯科技（深圳）有限公司 | Data verification method and device |
-
2016
- 2016-04-08 CN CN201610218491.6A patent/CN105790773A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102223228A (en) * | 2011-05-11 | 2011-10-19 | 北京航空航天大学 | Method for designing AES (Advanced Encryption Standard) encryption chip based on FPGA (Field Programmable Gate Array) and embedded encryption system |
| CN104035832A (en) * | 2013-03-04 | 2014-09-10 | 联想(北京)有限公司 | Electronic device and data verification method |
| CN104424434A (en) * | 2013-08-29 | 2015-03-18 | 腾讯科技（深圳）有限公司 | Data verification method and device |
Non-Patent Citations (1)
| Title |
|---|
| 彭建辉: "10G以太网接口并行CRC校验的一种简化算法", 《微计算机信息》 * |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108574490A (en) * | 2018-05-08 | 2018-09-25 | 华为技术有限公司 | Calculate the method and device of cyclic redundancy check (CRC) coding |
| CN110504975A (en) * | 2019-09-29 | 2019-11-26 | 中国科学院微电子研究所 | A kind of parallel decoding method of CRC and the codec based on it |
| CN110504975B (en) * | 2019-09-29 | 2022-12-27 | 中国科学院微电子研究所 | CRC parallel coding and decoding method and coder-decoder based on same |
| CN113190376A (en) * | 2021-05-10 | 2021-07-30 | 天津光电通信技术有限公司 | Method for checking FCS value of 100GE data packet |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10063347B2 (en) | Signal segmentation method and CRC attachment method for reducing undetected error | |
| US9280414B2 (en) | Combination of error correction and error detection for transmitting digital data | |
| CN105790773A (en) | Novel 10 gigabit Ethernet parallel CRC encoding and decoding method | |
| CN107154836A (en) | A kind of cardiopulmonary bypass in beating heart redundancy CRC check method based on FPGA | |
| US20120229310A1 (en) | Using Bus Inversion to Reduce Simultaneous Signal Switching | |
| CN101662335A (en) | Forward error correction encoding method, forward error correction decoding method and devices thereof | |
| CN104158624A (en) | Redundancy two-out-of-two decoding control device for BTM (Balise Transmission Module) system and redundancy two-out-of-two decoding method | |
| CN103731239A (en) | Universal CRC parallel calculation component suitable for being used for vector processor and method | |
| CN105119949B (en) | Method of data synchronization and system based on multi-stage slicing difference distribution statistics | |
| WO2019001436A1 (en) | Polar code encoding method and device | |
| CN101345607A (en) | Encoding/decoding method of multidimensional crossing parallel cascade single-parity check code | |
| CN104378122B (en) | A kind of Compilation Method of variable-length Turbo code | |
| CN103986557A (en) | LTE Turbo code parallel block decoding method with low path delay | |
| US6691275B1 (en) | Encoder with vector-calculated disparity logic | |
| CN104821863A (en) | Forward stack decoding method for rateless Spinal code | |
| CN108462561A (en) | The channel decoding method and device gone here and there and combined in ultrahigh speed communication system | |
| CN103973310A (en) | Test data compression method based on xor logical operation binary classification | |
| CN107231213A (en) | Method for implementing CRC-32 algorithm in USB3.0 data packet | |
| CN102244521A (en) | Blind identification method for coding parameter of return-to-zero Turbo code | |
| CN100456857C (en) | Code element expanding method and device for use in communication system | |
| CN107196733B (en) | Modulation method and device | |
| WO2012126289A1 (en) | Method and device for adjusting line sequences in ethernet transmission | |
| CN103716657B (en) | Code rate distributing method and system for channel | |
| CN107070592A (en) | Hybrid decoding method and its Fast Ethernet network receiver | |
| CN101908943B (en) | Channel decoding method applied to time division-synchronization code division multiple access (TD-SCDMA) |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20160720 |
|
| RJ01 | Rejection of invention patent application after publication |