CN100388629C - A rapid calculation method for cyclic redundant check - Google Patents
A rapid calculation method for cyclic redundant check Download PDFInfo
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Abstract
The present invention discloses a rapid calculation method for cyclic redundant check. According to the corresponding logic structure of the current adopted CRCn generator polynomial, the relation between state update situations of each shift register used by the CRCn, and other shift registers and input bits, is obtained in advance in processing states with different input bits, and a corresponding lookup table is generated according to the relation; during the CRCn check, the output of each shift register in current states can be obtained in advance through the generated lookup table. The present invention greatly improves the processing speed of the CRC check and reduces the processing time delay of the CRC check, so the service processing capacity is improved to a certain degree; in addition, the present invention ensures the rapid calculation speed and reaches the optimum memory space / time delay configuration simultaneously.
Description
Technical field
The present invention relates to the cyclic redundancy check (CRC) technology, be meant a kind of quick calculation method of cyclic redundancy check (CRC) especially.
Background technology
Along with continuous advancement in technology, the application of various data communication more and more widely because all multifactor influences such as transmission ranges, field conditions, interference, some unpredictable mistakes take place in the communication data regular meeting between the equipment.In order to reduce the wrong influence that is brought, generally when communication, adopt the method for data check, CRC (CRC) is exactly one of important method of calibration commonly used.
CRC check provides a kind of simple effectively burst error detection method for transfer of data, applicable to a lot of aspects.CRC check adopts the multinomial coding method, and processed data block can be regarded as the binary system multinomial on n rank.Such as: suppose that binary data section to be sent is g (x), generator polynomial is m (x), the CRC check sign indicating number that then obtains is c (x), be exactly specifically, the coding method of CRC check sign indicating number be with binary data g (x) to be sent divided by generator polynomial m (x), with last remainder as the CRC check sign indicating number.This CRC coding both can be realized by software, also can realize by hardware; Both can be with simple in structure, but the bigger serial approach structure of processing delay; Also can use complex structure, but the less parallel method structure of processing delay.
At present, the CRC coding techniques is comparatively ripe, and the main implementation that adopts has following three kinds:
First kind is basic bit-level building method, may also be referred to as direct computing method, and this is the simplest CRC computational methods, is by hard-wired, and as shown in Figure 1, this method mainly realizes by linear feedback shift register (LFSR) on hardware.Shift register is driven by clock, and each clock input data shift register participates in calculating, simultaneously also directly output; After all input bits were all finished dealing with, what be left in the shift register was exactly the CRC bit, and this CRC bit is moved out on the data flow successively, has just finished the CRC coding.In actual applications, can adopt following algorithm specific implementation:
A1. define a register R and be used for depositing cyclic redundancy check (CRC) code, the length of register is generally the integral multiple of the basic unit of storage of processor, such as 8 bits, 16 bits, 32 bits or the like, and the value of register R is changed to 0;
If a2. the leftmost bit of register R equals 1, then next message bit is moved into, and register R and generator polynomial are carried out XOR; Get final product otherwise only message bit is moved into;
A3. repeating step a2 is moved into processing up to all message bit, and staying among the register R is exactly the cyclic redundancy check (CRC) code of list entries.
The used block code of this method is few, does not need store look-up tables, calculates simply, revises flexibly, and portable good, the complexity that software and hardware is realized is similar, and random length generator polynomial m (x) is suitable for.If but the data block that sends is very long, this method is just not too suitable, because this method need be pursued bit process, just once can only handle the one digit number certificate, and efficient is too low, and operand is big, can not satisfy the requirement of real-time processing, and is more inapplicable for high-speed data communication.
Second kind is the standard lookup table algorithm, and the CRC calculating of this method can be thought the remainder of the multinomial of input bit and shift register status bits formation to generator polynomial, and this method need provide CRC generation table in advance.The width of supposing register is n, and the input bit figure place is m, then in actual applications, when m＜n, can take following operating procedure:
B1. the register R that to define a width be the n bit is used for depositing cyclic redundancy check (CRC) code, the length of register is generally the integral multiple of the basic unit of storage of processor, such as 8 bits, 16 bits, 32 bits or the like, and the value of register R is changed to 0, (r promptly is set
N-1..., r
0) bit sequence is 0;
B2. the n-m bit that register R moved to right promptly obtains (r
N-1..., r
N-k-r) sequence, resulting then sequence and m input bit XOR;
B3. in look-up table, find corresponding value, with the register R sequence (r that the m bit obtains that moves to left
M-1..., r
0) XOR, just obtain new crc value;
B4. repeating step b2 and b3 are moved into processing up to all message bit, and staying among the register R is exactly the cyclic redundancy check (CRC) code of list entries.
When n=m, step b2 and step b3 have a little change:
B2 '. with m the bit and the register R XOR of input, just with the m bit and the (r that import
N-k-1..., r
0) XOR;
B3 '. find corresponding value in the look-up table the inside, just obtain new crc value.
When n＜m, can not take this algorithm.
This algorithm need provide storage 2
mThe look-up table of * n bit size, every processing m bit need be carried out and once table look-up and twice xor operation, and complexity and poor performance were few when software and hardware was realized.Opposite with direct computing method, this method operand is little, and speed is fast, but portable relatively poor, and use limitation is arranged, the situation in the time of can not handling m＞n, that is to say that each bit number m that handles can not be greater than the top step number n of generator polynomial, otherwise just can not use this algorithm.
In addition, the look-up table of being stored increases along with the increase of m forms 2 index, such as: when handling 8 bits, the look-up table size is 256 memory cell at every turn; During 16 bits of each processing, the look-up table size just becomes 65536 memory cell, and as seen, the degree of parallelism of this method can not be too high.
The third is parallel cyclic redundancy check encoding method, and as shown in Figure 2, this is a kind of parallel organization based on linear feedback shift register, among Fig. 2, and d
0～d
M-1M bit of the parallel list entries of expression, e
R, cBe matrix F
wThe capable c of r row, x
0～x
M-1Be the system mode column vector of output, wherein w is parallel input progression.This method is actual to be to make up relation between pairing each register of current C RCn generator polynomial by the hardware gate circuit, finally obtains crc value.
Be not difficult to find out that the speed of this method is w times of conventional method, cost is stored a F exactly
16Matrix also increases the complexity of hardware.The degree of parallelism of this method is very high, and be fit to hardware and realize as adopting FPGA, but this algorithm and be not suitable for software such as realizing with dsp chip.Reason is very simple, and parallel organization degree of parallelism shown in Figure 2 is m, and general processor does not all reach so high degree of parallelism.
Along with the development of 3G (Third Generation) Moblie high speed data service, CRC check is also widely applied in the transfer of data of 3G (Third Generation) Moblie.But because the delay requirement of 3GPP Base-Band Processing is quite strict, the traffic handing capacity in the performance of baseband processor and unit interval is closely related, and like this, the efficient quality that CRC encodes will directly have influence on the performance of baseband processor.If there are not the computational methods of suitable quick CRC check, will make the traffic handing capacity in the high-speed data communication be subjected to very big influence.
Summary of the invention
In view of this, main purpose of the present invention is to provide a kind of quick calculation method of cyclic redundancy check (CRC), can improve the processing speed of CRC check greatly, reduces the processing delay of CRC check, and then improves traffic handing capacity to a certain extent.
Further aim of the present invention is a kind of quick calculation method of cyclic redundancy check (CRC), makes it when guaranteeing quick computational speed, reaches best memory space/time delay configuration.
For achieving the above object, technical scheme of the present invention is achieved in that
A kind of quick calculation method of cyclic redundancy check (CRC), this method may further comprise the steps:
A. according to the current logical construction that adopts the CRCn maker, obtain and store the state of each shift register when handling each input bit of list entries in this maker;
B. whole states of all shift registers that obtained from step a, extract the state of each shift register in the CRCn maker of handling behind each bit of list entries; And the shift register initial condition during each the shift register state that is extracted formed represents that part and list entries represent that part stores respectively;
C. with each respectively the storage area different values that comprise independent variable be allocation index, generate the look-up table of this storage area correspondence, comprise the different values of described independent variable in the described look-up table and describedly handle behind each bit of list entries the corresponding relation between each shift register state in the CRCn maker;
When d. carrying out CRC check, whether judge the current bit number that needs to handle greater than each treatable bit number m with the CRCn pattern, if not, then handle by serial mode; If, then read the m bit, current value with input bit and shift register variable is an allocation index respectively, search list entries and represent the look-up table of part correspondence and the look-up table that the shift register initial condition is represented the part correspondence, then all lookup results are carried out XOR and preserve the XOR result; The XOR result of corresponding each shift register respectively as the current state of this shift register, is returned steps d.
Wherein, further comprise between step c and the steps d: the shift register initial condition of judging storage respectively represents part or list entries represent partly whether need to continue segmentation, if desired, then current storage area further is divided into an above storage area, and each storage area after dividing is generated corresponding look-up table respectively by specified criteria; Otherwise, direct execution in step d.
This method further comprises: set in advance the condition that need segment, then described judge whether to be subdivided into judge whether to meet sub-divided condition, if meet, then need the segmentation; Otherwise do not need segmentation.Here, the described condition of segmenting is: the memory space of the difference storage area of being divided among the step b is greater than given memory space.
If current storage area further is divided into an above storage area, then searches list entries described in the steps d and represent that the look-up table of part correspondence and shift register initial condition represent that the look-up table of part correspondence is: search at least one list entries respectively and represent the look-up table of part correspondence and the look-up table that above shift register initial condition is represented the part correspondence.
In the such scheme, the content of each storage area can be stored in the table respectively.In addition, the initial condition of each shift register is stored in the register in the CRCn maker, or is placed in the vector.
The quick calculation method of cyclic redundancy check (CRC) provided by the present invention, because according to the current logical construction that adopts CRCn generator polynomial correspondence, draw in advance under the treatment state of different input bits, the relation of the current state of used each register of CRCn and other registers and input bit position, generate corresponding look-up table, make when carrying out CRC check, can be directly calculate output under each register current state according to the look-up table that generates in advance, thereby improved the processing speed of CRC check greatly, just reduced the processing delay of CRC check.
Method of the present invention is divided by register value and input bit place value resulting relation, and can be as required or according to the situation of algorithm complex, register section or the input bit bit position of having divided segmented again, so, can reduce memory space in various degree, with less storage cost, exchanged very big processing delay for.And the inventive method has suitable flexibility, is guaranteeing under the fast prerequisite of computational speed, can determine best memory space/configuration computing time at any time according to actual conditions, can realize very high degree of parallelism.
Description of drawings
Fig. 1 is the composition structural representation of a kind of LFSR;
Fig. 2 is the Parallel CRC architectural schematic;
Fig. 3 is the realization flow figure of the inventive method;
Fig. 4 is the logical construction schematic diagram of one embodiment of the invention;
Fig. 5 is the CRC computational process schematic diagram of the described embodiment of Fig. 4.
Embodiment
Basic thought of the present invention is exactly: according to the current logical construction that adopts CRCn generator polynomial correspondence, draw in advance under the treatment state of different input bits, the state of used each shift register of CRCn is the relation between new situation and other shift register and the input bit position more, and generates corresponding look-up table according to this relation; When carrying out the CRCn verification, the look-up table that direct utilization generates in advance obtains the output under each shift register current state.
As shown in Figure 3, the specific implementation process of the inventive method may further comprise the steps:
Step 301:, obtain and store the state of each related in this maker shift register when handling each input bit according to the current logical construction that adopts the CRCn maker.
Step 302: whole states of all shift registers that obtain from step 301, extract the state of handling each shift register of CRCn maker behind each bit of list entries.
Step 303～304: the shift register initial condition that step 302 extracted during each shift register state forms is represented that part and list entries represent that part stores respectively; And with each respectively the independent variable that comprises of storage area be allocation index, generate the look-up table of this storage area correspondence.
Step 305～306: when carrying out CRC check, whether judge earlier the current bit number that needs to handle greater than each treatable bit number m with the CRCn pattern, if not, then handle by serial approach general in the prior art; If then execution in step 307.
Step 307～310: the information that reads the m bit, be allocation index with input bit and shift register variable respectively, search list entries and represent the look-up table of part correspondence and the look-up table that the shift register initial condition is represented the part correspondence, and all lookup results are carried out XOR, preserve the XOR result; And, the XOR result of corresponding each shift register respectively as the current state of this shift register, is returned step 305 then.
Between step 304 and step 305, can also increase a judgement, judge that the shift register initial condition of storing is respectively represented partly or list entries represents whether part also need continue segmentation, if desired, then connect specified criteria current storage area further is divided into an above storage area, and each storage area after dividing is generated corresponding look-up table respectively.Can set in advance sub-divided condition, such as: the memory space of look-up table is greater than the just segmentation again of certain set-point, so, just decide during segmentation and how to segment according to the memory space set-point, be exactly specifically, the look-up table stores amount of current storage area is 64K, and set-point is 32K, so, current storage area further will be divided into two storage areas again.If segment, then step 308 or step 309 or step 308 and step 309 will be allocation index with the contained independent variable of each storage area respectively, search corresponding look-up table, again all lookup results are carried out XOR.
For the storage that above-mentioned each step is mentioned, a table can be set store, if certain two table is divided from certain table, then these two tables can be described as the sublist of former table.
Further describing the quick calculating principle of CRC among the present invention for convenience, is example below with CRC16, simultaneously in conjunction with the generator polynomial of CRC16 and building-block of logic as a reference.
The generative process of the look-up table that CRC16 adopted comprises following step:
The first step, obtain the state of each shift register when handling each input bit according to the logical construction of CRC16 maker.
The generator polynomial of CRC16 is as shown in Equation (1):
g
crc16(D)＝D
16+D
12+D
5+1 (1)
The logical construction of CRC16 as shown in Figure 4, the maker of CRC16 comprises 16 shift register R1～R16, among Fig. 4
Expression mould 2 adds, just XOR.Suppose to represent respectively with R1～R16 the initial condition of these 16 shift registers, and current list entries is M, Mi represents the i bit of list entries, and in the present embodiment, list entries M is made up of 8 bits, i.e. M1～M8.So, the state of each shift register new situation more in the time of can drawing input bit of each processing according to Fig. 4, wherein all states of shift register are all represented by initial condition R1～R16 and list entries M.Each state constantly of each shift register is specifically as shown in Table 1:
| M1 | M2 | M3 | M4 | M5 | M6 | M7 | M8 | |
| R16 | R15 | R14 | R13 | R12+M1 +R16 | R11+M2 +R15 | R10+M3+ R14 | R9+M4+R13 | R8+M5+ R12+M1 +R16 |
| R15 | R14 | R13 | R12+M 1+R16 | R11+M2 +R15 | R10+M 3+R14 | R9+M4+ R13 | R8+M5+R12 +M1+R16 | R7+M6+ R11+M2 +R15 |
| R14 | R13 | R12+ M1+ R16 | R11+M 2+R15 | R10+M3 +R14 | R9+M4 +R13 | R8+M5+ R12+M1+ R16 | R7+M6+R11 +M2+R15 | R6+M7+ R10+M3 +R14 |
| R13 | R12 +M1 +R1 6 | R11+ M2+ R15 | R10+M 3+R14 | R9+M4+ R13 | R8+M5 +R12+ M1+R1 6 | R7+M6+ R11+M2+ R15 | R6+M7+R10 +M3+R14 | R5+M1+ R16+M8 +R9+M4 +R13 |
| R12 | R11 | R10 | R9 | R8 | R7 | R6 | R5+M1+R16 | R4+M2+ R15 |
| R11 | R10 | R9 | R8 | R7 | R6 | R5+M1+ R16 | R4+M2+R15 | R3+M3+ R14 |
| R10 | R9 | R8 | R7 | R6 | R5+M1 +R16 | R4+M2+ R15 | R3+M3+R14 | R2+M4+ R13 |
| R9 | R8 | R7 | R6 | R5+M1+ R16 | R4+M2 +R15 | R3+M3+ R14 | R2+M4+R13 | R1+M5+ R12+M1 +R16 |
| R8 | R7 | R6 | R5+M1 +R16 | R4+M2+ R15 | R3+M3 +R14 | R2+M4+ R13 | R1+M5+R12 +M1+R16 | M1+R16 +M6+R1 1+M2+R 15 |
| R7 | R6 | R5+ M1+ R16 | R4+M2 +R15 | R3+M3+ R14 | R2+M4 +R13 | R1+M5+ R12+M1+ R16 | M1+R16+M6 +R11+M2+R 15 | R15+M2 +M7+R1 0+M3+R 14 |
| R6 | R5+ M1+ R16 | R4+ M2+ R15 | R3+M3 +R14 | R2+M4+ R13 | R1+M5 +R12+ M1+R1 6 | M1+R16+ M6+R11+ M2+R15 | R15+M2+M7 +R10+M3+R 14 | R14+M3 +M8+R9 +M4+R1 3 |
| R5 | R4 | R3 | R2 | R1 | M1+R1 6 | R15+M2 | R14+M3 | R13+M4 |
| R4 | R3 | R2 | R1 | M1+R16 | R15+M | R14+M3 | R13+M4 | R12+M1 |
| 2 | +R16+M 5 | |||||||
| R3 | R2 | R1 | M1+R1 6 | R15+M2 | R14+M 3 | R13+M4 | R12+M1+R1 6+M5 | R11+M2 +R15+M 6 |
| R2 | R1 | M1+ R16 | R15+M 2 | R14+M3 | R13+M 4 | R12+M1+ R16+M5 | R11+M2+R1 5+M6 | R10+M3 +R14+M7 |
| R1 | R16 +M1 | R15+ M2 | R14+M 3 | R13+M4 | R12+M 1+R16+ M5 | R11+M2+ R15+M6 | R10+M3+R1 4+M7 | R9+M4+ R13+M8 |
Table one
In the table one, first row are represented 16 shift registers, the input bit Mi that the first row representative is handled, and corresponding, second classifies the current state of 16 shift registers when handling the first input bit M1 as; Second classifies the current state of 16 shift registers when handling the second input bit M2 as, and by that analogy, "+" expression mould 2 in the table adds.
The concrete generation method of above-mentioned table one comprises following process: at first, the initial condition of 16 shift registers among Fig. 4 is left in first row of table one; Then, carry out for each input bit: according to current input bit, the state of expressing the current time shift register with the shift register state and the current input of previous moment is until handling 8 bits.Such as: the current state of shift register R1 should equal the current state of shift register R16 and the XOR of list entries M, and the current state of shift register R2 just equals the current state of shift register R1; For another example: just equal the current state of shift register R5 and shift register R16 current state and list entries M XOR result XOR again according to the current state of Fig. 4 shift register R6, the shift register state in the CRC16 maker all by that analogy.
Second step, extract the state handle each shift register of CRC16 maker behind each bit of list entries.
After table one generates, can obtain each shift register according to last row of table one and handle 8 states behind the input bit, use R ' 1～R ' 16 to represent respectively, then obtain table two, table two is for handling the status list of each bit backward shift register of list entries:
| R′16 | R8+R12+R16+M5+M1 |
| R′15 | R7+R11+R15+M2+M6 |
| R′14 | R6+R10+R14+M7+M3 |
| R′13 | R5+R9+R13+R16+M1+M4+M8 |
| R′12 | R4+R15+M2 |
| R′11 | R3+R14+M3 |
| R′10 | R2+R13+M4 |
| R′9 | R1+R12+R16+M1+M5 |
| R′8 | R16+R11+R15+M1+M2+M6 |
| R′7 | R15+R10+R14+M2+M3+M7 |
| R′6 | R14+R9+R13+M3+M8+M4 |
| R′5 | R13+M4 |
| R′4 | R12+R16+M1+M5 |
| R′3 | R11+R15+M2+M6 |
| R′2 | R10+R14+M3+M7 |
| R′1 | R9+R13+M4+M8 |
Table two
The 3rd step, the state of handling each shift register behind all bits of list entries that is obtained formed divides, and construct corresponding look-up table.
In order to reduce the complexity of memory space and simplified construction look-up table, table two is divided into two sublists according to shift register initial condition R1～R16 and input bit sequence M1～M8, table three is for handling each shift register state part relevant with other shift register initial condition behind the list entries, and table four is to handle each shift register state part relevant with the input bit sequence behind the list entries.
| R′16 | R8+R12+R16 |
| R′15 | R7+R11+R15 |
| R′14 | R6+R10+R14 |
| R′13 | R5+R9+R13+R16 |
| R′12 | R4+R15 |
| R′11 | R3+R14 |
| R′10 | R2+R13 |
| R′9 | R1+R12+R16 |
| R′8 | R16+R11+R15 |
| R′7 | R15+R10+R14 |
| R′6 | R14+R9+R13 |
| R′5 | R13 |
| R′4 | R12+R16 |
| R′3 | R11+R15 |
| R′2 | R10+R14 |
| R′1 | R9+R13 |
Table three
| R′16 | M5+M1 |
| R′15 | M2+M6 |
| R′14 | M7+M3 |
| R′13 | M1+M4+M8 |
| R′12 | M2 |
| R′11 | M3 |
| R′10 | M4 |
| R′9 | M1+M5 |
| R′8 | M1+M2+M6 |
| R′7 | M2+M3+M7 |
| R′6 | M3+M8+M4 |
| R′5 | M4 |
| R′4 | M1+M5 |
| R′3 | M2+M6 |
| R′2 | M3+M7 |
| R′1 | M4+M8 |
Table four
Here, the corresponding look-up table of described structure is exactly: according to the different values of all independents variable in table three or the table four, calculate corresponding R ' 1～R ' 16 values.With table four is example, and the independent variable in the table four is M1～M8, because each bit of M1～M8 all desirable 0 or get 1, so the value of M1～M8 has 256 kinds of various combinations.So, the detailed process of structure look-up table is: 256 kinds of values listing M1～M8 earlier; According to the relation of R ' 1～R ' in the table four 16, calculate the value of every kind of pairing R ' 1～R ' 16 of different values of M1～M8 again with M1～M8; With M1～M8 is allocation index, all R ' 1～R ' 16 values is all stored in the register into word of the addressing of address of each byte; 256 kinds of values about R ' 1～R ' 16 of Xing Chenging are exactly required look-up table at last.Such as: the value of M1～M8 is 01111010 o'clock, because R ' 1 is M4+M8, M4=1 here, M8=0, the value that then calculates R ' 1 is 1; Same R ' 2 is M3+M7, M3=1 here, and M7=1, the value that then calculates R ' 2 is 0; (i=3, computational methods 4...16) are similar, repeat no more for other R ' i.If the dsp chip that is used to handle is to be memory cell with the word, just do not need particular processing; If be memory cell, just need carry out 2 times expansion to the M allocation index of 8 bit widths with the byte.
Independent variable in the table three is R1～R16, always has 2
16Plant combination.If be allocation index directly with R1～R16, the R ' 1～R ' 16 of correspondence is stored in the memory, memory space is exactly the 64K word.For the memory space of 64K word, can directly adopt; Also can continue table three is divided, to reduce memory space.Continue if desired to divide table three, then carried out for the 4th step.
The 4th step, further each shift register state part relevant with other shift register initial condition behind the intact list entries of thinning processing just further is divided into table three two sublists, and constructs the corresponding look-up table of each sublist.
Independent variable R1～R16 in the table three is divided into two groups of R1～R8 and R9～R16, corresponding, table three is divided into and two groups of two sublists that independent variable is corresponding: table five and table six.Generally, table five, stores corresponding R ' 1～R ' 16 values in the memory into as allocation index with independent variable R1～R8, forms look-up table; Table six, stores corresponding R ' 1～R16 value in the memory into as allocation index with independent variable R9～R16, forms look-up table.
| R′16 | R8 |
| R′15 | R7 |
| R′14 | R6 |
| R′13 | R5 |
| R′12 | R4 |
| R′11 | R3 |
| R′10 | R2 |
| R′9 | R1 |
| R′8 | 0 |
| R′7 | 0 |
| R′6 | 0 |
| R′5 | 0 |
| R′4 | 0 |
| R′3 | 0 |
| R′2 | 0 |
| R′1 | 0 |
Table five
| R′16 | R12+R16 |
| R′15 | R11+R15 |
| R′14 | R10+R14 |
| R′13 | R9+R13+R16 |
| R′12 | R15 |
| R′11 | R14 |
| R′10 | R13 |
| R′9 | R12+R16 |
| R′8 | R16+R11+R15 |
| R′7 | R15+R10++R14 |
| R′6 | R14+R9+R13 |
| R′5 | R13 |
| R′4 | R12+R16 |
| R′3 | R11+R15 |
| R′2 | R10+R14 |
| R′1 | R9+R13 |
Table six
In practical operation, if the bit number of list entries M is 16,32 etc., each shift register state part relevant with the input bit sequence after handling list entries can be divided by above-mentioned similar method equally, table four further can be divided into two sublists, and construct the corresponding look-up table of each sublist.Here, the process of formation look-up table is identical with the process of structure look-up table described in the 3rd step.
Through above four steps, required look-up table is just constructed and has been finished in the present embodiment.In fact, in the present embodiment, table five can not constructed look-up table, as long as allocation index R1～R8 is carried out arithmetic shift, can obtain corresponding R ' 1～R ' 16.
Based on top look-up table of constructing, when carrying out verification with CRC16, the computational process of CRC may further comprise the steps as shown in Figure 5:
Step 501: whether judge the current bit number of need handling less than each treatable bit number m, the m value gets 8 in the present embodiment, so, if remaining bits greater than 8, then execution in step 504; Otherwise, execution in step 502.
Step 502～503: according to general serial input method remaining bits is carried out the CRC computing, and read the value in the shift register, finish current C RC calculation process.
Step 504: shift register initial condition shown in Figure 4 is stored among the memory cell R of one 16 bit long.Here, if adopt DSP to realize, can store in the register; If adopt FPGA to realize, can be stored in the vector of one 16 bit.
Step 505～506: take out m bit storage from pending bit stream in memory cell M, wherein m often gets 8,16 equivalences, gets m=8 in the present embodiment.With M1～M8 is the look-up table that allocation index look-up table four generates, and obtains corresponding R ' 1～R ' 16, is stored in respectively among i the 16 bit memory cell Ti.If the M table is divided into a plurality of sublists, get 16,32 equivalent times such as M, search the look-up table of each sublist correspondence, and the R ' 1～R ' 16 that obtains is carried out being stored in respectively among the memory cell Ti after mould 2 adds.
Step 507: with R1～R8 is that allocation index carries out the arithmetic shift computing, and word that R ' 1～R ' of obtaining 16 is constituted or vector carry out mould 2 with the value among the corresponding memory cell Ti and add, and the result stores among the memory cell Ti of correspondence again; Be allocation index with R9～R16 again, the look-up table of look-up table six correspondences, word that R ' 1～R ' of obtaining 16 is constituted or vector carry out mould 2 with the value among the corresponding memory cell Ti and add, and the result is stored among the memory cell Ti of correspondence.
If there is more sublist, during such as CRC24, CRC32, initial condition has 24,32 bit widths, under these situations, search the look-up table of all sublist correspondences, at every turn the current list item that obtains is carried out mould 2 with the value among the corresponding memory cell Ti and add, store into again among the Ti of correspondence.
Step 508: the value of memory cell T1～T16 is deposited among R1～R16,, and, return step 501 as the initial condition that next stage CRC calculates shift register Ri as the state of handling m bit backward shift register Ri.
Carry out CRC according to the inventive method and calculate, on performance,, then need to carry out T table lookup operation and T-1 xor operation, can under the situation that complexity does not increase, accelerate the CRC computational speed if T sublist arranged.Aspect storage overhead, under even the situation about improving constant, can obviously reduce storage overhead in guaranteed performance.With commonly used 8,12,16 and 24 CRC patterns among the 3GPP is example, works as m=8, and when promptly handling 8 input bits, each sublist size all is 256 at every turn, and unit is determined by CRC length.Specifically storage overhead is as shown in Table 7:
| The CRC pattern | 8 | 12 | 16 | 24 |
| The sublist number | 2 | 3 | 3 | 4 |
| Form total length (bit) | 2×2 8×8 | 3×2 8×12 | 3×2 8×16 | 4×2 8×24 |
Table seven
The above is preferred embodiment of the present invention only, is not to be used to limit protection scope of the present invention.
Claims (7)
1. the quick calculation method of a cyclic redundancy check (CRC) is characterized in that, this method may further comprise the steps:
A. according to the current logical construction that adopts the CRCn maker, obtain and store the state of each shift register when handling each input bit of list entries in this maker;
B. whole states of all shift registers that obtained from step a, extract the state of each shift register in the CRCn maker of handling behind each bit of list entries; And the shift register initial condition during each the shift register state that is extracted formed represents that part and list entries represent that part stores respectively;
C. with each respectively the storage area different values that comprise independent variable be allocation index, generate the look-up table of this storage area correspondence, comprise the different values of described independent variable in the described look-up table and describedly handle behind each bit of list entries the corresponding relation between each shift register state in the CRCn maker;
When d. carrying out CRC check, whether judge the current bit number that needs to handle greater than each treatable bit number m with the CRCn pattern, if not, then handle by serial mode; If, then read the m bit, current value with input bit and shift register variable is an allocation index respectively, search list entries and represent the look-up table of part correspondence and the look-up table that the shift register initial condition is represented the part correspondence, then all lookup results are carried out XOR and preserve the XOR result; The XOR result of corresponding each shift register respectively as the current state of this shift register, is returned steps d.
2. method according to claim 1, it is characterized in that, further comprise between step c and the steps d: the shift register initial condition of judging storage respectively represents part or list entries represent partly whether need to continue segmentation, if desired, then current storage area further is divided into an above storage area, and each storage area after dividing is generated corresponding look-up table respectively by specified criteria; Otherwise, direct execution in step d.
3. method according to claim 2 is characterized in that, this method further comprises: set in advance the condition that need segment, then described judge whether to be subdivided into judge whether to meet sub-divided condition, if meet, then need the segmentation; Otherwise do not need segmentation.
4. method according to claim 3 is characterized in that, the described condition of segmenting is: the memory space of the difference storage area of being divided among the step b is greater than given memory space.
5. method according to claim 2, it is characterized in that, if current storage area further is divided into an above storage area, then searches list entries described in the steps d and represent that the look-up table of part correspondence and shift register initial condition represent that the look-up table of part correspondence is: search at least one list entries respectively and represent the look-up table of part correspondence and the look-up table that above shift register initial condition is represented the part correspondence.
6. method according to claim 1 is characterized in that, the content of each storage area is stored in the table respectively.
7. method according to claim 1 is characterized in that the initial condition of each shift register is stored in the register in the CRCn maker, or is placed in the vector.
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| CN101207467B (en) * | 2006-12-19 | 2011-05-18 | 大唐移动通信设备有限公司 | Generation of cyclic redundancy check code as well as method and apparatus for sending and testing data sequence |
| CN101847999B (en) * | 2010-05-28 | 2012-10-10 | 清华大学 | Method for performing parallel check by using cyclic redundancy check codes |
| CN101976214B (en) * | 2010-09-30 | 2012-12-19 | 西北工业大学 | Self-adaptive rate cyclic redundancy check (CRC) code implementation method and device |
| CN102612173B (en) * | 2011-01-21 | 2016-08-10 | 芯讯通无线科技（上海）有限公司 | The means of communication between multi mode terminal and communication module thereof |
| CN102739258A (en) * | 2011-04-14 | 2012-10-17 | 普天信息技术研究院有限公司 | Method and apparatus for calculating cyclic redundancy check code |
| CN102761394A (en) * | 2012-07-05 | 2012-10-31 | 中兴通讯股份有限公司 | Method and device for processing data |
| CN103795502B (en) * | 2014-02-28 | 2017-04-12 | 杭州华三通信技术有限公司 | Data frame check code generating method and device |
| CN106788878B (en) * | 2015-11-24 | 2019-11-15 | 中国航空工业第六一八研究所 | A kind of Parallel CRC error correction method with monobit errro correction function |
| CN108574490B (en) * | 2018-05-08 | 2022-05-10 | 华为技术有限公司 | Method and device for calculating Cyclic Redundancy Check (CRC) code |
| CN111740882B (en) * | 2020-07-29 | 2020-12-08 | 江苏金智科技股份有限公司 | Method for automatically checking configuration file of line protection measurement and control device |
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| US6609226B1 (en) * | 2000-04-10 | 2003-08-19 | Nortel Networks Limited | Networking device and method for making cyclic redundancy check (CRC) immune to scrambler error duplication |
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