CN117097440A - CRC (cyclic redundancy check) method for Ethernet packet - Google Patents
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Abstract
The application discloses an Ethernet packet CRC (cyclic redundancy check) method, which relates to the technical field of data processing and is used for realizing continuous CRC (cyclic redundancy check) of a large-bit-width Ethernet data packet. In addition, the scheme of the application converts the calculation of the large bit width data into the calculation of a plurality of small bit width data, so that the structure of a hardware circuit used for processing the data can be simplified, the use area and the design difficulty of a hardware logic circuit are reduced, and the implementation of actual engineering is facilitated.
Description
Technical Field
The application relates to the technical field of data processing, in particular to an Ethernet packet CRC (cyclic redundancy check) method.
Background
Currently, cyclic redundancy check (Cyclic Redundancy Check, CRC) calculation is widely applied to fields of computer network communication and the like, and different application scenarios may put different requirements on the CRC calculation.
For example, when the network information transmission reaches 400G, 1024 bits are required to be transmitted in parallel per cycle of the ethernet packet to meet the above-mentioned transmission rate requirement. In this case, if the conventional CRC calculation method is used, the problems of complex calculation circuit, difficult timing convergence, etc. are existed, and it is difficult to satisfy the CRC detection of the large-bit-width ethernet packet in the scenarios of 400G/800G ethernet transceiving, etc.
Therefore, a need exists for an ethernet packet CRC check method to solve the problem of difficult timing convergence in the process of receiving and transmitting a large-bit-width ethernet packet in the conventional CRC check method.
Disclosure of Invention
The application aims to provide an Ethernet packet CRC (cyclic redundancy check) method for solving the problem that the conventional CRC detection method is difficult in timing sequence convergence in the receiving and transmitting process of a large-bit-width Ethernet packet.
In order to solve the above technical problems, the present application provides a method for checking a CRC of an ethernet packet, including:
acquiring parallel input data of an Ethernet packet as data to be checked;
dividing the data to be checked to obtain a plurality of groups of first divided data, and determining a truth table of each group of first divided data; substituting each group of first segmentation data into a corresponding truth table to obtain corresponding first output values, and determining new data to be checked according to each first output value;
and carrying out CRC calculation on the data to be checked to determine a CRC check value, and attaching the CRC check value to the Ethernet packet.
Preferably, the data to be checked is segmented to obtain a plurality of groups of first segmented data, and a truth table of each group of first segmented data is determined; substituting each group of first segmentation data into a corresponding truth table to obtain corresponding first output values, and determining new data to be checked according to each first output value comprises:
after dividing the data to be checked each time to determine new data to be checked, judging whether the bit width of the data to be checked is smaller than or equal to a preset threshold value;
if not, repeating the step of dividing the data to be checked to determine new data to be checked;
if yes, the method goes to a step of performing CRC calculation on the data to be checked to determine a CRC check value.
Preferably, performing CRC calculation on the data to be checked to determine a CRC check value includes:
performing exclusive OR operation on the data to be checked and the coefficient initialization matrix to obtain a first intermediate result; wherein the coefficient initialization matrix is determined according to the CRC algorithm used;
performing exclusive-or calculation of the first degree on the CRC value currently stored in the check register based on the polynomial matrix to obtain a second intermediate result; wherein the polynomial matrix is determined according to the CRC algorithm used, the first order number being equal to the bit width of the parallel input data;
and determining a CRC check value according to the first intermediate result and the second intermediate result.
Preferably, determining the CRC check value based on the first intermediate result and the second intermediate result includes:
determining a first order power of a polynomial matrix to obtain a polynomial power matrix; and determining a truth table of the polynomial power matrix;
splicing the data of the corresponding rows of the first intermediate result and the second intermediate result in the sequence of the first intermediate result before and the second intermediate result after to obtain an intermediate result array;
substituting the data of each row of the intermediate result array into the corresponding row of the polynomial power matrix truth table to obtain an output value corresponding to the data of each row so as to determine a third intermediate result;
and performing exclusive OR calculation on the data of each row of the third intermediate result to obtain a CRC check value.
Preferably, determining the truth table of the polynomial power matrix comprises:
dividing each row of data of the polynomial power matrix to obtain a plurality of groups of second divided data; and determining a truth table for each set of second partition data;
correspondingly, substituting the data of each row of the intermediate result array into the corresponding row of the polynomial power matrix truth table to obtain the corresponding output value of the data of each row, so as to determine a third intermediate result comprises:
dividing the data of each row of the intermediate result array to obtain a plurality of groups of third divided data; the bit number of the third divided data is equal to that of the second divided data;
substituting the third divided data into a truth table of the corresponding second divided data to obtain a plurality of output values of each row of data corresponding to different groups of second divided data;
exclusive OR calculation is carried out among a plurality of output values corresponding to each row of data, and a unique output value corresponding to each row of data is determined so as to determine a third intermediate result.
Preferably, determining the truth table of the first split data/the second split data comprises:
determining an input-output expression of the first division data/the second division data;
all the different binary numbers with the bit number equal to the bit width of the first division data/the second division data are respectively substituted into the input and output expressions of the first division data/the second division data to determine the truth tables of the corresponding first division data/the second division data.
Preferably, acquiring parallel input data of the ethernet packet as data to be verified includes:
if the effective data of the parallel input data in the last period of the Ethernet packet is insufficient in bit width, zero padding is carried out on the last bit of the parallel input data so as to obtain data to be checked;
dividing the data to be checked to obtain a plurality of groups of first divided data, wherein the steps of:
equally dividing the data to be checked;
correspondingly, if the number of bits of the data to be verified cannot be divided equally, the method further comprises:
and carrying out zero padding on the last bit of the data to be checked.
Preferably, after determining the CRC check value according to the first intermediate result and the second intermediate result, the method further includes:
determining the zero padding bit number of parallel input data of the last period of the Ethernet packet;
and performing compensation calculation on the CRC check value according to the zero padding bit number to determine a new CRC check value.
Preferably, performing compensation calculation on the CRC check value according to the zero padding number includes:
and performing compensation calculation on the CRC value by adopting a multi-stage pipeline calculation mode.
Preferably, the ethernet packet CRC check method is alternated by at least two execution bodies.
The application provides an Ethernet packet CRC checking method, which is characterized in that data of an Ethernet packet are obtained in a parallel mode; dividing parallel input data of each period of the Ethernet packet as data to be checked to obtain a plurality of groups of first divided data, and realizing the reduction of the bit width of the data to be calculated in the subsequent calculation process; after the first divided data are acquired, the truth table of the first divided data is determined, and the truth table is used for solving exclusive-or calculation results (namely first output values) of each group of the first divided data, so that the large-bit-width parallel input data are further simplified; and finally, performing CRC calculation on the reduced data to obtain a CRC check value, wherein the CRC check value is used for realizing CRC check of the Ethernet packet. The application receives Ethernet packet data through a parallel structure, and disassembles CRC calculation of the whole Ethernet packet data into CRC calculation of parallel data input in each period; dividing the large-bit-width parallel input data by a dividing method, performing exclusive-or calculation on each divided group of data by using a truth table, and simplifying each group of data into one-bit output so as to realize bit-width simplification of the large-bit-width parallel input data; in addition, when CRC calculation is carried out on data, the increase of the data bit width is exponentially increased to cause the difficulty of CRC calculation, and the CRC calculation of one large bit width data is converted into the CRC calculation of a plurality of times of small bit width data through dividing parallel input data, and the index of the calculation difficulty is reduced through linear rising, so that the higher efficiency of the whole CRC check value generation process is obtained, the time sequence convergence of the CRC calculation is facilitated, and the high-speed transmission requirement of a large data amount Ethernet packet is met. In addition, the scheme of the application converts the calculation of the large bit width data into the calculation of a plurality of small bit width data, so that the structure of a hardware circuit used for processing the data can be simplified, the use area and the design difficulty of a hardware logic circuit are reduced, and the implementation of actual engineering is facilitated.
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For a clearer description of embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described, it being apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to the drawings without inventive effort for those skilled in the art.
FIG. 1 is a flow chart of a CRC method for Ethernet packets provided by the application;
fig. 2 is a logic block diagram of a method for checking CRC of an ethernet packet according to the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. Based on the embodiments of the present application, all other embodiments obtained by a person of ordinary skill in the art without making any inventive effort are within the scope of the present application.
The core of the application is to provide a CRC checking method of an Ethernet packet.
In order to better understand the aspects of the present application, the present application will be described in further detail with reference to the accompanying drawings and detailed description.
Currently, cyclic redundancy check (Cyclic Redundancy Check, CRC) computation has been widely used in various fields. However, there are still some problems, one of which is that the efficiency of serial calculation is low, and a long time is required for calculating the CRC value of a data packet with a slightly larger data amount, so that the data transmission rate requirement cannot be satisfied.
Therefore, a parallel calculation method is also used in the CRC check value generation process. Although the parallel computing efficiency is high, the CRC computing method related to the parallel of the continuous large-bit-width Ethernet packet is not much. Especially for the scene that the bit width of parallel input data is 1024 bits or more, no mature CRC calculation scheme exists at present. And the larger the bit width is, the higher the parallelism is, the more complex the calculation circuit is, the more difficult the timing convergence is, and the check detection of the CRC of the 400G/800G Ethernet receiving and transmitting Ethernet packet is difficult to meet.
In order to solve the above problems, the present application provides a method for checking CRC of an ethernet packet, as shown in fig. 1, including:
s10: and acquiring parallel input data of the Ethernet packet as data to be checked.
S20: dividing the data to be checked to obtain a plurality of groups of first divided data, and determining a truth table of each group of first divided data; substituting each group of first segmentation data into a corresponding truth table to obtain corresponding first output values, and determining new data to be checked according to each first output value.
S30: and carrying out CRC calculation on the data to be checked to determine a CRC check value, and attaching the CRC check value to the Ethernet packet.
In order to more clearly illustrate the method for checking the CRC of the Ethernet packet, the application combines the CRC check in the transmission process of the Ethernet packet in the Ethernet as an application scene, and takes the transmission of the 400G Ethernet packet as an example to illustrate the method:
firstly, for an ethernet packet with 400G size, in order to meet transmission requirements, the bit width of parallel input data of each period of the ethernet packet should reach 1024 bits, and the parallel input data of each period of the ethernet packet with continuous large bit width is set as:
；
wherein,B n representing parallel input data received at a clock cycle;nbit width representing parallel input data, in this example 1024 in particular;b i represent the firstiBit data.
Thus, for step S10, the parallel input data is acquiredB n Is a process of (2). It is easy to know that the parallel input data can be obtained by a hardware logic circuit such as a field programmable gate array (Field Programmable Gate Array, FPGA) and a complex programmable logic device (Complex Programmable logic device, CPLD). For the design of the hardware receiving circuit for parallel input data, various mature technical schemes exist at present, and the embodiment is not described herein again.
In addition, although the processing in step S10 is not limited to the processing in steps S20 and S30 after acquiring the parallel input data of one cycle, and the processing in steps S20 and S30 after acquiring the parallel input data of all cycles of the ethernet packet, the former embodiment is often adopted in consideration of timeliness and continuity of data transmission in actual application scenarios. That is, each time parallel input data of a period is received, that is, the CRC value is calculated for the parallel input data of the period, the CRC value determined by calculation of the previous period can be used as the initialization value of the next period, and then after the calculation of the CRC value of the parallel input data of the last period is completed, the obtained CRC value is the CRC value of the whole data of the ethernet packet.
For step S20, it is easy to see that the step S20 includes a plurality of sub-steps, but the whole purpose of step S20 is to divide the parallel input data based on the dividing method, so as to reduce the data bit width, so as to facilitate the subsequent CRC calculation.
Before describing step S20 in detail, this embodiment first describes the basic principle of determining the CRC check value according to the present application, which is derived from the following formula:
；
further, there are:
；
finally, the formula (1) is obtained:
；
wherein,is a CRC check value; />The initialization value for the CRC calculation of this time, namely the CRC value obtained by the last CRC calculation, is stored in a check register;W ln initializing a matrix for coefficients, which is of a size ofl×nWhereinlIn relation to the number of bits of the CRC algorithm used, when the CRC-32 algorithm is used,lthe value of (2) is 32, which can be obtained by the following formula (2):
；
Tis a polynomial matrix, and is uniquely determined according to the number of bits of the CRC algorithm; for example, in an embodiment where the bit width of the parallel input data is 1024 bits, most of the adopted CRC algorithm is CRC-32 algorithm, that is, the generated CRC check value is 32 bits CRC algorithm; at this time, the polynomial matrix is uniquely determined as a matrix of 32×32 size, and is entirely composed of 0 and 1, and is used to represent the exclusive-or calculation process of parallel input data.
Similarly, S is a polynomial vector, determined by the generator polynomial of the CRC algorithm used, where the CRC algorithm used is known, vector S is also known and uniquely determined. Also taking the CRC-32 algorithm as an example, the generator polynomial is:
F(x)=x 32 +x 26 +x 23 +x 22 +x 16 +x 12 +x 11 +x 10 +x 8 +x 7 +x 5 +x 4 +x 2 +x 1 +1；
then there is a vector S of:
S=[0;0;0;0;0;1;0;0;1;1;0;0;0;0;0;1;0;0;0;1;1;1;0;1;1;0;1;1;0;1;1;1]；
based on the above principle, the only unknown in the formula (1) is the CRC value to be calculatedTherefore, the determination of the CRC check value can be achieved by the expression (1). From equation (1), it is also known that the calculation of the CRC check value can be divided into two parts, namely P +.>AndW ln B n is calculated by the computer.
But from the above derivation, it can be seen that the polynomial matrixnPower of th(called polynomial power matrix) and coefficient initialization matrixW ln All of a relatively large matrix and parallel input dataB n The bit width of the bit is up to 1024 bits, so the direct calculation is very difficult, the calculation efficiency is very low, and the method is very difficult to realize through a hardware circuit.
Therefore, the present application simplifies the calculation process by step S20, mainly by simplifying the data amount of the data participating in the calculation. Specifically, step S20 includes:
s21: dividing the data to be checked to obtain a plurality of groups of first divided data;
it should be noted that, the embodiment is not limited to the specific division manner, and may be an equally divided manner or an unequally divided manner, but in consideration of normalization and unified calculation of actual engineering implementation, it is preferable to use an equally divided manner, that is, the bit widths of the divided sets of first division data are identical.
Similarly, the present embodiment is not limited to the number of bits for dividing, and any desired number of bits may be used to divide the parallel input data. In general, the number of bits divided in practical applications is determined according to the hardware circuit for performing the above calculation, and it is preferable to fully utilize the calculation resources of the hardware circuit.
Illustratively, if the CRC check calculation of the above method is implemented by an FPGA, specifically by a Logic Unit (LUT) in the FPGA. One possible way of splitting is 5 splitting, i.e. splitting every 5 bits of parallel input data into a set of first split data. If the parallel input data is not divided by 5 (1024 is not divided by 5), the effective data of the last group of the split data does not satisfy 5 bits, and zero padding can be performed at this time to ensure equal division.
S22: determining a truth table of each set of first segmentation data;
similarly, step S22 may be implemented by a LUT in the FPGA, where the truth table is the input-output relationship of the first split data, and the embodiment of the present application is not limited to a specific implementation of the truth table of the first split data, but provides a possible implementation, including:
determining an input-output expression of the first split data; all the different binary numbers with the bit number equal to the bit width of the first division data are respectively substituted into the first division data to determine a truth table of the corresponding first division data.
In combination with the above example, taking the example that the first division data is obtained by a 5-division method, the bit width of each group of the first division data is 5 bits; since the range that can be represented by a 5-bit binary number is 0 to 31, b×32 values can be obtained by substituting 0 to 31 into 5 equally divided b sets of data in binary form.
For example: substituting the 5 data of group q (q=1, 2,3.. Multidot.b), let the 5bit data of the q-th group be "1,0, 1", the input-output expression of the q-th group data can be obtained:
Y=x 1 +x 4 +x 5 ；
where Y represents the output value and x represents the input value.
And then 0-31 is brought into the input/output expression to obtain a truth table shown in the following table 1:
truth table of the q-th group of first divided data of table 1
From the truth table shown in table 1 above, the corresponding initialization value can be determined to be 32' h55 aaaaa 55.
Similarly, a truth table and corresponding initialization values of each group of first divided data can be determined, and corresponding hardware circuits are designed based on the obtained initialization values, so that the logic complexity of continuous large-bit-width Ethernet CRC calculation is reduced, and the occupation resource of LUT table lookup is greatly reduced.
S23: substituting each group of first segmentation data into a corresponding truth table to obtain a corresponding first output value.
S24: and determining new data to be checked according to each first output value.
After the truth tables of the first divided data of each group are obtained, the original data of the first divided data obtained by dividing the parallel input data are brought into the corresponding truth tables, and one-bit output value is obtained, namely one-bit data is reduced to one-bit data. The 5-division method as the example above, namely, the parallel input data is subjected to 5-multiplying reduction, so that the complexity of subsequent CRC calculation is reduced.
It is easy to know that when the 5-split method is used, 1024-bit parallel input data can be reduced to 205-bit data through one data split. However, the difficulty of CRC calculation of 205bit data (i.e. the difficulty of performing exclusive-or calculation on 205bit data) is still relatively high, so the process of step S20 may be repeated, that is, the data to be checked after the compaction of step S24 is replaced as new data to be checked into step S21 for performing new round of segmentation and compaction.
Based on the above, the present embodiment provides a preferred embodiment, and the step S20 specifically further includes:
s25: after dividing the data to be checked each time to determine new data to be checked, judging whether the bit width of the data to be checked is smaller than or equal to a preset threshold value; if not, returning to the step S21; if yes, go to step S30.
As described above, in the example, 1024 bits are divided and reduced by 5 to obtain 205 bits of data, and the 205 bits of data are divided by 5 again to obtain 41 bits of data, and the steps are repeated until the number of bits of the data after the final reduction is less than or equal to the preset threshold. The specific value of the preset threshold is not limited in this embodiment, but one possible scheme does not preset the threshold to 1, i.e. step S20 is repeatedly performed to convert the bit width of the result data to 1bit.
In addition, it should be noted that the data segmentation reduction in step S20 is aimed at parallel input dataFrom the above formula (1), it is known that +.>AndW ln B n the determination of the CRC value can be achieved. Therefore, after the parallel input data is reduced in step S20, further calculation is required to determine the CRC check value, that is, step S30 specifically further includes:
s31: and performing exclusive OR operation on the data to be checked and the coefficient initialization matrix to obtain a first intermediate result.
S32: and performing exclusive or calculation of the first degree on the CRC value currently stored in the check register based on the polynomial matrix to obtain a second intermediate result.
Wherein the first number is equal to the bit width of the parallel input data.
S33: and determining a CRC check value according to the first intermediate result and the second intermediate result.
From the above derivation, the first intermediate result in step S31 is represented by formula (1)W ln B n The second intermediate result in step S32 is represented by formula (1)Step S33 is a step of determining a CRC check value according to equation (1).
For step S31, a CRC-32 algorithm is used,Is 1024bit wide data,W ln Is thatl×nIn the case of the size matrix, step S20 uses 1 as a preset threshold value, and finally, the size matrix is reducedW ln B n The result of (2) should be 1XlAn array of sizes, whereinl=32, soW ln B n I.e. the first intermediate result VwBn is a 32bit size data.
In addition, it should be noted that, as is known from the above principle, the calculation of the CRC check value is sequentially performed on parallel input data of one cycle and one cycle, and the CRC calculation of each cycle also has the setting of the initialization value, and after the calculation is completed, the corresponding initialization needs to be performed, so that the unified execution body cannot continuously execute the CRC calculation process of multiple cycles.
Based on the above problems, the present example provides a preferred embodiment:
the above steps are alternately performed by at least two execution bodies.
That is, this embodiment provides an implementation manner of implementing the ethernet packet CRC checking method according to the present application by using a ping-pong mechanism, i.e. performing two-stage operations by at least two execution bodies.
Thereafter, for step S32, i.e. determining a second intermediate resultIt is readily apparent that the polynomial power matrix isl×lThe matrix of (32×32), which is also complicated to directly perform subsequent exclusive-or calculations, is disadvantageous for timing closure, so for step S32, this embodiment also provides a preferred implementation, including:
s321: determining a first order power of a polynomial matrix to obtain a polynomial power matrix; and determining a truth table of the polynomial power matrix;
s322: splicing the data of the corresponding rows of the first intermediate result and the second intermediate result in the sequence of the first intermediate result before and the second intermediate result after to obtain an intermediate result array;
s323: substituting the data of each row of the intermediate result array into the corresponding row of the polynomial power matrix truth table to obtain an output value corresponding to the data of each row so as to determine a third intermediate result;
s324: and performing exclusive OR calculation on the data of each row of the third intermediate result to obtain a CRC check value.
For step S321, the same method as described above for determining the truth table of parallel input data may be employed, i.e. one possible implementation comprises:
dividing each row of data of the polynomial power matrix to obtain a plurality of groups of second divided data; and a truth table for each set of second partition data is determined.
I.e. forl×lPolynomial power matrix of (a)I (i=1, 2,3.l) Line of rowslColumn data 6 is equally divided (not limited to being necessarily equally divided by 6, but this embodiment is merely to provide another dividing method different from the above 5). And taking into account that 32 cannot be divided by 6, an algorithm of pre-zero padding can be used, i.e. if each rowlNot divided by 6, h columns of zeros are added before each row, h beinglmod6。
Based on the zero padding operation, matrixChanging into a matrixTaMatrixTaA matrix of 36 x 32 size. Pair matrixTaAnd 6, dividing each data to obtain a plurality of groups of second divided data. The same method as that used in step S22 of the above embodiment can be used to determine a truth table of the second divided data, which is an array of 32×6×64 bits in size.
For example, if one set of the second partition data is "111111", the input/output expression of the set of the second partition data is: x1+x2+x3+x4+x5+x6. And substituting the values 0-63 which can be represented by the 6bit binary numbers into the input and output expressions respectively to obtain a truth table of the set of second divided data, wherein the initial value is represented as 64' h6996966996696996. Based on the same way, a matrix can be foundTaThe truth table of each row of data is 6×64 bits, and the matrixTaHas the following componentslRow, 32 rows, so matrixTaIs an array of size 32 x6 x 64 bits.
In the process of obtaining a matrixTaAfter the truth table of (3), the process proceeds to step S322:
to the first intermediate result vwBnlThe number and a second intermediate result value (cin, also referred to as a feedback value) are bit-wise concatenated as follows:
Cin_merge[0]={3’b0，VwBn[0]，cin}；
Cin_merge[1]={3’b0，VwBn[1]，cin}；
Cin_merge[2]={3’b0，VwBn[2]，cin}；
Cin_merge[3]={3’b0，VwBn[3]，cin}；
…
Cin_merge[31]={3’b0，VwBn[31]，cin}；
in the above-mentioned splicing process, 3' b0 is complementary 3bit data 0, vwBn [ i ] is the 1bit value corresponding to the i-th row in the first intermediate result array, and Cin is the 32bit data value, so that an intermediate result array cin_merge is obtained as an array with a size of 32×36.
Correspondingly, the embodiment also provides a preferable scheme of step S323, which includes:
dividing the data of each row of the intermediate result array to obtain a plurality of groups of third divided data; the bit number of the third divided data is equal to that of the second divided data;
substituting the third divided data into a truth table of the corresponding second divided data to obtain a plurality of output values of each row of data corresponding to different groups of second divided data;
exclusive OR calculation is carried out among a plurality of output values corresponding to each row of data, and a unique output value corresponding to each row of data is determined so as to determine a third intermediate result.
That is, in the present embodiment, the i-line data of the intermediate result array cin_merge is divided into 6 groups of third divided data by 6 division, and substituted into the matrixTaA 6 x 64bit truth table corresponding to the i rows of (a), 32 x6 result values can be obtained; and further, according to step S324, the 6 result values of each row are different or, thereby obtaining 32 numerical values C_value\utemp, that is, the result of equation (1), if there is no other subsequent calculation step, it is considered that the CRC value of the ethernet packet periodic parallel input data is determined.
However, in the scheme of determining the CRC value for the parallel input data of different periods of the ethernet packet, the effective data of the last period of the ethernet packet is sometimes not exactly 1024 bits, which does not meet the requirement of the unified calculation flow of the actual engineering, so that zero padding needs to be performed on the parallel input data of the last period to ensure that the bit widths of the parallel input data of all periods are uniform.
Based on the above example, the inverse calculation of the CRC value of the ethernet packet is needed to remove the error caused by zero padding, and this example provides a possible implementation:
s41: determining the zero padding bit number of parallel input data of the last period of the Ethernet packet;
s42: and performing compensation calculation on the CRC check value according to the zero padding bit number to determine a new CRC check value.
Taking the application scenario of the above example as an example, let the last period valid data bepZero padding data bit isqThe last cycle of data is represented as:。
namely, the following relationship is provided:
；
further, there are:
；
formula (3) can be obtained:
；
as can be obtained from the formula 3,and->The relationship of (2) is represented by the following formula (4):
；
from the formula (4), the matrix is passedThe CRC result value obtained in the above step can be realized>Compensation calculation is performed to finally obtain an accurate CRC check value +.>。
Since the ethernet data is transmitted in bytes and has 1024 bits/8=128 bytes, the number of zero padding in the last cycle is a multiple of 8, so the number of zero padding bytes of parallel input data in the last cycle may be 1 to 127, and if zero padding calculation is directly performed, the following two problems exist: 127 cases need to be calculated, the complexity is high, and corresponding hardware circuits cannot be designed for all cases; the separate calculation of 127 cases can make timing convergence very difficult, and cannot meet the data transmission rate requirement, so that engineering is difficult to realize.
To solve the above problems, the present example also provides a preferred embodiment: the step S42 performs compensation calculation on the CRC check value by using a multi-stage pipeline calculation method.
Specifically, since each value in the range of 1 to 127 can be added by using several of 7 values of 1,2, 4, 8, 16, 32, 64. For example 121=64+32+16+8+1, 55=32+16+4+2+1. Therefore, the multi-stage pipeline calculation provided in this embodiment is specifically 7-stage pipeline calculation, and the 127 cases can be covered by 7 times of calculation, so that the CRC value can be calculated in a fixed period and compared with the received CRC value, and if the two CRC values are consistent, the packet transmission is correct, otherwise, an error occurs.
From equation (4), it can be calculated separatelyT -64 、T -32 、T -16 、T -8 、T -4 、T -2 、T -1 The matrix, i.e. corresponding to 7 different levels of 7-level pipeline computation, is of the sizel×l（32×32）。
Here byT -64 For example pairT -64 The initialization calculation is performed, and a 6-division mode is still adopted.
For the followinglThe j-th row (j=1, 2, …,l) Data, j rows of 32 values, iflCan be divided by 6, then f=l/6 sets of data can be obtained, iflAnd the zero cannot be divided by 6, and the zero is added before the zero is added, so that the zero can be divided by 6.
The F group data is substituted with 0-63 respectively by the way in the above-mentioned true value table, so as to obtain F group 64bit numerical value F_vlue [ j ]]The j rows complete initialization. The same method initializes other rows to obtainT -64 Is used to initialize the initialization value of (a). Similarly, also toT -32 、T -16 、T -8 、T -4 、T -2 、T -1 And respectively initializing the matrixes to finish the preparation work of the compensation 7-stage pipeline calculation.
Then, according to the result value c_value_temp obtained in the above formula (1), if the value can be divided by 6 (the number of divided bits adopted in the above initialization process), zero padding is not needed, otherwise, zero with corresponding bit number needs to be added in front to obtain c_v, and then, the first stage pipeline calculation is performed:
the c_v and the byte value empty (zero-filling bit number/8) of zero filling in the pair C_value_temp are combined with the first level, namelyT -64 Performing calculation to obtain CV_1 and empty_1;
first, judge empty:
branch a: if empty is greater than or equal to 64, then empty_1=empty-64, cv_1 is equal to×C_v；
Branch B: if the empty is less than 64, empty_1=empty, cv_1 is equal to c_v;
thus, after the first stage pipeline calculation is completed, the second stage pipeline calculation is performed, and the same principle as the first stage pipeline calculation is adopted, and the method comprises the following steps:
CV_1 and empty_1 calculated by first stage pipeline andT -32 calculating and judging empty_1:
branch a: if empty_1 is greater than or equal to 32, then empty_2=empty_1-32, cv_2 is equal to×CV_1；
Branch B: if empty_1 is less than 32, empty_2=empty_1, cv_2 is equal to cv_1;
the same applies to the subsequent stages of pipeline computation, and this embodiment is not described here in detail. Based on the scheme, the upper-level data are substituted into the lower level in sequence to be calculated, so that the 7-level pipelining calculation is carried out, and the accurate Ethernet CRC check value after compensation can be obtained, thereby being capable of comparing with the CRC check value attached to the Ethernet packet and realizing the CRC check of the Ethernet data packet.
In summary, the method for checking the CRC of the ethernet packet according to the present application, a method flow combining the above preferred embodiments is shown in fig. 2, and includes:
parallel data input-segmentation truth table calculation-pipeline level exclusive-or logic calculation-)Calculation-multistage pipeline compensation calculation.
Wherein, after the calculation of the result value c_value_temp of the formula (1), the second intermediate result value cin needs to be fed back. And after the pipeline stage exclusive OR logic computation, equation (1)The calculation process of the result value C_value_temp involves the problem of initializing the value, so that the calculation cannot be continuously performed by a single execution body, and the calculation is realized by a ping-pong structure consisting of two execution bodies.
The application provides an Ethernet packet CRC checking method, which adopts a highly parallel structure to acquire the data of an Ethernet data packet, simplifies the big data first, and corresponds to 1024bit single-period parallel input data of the 400G Ethernet packet. Simplifying the exclusive-or calculation of the large bit width data and the large matrix through multiple times of segmentation calculation and application of a truth table, and converting the exclusive-or calculation into exclusive-or calculation among multiple times of small bit width and small matrix. The problem that the calculation difficulty increases exponentially along with the increase of the bit width is solved by utilizing multiple times of calculation with the linearly increased calculation difficulty, so that the CRC check requirement of the Ethernet high-speed data transmission is met. For 1024-bit Ethernet packet CRC calculation, the maximum clock frequency of the circuit can be ensured to be more than 390Mhz, and the data throughput rate of more than 425G/bits can be ensured. Moreover, due to the reduction of data quantity involved in the calculation process, the logic structure of a hardware circuit for realizing the CRC of the Ethernet packet can be simpler, and the realization of actual engineering is facilitated.
The method for checking the CRC of the Ethernet packet provided by the application is described in detail above. In the description, each embodiment is described in a progressive manner, and each embodiment is mainly described by the differences from other embodiments, so that the same similar parts among the embodiments are mutually referred. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section. It should be noted that it will be apparent to those skilled in the art that various modifications and adaptations of the application can be made without departing from the principles of the application and these modifications and adaptations are intended to be within the scope of the application as defined in the following claims.
It should also be noted that in this specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
Claims (10)
1. An ethernet packet CRC check method, comprising:
acquiring parallel input data of an Ethernet packet as data to be checked;
dividing the data to be verified to obtain a plurality of groups of first divided data, and determining a truth table of each group of first divided data; substituting each group of the first segmentation data into the corresponding truth table to obtain corresponding first output values, and determining new data to be verified according to each first output value;
and carrying out CRC calculation on the data to be checked to determine a CRC check value, and attaching the CRC check value to the Ethernet packet.
2. The method for CRC checking of ethernet packets according to claim 1, wherein said data to be checked is partitioned to obtain a plurality of sets of first partitioned data, and a truth table for each set of said first partitioned data is determined; substituting each group of the first division data into the corresponding truth table to obtain corresponding first output values, and determining new data to be verified according to each first output value comprises:
after dividing the data to be verified each time to determine new data to be verified, judging whether the bit width of the data to be verified is smaller than or equal to a preset threshold value;
if not, repeating the step of dividing the data to be checked to determine new data to be checked;
if yes, the step of performing CRC calculation on the data to be checked to determine a CRC check value is transferred.
3. The method according to claim 1 or 2, wherein performing CRC calculation on the data to be checked to determine a CRC check value comprises:
performing exclusive OR operation on the data to be checked and the coefficient initialization matrix to obtain a first intermediate result; wherein the coefficient initialization matrix is determined according to the CRC algorithm used;
performing exclusive-or calculation of the first degree on the CRC value currently stored in the check register based on the polynomial matrix to obtain a second intermediate result; wherein the polynomial matrix is determined from the CRC algorithm used, the first order number being equal to the bit width of the parallel input data;
and determining the CRC value according to the first intermediate result and the second intermediate result.
4. The ethernet packet CRC check method as claimed in claim 3, characterized in that said determining the CRC check value based on the first intermediate result and the second intermediate result comprises:
determining the first order power of the polynomial matrix to obtain a polynomial power matrix; and determining a truth table for the polynomial power matrix;
splicing the data of the corresponding rows of the first intermediate result and the second intermediate result in the sequence of the first intermediate result before and the second intermediate result after to obtain an intermediate result array;
substituting the data of each row of the intermediate result array into the corresponding row of the polynomial power matrix truth table to obtain an output value corresponding to the data of each row so as to determine a third intermediate result;
and performing exclusive OR calculation on the data of each row of the third intermediate result to obtain the CRC value.
5. The ethernet packet CRC check method according to claim 4, characterized in that determining the truth table of the polynomial power matrix comprises:
dividing each row of data of the polynomial power matrix to obtain a plurality of groups of second divided data; and determining a truth table for each set of the second partition data;
correspondingly, substituting the data of each row of the intermediate result array into the corresponding row of the polynomial power matrix truth table to obtain the output value corresponding to the data of each row, so as to determine a third intermediate result includes:
dividing the data of each row of the intermediate result array to obtain a plurality of groups of third divided data; wherein the number of bits of the third division data is equal to the second division data;
substituting the third divided data into a truth table of the corresponding second divided data to obtain a plurality of output values of each row of data corresponding to different groups of the second divided data;
exclusive OR calculation is carried out among a plurality of output values corresponding to each row of data, and a unique output value corresponding to each row of data is determined so as to determine the third intermediate result.
6. The ethernet packet CRC check method according to claim 5, wherein determining a truth table for the first split data/the second split data comprises:
determining an input-output expression of the first division data/the second division data;
all different binary numbers with the bit number equal to the bit width of the first division data/the second division data are respectively substituted into the input-output expression of the first division data/the second division data to determine a truth table of the corresponding first division data/the second division data.
7. The method for CRC checking of ethernet packets according to claim 5, wherein said obtaining parallel input data of ethernet packets as data to be checked comprises:
if the effective data of the parallel input data in the last period of the Ethernet packet is insufficient in bit width, zero padding is carried out on the last bit of the parallel input data so as to obtain the data to be checked;
the step of dividing the data to be verified, the step of obtaining a plurality of groups of first divided data comprises the following steps:
equally dividing the data to be checked;
correspondingly, if the number of bits of the data to be verified cannot be divided equally, the method further comprises:
and carrying out zero padding on the last bit of the data to be checked.
8. The ethernet packet CRC check method as claimed in claim 7, further comprising, after determining the CRC check value based on the first intermediate result and the second intermediate result:
determining the zero padding bit number of the parallel input data of the last period of the Ethernet packet;
and performing compensation calculation on the CRC check value according to the zero padding bit number so as to determine a new CRC check value.
9. The ethernet packet CRC check method according to claim 8, characterized in that said performing a compensation calculation of said CRC check value according to said zero padding bits comprises:
and performing compensation calculation on the CRC value by adopting a multi-stage pipeline calculation mode.
10. The ethernet packet CRC check method according to claim 1, characterized in that the ethernet packet CRC check method is performed alternately by at least two execution bodies.
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