CN113300716A

CN113300716A - Method and device for generating cyclic redundancy check code and computer readable medium

Info

Publication number: CN113300716A
Application number: CN202010672965.0A
Authority: CN
Inventors: 刘兴奎; 刘攀; 李强; 曹政; 高山渊; 刘帆
Original assignee: Alibaba Group Holding Ltd
Current assignee: Alibaba Group Holding Ltd
Priority date: 2020-07-14
Filing date: 2020-07-14
Publication date: 2021-08-24

Abstract

The application provides a cyclic redundancy check code generation scheme, which is characterized in that a first register and a second register are added for each bit of a target cyclic redundancy check code to be generated, wherein a first parameter of the first register is used for marking the bit of data participating in exclusive-or logic operation, and a second parameter of the second register is used for marking the bit of the current cyclic redundancy check code participating in exclusive-or logic operation, so that when the standard of the cyclic redundancy check code changes, the bit participating in operation is adjusted by changing the parameters in the first register and the second register, and the cyclic redundancy check code is suitable for the changed standard.

Description

Method and device for generating cyclic redundancy check code and computer readable medium

Technical Field

The present application relates to the field of information technologies, and in particular, to a method and an apparatus for generating a cyclic redundancy check code, and a computer readable medium.

Background

Cyclic Redundancy Check (CRC) is a coding technique that generates a short fixed-length parity Check code based on a piece of data of indefinite length, and is mainly used to detect or Check errors that may occur after the data is transmitted or stored. The generated check code is calculated before transmission or storage and appended to the data, and the receiver checks to determine whether the data has changed.

In each processing period for generating the cyclic redundancy check code, a target cyclic redundancy check code (i.e., the cyclic redundancy check code obtained by processing in the current processing period) is calculated and obtained according to the current cyclic redundancy check code (i.e., the cyclic redundancy check code obtained by processing in the last period). Taking the 8-bit cyclic redundancy check code with the generating polynomial of x ^8+ x ^6+ x ^3+1 as an example, assuming that 4-bit input data is processed in each period and is represented as din [3:0], the current cyclic redundancy check code is represented as c [7:0], the target cyclic redundancy check code obtained in the current period processing is represented as newcrc [7:0], and the value of each bit in the newcrc [7:0] can be represented by the following expression:

wherein the content of the first and second substances,

representing an exclusive-OR logical operation, newcrc [ i ]]、c[i]And din [ i]Respectively representing the target cyclic redundancy check code, the current cyclic redundancy check code and the ith bit of the input data. In practical scenarios, different generation polynomials are used for different standard CRC codes, for example, the generation polynomial used for the 32-bit CRC code used in Ethernet is X ^32+ X ^26+ X ^23+ X ^22+ X ^16+ X ^12+ X ^11+ X ^10+ X ^8+ X ^7+ X ^5+ X ^4+ X ^2+ X ^1+1, and the generation polynomial used for the 16-bit CRC code of X25 standard is X ^16+ X ^12+ X ^5+ 1.

In an actual cyclic redundancy check code application scenario, a circuit for calculating the cyclic redundancy check code is generally determined according to a polynomial and a bit width defined in advance. Different generator polynomials may need to be generated using different circuitry once the circuitry determines that it cannot be used to generate other standard cyclic redundancy check codes. However, in some application scenarios, cyclic redundancy check codes of a plurality of standards need to be supported, and cyclic redundancy check codes of different standards adopt different generator polynomials, so that the existing method can only support a cyclic redundancy check code of a fixed standard, but cannot support a plurality of cyclic redundancy check codes of different standards at the same time.

Disclosure of Invention

An object of the present application is to provide a method, an apparatus and a computer readable medium for generating a cyclic redundancy check code, so as to solve the problem that multiple cyclic redundancy check codes of different standards cannot be simultaneously supported.

The embodiment of the application provides a method for generating a cyclic redundancy check code, which comprises the following steps:

acquiring a first parameter of a first register and a second parameter of a second register corresponding to an ith bit of a target cyclic redundancy check code to be generated, wherein the first parameter is used for marking the bit of data participating in exclusive-or logic operation, and the second parameter is used for marking the bit of a current cyclic redundancy check code participating in exclusive-or logic operation;

determining a valid data bit and a valid check bit according to the first parameter and the second parameter, wherein the valid data bit is a bit of data participating in exclusive-or logic operation, and the valid check bit is a bit of a current cyclic redundancy check code participating in exclusive-or logic operation;

determining values of an effective data bit and an effective check bit according to input data and a current cyclic redundancy check code, and performing exclusive-or logic operation on the values of the effective data bit and the effective check bit to generate a value of an ith bit of the target cyclic redundancy check code;

and determining the target cyclic redundancy check code according to the values of all bits of the target cyclic redundancy check code.

The embodiment of the application also provides a data storage method, which comprises the following steps:

determining the target cyclic redundancy check code according to the values of all bits of the target cyclic redundancy check code;

and sending the data and the target cyclic redundancy check code to a storage node so that the storage node stores the data after completing the check on the data according to the target cyclic redundancy check code.

The embodiment of the application provides a device for generating a cyclic redundancy check code, which comprises:

the parameter determining module is used for acquiring a first parameter of a first register and a second parameter of a second register corresponding to the ith bit of a target cyclic redundancy check code to be generated, wherein the first parameter is used for marking the bit of data participating in exclusive-or logic operation, and the second parameter is used for marking the bit of the current cyclic redundancy check code participating in exclusive-or logic operation;

the logic operation module is used for determining an effective data bit and an effective check bit participating in operation according to the first parameter and the second parameter, determining values of the effective data bit and the effective check bit according to input data and a current cyclic redundancy check code, and performing exclusive-or logic operation on the values of the effective data bit and the effective check bit to generate a value of an ith bit of the target cyclic redundancy check code, wherein the effective data bit is a bit of the data participating in exclusive-or logic operation, and the effective check bit is a bit of the current cyclic redundancy check code participating in exclusive-or logic operation;

and the generating module is used for determining the target cyclic redundancy check code according to the values of all bits of the target cyclic redundancy check code.

An embodiment of the present application further provides a data storage device, where the data storage device includes:

a generating module, configured to determine the target cyclic redundancy check code according to values of all bits of the target cyclic redundancy check code;

and the sending module is used for sending the data and the target cyclic redundancy check code to a storage node so that the storage node stores the data after completing the check on the data according to the target cyclic redundancy check code.

Some embodiments of the present application provide another apparatus for generating a cyclic redundancy check code, where the apparatus includes a data register, a current check code register, a target check code register, and N groups of generating circuits, and a value of N is the same as a bit width of the target check code register and the current check code register;

each group of generating circuits comprises a first register, a second register, an exclusive-OR gate circuit and a plurality of AND gate circuits, wherein the bit width of the first register is the same as that of the data register, and the bit width of the second register is the same as that of the current check code register;

the input end of the AND gate circuit inputs the jth bit of the data register and the jth bit of the first register or inputs the kth bit of the current check code register and the kth bit of the second register, the output end of the AND gate circuit is connected with the input end of the XOR gate circuit, and the output end of the XOR gate circuit outputs the ith bit of the target check code register.

each group of generating circuits comprises a first register, a second register, a plurality of AND gate circuits and an XOR gate circuit divided into multiple stages, wherein the bit width of the first register is the same as that of the data register, and the bit width of the second register is the same as that of the current check code register;

the input end of the AND gate circuit inputs the jth bit of the data register and the jth bit of the first register or inputs the kth bit of the current check code register and the kth bit of the second register, the output end of the AND gate circuit is connected with the input end of the first stage of XOR gate circuit, the output end of each stage of XOR gate circuit is connected with the input end of the next stage of XOR gate circuit, and the input end of the last stage of XOR gate circuit outputs the ith bit of the target check code register.

Some embodiments of the present application also provide a computing device, wherein the device comprises a memory for storing computer program instructions and a processor for executing the computer program instructions, wherein the computer program instructions, when executed by the processor, trigger the device to perform the aforementioned method of generating cyclic redundancy check codes or data storage method.

Further embodiments of the present application also provide a computer readable medium having stored thereon computer program instructions executable by a processor to implement the method of generating a cyclic redundancy check code or the method of storing data.

In the scheme for generating the cyclic redundancy check code provided by the embodiment of the application, a first parameter of a first register and a second parameter of a second register corresponding to an ith bit of a target cyclic redundancy check code to be generated are firstly obtained, an effective data bit and an effective check bit are determined according to the first parameter and the second parameter, then values of the effective data bit and the effective check bit are determined according to input data and the current cyclic redundancy check code, an exclusive-or logic operation is performed on the values of the effective data bit and the effective check bit to generate the value of the ith bit of the target cyclic redundancy check code, and the target cyclic redundancy check code can be determined after the values of all the bits are generated. According to the scheme, a first register and a second register are added for each bit of a target cyclic redundancy check code to be generated, wherein a first parameter of the first register is used for marking the bit of data participating in exclusive-or logic operation, and a second parameter of the second register is used for marking the bit of the current cyclic redundancy check code participating in exclusive-or logic operation, so that when the standard of the cyclic redundancy check code changes, the bit participating in operation is adjusted by changing the parameters in the first register and the second register, and the cyclic redundancy check code is suitable for the changed standard.

Drawings

Other features, objects and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:

fig. 1 is a processing flow chart of a method for generating a cyclic redundancy check code according to an embodiment of the present application;

FIG. 2 is a diagram of a circuit implementation for calculating the ith bit of a CRC code according to an embodiment of the present application;

FIG. 3 is a diagram of another circuit implementation for calculating the ith bit of the CRC code in the embodiment of the present application;

fig. 4 is a schematic structural diagram of a cyclic redundancy check code generation device according to an embodiment of the present application;

fig. 5 is another schematic structural diagram of a cyclic redundancy check code generation device according to an embodiment of the present application;

fig. 6 is a schematic structural diagram of a computing device for implementing cyclic redundancy check code generation according to an embodiment of the present application;

the same or similar reference numbers in the drawings identify the same or similar elements.

Detailed Description

Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are illustrative only and should not be construed as limiting the invention.

As used herein, the singular forms "a", "an", "the" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present. Further, "connected" or "coupled" as used herein may include wirelessly connected or wirelessly coupled. As used herein, the term "and/or" includes all or any element and all combinations of one or more of the associated listed items.

The embodiment of the application provides a method for generating a cyclic redundancy check code, which is characterized in that a first register and a second register are added for each bit of a target cyclic redundancy check code to be generated, wherein a first parameter of the first register is used for marking the bit of data participating in exclusive-or logic operation, and a second parameter of the second register is used for marking the bit of the current cyclic redundancy check code participating in exclusive-or logic operation, so that when the standard of the cyclic redundancy check code changes, the bit participating in operation is adjusted by changing the parameters in the first register and the second register, and the cyclic redundancy check code is suitable for the changed standard.

Fig. 1 shows a processing flow of a method for generating a cyclic redundancy check code according to an embodiment of the present application, where the method at least includes the following processing steps:

step S101, a first parameter of a first register and a second parameter of a second register corresponding to the ith bit of a target cyclic redundancy check code to be generated are obtained. Where i represents any one bit, e.g., for an 8-bit target cyclic redundancy check code newcrc [7:0], which includes bits 0 to 7, newcrc [0], newcrc [1], newcrc [2], newcrc [3], newcrc [4], newcrc [5], newcrc [6], and newcrc [7], respectively. For each bit of the target cyclic redundancy check code, a corresponding set of registers may be set, for example, if the target cyclic redundancy check code has 8 bits, 8 sets of registers may be set, and each set of registers includes a first register and a second register.

The first parameter of the first register is used for marking the bit of the data participating in the exclusive-or logic operation, and the second parameter of the second register is used for marking the bit of the current cyclic redundancy check code participating in the exclusive-or logic operation. The current cyclic redundancy check code is the cyclic redundancy check code obtained by the previous cycle processing, and the target cyclic redundancy check code is the cyclic redundancy check code obtained by the current cycle processing, so that the number of the bits of the current cyclic redundancy check code is consistent with that of the bits of the target cyclic redundancy check code, and if the target cyclic redundancy check code has 8 bits, the current cyclic redundancy check code also has 8 bits.

In some embodiments of the present application, the bit width of the first register is the same as the bit width of the data participating in the exclusive or logic operation, and the bit width of the second register is the same as the bit width of the current cyclic redundancy check code participating in the exclusive or logic operation. For example, the input data is 4 bits, denoted din [3:0], and accordingly the bit width of the first register may also be 4 bits, and the value of the first register (i.e. the first parameter) is also 4 bits, denoted Rd [3:0 ]. Similarly, if the crc is 8 bits, denoted as c [7:0], correspondingly, the bit width of the second register may also be 8 bits, and the value of the second register (i.e. the second parameter) is also 8 bits, denoted as Rc [7:0 ].

And step S102, determining a valid data bit and a valid check bit according to the first parameter and the second parameter. The valid data bits are bits of data participating in an exclusive-or logic operation, i.e., several bits marked in the data by the first parameter. The first parameter may also be used to determine which bits of the input data participate in the xor logic operation in the current cycle when marking the bits of the data participating in the xor logic operation, and these determined bits are valid data bits.

In some embodiments of the present application, the manner of determining the valid data bit may be determined based on values of bits in the first parameter, that is, when a value of a jth bit in the first parameter meets a preset condition, the jth bit of the data is determined to be a valid data bit. Wherein j represents any one bit in the first parameter, for example, for a 4-bit first parameter Rd [3:0], the following 0 th to 3 Rd bits are included, Rd [0], Rd [1], Rd [2], and Rd [3 ]. For the 0 th bit, i.e. newcrc [0], in the 8-bit target cyclic redundancy check code newcrc [7:0], the first parameter of the corresponding first register is 2' b0101, i.e. the binary value 0101, so that Rd [0] ═ 1, Rd [1] ═ 0, Rd [2] ═ 1, and Rd [3] ═ 0 are known, and if the preset condition is that the value of the bit is 1, the data input in the current period is represented as din [3:0], it may be determined that the valid data bits of the data are the 0 th bit and the 2 nd bit, i.e. din [0] and din [2 ].

And the valid check bits are the bits of the current cyclic redundancy check code participating in the exclusive-or logic operation, i.e. several bits marked by the second parameter in the current cyclic redundancy check code. The second parameter may be used to determine which bits participating in the xor logical operation in the current cycle participate in the xor logical operation when marking the bits of the current cyclic redundancy check code participating in the xor logical operation, and the determined bits are valid check bits.

In some embodiments of the present application, the manner of determining the valid parity bit may be determined based on values of bits in the second parameter, that is, when a value of a kth bit in the second parameter meets a preset condition, the kth bit of the data is determined to be the valid parity bit. Where k represents any bit of the second parameter, and includes, for example, the 0 th to 7 th bits, Rc [0], Rc [1], Rc [2], Rc [3], Rc [4], Rc [5], Rc [6], and Rc [7], for an 8-bit second parameter Rc [7:0 ]. For the 0 th bit, that is, newcrc [0], in the 8-bit target cyclic redundancy check code newcrc [7:0], the first parameter of the corresponding first register is 2' b01010000, that is, the binary value 0101000, so that Rc [0] ═ 0, Rc [1] ═ 0, Rc [2] ═ 0, Rc [3] ═ 0, Rc [4] ═ 1, Rc [5] ═ 0, Rc [6] ═ 1, and Rc [7] ═ 0 can be known, and if the preset condition is that the value of the bit is 1 and the current cyclic redundancy check code in the current period is expressed as c [7:0], the valid check bits of the data can be determined to be the 4 th and 6 th bits, that is, c [4] and c [6 ].

Step S103, determining the values of the effective data bit and the effective check bit according to the input data and the current cyclic redundancy check code, and performing XOR logical operation on the values of the effective data bit and the effective check bit to generate the value of the ith bit of the target cyclic redundancy check code.

And step S104, determining the target cyclic redundancy check code according to the values of all bits of the target cyclic redundancy check code.

Using the aforementioned target cyclic redundancy check code newcrc [7:0]]Bit 0 newcrc [0] of (1)]For example, when the first parameter is 2'b0101 and the second parameter is 2' b01010000, the valid data bit of the data participating in the XOR logic operation is din [0]]And din [2]]And the valid parity bit of the current CRC code participating in the XOR logical operation is c [4]]And c [6]]From this, it can be seen that

Wherein the content of the first and second substances,

representing an exclusive or logical operation. And after each bit of the target cyclic redundancy check code is processed in a traversing way, determining the value of all bits of the target cyclic redundancy check code.

In an actual scenario, when the valid data and the valid check are determined to be yes, the judgment of the preset condition may be implemented by means of an and logic operation, that is, before performing the xor operation, the and logic operation is performed on the data and the corresponding bit of the first parameter, and the current cyclic redundancy check code and the corresponding bit of the second parameter. Thus, the value of the ith bit of the target cyclic redundancy check code is:

wherein the content of the first and second substances,

which represents an exclusive or logical operation of the logical operations,&and logic operation is represented, Wd is the bit width of the first parameter and the input data, and Wc is the bit width of the second parameter and the current cyclic redundancy check code. Fig. 2 shows one circuit implementation for calculating the value of the ith bit. Taking the 8-bit target cyclic redundancy check code as an example, the value of the 0 th bit is:

after substituting the first parameter 2'b0101 and the second parameter 2' b01010000, the value of the 0 th bit is:

when the first parameter and the second parameter are changed, the valid data bit and the valid check bit participating in the operation are also changed, for example, when newcrc [0] is changed]Is 2' b1101, the corresponding valid data bit is din [0]、din[2]And din [3]]When newcrc [0]]When the second parameter of (2') b01010011, the corresponding valid parity bit is c [0]]、c[1]、c[4]And c [6]]At this time

Similarly, the remaining bits of the target cyclic redundancy check code may be traversed to generate a complete target cyclic redundancy check code.

Therefore, different effective data bits and effective check bits can be determined by configuring different first parameters and second parameters for each bit of the target cyclic redundancy check code and writing the different first parameters and second parameters into the first register and the second register respectively, so that different expressions are constructed for each bit of each target cyclic redundancy check code, the target cyclic redundancy check code is suitable for different generating polynomials, and cyclic redundancy check codes with different standards are supported. For example, taking an 8-bit cyclic redundancy check code with a generator polynomial of x ^8+ x ^6+ x ^3+1 as an example, for each bit of the target cyclic redundancy check code, the values of the first parameter and the second parameter can be set as follows:

newcrc[0]：Rd[3:0]＝2’b0101 Rc[7:0]＝2’b01010000

newcrc[1]：Rd[3:0]＝2’b1010 Rc[7:0]＝2’b10100000

newcrc[2]：Rd[3:0]＝2’b0100 Rc[7:0]＝2’b01000000

newcrc[3]：Rd[3:0]＝2’b1101 Rc[7:0]＝2’b11010000

newcrc[4]：Rd[3:0]＝2’b1010 Rc[7:0]＝2’b10100001

newcrc[5]：Rd[3:0]＝2’b0100 Rc[7:0]＝2’b01000010

newcrc[6]：Rd[3:0]＝2’b1101 Rc[7:0]＝2’b11010100

newcrc[7]：Rd[3:0]＝2’b1010 Rc[7:0]＝2’b10101000

when cyclic redundancy check codes of other standards need to be supported, different first parameters and second parameters can be configured according to corresponding generator polynomials, so that the cyclic redundancy check codes of the corresponding standards can be generated after the equipment acquires the first parameters and the second parameters.

In some embodiments of the present application, when performing an exclusive or logic operation on the values of the valid data bits and the valid check bits to generate the value of the ith bit of the target cyclic redundancy check code, a multi-stage processing manner may be adopted, that is, performing a multi-stage exclusive or logic operation on the values of the valid data bits and the valid check bits to generate the value of the ith bit of the target cyclic redundancy check code.

For example, the multi-stage processing scheme shown in fig. 3 can be adopted by taking the ith bit newcrc [ i ] of the target cyclic redundancy check code as an example. The processing procedure divides the XOR logic operation into two stages, firstly divides the values of the effective data bits and the effective check bits into a plurality of groups, carries out the XOR logic operation on the values of the effective data bits and/or the effective check bits in each group, determines the intermediate operation result of each group, and marks the intermediate operation result of each group as part _ crc. And then carrying out exclusive-OR logic operation on the intermediate operation results of all the groups to generate the value of the ith bit of the target cyclic redundancy check code.

It will be understood by those skilled in the art that the specific manner of the above-described classification process is merely exemplary, and other existing or future possibilities may be adapted to the present invention and are intended to be included within the scope of the present invention and are hereby incorporated by reference. For example, more levels can be adopted, that is, the intermediate operation results of the previous level are grouped and subjected to exclusive or logic operation respectively to obtain the intermediate operation results of the next level until the value of the ith bit of the target cyclic redundancy check code is obtained.

In addition, in order to improve the processing efficiency, before acquiring the first parameter of the first register and the second parameter of the second register corresponding to the ith bit of the target cyclic redundancy check code to be generated, the bit width of the input data may be increased, so that the processing in one cycle may calculate the corresponding target cyclic redundancy check code for more data.

In other embodiments of the present application, the method for generating a cyclic redundancy check code may also be applied to a cloud computing storage scenario, so that this embodiment may provide a data storage method, where after a target cyclic redundancy check code corresponding to data is generated by using the foregoing generation method, the data and the target cyclic redundancy check code may be sent to a storage node. After receiving the data and the corresponding target cyclic redundancy check code, the storage node may check the data according to the target cyclic redundancy check code, and after the check is completed, store the data.

Based on the same inventive concept, the embodiment of the application also provides a device for generating the cyclic redundancy check code and a data storage device, the corresponding methods of the device are respectively the method for generating the cyclic redundancy check code and the data storage method in the previous embodiment, and the principle of solving the problem is similar to the method.

According to the cyclic redundancy check code generation device provided by the embodiment of the application, a first register and a second register are added for each bit of a target cyclic redundancy check code to be generated, wherein a first parameter of the first register is used for marking the bit of data participating in exclusive-or logic operation, and a second parameter of the second register is used for marking the bit of the current cyclic redundancy check code participating in exclusive-or logic operation, so that when the standard of the cyclic redundancy check code changes, the bit participating in operation is adjusted by changing the parameters in the first register and the second register, and the cyclic redundancy check code is suitable for the changed standard.

Fig. 4 shows a structure of a cyclic redundancy check code generation apparatus provided in an embodiment of the present application, including a parameter determination module 410, a logical operation module 420, and a generation module 430. The parameter determining module 410 is configured to obtain a first parameter of a first register and a second parameter of a second register corresponding to an i-th bit of a target cyclic redundancy check code to be generated. The logic operation module 420 is configured to determine a valid data bit and a valid check bit according to the first parameter and the second parameter, determine values of the valid data bit and the valid check bit according to the input data and the current cyclic redundancy check code, and perform an exclusive or logic operation on the values of the valid data bit and the valid check bit to generate a value of an ith bit of the target cyclic redundancy check code. The generating module 430 is configured to determine the target cyclic redundancy check code according to values of all bits of the target cyclic redundancy check code.

Where i represents any one bit, e.g., for an 8-bit target cyclic redundancy check code newcrc [7:0], which includes bits 0 to 7, newcrc [0], newcrc [1], newcrc [2], newcrc [3], newcrc [4], newcrc [5], newcrc [6], and newcrc [7], respectively. For each bit of the target cyclic redundancy check code, a corresponding set of registers may be set, for example, if the target cyclic redundancy check code has 8 bits, 8 sets of registers may be set, and each set of registers includes a first register and a second register.

The valid data bits are bits of the data that participate in the exclusive-or logic operation, i.e., several bits of the data that are marked by the first parameter. The first parameter may also be used to determine which bits of the input data participate in the xor logic operation in the current cycle when marking the bits of the data participating in the xor logic operation, and these determined bits are valid data bits.

In some embodiments of the present application, the determining of the valid data bit may be performed based on values of bits in the first parameter, that is, when a value of a jth bit in the first parameter meets a preset condition, the logic operation module determines the jth bit of the data as the valid data bit. Wherein j represents any one bit in the first parameter, for example, for a 4-bit first parameter Rd [3:0], the following 0 th to 3 Rd bits are included, Rd [0], Rd [1], Rd [2], and Rd [3 ]. For the 0 th bit, i.e. newcrc [0], in the 8-bit target cyclic redundancy check code newcrc [7:0], the first parameter of the corresponding first register is 2' b0101, i.e. the binary value 0101, so that Rd [0] ═ 1, Rd [1] ═ 0, Rd [2] ═ 1, and Rd [3] ═ 0 are known, and if the preset condition is that the value of the bit is 1, the data input in the current period is represented as din [3:0], it may be determined that the valid data bits of the data are the 0 th bit and the 2 nd bit, i.e. din [0] and din [2 ].

In some embodiments of the present application, the determining of the valid parity bit may be performed based on values of bits in the second parameter, that is, when the value of the kth bit in the second parameter meets a preset condition, the logic operation module determines that the kth bit of the data is the valid parity bit. Where k represents any bit of the second parameter, and includes, for example, the 0 th to 7 th bits, Rc [0], Rc [1], Rc [2], Rc [3], Rc [4], Rc [5], Rc [6], and Rc [7], for an 8-bit second parameter Rc [7:0 ]. For the 0 th bit, that is, newcrc [0], in the 8-bit target cyclic redundancy check code newcrc [7:0], the first parameter of the corresponding first register is 2' b01010000, that is, the binary value 0101000, so that Rc [0] ═ 0, Rc [1] ═ 0, Rc [2] ═ 0, Rc [3] ═ 0, Rc [4] ═ 1, Rc [5] ═ 0, Rc [6] ═ 1, and Rc [7] ═ 0 can be known, and if the preset condition is that the value of the bit is 1 and the current cyclic redundancy check code in the current period is expressed as c [7:0], the valid check bits of the data can be determined to be the 4 th and 6 th bits, that is, c [4] and c [6 ].

After the valid data bits and the valid check bits are determined, the logic operation module may calculate the value of the ith bit of the target cyclic redundancy check code. Using the aforementioned target cyclic redundancy check code newcrc [7:0]]Bit 0 newcrc [0] of (1)]For example, when the first parameter is 2'b0101 and the second parameter is 2' b01010000, the valid data bit of the data participating in the XOR logic operation is din [0]]And din [2]]And the valid parity bit of the current CRC code participating in the XOR logical operation is c [4]]And c [6]]From this, it can be seen that

Wherein the content of the first and second substances,

wherein the content of the first and second substances,

when the first parameter and the second parameter are changed, the valid data bit and the valid check bit participating in the operation are also changed, for example, when newcrc [0] is changed]Is 2' b1101, the corresponding valid data bit is din [0]、din[2]And din [3]]When newcrc [0]]The second parameter of (2' b)01010011, the corresponding valid parity bit is c [0]]、c[1]、c[4]And c [6]]At this time

newcrc[0]：Rd[3:0]＝2’b0101 Rc[7:0]＝2’b01010000

newcrc[1]：Rd[3:0]＝2’b1010 Rc[7:0]＝2’b10100000

newcrc[2]：Rd[3:0]＝2’b0100 Rc[7:0]＝2’b01000000

newcrc[3]：Rd[3:0]＝2’b1101 Rc[7:0]＝2’b11010000

newcrc[4]：Rd[3:0]＝2’b1010 Rc[7:0]＝2’b10100001

newcrc[5]：Rd[3:0]＝2’b0100 Rc[7:0]＝2’b01000010

newcrc[6]：Rd[3:0]＝2’b1101 Rc[7:0]＝2’b11010100

newcrc[7]：Rd[3:0]＝2’b1010 Rc[7:0]＝2’b10101000

In some embodiments of the present application, when the logic operation module performs an exclusive or logic operation on the values of the valid data bit and the valid check bit to generate the value of the ith bit of the target cyclic redundancy check code, a multi-stage processing manner may be adopted, that is, the values of the valid data bit and the valid check bit are subjected to a multi-stage exclusive or logic operation to generate the value of the ith bit of the target cyclic redundancy check code.

In addition, in order to improve processing efficiency, the parameter determining module may increase a bit width of the input data before acquiring the first parameter of the first register and the second parameter of the second register corresponding to the ith bit of the target cyclic redundancy check code to be generated, so that the processing in one period may calculate the corresponding target cyclic redundancy check code for more data.

In other embodiments of the present application, the generation scheme of the cyclic redundancy check code may also be applied to a cloud computing storage scenario, so that this embodiment may provide a data storage device, where the device includes a parameter determination module, a logic operation module, a generation module, and a sending module. After the parameter determining module, the logical operation module and the generating module adopt the target cyclic redundancy check code corresponding to the generated scheme data, the data and the target cyclic redundancy check code can be sent to the storage node by the sending module. After receiving the data and the corresponding target cyclic redundancy check code, the storage node may check the data according to the target cyclic redundancy check code, and after the check is completed, store the data.

In some embodiments of the present application, the apparatus for generating a cyclic redundancy check code may be implemented in the form of a logic circuit, and the structure of the logic circuit is as shown in fig. 5, and may include a data register 510, a current check code register 520, a target check code register 530, and N groups of generating circuits 540, where the value of N is the same as the bit width of the target check code register and the current check code register. Each group of generating circuits 540 includes a first register, a second register, an exclusive-or gate circuit, and a plurality of and gate circuits, where a bit width of the first register is the same as a bit width of the data register, and a bit width of the second register is the same as a bit width of the current check code register.

The xor gate circuit and the plurality of and gate circuits in the generating circuit realize a logic processing process based on the circuit structure shown in fig. 2, that is, the input end of the and gate circuit inputs the jth bit of the data register and the jth bit of the first register, or inputs the kth bit of the current check code register and the kth bit of the second register, the output end of the and gate circuit is connected to the input end of the xor gate circuit, and the output end of the xor gate circuit is output to the ith bit of the target check code register.

In some embodiments of the present application, a multi-stage xor operation mode may be adopted in each group of generating circuits to reduce the number of fan-ins during processing, and avoid that the frequency of the overall processing is affected by too many fan-ins. In this embodiment, each group of generating circuits includes a first register, a second register, a plurality of and gates, and an exclusive or gate divided into a plurality of stages. The xor gate circuit and the plurality of and gate circuits in the generating circuit realize the logic processing process based on the circuit structure shown in fig. 3, that is, the input end of the and gate circuit inputs the jth bit of the data register and the jth bit of the first register, or inputs the kth bit of the current check code register and the kth bit of the second register, the output end of the and gate circuit is connected with the input end of the xor gate circuit of the first stage, the output end of the xor gate circuit of each stage is connected with the input end of the xor gate circuit of the next stage, and the input end of the xor gate circuit of the last stage outputs the ith bit of the target check code register.

In addition, the generation device may further include an intermediate result register for storing an input value of the exclusive or gate circuit during the processing of the multi-stage exclusive or logic operation.

In an actual scenario, when a multi-stage logic operation is adopted, since one-stage calculation is performed in each clock cycle of the circuit, the generation efficiency of the cyclic redundancy check code is reduced. Therefore, the bit width of the input data can be adjusted, and after the bit width is increased, although the period for generating the target cyclic redundancy check code once is prolonged, the actual processing efficiency is not reduced due to the increase of the bit width of the input data.

In addition, some of the present application may be implemented as a computer program product, such as computer program instructions, which when executed by a computer, may invoke or provide methods and/or techniques in accordance with the present application through the operation of the computer. Program instructions which invoke the methods of the present application may be stored on a fixed or removable recording medium and/or transmitted via a data stream on a broadcast or other signal-bearing medium and/or stored within a working memory of a computer device operating in accordance with the program instructions. Some embodiments according to the present application include a computing device as shown in fig. 6, which includes one or more memories 610 storing computer-readable instructions and a processor 620 for executing the computer-readable instructions, wherein the computer-readable instructions, when executed by the processor, cause the device to perform the methods and/or aspects based on the embodiments of the present application.

Furthermore, some embodiments of the present application also provide a computer readable medium, on which computer program instructions are stored, the computer readable instructions being executable by a processor to implement the methods and/or technical solutions of the foregoing embodiments of the present application.

It should be noted that the present application may be implemented in software and/or a combination of software and hardware, for example, implemented using Application Specific Integrated Circuits (ASICs), general purpose computers or any other similar hardware devices. In an embodiment, the software program of the present application may be executed by a processor to implement the above steps or functions. Likewise, the software programs (including associated data structures) of the present application may be stored in a computer readable recording medium, such as RAM memory, magnetic or optical drive or diskette and the like. Additionally, some of the steps or functions of the present application may be implemented in hardware, for example, as circuitry that cooperates with the processor to perform various steps or functions.

It will be understood by those within the art that each block of the block diagrams and/or flowchart illustrations, and combinations of blocks in the block diagrams and/or flowchart illustrations, can be implemented by computer program instructions. Those skilled in the art will appreciate that the computer program instructions may be implemented by a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, implement the features specified in the block or blocks of the block diagrams and/or flowchart illustrations of the present disclosure.

Those of skill in the art will appreciate that various operations, methods, steps in the processes, acts, or solutions discussed in the present application may be alternated, modified, combined, or deleted. Further, various operations, methods, steps in the flows, which have been discussed in the present application, may be interchanged, modified, rearranged, decomposed, combined, or eliminated. Further, steps, measures, schemes in the various operations, methods, procedures disclosed in the prior art and the present invention can also be alternated, changed, rearranged, decomposed, combined, or deleted.

It will be evident to those skilled in the art that the present application is not limited to the details of the foregoing illustrative embodiments, and that the present application may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the application being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.

Claims

1. A method for generating cyclic redundancy check codes, wherein the method comprises the following steps:

2. The method of claim 1, wherein the first register has a same bit width as a bit width of data participating in an exclusive-or logic operation, and the second register has a same bit width as a bit width of a current cyclic redundancy check code participating in an exclusive-or logic operation;

determining valid data bits and valid check bits participating in operation according to the first parameter and the second parameter, including:

when the value of the jth bit in the first parameter meets a preset condition, determining the jth bit of the data as an effective data bit;

and when the value of the kth bit in the second parameter meets a preset condition, determining the kth bit of the current cyclic redundancy check code as an effective data bit.

3. The method of claim 1, wherein performing an exclusive-or logic operation on the values of the valid data bits and the valid check bits to generate a value of an ith bit of a target cyclic redundancy check code comprises:

and performing multi-stage XOR logic operation on the values of the effective data bit and the effective check bit to generate the value of the ith bit of the target cyclic redundancy check code.

4. The method of claim 3, wherein performing a multi-stage XOR logical operation on the values of the valid data bits and the valid check bits to generate a value of an ith bit of a target cyclic redundancy check code comprises:

dividing the values of the effective data bits and the effective check bits into a plurality of groups, and performing XOR logic operation on the values of the effective data bits and/or the effective check bits in each group to determine an intermediate operation result of each group;

and carrying out exclusive-OR logic operation on the intermediate operation results of all the groups to generate the value of the ith bit of the target cyclic redundancy check code.

5. The method according to claim 1, wherein before obtaining the first parameter of the first register and the second parameter of the second register corresponding to the ith bit of the target cyclic redundancy check code to be generated, the method further comprises:

the bit width of the input data is increased.

6. A method of data storage, wherein the method comprises:

7. An apparatus for generating a cyclic redundancy check code, wherein the apparatus comprises:

8. The apparatus of claim 7, wherein the first register has a same bit width as a bit width of data participating in an exclusive-or logic operation, and the second register has a same bit width as a bit width of a current cyclic redundancy check code participating in an exclusive-or logic operation;

the logic operation module is used for determining that the jth bit of the data is an effective data bit when the value of the jth bit in the first parameter meets a preset condition; and when the value of the kth bit in the second parameter meets a preset condition, determining the kth bit of the current cyclic redundancy check code as an effective data bit.

9. The apparatus of claim 7, wherein the logic operation module is configured to perform a multi-stage xor logic operation on the values of the valid data bits and the valid check bits to generate a value of an ith bit of the target cyclic redundancy check code.

10. The apparatus of claim 9, wherein the logic operation module is configured to divide the values of the valid data bits and the valid check bits into a plurality of groups, and perform an exclusive or logic operation on the values of each group including the valid data bits and/or the valid check bits to determine an intermediate operation result of each group; and carrying out exclusive-or logic operation on the intermediate operation results of all the groups to generate the value of the ith bit of the target cyclic redundancy check code.

11. The apparatus according to claim 7, wherein the parameter determining module is further configured to increase a bit width of the input data before acquiring the first parameter of the first register and the second parameter of the second register corresponding to an i-th bit of the target cyclic redundancy check code to be generated.

12. A data storage device, wherein the device comprises:

13. A computing device, wherein the device comprises a memory for storing computer program instructions and a processor for executing the computer program instructions, wherein the computer program instructions, when executed by the processor, trigger the device to perform the method of any of claims 1 to 6.

14. A computer readable medium having stored thereon computer program instructions executable by a processor to implement the method of any one of claims 1 to 6.

15. A cyclic redundancy check code generating device comprises a data register, a current check code register, a target check code register and N groups of generating circuits, wherein the value of N is the same as the bit width of the target check code register and the current check code register;

16. A cyclic redundancy check code generating device comprises a data register, a current check code register, a target check code register and N groups of generating circuits, wherein the value of N is the same as the bit width of the target check code register and the current check code register;

17. The apparatus of claim 14, wherein the apparatus further comprises an intermediate result register for storing an input value of the exclusive-or gate.