WO2007073695A1 - Circuit de traitement d'images analogiques pour capteur d'images cmos - Google Patents

Circuit de traitement d'images analogiques pour capteur d'images cmos Download PDF

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Publication number
WO2007073695A1
WO2007073695A1 PCT/CN2006/003645 CN2006003645W WO2007073695A1 WO 2007073695 A1 WO2007073695 A1 WO 2007073695A1 CN 2006003645 W CN2006003645 W CN 2006003645W WO 2007073695 A1 WO2007073695 A1 WO 2007073695A1
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Prior art keywords
input
output
positive
terminal
negative
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PCT/CN2006/003645
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English (en)
French (fr)
Inventor
Wenge Hu
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Byd Company Limited
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Priority claimed from CNB2005101214367A external-priority patent/CN100444613C/zh
Priority claimed from CNB2006100623135A external-priority patent/CN100574385C/zh
Application filed by Byd Company Limited filed Critical Byd Company Limited
Priority to US12/159,205 priority Critical patent/US8125548B2/en
Priority to EP06840681.8A priority patent/EP1971131B1/en
Publication of WO2007073695A1 publication Critical patent/WO2007073695A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H04N25/616—Noise processing, e.g. detecting, correcting, reducing or removing noise involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
    • H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H04N25/61—Noise processing, e.g. detecting, correcting, reducing or removing noise the noise originating only from the lens unit, e.g. flare, shading, vignetting or "cos4"
    • H04N25/615—Noise processing, e.g. detecting, correcting, reducing or removing noise the noise originating only from the lens unit, e.g. flare, shading, vignetting or "cos4" involving a transfer function modelling the optical system, e.g. optical transfer function [OTF], phase transfer function [PhTF] or modulation transfer function [MTF]
    • H04N25/6153—Noise processing, e.g. detecting, correcting, reducing or removing noise the noise originating only from the lens unit, e.g. flare, shading, vignetting or "cos4" involving a transfer function modelling the optical system, e.g. optical transfer function [OTF], phase transfer function [PhTF] or modulation transfer function [MTF] for colour signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H04N25/63—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to dark current
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H04N25/67—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to fixed-pattern noise, e.g. non-uniformity of response
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N3/00—Scanning details of television systems; Combination thereof with generation of supply voltages
    • H04N3/10—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical
    • H04N3/14—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical by means of electrically scanned solid-state devices
    • H04N3/15—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical by means of electrically scanned solid-state devices for picture signal generation
    • H04N3/155—Control of the image-sensor operation, e.g. image processing within the image-sensor
    • H04N3/1568—Control of the image-sensor operation, e.g. image processing within the image-sensor for disturbance correction or prevention within the image-sensor, e.g. biasing, blooming, smearing

Definitions

  • the present invention relates to a CMOS image sensor, and more particularly to a circuit for performing analog image signal processing in a CMOS image sensor. Background technique
  • CMOS image sensors are developing rapidly.
  • CMOS image sensing technology has replaced CCD sensing technology in the low-end image and video market.
  • CMOS image sensors have more CCD image sensors than CCD image sensors.
  • CMOS image sensors can also be used for military reconnaissance, satellite and other aspects.
  • the optocoupler can only sense the light intensity, can not sense the color information, and needs to pass the color filter to sense the color information.
  • Bayer filter which is a color array composed of three basic colors of RGB in a certain order, only on each pixel.
  • a color filter that covers one color allows only one color of the light permeable filter to be sensed by the photodiode and converted into an electrical signal. These signals are then sent in the direction of the column, and the analog voltage signal is obtained through the sampling circuit, and then sent to the analog signal processing circuit row by row.
  • an analog/digital converter is usually provided with an A/D converter to convert the analog image signal into a digital signal.
  • D-converters generally require a sampling speed of more than 20 , which is a high-speed ADC, and generally requires differential signal input.
  • the signal VIN from the image pixel array is single-ended, and the single-ended signal is changed to a differential signal in order to match the ADC.
  • differential operation has great advantages compared with single-ended operation. One of the important advantages is that it has environmental noise. There is a stronger anti-interference ability, another advantage is that it can increase the voltage swing. Therefore, differential work has become the main choice for contemporary high-performance analog circuits and mixed-signal circuits.
  • CMOS image sensor must first eliminate the FPN.
  • the traditional image sensor is to remove the FPN in the sampling circuit. This sampling circuit is called CDS Correlate Doubled Sampling, but this can only remove the noise caused by the unevenness of the circuit before the sampling circuit.
  • CDS Correlate Doubled Sampling This sampling circuit is called CDS Correlate Doubled Sampling, but this can only remove the noise caused by the unevenness of the circuit before the sampling circuit.
  • CDS Correlate Doubled Sampling CDS Correlate Doubled Sampling
  • color gain adjustment and exposure adjustment are usually performed in the analog signal processing circuit of the image sensor.
  • the black background value is not suitable, the gamma-corrected image is used. Contrast is greatly affected, so adjusting the black background value will give the gamma corrected image a better result.
  • the pixel signals are divided into two paths by parity and are respectively processed by two symmetric analog signal processing circuits, and then combined into the same ADC for analog-to-digital conversion.
  • Each analog signal processing circuit (A or B) processes pixel signals of two different colors.
  • different color signals through timing control, use a first-order switched capacitor circuit in the analog signal processing circuit structure to achieve different color gain control, exposure control and black background control, which increases the adjustment function of the processing circuit and reduces the image.
  • the noise, and the circuit structure is more simplified, reducing the chip area and reducing the cost.
  • the CDS is performed in each column, but the subtraction operation is the same for all odd columns or even columns, and all the odd or even CDSs are implemented at the corresponding analog signal processing circuit level.
  • the subtraction operation completely eliminates the FPN and is not affected by the unevenness of each column. Summary of the invention
  • the invention discloses an architecture and a circuit for analog image signal processing of a CMOS image sensor, comprising: transmitting different color optical signals of a pixel array in two ways, and converting the single-ended analog image signal into a differential signal for analog image signal processing.
  • the circuit-differential operational amplifier also includes a timing control circuit that divides the signal into two ways. See Figure 1 and Figure 2.
  • the architecture of the analog image signal processing divides a pixel array into two signals of different colors of A and B channels, A channel is connected to an odd column of the pixel array, and B channel is connected to an even column of the pixel array, and each channel
  • the signals received by the processing circuit are divided into odd and even lines to process exactly one different color signal per line.
  • the Row-Clock clock controls the row decoder for address decoding. We assume that the pixels in the first column and the first column of the pixel matrix are red.
  • the signal sent from the A channel to the analog signal processing circuit is the voltage signal of the red light (R).
  • the signal to the analog signal processing circuit is the green light (G) voltage signal.
  • the signal sent from the A channel to the analog signal processing circuit is the green light (G) voltage signal, and the B channel.
  • the signals sent to the analog signal processing circuit are all voltage signals of blue light (B).
  • B blue light
  • the analog image signal processing circuit (Fig. 2) - the output of the differential operational amplifier is used to connect an analog to digital converter, and further includes an input stage capacitor and an output stage capacitor, the input stage capacitor including a first positive input stage switched capacitor An array and a first negative input stage switched capacitor array; an input of the first positive input switched capacitor array is used to input an analog image signal, a control end is connected to the color gain control signal end, and an output end is coupled to the input of the differential operational amplifier
  • the input end of the first negative input switched capacitor array is used for inputting a reference level signal, the control end is connected to the color gain control signal end, and the output end is coupled to the input negative end of the differential operational amplifier; the output stage capacitor connection Between the differential op amp output and the input.
  • the input end of the first positive input switched capacitor array inputs the exposed analog image signal in the positive half cycle of the clock ClockA or ClockB, and inputs the analog image signal before the exposure in the negative half cycle of the clock ClockA or ClockB, ClockA and ClockB is a clock signal with equal frequency and opposite phase, as shown in Figure 3.
  • the output stage capacitor comprises a positive output stage switched capacitor array and a negative output stage switched capacitor array, the positive output stage switched capacitor array being connected to the output positive end of the differential operational amplifier And the input negative terminal, the negative output stage switched capacitor array is connected between the output negative terminal of the differential operational amplifier and the input positive terminal, and the control terminal of the positive and negative output stage switched capacitor array and the exposure gain control signal end Connected.
  • the input stage capacitor further includes a second positive input stage switched capacitor array and a second negative input stage switched capacitor array; the second positive input switched capacitor array input Terminal for inputting first offset voltage, output coupling The input is coupled to the input positive terminal of the differential operational amplifier; the input of the second negative input switched capacitor array is used to input a second offset voltage, and the output is coupled to the input negative terminal of the differential operational amplifier.
  • control terminal of the second positive input switched capacitor array and the control terminal of the second negative input switched capacitor array are also connected to the exposure gain control signal terminal.
  • the present invention also discloses an analog image signal processing circuit for a CMOS image sensor, comprising a differential operational amplifier for converting a single-ended analog image signal into a differential signal output, the output of the differential operational amplifier
  • the terminal is configured to connect the analog to digital converter, and further includes an input stage capacitor and an output stage capacitor, the input stage capacitor includes a second positive input stage switched capacitor array and a second negative input stage switched capacitor array; the second positive input switch An input end of the capacitor array is configured to input an analog image signal and a first offset voltage signal, and an output end is coupled to an input positive terminal of the differential op amp; and an input end of the second negative input switch capacitor array is used to input a second bias The voltage is shifted, and the output is coupled to the input negative terminal of the differential operational amplifier; the output stage capacitor is coupled between the output and the input of the differential operational amplifier.
  • the output stage capacitor comprises a positive output stage switched capacitor array and a negative output stage switched capacitor array, the positive output stage switching capacitor array being connected to the output positive end of the differential operational amplifier And the input negative terminal, the negative output stage switched capacitor array is connected between the output negative terminal of the differential operational amplifier and the input positive terminal, and the control terminal of the positive and negative output stage switched capacitor array and the exposure gain control signal end Connected.
  • the input end of the second positive input switched capacitor array and the control end of the second negative input switched capacitor array are connected to the exposure gain control signal end.
  • the input stage capacitor further includes a first positive input stage switched capacitor array and a first negative input stage switched capacitor array; the first positive input switched capacitor array input The end is used to input the analog image signal, and the control terminal The color gain control signal end is connected, and the output end is coupled to the input positive end of the differential operational amplifier; the input end of the first negative input switched capacitor array is used for inputting a reference level, and the control end is connected to the color gain control signal end, and the output end is connected Coupled to the input negative terminal of the differential op amp.
  • the A channel sent by the sampling circuit is a red light (R) voltage signal
  • the B channel sent by the sampling circuit is a green light (G) voltage signal
  • the analog signal processing circuit of the A channel can control the gain of the red light (R) by controlling the gain value of the color A
  • the analog signal processing circuit of the B channel can control the green by controlling the gain value of the color B.
  • the A signal is the green light (G)
  • the B channel is the blue light (B)
  • the color gain selection circuit A The analog signal processing circuit of the circuit can control the gain of the green light (G) by controlling the gain value of the color A.
  • the analog signal processing circuit of the B channel can control the gain of the blue light (B) by controlling the gain value of the color B. . Therefore, color gain control can be realized only by using a one-stage fully differential operational amplifier circuit. As shown in Figure 3. DRAWINGS
  • FIG. 1 is a block diagram of a signal processing architecture of the present invention
  • FIG. 2 is a block diagram of an analog image signal processing circuit in the present invention
  • FIG. 3 is a timing diagram of the present invention.
  • Figure 4 is a block diagram showing a preferred embodiment of the analog image signal processing circuit of the present invention.
  • FIG. 5 is a schematic illustration of the connection of the present invention to other external circuits. detailed description
  • the differential operational amplifier A1 is used to convert a single-ended analog image signal into a differential signal output, the output of which is connected to an analog-to-digital converter, and the input stage capacitor includes a first positive input stage switched capacitor array.
  • C4 consisting of capacitors C40...C4j...C45 in parallel
  • first negative input stage switched capacitor array C1 consististing of capacitors C10...Clj...C15
  • the input terminal d of the first positive input switched capacitor array C4 inputs an analog image signal VIN, the control terminal c is connected to the color gain control signal terminal b, and the output terminal is coupled to the input positive terminal IM> of the differential op amp A1; the first negative input
  • the input terminal a of the switched capacitor array C1 is input with a reference level VREF, the control terminal is connected to the color gain control signal terminal b, the output terminal is coupled to the input negative terminal INN of the differential operational amplifier A1, and the output stage capacitor includes a positive output stage switched capacitor array.
  • the positive output stage switched capacitor array C5 is connected between the output positive terminal of the differential op amp A1 and the input negative terminal
  • the negative output stage switched capacitor array C6 is connected between the output negative terminal of the differential op amp A1 and the input positive terminal.
  • the control terminals of the positive and negative output stage switched capacitor arrays C5 and C6 are also connected to the exposure gain control signal terminal g.
  • the input terminal f of the second positive input switched capacitor array C3 inputs a first offset voltage VOFFP, and the output terminal is connected to the input positive terminal of the differential operational amplifier A1; the input terminal e of the second negative input switched capacitor array C2 is input with a second bias The voltage is shifted to VOFFN, and the output terminal is connected to the input negative terminal of the differential op amp A1.
  • the second positive input switch The control terminal of the capacitor array C3 and the control terminal of the second negative input switch capacitor array C2 are also connected to the exposure gain control signal terminal g.
  • a fully differential operational amplifier is used, one end of which is connected to the signal VIN from the image sensor array, and the other end is connected to a fixed reference level VREF. According to the characteristics of the fully differential operational amplifier, the single-ended signal to the differential signal can be realized. Transform. Thus, the dynamic noise of the imaging chip can be better suppressed.
  • the signal after exposure to the pixel and the signal before exposure (complex The bit level is sampled separately and then subtracted to get a clean signal.
  • the positive half cycle of the clock ClockA or ClockB is input to the post-exposure signal VIN1
  • the negative half cycle of the clock ClockA or ClockB is input to the pre-exposure signal VIN2
  • the positive half cycle resets the entire circuit, and the difference ⁇ (VIN2-VIN1) of the two signals can be obtained in the negative half cycle of the clock, and the non-uniformity of the transistor characteristic parameters and other identical or related interference signals and noise can be removed. , thereby removing the fixed noise FPN.
  • Vout OUTP-OUTN
  • Vin AVIN
  • Voffset 2VOFFP-2 VOFFN
  • Cin is the total capacitance of the input stage
  • Cout is the total capacitance of the output stage.
  • VOFFP and VOFFN are the first offset voltage and the second offset voltage, respectively.
  • the gain of the signal can be adjusted, so by controlling the color gain control signal at different times of inputting different colors of red, green and blue signals, correspondingly Adjusting the first positive input stage switched capacitor array C4 and the first negative input stage switching capacitor array C1, and changing the magnitude of the input stage capacitance value, the gain of the three primary color signals of red, green and blue can be respectively adjusted, thereby realizing color gain. (color gain) control, so that the color difference signal is zero.
  • the signals sent from the A channel to the analog signal processing circuit are all red light signals, and the signals sent from the B channel to the analog processing circuit during the positive half cycle of the clock CLOCKB. Both are green light signals.
  • Vout Vin*(Cin/Cout) +Voffset
  • the gain of the red light signal of channel A is:
  • the positive half cycle of CLOCKA, and the signal sent from A channel to the analog signal processing circuit are all green light signals.
  • the signals sent from B channel to the analog processing circuit are all Blue light signal.
  • the gain of the blue light signal of channel B is:
  • Cin is After setting, the exposure gain control signal terminal g is used to adjust the positive output stage switched capacitor array C5 and the negative output stage switched capacitor array C6, and the output stage capacitance value is changed, and the gains of the three colors are changed, so that it can be simultaneously adjusted.
  • the gain of all color signals thus achieving global gain control, so that the brightness signal of the image reaches the target value.
  • the signals sent from the A channel to the analog signal processing circuit are all red light signals, and the signals sent from the B channel to the analog processing circuit are all green light signals.
  • the red light gain of channel A is:
  • the green light gain of road B is:
  • the red light gain of channel A is:
  • Vout/Vin- Cin/Cout+ Voffset/Vin Ci/2 4 Cout+ Voffset Vin,
  • the signals sent from the A channel to the analog signal processing circuit are all green light signals
  • B The signals sent to the analog processing circuit are all blue light signals.
  • the green light gain of road A is:
  • the blue light gain of channel B is:
  • the green light gain of road A is:
  • the blue light gain of channel B is:
  • Voffset Voffset
  • the Voffset can be adjusted by adjusting the DC levels of the first and second offset voltages VOFFP and VOFFN of the second positive input stage switched capacitor array C3 and the second negative input stage switched capacitor array C2.
  • the output value of the analog-to-digital converter ADC is adjusted so that the digital value of the black signal reaches an ideal value, thus achieving black level control.
  • the exposure gain is controlled by adjusting the positive output stage switched capacitor array C5 and the negative output stage switched capacitor array C6, if the second positive input stage switched capacitor array C3 and the second negative input stage switched capacitor array C2 are not moving, the offset voltage Voffset will be affected. Therefore, the control stages of the second positive input stage switched capacitor array C3 and the second negative input stage switched capacitor array C2 are also connected to the exposure control signal terminal g, so that the exposure control signal g simultaneously controls the second positive input stage switching capacitor. Array C3 and the second negative input stage switch capacitor array C2 to ensure that the black background of the image is unaffected.
  • the present embodiment realizes color gain adjustment, exposure gain adjustment, and black background control using the same circuit, and simultaneously eliminates dynamic noise and fixed pattern noise.
  • the function of the FPN is the function of the FPN.
  • the capacitances Clj, C2j, C3j, C4j and C5j, C6j, j of the input stage capacitor arrays C1, C2, C3, C4 and the output stage capacitor array C5, C6 can also be equal to 3, 4, 6, 7 corresponding color gain control and global gain control control bits are [3: 0], [4: 0], [6: 0], [7: 0].
  • the input stage capacitor may not include the second positive input stage switched capacitor array C3 and the second negative input stage switched capacitor array C2, and the offset voltages VOFFP, VOFFN may pass through the first positive input stage switched capacitor array, respectively.
  • C4 and the first negative input stage switched capacitor array C1 are input to the differential op amp A1 or not.
  • This embodiment utilizes the same circuit to achieve color gain adjustment and exposure gain adjustment while eliminating the effects of dynamic noise and fixed noise FPN.
  • the input stage capacitor may not include the first positive input stage switched capacitor array C4 and the first negative input stage switched capacitor array C1, and the analog image signal VIN is input to the differential through the second positive input stage switched capacitor array C3.
  • This implementation uses the same circuit to achieve color gain adjustment and black background control while eliminating the effects of dynamic noise and fixed noise FPN.
  • FIG. 5 is a schematic diagram of a preferred embodiment of the present invention connected to other circuits. It can be seen from the figure that the output of the analog processing circuit is connected to an analog-to-digital converter ADC, and the image signal processing circuit ISP (image signal process) outputs color according to the automatic adjustment function.
  • the gain signal b and the exposure gain signal g, the color gain signal b are respectively used to adjust the capacitance values of the first positive input stage switched capacitor array C4 and the first negative input stage switched capacitor array C1, thereby changing the input stage capacitance, thereby realizing Color gain control.
  • the exposure gain signal g is used to adjust the positive output stage switched capacitor array C5 and the negative output stage switched capacitor array C6, respectively, to achieve exposure gain control, and the offset voltages VOFFP and VOFFN are output by the black background control circuit and input to the second positive input stage, respectively.
  • the switched capacitor array C3 and the second negative input stage switched capacitor array C2 implement black background control.

Description

用于 CMOS图像传感器的模拟图像信号处理电路 技术领域
本发明涉及 CMOS图像传感器，尤其涉及 CMOS图像传感器中用于 进行模拟图像信号处理的电路。 背景技术
随着 CMOS工艺和固体图像传感器技术的不断完善， CMOS图像传 感器发展很快， CMOS 图像传感技术在低端图像和视频市场上已经取代 了 CCD传感技术， CMOS图像传感器比起 CCD图像传感器有低功耗、 宽动态范围， 高速视频、高集成度，低成本等优势，适用于微型数码相机， 便携式可视电话， 电脑摄像头等领域， CMOS 图像传感器还可以用于军 事侦察、 卫星等方面。
光电耦合器件只能感应光线强度， 不能感应色彩信息， 需要通过滤 色镜来感应色彩信息，我们称之为 Bayer滤色镜,它是由 RGB三种基色按 一定的顺序组成的色彩阵列， 每个像素上只覆盖一种颜色的滤色片， 只 允许一种颜色的光透过滤片被光电二极管感光并转成电信号。 这些电信 号再按列方向送出， 经过采样电路得到模拟电压信号， 然后逐行逐列地 被送到模拟信号处理电路。
为了方便后端的数字图像处理， 通常在模拟信号处理电路后面都带 有 A/D转换器,把模拟图像信号转换成数字信号。这种 D转换器一般要 求釆样速度在 20ΜΉζ以上，属于高速 ADC，一般要采用差分信号输入。 而 从图像像素阵列中出来的信号 VIN是单端的,为了跟 ADC相匹配， 要把 单端信号变成差分信号。 并且， 在模拟信号电路处理中， 差动工作与单 端工作相比有很大的优势， 其中一个重要的优势就在于它对环境噪声具 有更强的抗干扰能力， 另一个优势是可以增大电压摆幅。 所以差动工作 已经成为当代高性能模拟电路和混合信号电路的主要选择。
由于 CMOS 工艺存在缺陷， 晶体管特性参数及无源元件参数不均 匀， 所以在 CMOS 传感器中存在固定模式噪声 FPN (Fixed Pattern Noise) ， 它是 CMOS图像传感器中固有的噪声， 而人眼对这种噪声特别 敏感， 所以对传感器的图像质量影响特别大， 因此 CMOS图像传感器一 定要首先消除 FPN。 传统的图像传感器都是在采样电路实现去除 FPN， 这个采样电路称为相关双釆样 （CDS Correlate Doubled Sampling), 但是 这只能去除采样电路之前的电路的不均勾性所带来的噪声， 但是去除不 掉由于采样电路之后的各列电路中器件的差异所带来的 FPN噪声。
为了使 CMOS图像传感器拍出来的图像能正确反映景物的真实颜色 和亮度， 通常要在图像传感器的模拟信号处理电路中进行色彩增益调节 和曝光调节。
在后端的数字图像信号处理 ISP(image signal process)中，尤其是伽玛 校正 (gamma correction)—般需要确定黑色背景值 (black level), 黑色背景 值不合适的话， 经过伽玛校正后的图像对比度会受很大影响， 因此调整 黑色背景值就可以使伽玛校正后的图像达到一个较优的效果。
现有的 CMOS图像传感器技术， 在模拟信号处理电路中四种不同的 色彩信号分别采用四路电路或两级电路去实现色彩增益控制、 曝光控制、 黑色背景控制和消除固定噪声 FPN， 而且通常的消除固定噪声 FPN都是 在每一列内进行的， 因此消除的结果和每一列地电路的不均匀性相关， 也即不能完全消除 FPN。 其处理电路功能单一， 电路复杂， 所以导致芯 片的体积增大， 而在 IC市场竞争激烈的今天， 在成像效果不受影响的前 提下， 缩小体积， 降低成本， 已成为 CMOS图像传感器设计厂商竞争的 ° 为了解决上述问题， 本发明提出了一种不同的架构， 将像素信号按 奇偶列分两路， 分别由两路对称的模拟信号处理电路处理， 然后合并到 同一个 ADC作模数转换。 每路模拟信号处理电路 （A路 或 B路） 处理 两种不同颜色的像素信号。 这样， 不同色彩的信号， 通过时序控制， 在 模拟信号处理电路结构中用一级开关电容电路就实现了不同色彩增益控 制， 曝光控制和黑色背景控制， 增加了处理电路的调节功能， 降低了图 像的噪声， 并使电路结构更加简化， 缩小了芯片的面积， 降低了成本。 本发明的架构里， CDS在每列内进行， 但是其减法操作对所有奇列或偶 列来说都一样， 都是在对应的模拟信号处理电路这一级实现所有奇列或 偶列的 CDS减法运算， 从而彻底消除 FPN， 不受各列不均匀性的影响。 发明内容
本发明公开了一种用于 CMOS图像传感器的模拟图像信号处理的架 构和电路， 包括将像素阵列的不同色彩光信号分两路送出， 将单端模拟 图像信号转换成差分信号的模拟图像信号处理电路一差分运算放大器，还 包括将信号分两路处理的时序控制电路。 如图 1和图 2。
所述的模拟图像信号处理的架构将一个像素阵列按列划分为 A路和 B路两路不同色彩的信号， A路接像素阵列的奇数列， B路接像素阵列的 偶数列， 而每一路处理电路接收到的信号按奇偶行划分正好每一行处理 一种不同颜色信号。 Row-Clock时钟控制行解码器进行地址解码。我们假 设像素矩阵的第一行第一列的像素是红色， 那么当行地址解码送出第一 行时， A路送到模拟信号处理电路的信号都是红色光 (R)的电压信号， B 路送到模拟信号处理电路的信号都是绿色光 (G)的电压信号， 当行地址解 码送出第二行时， A路送到模拟信号处理电路的信号都是绿色光 (G)的电 压信号， B 路送到模拟信号处理电路的信号都是蓝色光 (B)的电压信号。 依次类推， 我们就可以分别将不同的色彩信号釆样并送到模拟信号处理 电路， 每一路需要处理两种颜色的信号， 而每一行的时间内处理的是同 一种颜色信号， 方便了模拟信号处理电路的色彩增益控制。 为控制色彩 增益， 我们只需在每行开始时对每路的色彩增益控制端口根据所在行的 色彩分别切换各自的增益值。
所述的模拟图像信号处理电路（图 2)—差分运算放大器的输出端用 于连接模数转换器， 还包括输入级电容和输出级电容， 所述输入级电容 包括第一正输入级开关电容阵列和第一负输入级开关电容阵列； 所述第 一正输入开关电容阵列的输入端用于输入模拟图像信号， 控制端与色彩 增益控制信号端相连， 输出端耦合至差分运算放大器的输入正端； 所述 第一负输入开关电容阵列的输入端用于输入参考电平信号， 控制端与色 彩增益控制信号端相连， 输出端耦合至差分运算放大器的输入负端； 所 述输出级电容连接在差分运放器输出端和输入端之间。
其中， 所述第一正输入开关电容阵列的输入端在时钟 ClockA或 ClockB的正半周期输入曝光后的模拟图像信号，在时钟 ClockA或 ClockB 的负半周期输入曝光前的模拟图像信号， ClockA和 ClockB是频率相等， 相位相反的时钟信号， 如图 3。
为了实现曝光控制， 本发明的进一步改进是： 所述输出级电容包括 正输出级开关电容阵列和负输出级幵关电容阵列， 所述正输出级开关电 容阵列连接在差分运算放大器的输出正端和输入负端之间， 所述负输出 级开关电容阵列连接在差分运算放大器的输出负端和输入正端之间， 所 述正、 负输出级开关电容阵列的控制端与曝光增益控制信号端相连。
为了实现黑色背景控制， 本发明的更进一步改进是： 所述输入级电 容还包括第二正输入级开关电容阵列和第二负输入级开关电容阵列； 所 述第二正输入开关电容阵列的输入端用于输入第一偏移电压， 输出端耦 合至差分运算放大器的输入正端； 所述第二负输入开关电容阵列的输入 端用于输入第二偏移电压， 输出端耦合至差分运算放大器的输入负端。
为了保证黑色背景在曝光调节时不变， 所述第二正输入开关电容阵 列的控制端和第二负输入开关电容阵列的控制端还与曝光增益控制信号 端相连。
为实现上述目的， 本发明还公开了一种用于 CMOS图像传感器的模 拟图像信号处理电路， 包括用于将单端模拟图像信号转换成差分信号输 出的差分运算放大器， 所述差分运算放大器的输出端用于连接模数转换 器， 还包括输入级电容和输出级电容， 所述输入级电容包括第二正输入 级开关电容阵列和第二负输入级开关电容阵列； 所述第二正输入开关电 容阵列的输入端用于输入模拟图像信号和第一偏移电压信号， 输出端耦 合至差分运放器的输入正端； 所述第二负输入开关电容阵列的输入端用 于输入第二偏移电压， 输出端耦合至差分运算放大器的输入负端； 所述 输出级电容连接在差分运算放大器输出端和输入端之间。
为了实现曝光控制， 本发明的进一步改进是： 所述输出级电容包括 正输出级开关电容阵列和负输出级开关电容阵列， 所述正输出级幵关电 容阵列连接在差分运算放大器的输出正端和输入负端之间， 所述负输出 级开关电容阵列连接在差分运算放大器的输出负端和输入正端之间， 所 述正、 负输出级开关电容阵列的控制端与曝光增益控制信号端相连。
为了保证黑色背景在曝光调节时不变， 所述第二正输入开关电容阵 列的输入端和第二负输入开关电容阵列的控制端与曝光增益控制信号端 相连。
为了实现色彩增益控制， 本发明的更进一步改进是： 所述输入级电 容还包括第一正输入级开关电容阵列和第一负输入级开关电容阵列； 所 述第一正输入开关电容阵列的输入端用于输入模拟图像信号， 控制端与 色彩增益控制信号端相连， 输出端耦合至差分运算放大器的输入正端； 所述第一负输入开关电容阵列的输入端用于输入参考电平， 控制端与色 彩增益控制信号端相连， 输出端耦合至差分运算放大器的输入负端。 当 地址解码电路送出像素矩阵的第一行的信号时， 采样电路送出的 A路是 红色光 (R)的电压信号， 釆样电路送出的 B 路是绿色光 (G)的电压信号， 经过色彩增益选择电路选， A路的模拟信号处理电路通过控制色彩 A的 增益值， 就可以控制红色光 (R)的增益， B路的模拟信号处理电路通过控 制色彩 B的增益值， 就可以控制绿色光 (G)的增益。 当地址解码电路送出 像素矩阵的第二行的信号时， A路送出的是绿色光 (G)的电信号， B路送 出的是蓝色光 (B)的电信号， 经过色彩增益选择电路， A路的模拟信号处 理电路通过控制色彩 A的增益值， 就可以控制绿光 (G)的增益， B路的模 拟信号处理电路通过控制色彩 B的增益值，就可以控制蓝色光 (B)的增益。 因此仅利用一级全差分运算放大电路就可以实现色彩增益控制。 如图 3。 附图说明
图 1是本发明的信号处理架构框图；
图 2是本发明中模拟图像信号处理电路的框图；
图 3是本发明的时序图；
图 4是本发明中模拟图像信号处理电路最佳实施例的框图;
图 5是本发明与其他外部电路的连接示意图。 具体实施方式
下面对本发明中每一路模拟处理电路的最佳实施例进行说明。如图 4 所示，差分运算放大器 A1用于将单端模拟图像信号转换成差分信号输出, 其输出端连接模数转换器， 输入级电容包括第一正输入级开关电容阵列 C4 (由电容 C40...C4j...C45并联组成）和第一负输入级开关电容阵列 C1 (由的电容 C10...Clj...C15并联组成）； 其中 C4j=Clj=2 Ci。 第一正输 入开关电容阵列 C4的输入端 d输入模拟图像信号 VIN，控制端 c与色彩 增益控制信号端 b相连， 输出端耦合至差分运放器 A1的输入正端 IM>; 第一负输入开关电容阵列 C1的输入端 a输入参考电平 VREF， 控制端与 色彩增益控制信号端 b相连， 输出端耦合至差分运放器 A1 的输入负端 INN;输出级电容包括正输出级开关电容阵列 C5 (由电容 C50...C5j...C55 并联组成）和负输出级开关电容阵列 C6 (由电容 C60...C6j...C65并联组 成）， 其中 C5j=C6j=2^'C0。 正输出级开关电容阵列 C5连接在差分运放器 A1 的输出正端和输入负端之间， 负输出级开关电容阵列 C6连接在差分 运放器 A1的输出负端和输入正端之间， 正、 负输出级开关电容阵列 C5、 C6的控制端还与曝光增益控制信号端 g相连。
输入级电容还可以进一步包括第二正输入级开关电容阵列 C3 (由电 容 C30...C3j...C35并联组成）和第二负输入级开关电容阵列 C2 (由电容 C20...C2j...C25并联组成）； 其中 C3j=C2j=2^Ci。第二正输入开关电容阵 列 C3的输入端 f输入第一偏移电压 VOFFP,输出端与差分运放器 A1的 输入正端相连；第二负输入开关电容阵列 C2的输入端 e输入第二偏移电 压 VOFFN, 输出端与差分运放器 A1的输入负端相连。 第二正输入开关 电容阵列 C3的控制端和第二负输入开关电容阵列 C2的控制端还与曝光 增益控制信号端 g相连。
本实施例采用了全差分运算放大器， 其一端接图像传感器阵列中出 来的信号 VIN, 另外一端接固定的参考电平 VREF, 根据全差分运算放大 器的特性， 就可以实现单端信号到差分信号的变换。这样成像芯片的动态 噪声可得到较好的抑制。
根据开关电容电路的特性，对像素曝光后的信号和曝光前的信号（复 位电平） 分别取样， 然后相减来得到干净的信号。 在第一正输入级开关 电容阵列 C4的输入端 d， 时钟 ClockA或 ClockB的正半周期输入曝光后 信号 VIN1， 时钟 ClockA或 ClockB的负半周期输入曝光前信号 VIN2, 根据电荷平衡原理， 在时钟正半周期对整个电路复位， 就可在时钟的负 半周期得到两个信号的差值 ΔνΐΝ (VIN2-VIN1 ), 就可以去掉晶体管特 性参数的不均匀性以及其它相同或相关的干扰信号和噪声， 从而去除固 定噪声 FPN。
上述电路的传递函数是： Vout=Vin*(Cin/Cout) +Voffset
其中， Vout=OUTP-OUTN, Vin=AVIN， Voffset=2VOFFP-2 VOFFN ， Cin为输入级的总电容， Cout 为输出级的总电容。 VOFFP、 VOFFN分别 为第一偏移电压和第二偏移电压。
从上式可以知道， 通过调节输入级电容阵列或输出级电容阵列的大 小， 就可以调节信号的增益大小， 所以通过控制色彩增益控制信号在输 入红、 绿、 蓝不同颜色信号的不同时刻相应地调节第一正输入级开关电 容阵列 C4和第一负输入级幵关电容阵列 Cl，改变输入级电容值的大小， 就可以分别调节红、 绿、 蓝三基色信号的增益大小， 从而实现色彩增益 (color gain)控制， 使色差信号为零。
当地址解码输出第一行时,在时钟 CLOCKA的正半周期， A路送到 模拟信号处理电路的信号都是红色光信号，在时钟 CLOCKB的正半周期， B路送到模拟处理电路的信号都是绿色光信号。
如果 A路的 color gain control[5 :0]= 101010， 贝 U
Cl=(25 + 23 + 2' )Ci, C4=( 25 + 23 + 21 )Ci；
如果 B路的 color gain control[5:0]=100100,则
Cl=(25 + 22)Ci, C4=(25 + 22)Ci,
所以此时 八路^ ^+ 1) ，
B路 Cin=Cl=(25 +22)Ci，
如果此时固定 global gain control[5:0]=000001,则 C5=C6=Co.
由公式 Vout=Vin*(Cin/Cout) +Voffset,
A路红色光信号的增益为：
Vout/Vin=Cin/Cout+Voffset/Vin=(25 +23 + 21 )Ci/Co+Voffset/Vin, B路绿色光信号的增益为：
Vout/Vin=Cin/Cout+Voffset/Vin=( 25 + 22)Ci/Co+Voffset/Vin。
当地址解码输出第二行时， CLOCKA 的正半周期， A路送到模拟信 号处理电路的信号都是绿色光信号， 在时钟 CLOCKB的正半周期， B路 送到模拟处理电路的信号都是蓝色光信号。
如果 A路的 color gain control[5:0]=100010,
则 Cl=(25 +21)Ci, C4=(25 +2')Ci;
如果 B路的 color gain control[5:0]=l 00001,
则 Cl=(25 +2°)Ci， C4=(25 +2°)Ci,
所以此时
A路 Cin=(25+2')Ci,
B路 Cin=Cl=(25 +20)Ci，
如果此时仍固定 global gain control[5:0]=000001,
则 A路绿色光信号的增益为：
Vout n=Cin/Cout+Voffset n=( 25 + 21 )Ci/Co+Voffset/Vin,
B路蓝色光信号的增益为：
Vout/Vin=Cin/Cout+VoffsetMn=( 25+2° )Ci/Co+Voffset/Vin。
因此实现了不同色彩的增益控制。 时序图见图 4 。
依旧从上面的传递函数可以知道， 在调节输入端电容之后， Cin就是 定值，再通过曝光增益控制信号端 g去调节正输出级开关电容阵列 C5和 负输出级开关电容阵列 C6，改变输出级电容值的大小,三种颜色的增益都 会改变，所以就可以同时调节所有颜色信号的增益大小， 从而实现曝光增 益 (global gain)控制， 使图像的亮度信号达到目标值。
当地址解码输出第一行时 , A路送到模拟信号处理电路的信号都是红 色光信号， B路送到模拟处理电路的信号都是绿色光信号。
固定 A路的 color gain control[5:0]=000001 ,
B路的 color gain control [5: 0]=0000010,
当 global gain control[5:0]= 100000时，
A路红色光增益为：
Vout/Vin= Cin/Cout+ Voffset/Vin=Ci/25 Cout+ Voffset/Vin,
B路绿色光增益为：
Vout/Vin= Cin/Cout+ Voffset/Vin=2' Ci/25 Cout+ Voffset/Vin。
当 global gain control[5:0]=010000时，
A路红色光增益为：
Vout/Vin- Cin/Cout+ Voffset/Vin=Ci/24 Cout+ Voffset Vin,
B路绿色光增益为-
Vout/Vin= Cin/Cout+ Voffset/Vin= 2' Ci/24 Cout+ Voffset/Vin <= 当地址解码输出第二行时， A路送到模拟信号处理电路的信号都是绿 色光信号， B路送到模拟处理电路的信号都是蓝色光信号。
固定 A路的 color gain control[5:0]=000001，
B路的 color gain control[5:0]=0000010,
当 global gain control[5:0]=100000时，
A路绿色光增益为： ·
Vout/Vin= Cin/Cout+ Voffset Vin=Ci/25 Cout+ Voffset Vin, B路蓝色光增益为：
Vout Vin= Cin/Cout+ Voffset/Vin=2' Ci/25 Cout+ Voffset/Vin。
当 global gain control[5:0]=010000时，
A路绿色光增益为：
Vout/Vin= Cin/Cout+ Voffset/Vin=Ci/ 24 Cout+ Voffset/Vin，
B路蓝色光增益为：
Vout/Vin= Cin/Cout+ Voffset/Vin=21 Ci/24 Cout+ Voffset/Vin0
所以即使 A路和 B路的 color gain control 不变，但是如果调整 global gain control,四种色彩的光信号都会随着改变。因此实现了曝光增益控制。
再由上述电路的传递函数 Vout=Vin*(Cin/Cout) +Voffset可以知道，, 当黑色信号 Vin(AVIN) 为零时，即像素曝光后的信号和曝光前的信号（复 位电平） 相等时， Vout= Voffset, 所以调节第二正输入级开关电容阵列 C3和第二负输入级开关电容阵列 C2的输入第一、二偏移电压 VOFFP和 VOFFN 的直流电平， 就可以调节 Voffset 的大小， 从而调节模数转换器 ADC 的输出数值， 使黑色信号的数字数值达到一个理想值， 这样就实现 了黑色背景控制 (black level control)。
在通过调节正输出级开关电容阵列 C5和负输出级开关电容阵列 C6 控制曝光增益时，如果第二正输入级开关电容阵列 C3和第二负输入级开 关电容阵列 C2不动， 则偏移电压 Voffset会受影响。 所以将第二正输入 级开关电容阵列 C3和第二负输入级开关电容阵列 C2的控制级也与曝光 控制信号端 g相连， 使曝光控制信号 g也同时同样地控制第二正输入级 开关电容阵列 C3和第二负输入级开关电容阵列 C2, 从而保证图像的黑 色背景不受影响。
从以上分析可知， 本实施例利用同一个电路实现了色彩增益调节、 曝光增益调节和黑色背景控制， 并同时消除动态噪声和固定模式噪声 FPN的功能。
当然， 最佳实施例中， 输入级电容阵列 C1,C2,C3， C4和输出级电容 阵列 C5,C6中的电容 Clj,C2j,C3j， C4j和 C5j,C6j，j还可以等于 3， 4， 6， 7相应的 color gain control和 global gain control的控制位为 [3 : 0]， [4： 0]， [6： 0]， [7： 0]。 当 j=3 时， 这种实施例的色彩增益控制和曝光增益 控制的调节阶数仅为 23 ; 当 j=4时，实施例的色彩增益控制和曝光增益控 制的调节阶数为 24；当 j=6时实施例的色彩增益控制和曝光增益控制的调 节阶数位 26；当 j=7时实施例的色彩增益控制和曝光增益控制的调节阶数 位 27。 J值越大， 色彩增益控制和曝光增益控制的分辨率就越高。
最佳实施例中， 输入级电容也可以不包括第二正输入级开关电容阵 列 C3和第二负输入级开关电容阵列 C2， 偏移电压 VOFFP、 VOFFN可 以分别通过第一正输入级开关电容阵列 C4 和第一负输入级开关电容阵 列 C1输入到差分运放器 A1或不输入。 这种实施方式利用同一个电路实 现了色彩增益调节和曝光增益调节， 并同时消除动态噪声和固定噪声 FPN的功能。
最佳实施例中， 输入级电容也可以不包括第一正输入级开关电容阵 列 C4和第一负输入级开关电容阵列 Cl， 模拟图像信号 VIN通过第二正 输入级开关电容阵列 C3输入到差分运放器 A1的输入正端。 这种实施方 式利用同一个电路实现了色彩增益调节和黑色背景控制， 并同时消除动 态噪声和固定噪声 FPN的功能。
图 5 是本发明的最佳实施例与其它电路连接的示意图， 从图中可知 模拟处理电路的输出端连接模数转换器 ADC， 图像信号处理电路 ISP(image signal process)根据自动调节功能输出色彩增益信号 b和曝光增 益信号 g， 色彩增益信号 b分别用来调节第一正输入级开关电容阵列 C4 和第一负输入级开关电容阵列 C1的电容值， 从而改变输入级电容， 实现 色彩增益控制。 曝光增益信号 g分别用来调节正输出级开关电容阵列 C5 和负输出级开关电容阵列 C6， 实现曝光增益控制， 偏移电压 VOFFP、 VOFFN由黑色背景控制电路输出， 分别输入到第二正输入级开关电容阵 列 C3和第二负输入级开关电容阵列 C2， 实现黑色背景控制。

Claims

权利要求书
1、一种用于 CMOS图像传感器的模拟图像信号处理电路，包括用于 将单端模拟图像信号转换成差分信号输出的差分运放器， 所述差分运放 器的输出端用于连接模数转换器， 其特征在于： 还包括输入级电容和输 出级电容， 所述输入级电容包括第一正输入级幵关电容阵列和第一负输 入级开关电容阵列； 所述第一正输入开关电容阵列的输入端用于输入模 拟图像信号， 控制端与色彩增益控制信号端相连， 输出端耦合至差分运 放器的输入正端； 所述第一负输入开关电容阵列的输入端用于输入参考 电平信号， 控制端与色彩增益控制信号端相连， 输出端耦合至差分运放 器的输入负端； 所述输出级电容连接在差分运放器输出端和输入端之间。
2、 如权利要求 1所述的处理电路， 其特征在于： 所述第一正输入开 关电容阵列的输入端在时钟的正半周期输入曝光后的模拟图像信号， 在 时钟的负半周期输入曝光前的模拟图像信号。
3、 如权利要求 1所述的处理电路， 其特征在于： 所述输出级电容包 括正输出级开关电容阵列和负输出级开关电容阵列， 所述正输出级开关 电容阵列连接在差分运放器的输出正端和输入负端之间， 所述负输出级 开关电容阵列连接在差分运放器的输出负端和输入正端之间， 所述正、 负输出级开关电容阵列的控制端与曝光增益控制信号端相连。
4、 如权利要求 1至 3中任一项所述的处理电路， 其特征在于： 所述 输入级电容还包括第二正输入级开关电容阵列和第二负输入级开关电容 阵列； 所述第二正输入开关电容阵列的输入端用于输入第一偏移电压， 输出端耦合至差分运放器的输入正端； 所述第二负输入开关电容阵列的 输入端用于输入第二偏移电压， 输出端耦合至差分运放器的输入负端。
5、 如权利要求 4所述的处理电路， 其特征在于： 所述第二正输入开 关电容阵列的控制端和第二负输入开关电容阵列的控制端还与曝光增益 控制信号端相连。
6、一种用于 CMOS图像传感器的模拟图像信号处理电路，包括用于 将单端模拟图像信号转换成差分信号输出的差分运放器， 所述差分运放 器的输出端用于连接模数转换器， 其特征在于： 还包括输入级电容和输 出级电容， 所述输入级电容包括第二正输入级开关电容阵列和第二负输 入级开关电容阵列； 所述第二正输入开关电容阵列的输入端用于输入模 拟图像信号和第一偏移电压信号， 输出端耦合至差分运放器的输入正端; 所述第二负输入开关电容阵列的输入端用于输入第二偏移电压， 输出端 耦合至差分运放器的输入负端； 所述输出级电容连接在差分运放器输出 端和输入端之间。
7、 如权利要求 5所述的处理电路， 其特征在于： 所述输出级电容包 括正输出级开关电容阵列和负输出级开关电容阵列， 所述正输出级开关 电容阵列连接在差分运放器的输出正端和输入负端之间， 所述负输出级 开关电容阵列连接在差分运放器的输出负端和输入正端之间， 所述正、 负输出级开关电容阵列的控制端与曝光增益控制信号端相连。
8、 如权利要求 7所述的处理电路， 其特征在于： 所述第二正输入开 关电容阵列的输入端和第二负输入开关电容阵列的控制端与曝光增益控 制信号端相连。
9、 如权利要求 6至 8中任一项所述的处理电路， 其特征在于： 所述 输入级电容还包括第一正输入级开关电容阵列和第一负输入级开关电容 阵列； 所述第一正输入开关电容阵列的输入端用于输入模拟图像信号， 控制端与色彩增益控制信号端相连， 输出端耦合至差分运放器的输入正 端； 所述第一负输入开关电容阵列的输入端用于输入参考电平， 控制端 与色彩增益控制信号端相连， 输出端耦合至差分运放器的输入负端。 10， 一种用于 CMOS图像传感器的模拟图像信号处理电路， 包括用 于将单端模拟图像信号转换成差分信号输出的差分运放器， 所述差分运 放器的输出端用于连接模数转换器， 其特征在于： 还包括连接在差分运 放器输入级、 用于输入模拟图像信号的输入级电容和输出级电容， 所述 输出级电容包括正输出级开关电容阵列和负输出级开关电容阵列， 所述 正输出级幵关电容阵列连接在差分运放器的输出正端和输入负端之间， 所述负输出级开关电容阵列连接在差分运放器的输出负端和输入正端之 间， 所述正、 负输出级开关电容阵列的控制端还与曝光增益控制信号端 相连。
PCT/CN2006/003645 2005-12-29 2006-12-28 Circuit de traitement d'images analogiques pour capteur d'images cmos WO2007073695A1 (fr)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102625060A (zh) * 2011-01-31 2012-08-01 海力士半导体有限公司 用于移动式应用的cmos图像传感器的动态范围扩展

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102104744B (zh) * 2011-03-04 2013-01-16 北京思比科微电子技术股份有限公司 Cmos图像传感器像素读出电路结构及像素结构
JP2012222529A (ja) * 2011-04-06 2012-11-12 Sony Corp 固体撮像素子および駆動方法、並びに電子機器
TWI501643B (zh) * 2013-07-29 2015-09-21 Uchange Technology Co Ltd 基於互補式金氧半導體之影像感測系統及其方法
US9734703B1 (en) 2016-06-23 2017-08-15 Nxp B.V. Sensor apparatuses and methods
CN109103209B (zh) * 2018-08-22 2024-04-16 苏州多感科技有限公司 一种图像传感器及其制备方法、电子设备
KR102523383B1 (ko) 2018-11-16 2023-04-19 엘지디스플레이 주식회사 포토 센서가 내장된 표시패널과 이를 이용한 표시장치

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020134918A1 (en) * 2001-02-19 2002-09-26 Takashi Miida Changeable gain amplifier, solid-state imaging device and optical signal reading method
CN2718905Y (zh) * 2003-06-11 2005-08-17 深圳源核微电子技术有限公司 信号压缩器
CN1671077A (zh) * 2004-03-15 2005-09-21 清华大学 一种用于微型飞行器的摄像与图像传输系统

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4555668A (en) 1983-10-14 1985-11-26 American Microsystems, Inc. Gain amplifier
JP3203290B2 (ja) 1994-03-31 2001-08-27 富士写真フイルム株式会社 ディジタル電子スチル・カメラおよびメモリ・カードへの記録方法
US6529237B1 (en) 1997-12-02 2003-03-04 Texas Instruments Incorporated Complete CDS/PGA sample and hold amplifier
JP3663973B2 (ja) 1999-05-06 2005-06-22 日本電気株式会社 画像信号処理装置および画像信号処理方法
US6617567B2 (en) * 2001-06-22 2003-09-09 Texas Instruments Incorporated Analog pre-processor with improved input common mode range
JP2003052048A (ja) 2001-08-07 2003-02-21 Olympus Optical Co Ltd 撮像素子、撮像装置および撮像方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020134918A1 (en) * 2001-02-19 2002-09-26 Takashi Miida Changeable gain amplifier, solid-state imaging device and optical signal reading method
CN2718905Y (zh) * 2003-06-11 2005-08-17 深圳源核微电子技术有限公司 信号压缩器
CN1671077A (zh) * 2004-03-15 2005-09-21 清华大学 一种用于微型飞行器的摄像与图像传输系统

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP1971131A4 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102625060A (zh) * 2011-01-31 2012-08-01 海力士半导体有限公司 用于移动式应用的cmos图像传感器的动态范围扩展

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