WO2007067860A2 - Contacts sans vide à faible résistance - Google Patents

Contacts sans vide à faible résistance Download PDF

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Publication number
WO2007067860A2
WO2007067860A2 PCT/US2006/061351 US2006061351W WO2007067860A2 WO 2007067860 A2 WO2007067860 A2 WO 2007067860A2 US 2006061351 W US2006061351 W US 2006061351W WO 2007067860 A2 WO2007067860 A2 WO 2007067860A2
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WIPO (PCT)
Prior art keywords
conductive material
openings
dielectric layer
conductive
opening
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PCT/US2006/061351
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English (en)
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WO2007067860A3 (fr
Inventor
Masaaki Higashitani
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Sandisk Corporation
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Publication date
Priority claimed from US11/296,235 external-priority patent/US7737483B2/en
Priority claimed from US11/296,022 external-priority patent/US7615448B2/en
Application filed by Sandisk Corporation filed Critical Sandisk Corporation
Priority to EP06848514A priority Critical patent/EP1958252A2/fr
Publication of WO2007067860A2 publication Critical patent/WO2007067860A2/fr
Publication of WO2007067860A3 publication Critical patent/WO2007067860A3/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region

Definitions

  • This invention relates to flash memory arrays and in particular to the structures of flash memory arrays and methods of forming them.
  • CMOS complementary metal-oxide-semiconductor
  • CF CompactFlashTM
  • MMC MultiMedia cards
  • SD Secure Digital
  • Smart Media cards Smart Media cards
  • P-Tag personnel tags
  • Memory Stick cards Memory Stick cards.
  • Hosts include personal computers, notebook computers, personal digital assistants (PDAs), various data communication devices, digital cameras, cellular telephones, portable audio players, automobile sound systems, and similar types of equipment.
  • PDAs personal digital assistants
  • a memory system is permanently connected to a host providing an embedded memory that is dedicated to the host.
  • NOR and NAND Two general memory cell array architectures have found commercial application, NOR and NAND.
  • memory cells are connected between adjacent bit line source and drain diffusions that extend in a column direction with control gates connected to word lines extending along rows of cells.
  • a memory cell includes at least one storage element positioned over at least a portion of the cell channel region between the source and drain. A programmed level of charge on the storage elements thus controls an operating characteristic of the cells, which can then be read by applying appropriate voltages to the addressed memory cells.
  • a NAND array series strings of more than two memory cells, such as 16 or 32, are connected along with one or more select transistors between individual bit lines and a reference potential to form columns of cells.
  • Word lines extend across cells within a large number of these columns.
  • An individual cell within a column is read and verified during programming by causing the remaining cells in the string to be turned on hard so that the current flowing through a string is dependent upon the level of charge stored in the addressed cell.
  • An example of a NAND architecture array and its operation as part of a memory system is found in the following United States patents: 5,570,315; 5,774,397; 6,046,935 and 6,522,580.
  • NAND memory devices have been found to be particularly suitable for mass storage applications such as those using removable memory cards.
  • the charge storage elements of current flash EEPROM arrays as discussed in the foregoing referenced patents, arc most commonly electrically conductive floating gates, typically formed from conductively doped polysilicon material.
  • An alternate type of memory cell useful in flash EEPROM systems utilizes a non-conductive dielectric material in place of the conductive floating gate to store charge in a nonvolatile manner.
  • a triple layer dielectric formed of silicon dioxide, silicon nitride and silicon oxide (ONO) is sandwiched between a conductive control gate and a surface of a semi-conductive substrate above the memory cell channel.
  • the cell is programmed by injecting electrons from the cell channel into the nitride, where they are trapped and stored in a limited region, and erased by injecting hot holes into the nitride.
  • Increased data density can also be achieved by reducing the physical size of the memory cells and/or the overall array.
  • Shrinking the size of integrated circuits is commonly performed for all types of circuits as processing techniques improve over time to permit implementing smaller feature sizes. But there are usually limits of how far a given circuit layout can be shrunk in this manner, since there is often at least one feature that is limited as to how much it can be shrunk. When this happens, designers will turn to a new or different layout or architecture of the circuit being implemented in order to reduce the amount of silicon area required to perform its functions. The shrinking of the above-described flash EEPROM integrated circuit systems can reach such limits.
  • STI Shallow Trench Isolation
  • This uses STI structures to isolate adjacent strings of floating gate cells such as those of NAND type memory arrays.
  • a gate dielectric (tunnel dielectric) layer and floating gate polysilicon layer arc formed first.
  • STI structures are formed by etching the gate dielectric and floating gate polysilicon layers and the underlying substrate to form trenches. These trenches are then filled with a suitable material (such as oxide) to form STI structures.
  • a suitable material such as oxide
  • the STI structures have a width that is equal to the minimum feature size that can be produced with the processing technology used.
  • STI structures are also generally spaced apart by the minimum feature size.
  • the portions of the gate dielectric and floating gate polysilicon layers between STI regions may also have a width that is equal to the minimum feature size.
  • the strips of floating gate polysilicon are further formed into individual floating gates in later steps.
  • floating gates may have dimensions less than the minimum feature size that can be produced using photolithographic patterning alone. Examples of scheme for forming such floating gates are provided in U.S. Patent 6,888,755. [0009] Tn NAND and other types of nonvolatile memories, the amount of field coupling between floating gates and the control gates passing over them (the coupling ratio) is carefully controlled.
  • the amount of coupling determines how much of a voltage that is placed on the control gate is coupled to the underlying floating gates.
  • the percentage coupling is determined by a number of factors including the amount of surface area of the floating gate that overlaps a surface of the control gate. It is often desired to maximize the percentage coupling between the floating and control gates by maximizing the amount of overlapping area.
  • Yuan ct al in United States Patent No. 5,343,063. The approach described in that patent is to make the floating gates thicker than usual to provide large vertical surfaces that may be coupled with the control gates.
  • Individual portions of a memory array are generally connected together using conductive lines that extend across the memory array.
  • Some conductive lines may be connected to portions of the substrate so that electrical connections are made to those portions.
  • such connections are made by forming an opening in a dielectric layer that overlies the substrate and forming a conductive plug by filling the opening with a conductive material such as a metal or doped polysilicon.
  • a conductive material such as a metal or doped polysilicon.
  • the lateral dimensions of such plugs generally shrink along with other memory features.
  • the vertical dimensions of such plugs may not shrink in proportion. This may be because the thickness of floating gates remains high, or for other reasons.
  • the aspect ratio of an opening is the ratio of the height of the opening to a lateral dimension.
  • Figure 1 shows an opening 101 in a dielectric layer 103 on a substrate 105, opening 103 having a lateral dimension (width) of Xl and a height of Yl.
  • the aspect ratio of opening 101 is Yl/Xl.
  • the width of an opening used to form a contact may be 70nanometers or less.
  • the thickness of the dielectric layer may be 3000Angstroms (300nanometers) or more.
  • Plugs are generally made by depositing a conductive material so that the material fills an opening. However, where openings have high aspect ratios, the deposited material may not fill an opening fully. In some cases, voids are formed in the conductive material deposited in an opening.
  • Figure 2 shows an example of an opening having an aspect ratio of Y2/X2 that has conductive material deposited in it to form a plug 210. However, within plug 210, a void 212 is formed " because of the depth of the opening. Deposition near the top of the opening closes the opening before the lower part is completely filled so that void 212 is incorporated in plug 210.
  • Such voids may cause device failure by increasing the electrical resistance of the plug, preventing current flow and causing heating.
  • Some materials have good filling characteristics that allow good quality plugs to be formed even in openings having high aspect ratios. However, some of the materials that allow void-free plugs have relatively high resistivity so that the resistance of the plug is increased, which is undesirable. Certain formation techniques also have better filling characteristics than others.
  • a composite plug is formed of a first conductive material deposited to partially fill an opening and a second conductive material that fills the remaining portion of the opening.
  • the first material is chosen to have good filling characteristics so that no voids are formed in the first material even in an opening having a high aspect ratio.
  • the remaining portion of the opening has a reduced aspect ratio. This remaining portion is then filled using a second conductive material that has low resistivity so that the plug has a low overall resistance.
  • the thickness of the first material is chosen so that, after the first material is deposited, the remaining portion of the opening has an aspect ratio that is calculated to be the maximum, or near the maximum that can be filled by the second material without producing voids.
  • the thickness of the second material is made large where possible, while the thickness of the first material is made small. This provides low resistance because the resistivity of the second material is less than the resistivity of the first material.
  • low resistance, void-free plugs may be formed at either end of a NAND string in openings having high aspect ratios. Plugs at either end may be formed simultaneously. At one end of such. NAND strings, plugs are electrically connected together by a common source line. At the other end of such NAND strings, connection is made to bitlines that extend over strings.
  • Figure 1 shows a cross-section of an opening in a dielectric layer overlying a substrate of the prior art.
  • Figure 2 shows a cross-section of a prior art plug formed in an opening, the plug containing a void.
  • Figure 3A shows a cross-section of a high aspect ratio opening.
  • Figure 3B shows the opening of Figure 3 A partially filled by a first conductive material, with an unfilled remaining portion.
  • Figure 3C shows the opening of Figure 3B with the remaining portion filled by a second conductive material.
  • Figure 4 shows a cross-section of a NAND string formed by floating gate cells and select gates formed over a portion of a substrate covered by a dielectric layer.
  • Figure 5 shows the structure of Figure 4 having high aspect ratio openings formed in the dielectric layer.
  • Figure 6 shows the structure of Figure 5 with a first conductive material deposited in the openings to partially fill the openings, leaving unfilled portions of the openings.
  • Figure 7 shows the structure of Figure 6 with a second conductive material deposited in the openings to fill the previously unfilled portions of the openings.
  • Figure 8 shows the structure of Figure 7 after excess first conductive material and second conductive material are removed leaving plugs in. openings.
  • Figure 9 shows the structure of Figure 8 with a second dielectric layer overlying the first dielectric material and the plugs.
  • Figure 10 shows the structure of Figure 9 after the second dielectric layer is patterned to have openings aligned to the plugs.
  • Figure 11 shows the structure of Figure 10 with conductive material deposited in the openings in the second dielectric layer so that drain plugs are extended and source plugs are connected together by a common source line.
  • Figure 12 shows the structure of Figure 11 with a third dielectric layer formed over the second dielectric layer and a bitline formed over the third dielectric layer, the bitline connected to the drain side of the NAND string.
  • Figure 13 shows a top-down view of the structure of Figure 13 with strings extending in the Y-direction and wordlines, select lines and a common source line extending in the X-direction.
  • Figure 14 shows a circuit diagram corresponding to the circuit formed by the structure of Figures 12 and 13.
  • Figure 3A shows a cross-section of a portion of a substrate 320, a dielectric layer 332 overlying substrate 320 and an opening 324 in dielectric layer 322 that extends to a surface 326 of substrate 320.
  • Opening 324 has a width of X3 and a height of Y3.
  • the aspect ratio of opening 324 is Y3/X3.
  • Figure 3B shows a cross-section of substrate 320 and dielectric layer 322 after deposition of a first conductive material to form first conductive portion 328 in opening 324.
  • First conductive material is deposited in opening 324 to a thickness of Y4.
  • First conductive material is generally also deposited on top surface 330 of the dielectric layer 322 during this deposition, though material on top surface 330 may subsequently be removed. Some of the first conductive material may also deposit on sidewalls of opening 324, though this is not shown in Figure 3B.
  • a material used as first conductive material may be chosen to provide good, void-free deposition in high aspect ratio openings even though it may have higher resistivity than other materials.
  • first conductive material may be chosen to have adequate filling characteristics for an opening having aspect ratio Y3/X3.
  • Doped polysilicon deposited using Low Pressure Chemical Vapor Deposition (LPCVD) or other means is an example of such a material.
  • LPCVD Low Pressure Chemical Vapor Deposition
  • opening 324 is filled to a height of Y4, leaving a depth of Y5 still unfilled.
  • unfilled portion 325 of opening 324 has an aspect ratio of Y5/X3 after deposition of first conductive material.
  • Aspect ratio Y5/X3 is less than the original aspect ratio of Y3/X3.
  • Figure 3C shows a cross-section after deposition of a second conductive material to form second conductive portion 332 in the unfilled portion 325 of opening 324.
  • the second conductive material may be chosen for its electrical properties such as low resistivity.
  • the second conductive material has lower resistivity than the first conductive material.
  • the second conductive material may have poorer filling characteristics than the first conductive material.
  • second conductive material may be a material that would not provide good, void free deposition if used alone to fill an opening having an aspect ratio Y3/X3.
  • the second conductive material has good enough filling properties to fill unfilled portion 325 of the opening 324 after first conductive portion 328 is deposited, i.e.
  • second conductive material can give good, void free deposition in an opening having an aspect ratio of Y5/X3.
  • the second conductive material may be a metal, for example a refractory metal such as tungsten or some other metal such as aluminum.
  • First conductive portion 328 and second conductive portion 332 together form a composite plug 334 that fills opening 324.
  • Composite plug 334 formed by first conductive portion 328 and second conductive portion 332 has lower resistance than would be provided by a plug of similar dimensions formed by the first conductive material alone. Unlike a plug formed of the second conductive material alone, composite plug 334 does not suffer from voids. Thus, there are significant advantages over plugs formed from a single material.
  • opening 324 as shown Figures 3A-3C has smooth vertical sides
  • real openings may have irregular sides and may not be vertical.
  • the different layers may have different etching characteristics causing some layers to be etched back further than others.
  • An overhang may be formed where a layer is etched less than the layer below it. Such irregularities make filling an opening more difficult.
  • Plugs are generally used to connect to either end of a string of memory cells in such memories.
  • a string is formed by a series of floating gate cells connected by doped regions of the substrate.
  • Figure 4 shows a cross-section of an exemplary NAND string 440 at an intermediate stage of memory array fabrication.
  • Four floating gate memory cells are formed by four control gates 442a-442d, overlying four floating gates 444a-444d, with floating gates 444a-444d overlying channel regions 446a-446d.
  • Source and drain regions 448a-448g are shown in the substrate connecting memory cells together to form the string.
  • a first select gate 450 is shown near one end of string 440.
  • First select gate 450 consists of two parts 450a and 450b corresponding to floating gate and control gate layers respectively. Parts 450a, 450b are electrically connected together.
  • First select gate 450 may be considered the drain select gate.
  • a second select gate 452 is shown near the other end of NAND string 440.
  • Second select gate 452 may be considered to be a source select gate.
  • Second select gate 452 consists of two parts 452a and 452b corresponding to floating gate and control gate layers respectively. Parts 452a, 452b are electrically connected together. However, select gates are not floating, but are connected by select lines extending across the array. In an alternative arrangement, a select gate may be formed by a single conductive portion.
  • Select gates 450, 452 are used to control the voltage applied to the memory cells of NAND string 440.
  • a dielectric layer 454 covers floating gates 444a-444d, control gates 442a-442d and select gates 450, 452 and the underlying substrate 456.
  • Dielectric layer 454 may consist of a single material or two or more layers of different dielectric materials, which may be deposited at different times during the formation of NAND string 440.
  • Dielectric layer 452 may be considered a single body for electrical purposes, providing isolation for NAND string 440.
  • a typical material used to form a dielectric layer is Boro-Phospho-Silicate Glass (BPSG).
  • BPSG Boro-Phospho-Silicate Glass
  • a dielectric layer is comprised of approximately 2500Angstroms of BPSG overlying approximately 500 Angstroms of Silicon Nitride (SiN).
  • FIG. 5 shows NAND string 440 of Figure 4 after formation of openings 560, 562 in dielectric layer 454. Openings 560, 562 are formed at either end of NAND string 440 at locations adjacent to source select gate 452 and drain select gate 450. Openings 560, 562 may be formed by providing a patterned mask layer over dielectric layer 454, the mask layer having openings that are aligned to the desired locations of openings in dielectric layer 454. An anisotropic etch is then used to remove dielectric in the pattern established by the mask layer. Anisotropic etching may be Reactive Ion Etching (RIE) or another technique. Openings 560, 562 are formed so that they extend all the way to the surface of substrate 456.
  • RIE Reactive Ion Etching
  • impurities may be introduced into the exposed portion of the substrate.
  • N- type impurities such as Arsenic or Phosphorous are implanted to lower the resistivity of implanted regions 564, 566 of substrate 456.
  • impurities may be diffused.
  • P-type impurities such as Boron may also be used in some cases. In some examples, no impurities are introduced at this point.
  • doped polysilicon may be deposited in openings 560, 562 and some dopant from the polysilicon diffuses into the region below the opening to provide a sufficient doping level in this area. Even where doped polysilicon is not used, implantation of dopants may not always be necessary.
  • Tungsten is commonly used to fill openings and form plugs to contact a substrate. Tungsten has low resistivity allowing the formation of low resistance structures and is also capable of withstanding subsequent high temperature processing. However, in some designs, particularly newer designs with smaller features, the aspect ratio of the openings may be too high to form good plugs using Tungsten. Doped polysilicon is another conductive material that may be used to fill openings and form plugs. Polysilicon deposited by LPCVD generally forms good, void-free plugs even where openings have high aspect ratios. However, polysilicon has a higher resistivity than Tungsten, so polysilicon structures have higher resistance than similar Tungsten structures. To overcome these limitations, a composite plug is formed of polysilicon and Tungsten deposited in sequence.
  • Figure 6 shows NAND string 440 of Figure 5 after deposition of a first conductive material in openings 560, 562 and across the surface of dielectric layer 454.
  • the first conductive material forms conductive portions 670, 672 in openings 560, 562 and forms first conductive layer 674 on dielectric layer 454.
  • the first conductive material is polysilicon in this example, though other materials may also be used.
  • Polysilicon may be deposited in a furnace or by other suitable means. Polysilicon is doped so that it has a low resistivity. Polysilicon may be deposited so that it directly overlies substrate 456 in openings 560, 562.
  • a clean step may be performed prior to deposition of polysilicon to remove any native oxide or other material present on substrate 456 in openings 560, 562.
  • Deposition of polysilicon is stopped before openings 560, 562 are filled with polysilicon.
  • Polysilicon deposition may be stopped when the thickness of first conductive portions 670, 672 in openings 560, 562 has reached a predetermined thickness. The predetermined thickness can be calculated so that remaining unfilled portions 676, 678 of openings 560, 562 have aspect ratios that allow them to be adequately filled by tungsten.
  • Figure 7 shows NAND string 440 of Figure 6 after deposition of a second conductive material to form second conductive layer 780.
  • the second conductive material is Tungsten in this example, though other materials may also be used.
  • the second conductive material fills the unfilled portions 676, 678 of openings 560, 562 and extends across the first conductive layer 674.
  • a barrier layer Prior to deposition of Tungsten, a barrier layer (not shown) may be deposited prior to deposition of Tungsten.
  • the barrier layer may be deposited prior to deposition of Tungsten.
  • the barrier layer may be a composite
  • the second conductive material may be deposited directly on the first conductive material or a different barrier layer may lie between the first conductive material and the second conductive material.
  • Figure 8 shows NAND string 440 of Figure 7 after removal of excess first and second conductive material.
  • First conductive layer 674 is removed and second conductive layer 780 deposited over first conductive layer 674 is removed to the level of the top of dielectric layer 454, leaving second conductive portions 882, 884.
  • First and second conductive material may be removed by Chemical Mechanical Polishing (CMP) or by etching back or other means.
  • CMP Chemical Mechanical Polishing
  • CMP is used because it provides a planarized surface that is desirable for subsequent steps.
  • Remaining first conductive portions 670, 672 and second conductive portions 882, 884 form plugs 886, 888.
  • Plugs 886, 888 have lower resistance than would be provided by plugs of polysilicon alone.
  • Plugs 886, 888 are also void-free even though openings 560, 562 may have a higher aspect ratio than could normally be filled by Tungsten alone.
  • FIG 9 shows NAND string 440 of Figure 8 after deposition of a second dielectric layer 990 overlying first dielectric layer 454 and second conductive portions 882, 884.
  • Second dielectric layer 990 of this example is a Silicon Dioxide (SiO 2 ) layer, formed by Chemical Vapor Deposition (CVD) using Tetraethyl Orthosilicate, Si(OC 2 Hs) 4 (TEOS). Other dielectric materials may also be used.
  • SiO 2 Silicon Dioxide
  • CVD Chemical Vapor Deposition
  • TEOS Tetraethyl Orthosilicate
  • Other dielectric materials may also be used.
  • Figure 10 shows NAND string 440 of Figure 9 after patterning of second dielectric layer 990.
  • An opening 992 is formed in second dielectric layer 990 over second conductive portion 882. Opening 992 has roughly the same lateral dimensions as second conductive portion 882.
  • An opening 994 is also formed in second dielectric layer 990 over second conductive portion 884. However, opening 994 extends wider than second conductive portion 884 along the direction of NAND string 440 as shown in Figure 10. In addition, opening 994 extends in a direction perpendicular to the cross-section shown in Figure 10 so that it overlies plugs of multiple strings.
  • Openings 992, 994 are formed by a single process using a single mask that is aligned so that openings 992, 994 are positioned over second conductive portions 882, 884.
  • Figure 1 1 shows NATMD string 440 of Figure 10 after deposition and planarization of a third conductive layer to form conductive portions 1102, 1104.
  • conductive portions 1102, 1104 are formed of the same material as second conductive portions 882, 884 (in this example - Tungsten).
  • Drain plug 886 is extended in the vertical direction as a result of this step.
  • Source plug 888 is connected by this step to other source contact plugs of other strings (not shown in Figure 11) by conductive portion 1104.
  • Figure 12 shows NAISfD string 440 of Figure 11 after subsequent formation of a third dielectric layer 1210, a bitline 1212 and an additional conductive portion 1214 connecting drain plug 886 to bitline 1212.
  • Third dielectric layer 1210 may be formed of Silicon Dioxide (SiO 2 ).
  • Third dielectric layer 1210 may be formed by High Density Plasma (HDP), plasma enhanced deposition, using TEOS or in some other manner.
  • Additional conductive portion 1214 may be Aluminum, Copper, Tungsten or other suitable conductive material.
  • Bitline 1212 is generally formed of a conductive material such as Aluminum or Tungsten.
  • the combination of drain plug 886 and additional conductive portion 1214 that together connect one end of the NAND string 440 to bitline 1212 maybe referred to as a "bitline contact.”
  • Figure 13 shows a top-down view of NAND string 440 of Figure 12 and shows additional NAND strings 1320, 1322. While three strings 440, 1320, 1322 of four floating gate cells each are shown, actual memory arrays may have 8, 16, 32 or more floating gate cells in a string and thousands of strings may extend in two dimensions across a substrate. Individual strings 440, 1320, 1322 are separated by STT regions 1324a-1324d that extend on either side of strings 440, 1320, 1324. Wordlines 1326a-1326d (indicated by broken lines) overlie floating gates of different strings forming control gates (for example, control gates 442a-442d of NAND string 440) where they overlie floating gates.
  • Source/drain implanted regions for example source/drain implanted regions 448a-448g of NAND string 440
  • Source/drain implanted regions 448a-448g of NAND string 440 are shared by adjacent memory cells and provide electrical connection between memory cells of a NAND string.
  • Select lines 1328, 1330 extend parallel to wordlines 1326a- 1326d across strings 440, 1320, 1322, forming select gates (such as select gates 450, 452 of NAND string 440) where they overlie channel regions of NAND strings.
  • Plugs 886, 888 of NAND string 440 are shown in top-down view extending from implanted regions at either end of NAND string 440.
  • Source contact plugs 888, 1332, 1334 of NAND strings 440, 1320, 1322 are shown connected together by conductive portion 1104 (common source line) formed as shown in Figure 11.
  • Common source line 1104 extends parallel to wordlin.es 1326a-1326d and select lines 1328, 1330.
  • Figure 14 shows a circuit diagram for NAND strings 440, 1320, 1322 of Figure 13.
  • Figure 14 shows bitlines 1212, 1450, 1452 (not shown in Figure 13) extending in the same direction as NAND strings 440, 1320, 1322.
  • Bitlines 1212, 1450, 1452 are formed over strings 440, 1320, 1322 respectively, as shown in cross-section in Figure 12.

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Abstract

Un bouchon est formé par dépôt d'un premier matériau en vue du remplissage partiel d'une ouverture de façon qu'il reste une partie non remplie présentant un rapport de forme inférieur à celui de l'ouverture initiale. Un second matériau est alors déposé en vue du remplissage de la partie restante de l'ouverture. Le premier matériau présente de bonnes caractéristiques de remplissage mais une résistivité supérieure à celle du second matériau. Le second matériau présente une faible résistivité, ce qui confère une faible résistance au bouchon.
PCT/US2006/061351 2005-12-06 2006-11-29 Contacts sans vide à faible résistance WO2007067860A2 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP06848514A EP1958252A2 (fr) 2005-12-06 2006-11-29 Contacts sans vide à faible résistance

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US11/296,235 2005-12-06
US11/296,022 2005-12-06
US11/296,235 US7737483B2 (en) 2005-12-06 2005-12-06 Low resistance void-free contacts
US11/296,022 US7615448B2 (en) 2005-12-06 2005-12-06 Method of forming low resistance void-free contacts

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EP1530237A2 (fr) * 2003-11-10 2005-05-11 Kabushiki Kaisha Toshiba Mémoire non-volatile à sémiconducteur
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CN108766969B (zh) * 2017-04-13 2023-10-13 三星电子株式会社 制造半导体存储器装置的方法

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TWI332252B (en) 2010-10-21

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