TWI332252B - Low resistance void-free contacts - Google Patents

Description

1332252 IX. Description of the Invention: [Technical Field] The present invention relates to a flash memory array, and more particularly to a structure of a flash memory array and a method of forming the same. [Prior Art] There are many commercially successful non-volatile memory products used today, especially in the form of miniaturized cards, which use a flash EEPROM (electrically erasable and programmable only) Memory) cell array. Such cards can interface with the host by, for example, removably inserting a card into a card slot in the host. Some commercially available cards are C〇mpactFiashTM (cF) cards, multimedia cards (MMC), secure digital (SD) cards, Smart Media cards, personal tags (P-tags), and Memory Stick cards. Hosts include personal computers, notebook computers, personal digital assistants (PDAs), various data communication devices, digital cameras, cellular phones, portable audio players, car sound systems, and similar types of devices. In an alternative configuration of the split card and the host, in some examples, a memory system is permanently connected to a host and provides an embedded memory dedicated to the host. There are two general memory cell array architectures that have been applied in the commercial, namely NOR and NAND. In the typical! In the scale array, the memory cell is connected between the adjacent bit line source and the drain diffusion region and extends in the row direction, wherein the control gate is connected to the word line extending along the cell column. A suffix body το includes at least one storage element located at least over a portion of the cell channel region between the source and the drain. The programmed charge levels on the storage elements thus control the operational characteristics of the cells, and the cells can be read by applying an appropriate voltage to the addressed memory cells by U6809.doc 1332252. Examples of such units, their use in memory systems, are manufactured in the following US patents: 5 〇7〇〇32; 5 〇95, m 5,313'42!; 5'315 '541; 5 343, 〇 63; 5 66ι as and • 6,222,762. These patents, together with all other patents, patents and other publications referred to in this application, are hereby incorporated by reference in its entirety for all purposes. • In a pair of 〇 arrays, a string of more than two memory cells (eg, 16 or 32) connected between the individual bit lines and the - reference potential with the same or multiple select transistors Form a unit row. The word line extends across a large number of cells within the row. By making the remaining cells in the string hard-on so that the t-stream that flows through -_ depends on the level of charge stored in the addressed location, it is possible to read # and confirm a particular cell in a row during stylization - An example of a N-Architecture array and a portion of its operation into a memory system can be found in the following U.S. patents: mow; y, 7' 6'° 46, 935 and 6, 522, 58. The NAND memory device has been found to be particularly well suited for mass storage applications, such as those utilizing removable memory cards. • Current charge storage elements of flash EEPROM (10) arrays, as discussed in the previously cited patents, are the most common conductive floating closed electrodes, which are typically formed of conductively doped polycrystalline materials. An alternative type of memory cell that can be used in the pR〇M system is to replace the conductive floating gate with a non-conductive dielectric material to store charge in a non-volatile manner. The three-layer dielectric system formed by the dioxide, the nitrite, and the oxidized stone is sandwiched into a 116809.doc 1332252 conductive control gate and the memory cell channel - a semiconductive substrate Between the surfaces. Stylized by electrons injecting the nitride from the cell channel, in which the electrons are intercepted and stored in a confined region: and are injected by injecting a thermal cavity into the nitride. Erase. A number of special cell structures and arrays utilizing dielectric storage elements are described in U.S. Patent No. 6,925,007. ^

As in most integrated circuit applications, the flash EEpR〇M system also has the 矽 substrate area pressure required to reduce the performance of some integrated circuit functions, and the increase can be stored in the -shixi substrate. Given surface

The amount of digital data in the product to increase the storage capacity of a given size memory card and other package types, or to increase capacity and size at the same time. The method of increasing the storage density of the shell material is that the memory unit stores a plurality of data bits. This is achieved by dividing one window of a floating gate charge level range into two or more states. Four such states are used such that each cell can store two data bits, the ethical state can store three data bits 70 per cell, and so on. A multi-state flash EEpR 〇M structure and operating system is described in U.S. Patent Nos. 5,514,94, and 5,172,338, each incorporated herein by reference. Increased data density can also be obtained by reducing the physical size of the memory cells and/or the entire array. Since processing techniques are improved over time to allow for smaller feature sizes, the reduction in integrated circuit size can generally be performed for all types of circuits. However, this approach can often result in a given circuit layout. The extent to which it is reduced is limited because there are often at least one feature that is limited by H6809.doc 1332252 in terms of how much it can be reduced. Once this happens, the designer will seek to implement a new or different layout or architecture of the circuit in order to reduce the amount of area required to perform the function of the circuit, the flash EEPROM integrated circuit system described above. Shrinking may hit these limits. One way to form small cells is to use a self-aligned shallow trench isolation (STI) technique. This would utilize the 811 structure to isolate adjacent floating gate cells', such as those belonging to a NAND type memory array. According to this technique, a gate dielectric (via dielectric) layer and a floating gate polysilicon layer are first formed. Next, the STI structure is formed by etching the gate dielectric and the floating gate polycrystalline layer and the underlying substrate to form a trench. Subsequently, the trenches are filled with a suitable material (e.g., oxide) to form an STI structure. The portions of the gate dielectric and floating gate polysilicon layers between the STI structures are defined by the STI structures and thus can be considered to be self-aligned to the STI structures. In general, the sti structures will have a width that is comparable to the smallest feature size that can be produced by the processing techniques employed. STI structures are also typically separated by this minimum feature size. Thus, the portion of the gate dielectric and floating gate polysilicon layer between the STI regions may also have a width equal to the minimum feature size. The strips of the floating gate polysilicon will further form individual juice gates in a later step. In some examples, the 'floating gate' may have a size that can be fabricated using only lithographic patterning that is smaller than the minimum feature size. An example of a solution for forming such a floating gate is set forth in U.S. Patent No. 6,888,755. In NAND and other non-volatile memory types, the amount of electric field coupling (coupling ratio) between the floating gate and the control gate over which 116809.doc 1332252 passes is controlled to be small. The amount of coupling determines how much of the voltage at the control gate will be lightly coupled to the lower floating gate. The percentage face is determined by a number of factors, including the amount of surface area over which the floating gate overlaps the surface of the control gate. It is often desirable to maximize the percentage coupling between the floats and the control gates by maximizing the amount of overlap area. A method for increasing the coupling area is described in U.S. Patent No. 5,343,063 to Yuan et al. The method described in this patent will cause the floating gates to be thicker than the large vertical surfaces typically used to provide coupling to the control gates. Individual portions of a memory array (e.g., a NAND array string) are typically connected together using conductive lines extending across the memory array. A portion of the conductive lines can be attached to portions of the substrate to enable electrical connection to the portions. Generally, such a connection is formed by forming an opening in a dielectric layer covering the substrate and forming a conductive plug by filling the opening with a conductive material such as a metal or doped polysilicon. Due to memory shrinkage, the lateral dimensions of such plugs typically shrink along with other memory features. However, the vertical dimensions of such plugs may not shrink in proportion. This may be because the thickness of the floating gate is still high, or for other reasons. The aspect ratio of an opening is the ratio of the height of the opening to the lateral dimension. 1 shows an opening ιοί in a dielectric layer 103 on a substrate 105. The opening 1〇1 has a lateral dimension (width) of XI and a height of Y1. The aspect ratio of the opening 1〇1 is Y1/XI. In general, U6809.doc •10· 1332252 is used due to memory shrinkage.

The aspect ratio of the opening forming the contacts to the lower substrate is increased because the vertical dimensions are not scaled down relative to the lateral dimensions. In some of the more novel devices, the width of the opening used to form a joint may be 7 〇 1 m or less. The thickness of the dielectric layer can be 3,000 angstroms (3 angstroms) or more = an increase in the aspect ratio can present certain problems at the joints that form good quality. The plug is typically made by depositing a conductive material such that the material fills the opening. However, in the case where the opening has a high aspect ratio, the deposited material may not completely fill an opening. In some cases, voids are formed in the conductive material deposited in an opening. Figure 2 shows an example of an opening having an aspect ratio of Y2/X2 which deposits a conductive material in its body to form a plug 210. However, in the plug 21, a gap 212 is formed due to the depth of the opening. The deposition near the top of the opening closes the opening before completely filling the lower portion so that the void 2丨2 is contained in the plug 210. Such voids can cause device failure by increasing the electrical impedance of the plug, impeding current and generating heat. Some materials have good filling characteristics that can form good quality plugs even in openings with high aspect ratios. However, such portions of the material capable of producing a void-free plug have a relatively high impedance such that the impedance of the plug is increased, which is not desirable. Some forming techniques also have better filling characteristics than other techniques. Therefore, there is a need for a method of forming a conductive plug in such a manner that a void-free plug can be formed even in the case of a high aspect ratio opening. There is also a need for a method of forming such a plug such that it has a lower overall impedance. There is also a need for a method of forming such contacts in an efficient manner as part of the formation of a memory array. There is also a need for a void-free plug having a low impedance of 116809.doc 1332252 and for a memory array having such a plug. SUMMARY OF THE INVENTION A composite plug is formed by a first conductive material deposited to partially fill an opening and a second conductive material that fills the remainder of the open D. The first material having good filling characteristics is selected such that no voids are formed in the first material even in a high aspect ratio opening:

After depositing the first material and partially filling the opening, the remaining portion of the opening has a reduced aspect ratio. This remainder is then filled with a material having a low resistance m; such that the plug has a low overall impedance.

The void-free, low-impedance plug selects the thickness of the first material such that after depositing the first material, the remainder of the opening has - calculated as a maximum, or near maximum = can be produced without voids The second material is filled to fill the aspect ratio. Therefore, the thickness of the second material becomes larger as the case may be, and the thickness of the first material becomes smaller. This provides low impedance because the impedance of the second material is less than the impedance of the first material. In a NAND flashback delta recall array, a low impedance, void free plug can be formed at either end of a NAND string in an opening having a high aspect ratio. Plugs at the end = can be formed simultaneously. At one end of such a Nand string, the plugs are electrically connected together by a common source line. At the other end of the nand string, a connection is made to the bit lines extending over the string. [Embodiment] FIG. 3A shows a section of a substrate 32 一 a dielectric layer 116809.doc • 12- 1332252 322 covering the substrate and a section 324 extending into the opening 324 of the surface 326 of the substrate 320 in the dielectric layer 322. . The opening 324 has a width of X3 and a height of Υ3. Therefore, the aspect ratio of the opening 324 is Υ3/χ3. 3B shows a section of the substrate 320 and the dielectric layer 322 after deposition of a first conductive material to form the first conductive portion 328 in the opening 324. The first conductive material is deposited in the opening 324 to a thickness of γ4. . The first conductive material is also typically deposited on the top surface 330 of the dielectric layer 322 during this > however, the material on the top surface 330 can then be removed. Portions of the first electrically conductive material may also be deposited on the sidewalls of the opening 324, however this is not shown in Figure 3A. A material that provides good, void-free deposition in the high aspect ratio opening can be selected as the first conductive material, even though it may have higher resistance than other materials. In particular, a first electrically conductive material having suitable filling characteristics for an opening having an aspect ratio Υ3/Χ3 can be selected. An example of a doped polysilicon system deposited using low pressure chemical vapor deposition (LpcvD) or other methods. After depositing the first conductive portion 328, the opening 324 is filled to a height of ¥4 and leaves a depth of Y5 that is still unfilled. Thus, the unfilled portion 325 of the opening 324 has an aspect ratio of γ5/χ3 after deposition of the first conductive material. The aspect ratio Υ5/Χ3 is less than the initial aspect ratio of Υ3/Χ3. Figure 3C shows a cross section after depositing a second conductive material to form a second conductive portion 332 in the unfilled portion 325 of the opening 324. The second conductive material can be selected for its electronic properties such as low impedance. The second electrically conductive material has a lower resistance than the first electrically conductive material. There may be a filling characteristic that is inferior to the first conductive material. Example = \ 16809.doc •13- 丄幻2252

The material may be a material that does not provide good, void-free deposition if it is used to fill an opening having an aspect ratio y3/X3. However, the second conductive material has a sufficiently good filling characteristic to fill the unfilled portion 325 of the opening 324 after depositing the first conductive portion 328, that is, the second conductive material may have an opening having an aspect ratio of Y5/X3 Produces good, void-free deposits. The second electrically conductive material can be a metal such as a refractory metal such as tungsten or some other metal such as aluminum. The first conductive portion 328 and the second conductive portion 332 together form a composite plug 334 that will fill the opening 324. The composite plug 334 formed by the first conductive portion 328 and the second conductive portion 332 has a lower impedance than would be provided by a similarly sized plug formed separately from the first conductive material. Unlike the plug formed by the second conductive material alone, the composite plug 334 does not create a void. There are therefore many distinct advantages over plugs formed from a single material. Although the openings 324 shown in Figures 3A through 3C have smooth vertical sides, the actual openings may have irregular sides and may not be vertical. In particular, in the case where an opening is formed by penetrating a plurality of dielectric layers, the different layers may have different etching characteristics, causing partial layers to further etch back than other layers. In the case where the layer is less etched than the layer below it, a protrusion may be formed which makes it difficult to fill the opening. A specific application where a good, low impedance, void-free plug is required. The substrate is contacted in the hidden device. In particular, NAND flash memory devices continue to become smaller and faster, and the aspect ratio of the openings used to form the plugs continues to increase, requiring such plugs to have a low impedance but no voids. The plug is typically used to connect to the memory of the memory type 116809.doc. A string is formed by a series of floating gate cells connected to the doped regions of the substrate. Figure 4 shows a cross section of an exemplary NAND string 440 at an intermediate stage of memory array fabrication. The four floating gate memory cells are formed by four control gates 442a through 442d that cover the four floating gates 444a through 444d, and the floating gates 444a through 444d cover the channel regions 446a through 446d. The source and drain regions 448a through 448g shown in the substrate connect the memory cells together to form the string. A first select gate 450 is shown adjacent one end of the NAND string 440. The first selection gate 450 is composed of two portions 450a and 450b, which respectively correspond to the floating gate and the control gate layer. Portions 450a, 450b are electrically connected together. The first selection gate 450 can be considered as a drain selection gate. A second select gate 452 is shown adjacent the other end of the NAND string 440. The second select gate 452 can be considered as a source select gate. The second selection gate 452 is composed of two portions 452a and 452b, which respectively correspond to the floating gate and the control gate layer. Portions 452a, 452b are electrically connected together. However, the selection gates are not continuously floating, but are connected by a selection line extending across the array. In an alternative configuration, a select gate can be formed from a single conductive portion. The select gates 450, 452 are used to control the voltage applied to the memory cells of the NAND string 440. A dielectric layer 454 covers the floating gates 444a through 444d, the control interpoles 442a through 442d and the select gate 450' 452 and the lower substrate 456. Dielectric layer 454 may be comprised of a single material or two or more layers of different dielectric materials that may be deposited at different times during formation of NAND string 440. Dielectric layer 452 can be considered as a single body for electronic purposes, which provides isolation of NAND string 440. A typical material used to form a dielectric layer is borophosphonate glass filled (BPSG). In one example, a dielectric layer comprises a BPSG of about 2500 angstroms covering approximately 5 angstroms of tantalum nitride (SiN). FIG. 5 shows the NAND string 440 of FIG. 4 after the openings 560, 562 are formed in the dielectric layer 454. Openings 560, 562 are formed at either end of NAND string 440 adjacent the source select gate 452 and drain select gate 450. The openings 560, 562 can be formed by providing a patterned mask layer on the dielectric layer 454 having an opening aligned with the desired opening location of the dielectric layer 454. An anisotropic etch is then used to remove the dielectric in the pattern created by the mask layer. The anisotropic etch can be reactive ion etching (RIE) or other techniques. Openings 56, 562 are formed to extend all the way to the surface of the substrate 456. After the openings 560, 562 are formed, impurities may be introduced into the exposed portions of the substrate. Typically, N-type impurities such as arsenic or phosphorous are implanted to reduce the impedance of the implanted regions 564, 566 of the substrate 456. Or 疋, the impurities can be diffused. P-type impurities such as boron can also be used in some cases. In some examples, no impurities are introduced at this time. Thereafter, doped polysilicon can be deposited in openings 560, 562, and a portion of the dopant from the polysilicon will diffuse into the region under the opening to provide sufficient doping levels in this region. Implantation of dopants is not always necessary even in the absence of turning (8). A crane-like system that fills the opening and forms a plug to contact the substrate. Cranes have low resistance to form low-impedance structures and are also able to withstand subsequent high-temperature processing 'however' in some designs, especially newer designs with smaller features 116809.doc -16- It may be too high for the use of tungsten to form a good plug. Doped polysilicon is another electrically conductive material that can be used to fill the opening and form a plug. The polycrystalline stone deposited by LPCVD forms a good, void-free plug even in the case where the opening has a longitudinal ratio. However, 'polycrystalline stone has a higher resistance than tungsten, so the polycrystalline structure has a higher resistance than a similar tungsten structure. To overcome these limitations, a composite plug is formed by sequentially depositing polycrystalline germanium and tungsten. 6 shows the NAND string 440 of FIG. 5 after the openings 560, 562 and across the surface of the dielectric layer 454 deposit a first conductive material. The first conductive material forms conductive portions 670, 672 in openings 560, 562 and a first conductive layer 674 on dielectric layer 454. The first conductive material is polycrystalline germanium in this example, although other materials may be used. The polysilicon can be deposited in a furnace or by other suitable methods. Doped polysilicon makes it resistant to low resistance. The polycrystalline spine may be deposited to directly cover the substrate 456 in the openings 560,562. A cleaning step can be performed prior to depositing the polysilicon to remove any native oxide or other material present on the substrate 456 in the openings 56A, 562. The deposition of polycrystalline germanium is stopped prior to filling the openings 560, 562 with polysilicon. The polysilicon deposition can be stopped when the thickness of the first conductive portions 670, 672 in the openings 560, 562 reaches a predetermined thickness. The predetermined thickness can be calculated such that the remaining unfilled portions 676, 678 of the openings 560, 562 have an aspect ratio that is such that it is suitable for filling with tungsten. Figure 7 shows the NAND string 440 of Figure 6 after depositing a second conductive material to form a second conductive layer 78. The second electrically conductive material is tungsten in this example, although other materials may be used. The second conductive material fills the unfilled portions 676, 678 of the openings 116809.doc -17-560, 562 and extends across the first conductive layer 674. A barrier layer can be deposited prior to depositing tungsten (not display). The barrier layer can be a composite layer of titanium and titanium nitride deposited in sequence. In other examples, the second conductive material may be deposited directly onto the first conductive material or a different barrier layer may be positioned between the first conductive material and the second conductive material. Figure 8 shows the NAND string 440 of Figure 7 after removal of excess first and second conductive material. The second conductive layer 780, which is removed from the first conductive layer 674 and deposited over the first conductive layer 674, is removed to the level of the top of the dielectric layer 454, leaving the second conductive portions 882, 884. The first and second electrically conductive materials may be removed by chemical mechanical polishing (CMP) or by etch back or other methods. Typically, CMP systems are used because they provide a planarized surface that is required for subsequent steps. The remaining first conductive portions 67A, 672 and the second conductive portions 882, 884 form plugs 886, 888. The plugs 886, 888 have a lower impedance than the impedance provided by the plug of the polysilicon alone. Even though the openings 560, 562 can have a higher aspect ratio than the aspect ratio that would normally be filled by tungsten alone, the plugs 886, 888 are also void free. FIG. 9 shows the NAND string of FIG. 8 after depositing a second dielectric layer 990 covering the first dielectric layer 454 and the second conductive portions 882, 8 and the second dielectric layer 990 of this example. A layer of cerium oxide (si 〇 2) which is formed by chemical vapor deposition (CVD) using tetraethyl phthalate (Si(OC2H5) 4 (TEOS). Other dielectric materials can also be used. FIG. 10 shows the NAND string 440 of FIG. 9 after patterning the second dielectric layer 990. An opening 992 is formed in the second conductive portion 882 in the second dielectric layer 990 I16809.doc -18 · 1332252. The opening 992 has substantially the same lateral dimension as the second conductive portion 882. An opening 994 is also formed in the second dielectric layer 990 on the second conductive portion 884. However, as shown in FIG. 1A, the opening 994 may extend wider in the direction of the NAND string 440 than the second conductive portion 884. In addition, the opening 994 extends in a direction perpendicular to the section shown in Figure 10, so that it itself covers a plurality of strings of plugs. The openings 992, 994 are formed by a single process using a single mask that is aligned such that the openings 992, 994 are positioned over the second conductive portions 882, 884. Figure 11 shows the NAND string 440 of Figure 10 after deposition and planarization of a third conductive layer to form conductive portions 1102, 1104. In general, the conductive portions 1102, 1104 are formed of the same material (tungsten in this example) as the second conductive portions 882, 884. "This step causes the drain plug 886 to extend in the vertical direction. The source plug 888 is connected by this step to the other source contact plugs of other strings (not shown in Figure 11). Figure 12 shows the NAND string 440 of Figure 11 after successively forming a third dielectric layer 121, a bit line 1212, and a pad and 886 connected to the additional conductive portion 1214 of the bit line 1212. The third dielectric layer 121 can be formed of sich. The third dielectric layer 1210 can be formed using TE〇s by high density plasma (HDP), plasma enhanced deposition, or by some other method. The additional conductive portion 1214 can be aluminum, copper, tungsten or other suitable electrically conductive material. The bit το line 1212 is typically formed of a conductive material such as aluminum or tungsten, and the germanium bond pad plug 886 and the additional conductive portion 1214 are coupled together to connect the one end of the NAND string 440 to the bit line 1212. Meta-Line Contact " H6809.doc 19 Figure 13 shows a top view of NAND string 440 of Figure 12 and shows additional NAND strings 1320, 1322. Although three strings 440, 1320, 1322 are shown with four floating gate units, However, an actual memory array can have 8, 16, 32 or more floating gate cells in a string, and thousands of strings can extend across a substrate in two dimensions. Individual strings 440, 1320, 1322 are Separated by STI regions 1324a through 1324d extending on each side of strings 440, 1320, 1324. Word lines 1326a through 1326d (indicated by dashed lines) cover different strings of floating gates and cover floating gates Control gates are formed at the poles (eg, control gates 442a through 442d of NAND string 440). In substrate 456, source/drain implant regions (eg, source/drain implant regions 448a of NAND string 440) Up to 448g) shared by adjacent memory cells and will be Electrical connections are provided between the memory cells of the NAND string. The select lines 1328, 1330 extend across the strings 440, 1320, 1322 and parallel word lines 1326a through 1326d and form a select gate at the channel region of the NAND string itself. A pole (e.g., select gates 450, 452 of NAND string 440). Plugs 886, 888 showing NAND string 440 in a top view extend from the implanted region at each end of NAND string 440. The displayed NAND string 440' The source contact plugs 888, 1332, and 1334 of 1320 and 1322 are connected together by a conductive portion 1104 (common source line) formed as shown in Fig. 11. The common source line 1104 is parallel to the word line. 1326a through 1326d extend with select lines 1328, 1330. Figure 14 shows a circuit diagram of NAND strings 440, 1320, 1322 of Figure 13. In addition, Figure 14 shows bit lines extending in the same direction as NAND strings 440, 1320, 1322. 1212, 1450, 1452 (not shown in Figure 13). Bit lines 116809.doc -20· 1332252 12, 1450, 1452 are formed on the strings "Ο, 1320, 1322", respectively, as in the section of Figure 12. The general display. While the invention has been described with respect to the exemplary embodiments of the invention, it should be understood that BRIEF DESCRIPTION OF THE DRAWINGS Circle 1 shows a cross section of a prior art-opening in a dielectric layer covering a substrate.

2·4 shows a section of a prior art plug formed in an opening, the trap including a gap. Figure 3 shows a section of a high aspect ratio opening. Figure 3B shows the opening of Figure 3A partially filled with a first tenth spear conductive material, having an unfilled remainder.

: showing that the remaining portion is filled with the second conductive material, the opening β M of FIG. 3B. FIG. 4 shows one NAND string formed by the floating gate unit and one of the substrates covered by the dielectric layer. The section of the selected gate formed on the upper forging 卩°卩 injury. Figure 5 shows that it has formed in the mediation. Figure 6 of Figure 4 shows the deposition of the openings in the openings, and leaves (4) material to partially fill the unfilled portions of the openings H. Figure 7 is shown in the openings. Opening the second conductive material to fill the structure of the open unfilled portion of Fig. 6. Fig. 8 shows the removal of excess first conductive material and second conductive material and 116809.doc • 21· 1332252 opening The structure of Figure 7 after the lower plug. Figure 9 shows a structure of Figure 8 covering the first dielectric material and a second dielectric layer of the plugs. Figure 1A shows the patterning of the first The second dielectric layer aligns the opening to the structure of Figure 9 after the plugs. Figure 11 shows that a conductive material is deposited in the opening of the second dielectric layer to extend the drain plug and the source plug system The structure of FIG. 10 is connected together by a common source line. FIG. 12 shows that a third dielectric layer is formed on the second dielectric layer and a bit line is formed on the second dielectric layer ( The structure of Fig. 11 connected to the bit line of the drain side of the NAND string. Fig. 13 shows the string extending in the x direction And a top view of the structure of the sub-line extending in the X direction, the selection line and a common source line of Fig. 12. Fig. 14 shows the circuit corresponding to the circuit formed by the structures of Figs. 2 and 13 [main component symbol Description] 101 opening 103 dielectric layer 105 substrate 21 plug 212 gap 320 substrate 322 dielectric layer 116809.doc -22. 1332252

324 opening 325 unfilled portion 326 surface 328 first conductive portion 330 top surface 332 second conductive portion 334 composite plug 440 NAND string 442a control gate 442b control gate 442c control gate 442d control gate 444a floating gate 444b floating Gate 444c floating gate 444d floating gate 446a channel region 446b channel region 446c channel region 446d channel region 448a source and drain region 448b source and drain region 448c source and drain region 448d source and drain regions Ll6809.doc -23 · 1332252

448e source and drain regions 448f source and gate regions 448g source and drain regions 450 first select gate 450a portion 450b portion 452 second select gate 452a portion 452b portion 454 first dielectric layer 456 substrate 560 Opening 562 opening 564 implant region 566 implant region 670 first conductive portion 672 first conductive portion 674 first conductive layer 676 unfilled portion 678 unfilled portion 780 second conductive layer 882 second conductive portion 884 second conductive portion 886 Plug 116809.doc -24- 1332252

888 plug 990 second dielectric layer 992 opening 994 opening 1102 conductive portion 1104 conductive portion 1210 third dielectric layer 1212 bit line 1214 additional conductive portion 1320 NAND string 1322 NAND string 1324a STI region 1324b STI region 1324c STI region 1324d STI Area 1326a Word Line 1326b Word Line 1326c Word 7L Line 1326d Word Line 1328 Select Line 1330 Select Line 1332 Source Contact Plug 1334 Source Contact Plug 1450 Bit Line 1452 Bit Line 116809.doc -25 -

Claims (1)

1332252 ____ • Patent application No. 095145418 „ " ~~ ·- Chinese patent application scope replacement (January 99^如汾修(更成·Replacement page 10, patent application scope: 1 · A non-volatile memory a body array comprising: a floating gate memory ft unit_ extending between a first doped region of the substrate and a second doped region of the substrate; the first contact comprising a first material a first portion and a second portion of the first material, the first portion contacting the first 4 impurity region of the substrate, the second portion of the β hai covering the first portion, and the first portion and the second portion φ Formed in one of the vertical openings of the dielectric layer, the first contact is a one-dimensional line contact; and the first contact includes a third portion of the first material and a first material a fourth portion, the third portion contacts the second doped region of the substrate, the fourth portion covers the third portion, and the third portion and the fourth portion are all vertically open in one of the dielectric layers Formed in the second contact for the floating gate memory cell string; and A common source line is on the second contact, and the second contact is electrically connected to the common φ source line. 2. The non-volatile memory array of claim 1, wherein the first material system The polysilicon is doped and the second material is tungsten. 3. The non-volatile memory array of claim 1 further comprising a shallow trench isolation structure extending along a side of the sub-movement memory cell string. The non-volatile memory array of claim 1, wherein the word line extends across the string in one of the vertical far strings. 5. The non-volatile memory array of claim 1, wherein the floating gate The memory cell string includes a first selection gate and a second selection gate. 116809.990l22.doc II..... _ , 6 · A non-volatile memory array comprising: a plurality of floating gate memories a string of body cells, one string extending in a first direction between a first doped region of the substrate and a second doped region of the substrate; a plurality of word lines perpendicular to the first direction Extending in a second direction and covering the plurality of floating gates a floating gate of the memory cell; a plurality of select lines extending in the second direction to connect the plurality of select gates of the plurality of strings; a plurality of composite plugs, the one composite plug comprising a first material a first portion and a second portion of a second material, the second portion covering the first portion, the first portion and the second portion being formed in one of the vertical openings in a dielectric layer, the plurality of composites The plug includes a first group composite plug connected to the first doped region of the substrate and a second group composite plug connecting the second doped region of the substrate; a common source line, wherein Extending in the second direction, the common source line is over the first group of composite plugs and connected to each composite plug of the first group of composite plugs; and a plurality of bit lines The first direction extends over the plurality of strings. A single bit line is connected to a composite plug of the second group of composite plugs. 7. The non-volatile memory array of claim 6, wherein the proximity is separated by a shallow trench isolation region. 8_ The non-volatile memory array of claim 6, wherein the first material is replaced by a doped polysilicon and the second material is tungsten. One of the barrier layers extends wherein the barrier layer is titanium, wherein the vertical opening has a first non-volatile memory array between the first material and the second material. 〇. A combination of the non-volatile memory array of claim 9 and the nitride. U. The non-volatile memory array of claim 6 having an aspect ratio which is too high for filling the vertical opening. 12. A method of forming a non-volatile memory material column on a semi-four substrate: comprising: forming a memory cell string having a floating gate and a control gate covered by a dielectric layer Extending from a first substrate region to a second substrate region; forming a first opening in the dielectric layer on the first substrate region, the first opening extending to the first substrate region; Forming a second opening in the dielectric layer on the substrate region, the second opening extending to the second substrate region; then depositing a first conductive material contacting the first and second substrate regions, the first The conductive material partially but not completely fills the first and second openings, the first conductive material completely filling the first openings to a first height 'and completely filling the second openings to a second height And depositing a second conductive material in the first and second openings, the second conductive material directly covering the 116809-990122.doc material in the first and second openings Waiting for the first two Electric: filling the second opening of the temple 'of the first - and the second electrically conductive material: two! And forming a bit line contact in the first opening and forming a source line contact in the first password. U. As in the method of claim 12, 1 enters the upper surface of the array of cattle, ... the receiver flattens the amount of the memory;: Ϊ: 13 method, the further step comprises forming and patterning -=^ The material is outside, and (4) the electricity (4) is used to fill the mouth. & 'The additional openings are aligned with the first and second openings 15 as in the method of claim 12, the first and second openings in the middle of the basin have a vertical one and eight to prevent early independence a second material to fill the first and first openings, and the first conductive material fills the first 盥笸, can leave and have a first... The two conductive materials are filled with - the aspect ratio of the unfilled portion. Formed on a semiconductor substrate - a non-volatile memory method, comprising: a dry illusion force forming a plurality of floating gate memory cells extending over the scorpion and crossing a stinky wall ^ first direction will be from a Separating upwards--the first one of the individual competitions extends to a second end; forming a dielectric layer on a plurality of floating gate unit strings such as °H; removing the part of the "Hai" electric layer for And forming a plurality of openings on the ff end and the second end of the plurality of strings, the plurality of openings extending from the top surface of the dielectric layer to the surface of the substrate; a 116809-990I22.doc And then depositing a plurality of openings _ a conductive-conductive material contacting the substrate 'μ 攸 攸 亚 亚 亚 亚 该 该 低 低 低 低 低 低 低 低 低 低 低 低 低 低 低 低 低 低 低 低 低 低 低 低 低 低 低 低 低 低 低 低 低 低 低In the middle of the 荽... a conductive material 垃 几 - - - 弟 弟 - - - - - - - - - - 弟 弟 弟 弟 弟 “ “ “ “ “ “ “ “ “ “ “ “ “ “ “ “ “ “ “ “ 直接Second! 更低 lower than the first - conductive material - resistance The second conductive material forms a first contact to the first ends of the plurality of strings and a second contact to the plurality (four) of the second ends; forming a common source line, the second contacts Each forming an electrical connection to at least a portion of the common source line; and forming a plurality of bit lines, each of the first contacts forming an electrical connection to the bit line At least a portion. 17. 18. 19. The method of claim 16, wherein the method further comprises performing a chemical mechanical polishing to remove a portion of the second conductive material, the contact being formed on the first dielectric layer - The second dielectric layer 'patterns the second dielectric layer and deposits additional conductive material. The method of the method of the present invention, wherein the additional conductive material is the second conductive material. A method of forming a low-impedance void-free plug in an array, comprising: the outer 'slip layer forming an opening, the opening having a first vertical dimension / a first horizontal dimension, which gives a first aspect ratio, The opening exposes a portion of a substrate; 116809-990122.doc 1332252 ί - -**^-*1 : 夕年/ 趁·(more) is replacing the part of the substrate that is exposed to the substrate by the opening; depositing in the opening a first conductive portion of a first conductive material, the first conductive portion having a second vertical dimension, the deposit leaving an unfilled portion of the opening having a second vertical dimension, the unfilled portion D Having a second aspect ratio smaller than the first aspect ratio; forming a second conductive portion in the unfilled portion, the second conductive portion being a second having a lower resistance than the first conductive material Formed by a conductive material, the second conductive material providing void-free filling having the second longitudinal: opening, and providing no void-free filling having the opening of the first aspect ratio; and on the second conductive portion Forming a third conductive portion, the third conductive portion m source line, the first and the first conductive material providing an electric current between the portion of the substrate having implanted doping and the common source line At least a part of the connection. The conductive material is doped with polysilicon. The method of claim 19, wherein the second conductive material is tungsten. 21. The method of claim 19, wherein the second vertical dimension is selected such that the first aspect ratio is approximately contiguous from the first to the second aspect ratio. The maximum amount of electrically conductive material properly filled. 22. The method of claim 19, wherein the first 盥 导 雷 _ ^ 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一point. (4) Array-NAND 23. The method of claim 19, wherein a further step is formed between the first conductive material and the first barrier layer. Conductive material and 116809-990122.doc • 6- 1332252 Financial repair (more) replacement page 24. As in the case of claim 19, the first and second 暮 are formed by blanket deposition, and the brother removes Excessive excess of the second conductive material. The method of claim 24, wherein the excess first conductive second conductive material is removed by chemical mechanical polishing to form an additional conductive portion thereon. Part of the two are made of conductive materials and multiple materials with this excess to leave a flat 116809-990122.doc