WO2007058489A1 - An interrupt signal control apparatus for receiving and transmitting a series of asynchronous information having 4 channels - Google Patents
An interrupt signal control apparatus for receiving and transmitting a series of asynchronous information having 4 channels Download PDFInfo
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- WO2007058489A1 WO2007058489A1 PCT/KR2006/004835 KR2006004835W WO2007058489A1 WO 2007058489 A1 WO2007058489 A1 WO 2007058489A1 KR 2006004835 W KR2006004835 W KR 2006004835W WO 2007058489 A1 WO2007058489 A1 WO 2007058489A1
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- Prior art keywords
- signal line
- interrupt
- interrupt signal
- common
- generated
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- 230000005540 biological transmission Effects 0.000 claims abstract description 74
- 238000007689 inspection Methods 0.000 claims description 6
- 102100028043 Fibroblast growth factor 3 Human genes 0.000 description 28
- 108050002021 Integrator complex subunit 2 Proteins 0.000 description 28
- 101710092886 Integrator complex subunit 3 Proteins 0.000 description 28
- 102100025254 Neurogenic locus notch homolog protein 4 Human genes 0.000 description 28
- 238000000034 method Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
Abstract
The present invention relates to a common interrupt generation/block apparatus wherein UART(Universal Asynchronous Receiver/Transmitter), a asynchronous series communication transmitter/receiver generates/blocks an interrupt signal generated in each UART of QUAD UART including 4 channels, or generate/blocks an interrupt signal line generated in each of 4 channels as one common interrupt signal line. That is, the present invention provides an interrupt signal control apparatus for receiving and transmitting a series of asynchronous information having 4 channels in which a common interrupt signal line which can be used commonly is generated by controlling an individual interrupt signal line by using a signal line of an interrupt transmission/block control means operated by an outside circuit, it is determined that the core portion of an UART where the signal line is generated, and after switching the polarity of the generated common interrupt signal line, an interrupt signal through which is to be connected to outside is selected.
Description
Description AN INTERRUPT SIGNAL CONTROL APPARATUS FOR
RECEIVING AND TRANSMITTING A SERIES OF ASYNCHRONOUS INFORMATION HAVING 4 CHANNELS
Technical Field
[1] This application claims priority to and benefit of Korean Patent application NO.
2005-110311 filed on November 17, 2005, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference.
[2] The present invention relates to a control of an interrupt generated when a asynchronous series communication transmitter/receiver receives and transmits data, and in particular, relates to a control for allowing each interrupt signal line of an UART to be connected outside, or each of plurality of interrupt signal lines generated in an UART to be connected outside via a common interrupt signal line when many interrupts are generated in the asynchronous series communication transmitter/ receiver. Background Art
[3] Generally, XR16C854/854D which is selling in EXAR is used as a 4 channels asynchronous transmitting and receiving apparatus of the prior art. As shown in FIG. 1, such a 4 channels asynchronous transmitting and receiving apparatus(QUAD UART) 100 includes 4 UART channels 120. An inside interrupt signal is generated in 1 channel UART of these 4 channels, respectively, and each outside interrupt signal line 140 corresponding to the generated inside interrupt signal line INTO, INTl, INT2, INT3 is provided.
[4] That is, in the 4 channels asynchronous transmitting and receiving apparatus (QUAD UART) of the prior art, 4 outside interrupt signal line 140 corresponding to each of QUAD UART 120 are provided, and it becomes possible to process all interrupt signals generated in QUAD UART only when an outside circuit which receive and process the signals must have 4 interrupt signal lines. But, actually, it is a general case that the input terminals for receiving each of the interrupt signals generated in QUAD UART are not sufficiently provided to the outside circuit. Disclosure of Invention
Technical Problem
[5] In order to solve above problems, the object of the present invention is to control an interrupt signal control apparatus for receiving and transmitting a series of asynchronous information having 4 channels by using a control signal (a signal such as
Address, Data, Read, and Write) of a CPU device, and at the same time to switch a plurality of interrupt signals generated in QUAD UART to a common interrupt signal line, and generate them.
[6] Further, another object of the present invention is to investigate the channel where an individual interrupt signal is generated among 4 UART channels having only one individual interrupt signal line when a common interrupt signal is generated in a common interrupt signal line generated by switching each of the interrupt signals generated in QUAD UART.
[7] Further, another object of the present invention is to switch the common interrupt signal line to a polarity which is required according to outside conditions and to select, determine, and output a necessary interrupt signal line among the switched common interrupt signal line, and each of the individual interrupt signal lines generated in QUAD UART. Brief Description of the Drawings
[8] FIG. 1 illustrates a 4 channels asynchronous transmitting and receiving apparatus of the prior art.
[9] FIG. 2 illustrates an interrupt signal control apparatus for receiving and transmitting a series of asynchronous information having 4 channels according to the present invention.
[10] FIG. 3 illustrates a structure in which a common interrupt signal according to the present invention is generated.
[11] FIG. 4a illustrates a logic circuit for generating in which a common interrupt signal according to the present invention.
[12] FIG. 4b illustrates other logic circuit for generating in which a common interrupt signal according to the present invention.
[13] FIG. 5a illustrates a structure of an interrupt transmission/block control means for forming an interrupt signal control device of an interrupt signal control apparatus for receiving and transmitting a series of asynchronous information having 4 channels according to the present invention.
[14] FIG. 5b illustrates other structure of an interrupt transmission/block control means for forming an interrupt signal control device of an interrupt signal control apparatus for receiving and transmitting a series of asynchronous information having 4 channels according to the present invention. Best Mode for Carrying Out the Invention
[15] In order to accomplish above objects, the present invention provides an interrupt signal control apparatus for receiving and transmitting a series of asynchronous information having 4 channels comprising a common interrupt generation means for
switching and generating an individual interrupt line allocated to each UART to a common interrupt signal line so that the individual interrupt line allocated to each UART for notifying an interrupt generated in 4 UART to outside may be commonly used; an interrupt transmission/block control means for enabling an individual interrupt signal line generated in said 4 UART to be transmitted and blocked by transmission/ block control line based on an outside control signal in order to control generation of said common interrupt signal line generated by said common interrupt generation means; an interrupt generation state inspection means for inspecting whether said common interrupt signal line transferred by said transmission/block control signal line and generated by said common interrupt generation means is an individual interrupt signal line generated in one of said four UART or not; a common interrupt polarity control means for switching the common interrupt signal line generated by said common interrupt generation means to a polarity which is required depending on outside conditions when the common interrupt signal line is connected to outside; a common/individual interrupt selection means for determining an interrupt signal line when outputting said common interrupt signal line switched by said interrupt polarity control means, and an individual interrupt signal line generated in said 4 UART to outside. Mode for the Invention
[16] Below, referring to the drawings, the embodiment of the present invention will be explained in detail.
[17] FIG. 2 illustrates an interrupt signal control apparatus for receiving and transmitting a series of asynchronous information having 4 channels according to the present invention.
[18] As shown in FIG. 2, a transmission/reception unit 10 of the present invention is composed of a common interrupt generator 1, an interrupt transmission/block controller 2, an interrupt generation state inspection unit 3, a common interrupt polarity controller 4, a common/individual interrupt selector 5, and a UART core unit 8.
[19] The common interrupt generator 1 switches 4 allocated individual interrupt signal
INTO, INTl, INT2 to which an interrupt signal generated inside each of 4 UART core unit 4 is outputted to a common interrupt signal line GGINT for allowing INT3 to be commonly used. These switching procedures will be explained later.
[20] Further, the interrupt transmission/block controller 2 generates a transmission/block control signal line MO, Ml, M2, and M3 according to a control signal supplied from outside, and these transmission/block control signal lines MO, Ml, M2, and M3 controls transmission of an interrupt signal generated in individual interrupt signal line INTO, INTl, INT2, INT3 to a common interrupt signal line, and blocking of the
interrupt signal. Here, ADDRESS[2:0], DATA[7:0], WR#, RD#, CS0#, CS1#, CS2# and CS3# can be enumerated as the control signal inputted from outside. The circuit of the interrupt transmission/block controller 2 will be explained later.
[21] Further, the interrupt generation state inspection unit 3 inspects the line where an interrupt is generated among each individual interrupt signal line INTO, INTl, INT2, INT3 of 4 UART core unit 8 when an interrupt is generated in the common interrupt signal line GGINT.
[22] In addition, the common interrupt polarity controller 4 switches the common interrupt signal line GGINT to the common interrupt signal line GGINT the polarity of which is changed in order to switch the common interrupt signal line GGINT provided in the common interrupt generator 1 to a signal which is required from outside.
[23] Further, the common/individual interrupt selector 5 selects one of the common interrupt signal line GGINT the polarity of which is changed, and each of individual interrupt signal line INTO, INTl, INT2, INT3. Then, the selected signal line is connected to an external circuit and then used by an user.
[24] From now on, the structure of the whole circuit of the interrupt signal control apparatus 10 for receiving and transmitting a series of asynchronous information having 4 channels will be explained in detail.
[25] In the apparatus 10 for receiving and transmitting according to the present invention, generally,
[26] an external output control signal and UART individual selection signal CS0#,
CS1#, CS2# and CS3# are supplied to the UART core unit 8, and are allocated to each of the UART core unit, Therefore, each of the UART core unit 8 is controlled. Then, when each of the UART core unit 8 including 1 channel performs an interrupt generation operation in response to the control signal provided from outside, an interrupt signal is generated in the UART core unit 8, and the interrupt signal is outputted via individual interrupt signal line INTO, INTl, INT2, INT3 allocated to each of the UART core unit.
[27] Further, while the individual interrupt signal line INTO, INTl, INT2, INT3 is being outputted, at the same time, a common chip selection generator 6 which receives all of UART individual selection signal CS0#, CS1#, CS2# and CS3# switches the UART individual selection signal CS0#, CS1#, CS2# and CS3# to a common selection signal line GCS#. This common selection signal line GCS# selects a path connected to a common interrupt signal line GGINT.
[28] Then, in order to switch the individual interrupt signal line INTO, INTl, INT2,
INT3 to the common interrupt signal line GGINT, the common interrupt generator 1 is connected to interrupt transmission/block controller 2, and controls the individual interrupt signal line INTO, INTl, INT2, INT3 via the interrupt transmission/block
control signal line MO, Ml, M2, and M3 generated in the interrupt transmission/block controller 2 based on the signal supplied from outside, thereby an interrupt signal generated in the common interrupt signal line GGINT is transmitted/blocked.
[29] Here,sinceall ofthe generated common interrupt signal lines GGINT use the individual interrupt signal line INTO, INTl, INT2, INT3 commonly, it is not possible to grasp the fact that an interrupt is generated in the individual interrupt signal line of which UART core unit 8. Therefore, the interrupt generation state inspection unit 3 inspects the individual interrupt signal line INTO, INTl, INT2, INT3 to find the individual interrupt signal line where the interrupt signal generated in the common interrupt signal line GGINT is generated.
[30] Further, the common interrupt signal lines GGINT generated in the common interrupt generator 1 is outputted to the common interrupt polarity controller 4, and the common interrupt polarity controller 4 switches the common interrupt signal lines GGINT to the polarity required from outside for connection with outside and operations, and then is connected to the common/individual interrupt selector 5. If the common interrupt polarity controller 4 is used, there exists a merit that a logic circuit for switching a polarity of an interrupt signal required from outside can be removed.
[31] Further, as described above, the common/individual interrupt selector 5 which receives each of the individual interrupt signal line INTO, INTl, INT2, INT3 outputted from the UART core unit 8, and the common interrupt signal line GINT the polarity of which is switched selects and determines one of the inputted signal lines.
[32] For example, it is possible to output each of the individual interrupt signal line
INTO, INTl, INT2, INT3, or to output the common interrupt signal line GINT the polarity of which is switched and uses these signal lines commonly. Further, if the common interrupt signal line GINT the polarity of which is switched is used, it is possible to select one of the individual interrupt signal line INTO, INTl, INT2, INT3, and to output the common interrupt signal line GINT the polarity of which is switched to the selected individual interrupt signal line.
[33] FIG. 3 illustrates a structure in which a common interrupt signal line GGINT according to the present invention is generated.
[34] The common interrupt generator 1 of FIG. 2 switches the individual interrupt signal line INTO, INTl, INT2, INT3 generated in each of the UART core unit 8 to the common interrupt signal line GGINT. As shown in FIG. 3, the individual interrupt transmission/block circuit 20 included in the common interrupt generator receives the transmission/block control signal MO, Ml, M2, and M3 generated in the interrupt transmission/block controller 2 in response to the control signal provided from outside, and receives the individual interrupt signal line INTO, INTl, INT2, INT3 from the UART core unit 8. The individual interrupt transmission/block circuit 20 controls the
individual interrupt signal line INTO, INTl, INT2, INT3 from the UART core unit 8 viathe received transmission/block control signal line MO, Ml, M2, and M3, and decides whether a signal is transferred to the interrupt transmission signal line SINTO, SINTl, SINT2, SINT3 or not.
[35] For example, if the individual interrupt signal line INTO is blocked by one transmission/block control signal line MO, even though an interrupt signal is generated in the individual interrupt signal line INTO, the interrupt signal can not be transferred to the common interrupt generation circuit 21. That is, the individual interrupt transmission/block circuit 20 controls the individual interrupt signal line INTO by using one transmission/block control signal line MO, and if the individual interrupt signal line INTO is blocked as a result of the control, an interrupt transmission signal line SINTO can not be transferred.
[36] But, based on the control signal supplied from the outside, if the interrupt signal of the individual interrupt signal line INTO is transferred via the transmission/block control signal line MO generated in the interrupt transmission/block controller 2, the interrupt transmission signal line SINTO is transferred to the common interrupt generation circuit 21. That is, the individual interrupt transmission/block circuit 20 controls the individual interrupt signal line INTO by using one transmission/block control signal line MO, and if the individual interrupt signal line INTO is transferred as a result of the control, an interrupt transmission signal line SINTO is transferred.
[37] As described above, the interrupt transmission signal line SINTl, SINT2, SINT3 outputted via the individual interrupt transmission/block circuit 20 is transferred like the transmission method of the interrupt transmission signal line SINTO. For the transferred interrupt transmission signal line SINTl, SINT2, SINT3, one common interrupt signal line GGINT outputted from the common interrupt generation circuit 21.
[38] Further, it at least one of these interrupt transmission signal line SINTO, SINTl,
SINT2, SINT3 transferred via the transmission/block control signal line is transferred, the common interrupt generation circuit 21 generates a common interrupt signal line GGINT.
[39] FIG. 4a and FIG. 4b are the diagrams showing the circuit for realizing generation of a common interrupt signal line GGINT according to the present invention.
[40] As shown in FIG. 4a, if the logic value of the individual interrupt signal line INTO is 1, an interrupt is generated, and if the logic value of the transmission/block control signal line MO generated in the interrupt transmission/block controller 2 is 1, it is assumed that a signal is being transferred. For example, if the logic value of the individual interrupt signal line INTO and the logic value of the transmission/block control signal line MO are all 1, a logic value "1" is outputted via AND circuit unit 30,
an interrupt transmission signal line SINTO is outputted, and the outputted interrupt transmission signal line SINTO outputs the logic value "1" via OR circuit unit 31, and then is switched to a common interrupt signal line GGINT.
[41] But, if the logic value of the individual interrupt signal line INTO is 1, and the logic value of the transmission/block control signal line MO 0, the individual interrupt signal line INTO is generated, but the individual interrupt signal line INTO is blocked via the transmission/block control signal line MO generated in the interrupt transmission/block controller 2, and then the logic value "0" is outputted via AND circuit unit 30, thereby an interrupt transmission signal line SINTO is not transferred and thus is not switched to a common interrupt signal line GGINT.
[42] If the logic value of the individual interrupt signal line INTO is 1, and the logic value of the transmission/block control signal line MO is 1, the logic value "0" is outputted unconditionally via AND circuit unit 30, thereby an interrupt transmission signal line SINTO is not outputted, and thus is not switched to a common interrupt signal line GGINT.
[43] Further, If the logic value of the individual interrupt signal line INTO is 1, and the logic value of the transmission/block control signal line MO is 0, the logic value "0" is outputted via AND circuit unit 30, thereby an interrupt transmission signal line SINTO is not outputted, and thus is not also switched to a common interrupt signal line GGINT.
[44] Similarly, If the logic values of the individual interrupt signal line INTl, INT2,
INT3 are all 1, and the logic values of the transmission/block control signal line Ml, M2, M3 are all 1, the interrupt transmission signal line SINTl, SINT2, SINT3 are outputted via AND circuit unit 30, and these interrupt transmission signal line SINTl, SINT2, SINT3 are switched to a common interrupt signal line GGINT via OR circuit unit 31.
[45] But, If the logic values of the individual interrupt signal line INTl, INT2, INT3, and the logic values of the transmission/block control signal line Ml, M2, M3 are (1,0), (0, 1), (0, 0), the interrupt transmission signal line SINTl, SINT2, SINT3 are not outputted, and thus are not switched to a common interrupt signal line GGINT.
[46] That is, if any one of these interrupt transmission signal line SINTl, SINT2, SINT3 is outputted, there is a feature that the individual interrupt signal line INTl, INT2, INT3 are switched to a common interrupt signal line GGINT.
[47] Further, as shown in FIG. 4b, if the logic value of the individual interrupt signal line
INTO is 0, an interrupt is generated, and if the logic value of the transmission/block control signal line MO generated in the interrupt transmission/block controller 2 is 0, and a logic circuit formed by arranging inversely AND circuit and OR circuit of FIG. 4a is implemented under the assumption that a signal is being transferred, a common
interrupt signal line GGINT which is identical to that of FIG. 4a can be generated.
[48] It is to be understood that a circuit satisfying the structure can be implemented by using other methods except the above-mentioned examples.
[49] Next, FIG. 5a and FIG. 5b illustrate the diagrams showing a structure for generating a control signal for controlling an interrupt transmission/block according to the present invention.
[50] As shown in FIG, 5a, the interrupt transmission/block controller 2 is operated by an external electronic circuit, and then outputs the transmission/block control signal line MO, Ml, M2, M3. For example, if the controls signal WR#, CS0#, CS1#, CS2#, CS3# outputted by an external circuit, and the internal generation control signal GCS# are inputted to the address allocated by ADDRESS [7:0], the interrupt transmission/block controller 2 stores and outputs them to the input data DATA[7:0], the outputted signal becomes the transmission/block control signal line MO, Ml, M2, M3. That is, according to the data signal of the external circuit, and the signal of the common chip selection generator 6of FIG. 2, the transmission/block control signal line MO, Ml, M2, M3 are outputted.
[51] Therefore, it is possible to transfer or block the individual interrupt signal line
INTO, INTl, INT2, INT3 individually, and it is also possible to transfer or block four individual interrupt signal line INTl, INT2, INT3 at the same time.
[52] Here, it does not matter that the transmission/block control signal line MO, Ml, M2,
M3 receives any data of data DATA[7:0].
[53] Fig. 5b shows the state that the transmission/block control signal line MO, Ml, M2,
M3 outputted from the interrupt transmission/block controller 2 can be controlled simultaneously by one data of D [7:0].
[54] The interrupt generation state inspection unit 3 connected to the UART core unit 8 of FIG. 3 inspects the channel on which a common interrupt signal line GGINT to which the individual interrupt signal line INTl, INT2, INT3 generated in four channels of the UART core unit 8 is switched is generated. Therefore, the UART core unit 8 of the channel on which the individual interrupt signal line INTl, INT2, INT3 is generated can be grasped.
[55] Further, the common interrupt polarity controller 4 which receives the common interrupt signal line generated in the common interrupt generator of FIG. 3 switches the polarity of a signal to the polarity required by the external electronic circuit, and outputs the signal, thus it is not necessary to provide an additional logic circuit for the interrupt polarity controller to the outside. That is, the common interrupt signal line GGINT is switched 0 or 1, and is outputted as the common interrupt signal line GINT the polarity of which is switched for the external circuit to receive it directly.
[56] Further, as shown in FIG. 1, the common/individual interrupt selector 5 selects one
which of the common interrupt signal line GINT having a switched polarity, and the individual interrupt signal line INTl, INT2, INT3 is outputted to the outside. Industrial Applicability
[57] It is possible to switch the individual interrupt signal line INTl, INT2, INT3 generated in the UART core unit to a common interrupt signal line. Further, it is possible to inspect a UART core unit of a channel on which the individual interrupt signal line is generated among the UART core units including only one individual interrupt signal line when a common interrupt signal line generated by switching the individual interrupt signal line INTl, INT2, INT3 of the UART core unit is generated. Further, it is possible to switch the polarity of a common interrupt signal line to the polarity of the interrupt signal line required by outside, and decide the suitable interrupt signal line among the common interrupt signal line having a switched polarity, and the individual interrupt signal line INTl, INT2, INT3 of in the UART core unit.
[58] Therefore, there is an effect that the interrupt resources can be reduced by reducing the number of an interrupt pin which may be connected to the outside.
Claims
[1] An interrupt signal control apparatus for receiving and transmitting a series of asynchronous information having 4 channels, comprising: a common interrupt generation means for switching and generating an individual interrupt line allocated to each UART to a common interrupt signal line so that the individual interrupt line allocated to each UART for notifying an interrupt generated in 4 UART to outside may be commonly used; an interrupt transmission/block control means for enabling an individual interrupt signal line generated in said 4 UART to be transmitted and blocked by transmission/block control line based on an outside control signal in order to control generation of said common interrupt signal line generated by said common interrupt generation means; an interrupt generation state inspection means for inspecting whether said common interrupt signal line transferred by said transmission/block control signal line and generated by said common interrupt generation means is an individual interrupt signal line generated in one of said four UART or not; a common interrupt polarity control means for switching the common interrupt signal line generated by said common interrupt generation means to a polarity which is required depending on outside conditions when the common interrupt signal line is connected to outside; a common/individual interrupt selection means for determining an interrupt signal line when outputting said common interrupt signal line switched by said interrupt polarity control means, and an individual interrupt signal line generated in said 4 UART to outside.
[2] The interrupt signal control apparatus for receiving and transmitting a series of asynchronous information having 4 channels set forth in the claim 1, wherein said common interrupt signal is generated when at least of the individual interrupt signal lines generated in said 4 UART is transmitted via said transmission/block control signal line generated by said interrupt transmission/ block control means.
[3] The interrupt signal control apparatus for receiving and transmitting a series of asynchronous information having 4 channels set forth in the claim 1, wherein said common interrupt signal comprises one signal line.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020050110311A KR100660452B1 (en) | 2005-11-17 | 2005-11-17 | A interrupt signal control apparatus for receiving and transmitting a series of asynchronous information having 4 channel |
| KR10-2005-0110311 | 2005-11-17 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2007058489A1 true WO2007058489A1 (en) | 2007-05-24 |
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ID=37815272
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/KR2006/004835 WO2007058489A1 (en) | 2005-11-17 | 2006-11-16 | An interrupt signal control apparatus for receiving and transmitting a series of asynchronous information having 4 channels |
Country Status (2)
| Country | Link |
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| KR (1) | KR100660452B1 (en) |
| WO (1) | WO2007058489A1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101829642B1 (en) | 2016-04-15 | 2018-02-19 | 엘에스산전 주식회사 | Serial transceiver |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0469549A2 (en) * | 1990-07-30 | 1992-02-05 | Kabushiki Kaisha Toshiba | Interrupt control unit |
| US5291609A (en) * | 1991-06-13 | 1994-03-01 | Sony Electronics Inc. | Computer interface circuit |
| KR19990015527A (en) * | 1997-08-07 | 1999-03-05 | 윤종용 | Interrupt handler |
| US20020078287A1 (en) * | 2000-12-05 | 2002-06-20 | Noriaki Shinagawa | Data transfer control circuit with interrupt status register |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19980034794A (en) * | 1996-11-08 | 1998-08-05 | 유기범 | Multiple Interrupt Matching Units |
| KR20030027307A (en) * | 2001-09-28 | 2003-04-07 | 엘지전자 주식회사 | Serial interface of universal processor |
-
2005
- 2005-11-17 KR KR1020050110311A patent/KR100660452B1/en not_active IP Right Cessation
-
2006
- 2006-11-16 WO PCT/KR2006/004835 patent/WO2007058489A1/en active Application Filing
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0469549A2 (en) * | 1990-07-30 | 1992-02-05 | Kabushiki Kaisha Toshiba | Interrupt control unit |
| US5291609A (en) * | 1991-06-13 | 1994-03-01 | Sony Electronics Inc. | Computer interface circuit |
| KR19990015527A (en) * | 1997-08-07 | 1999-03-05 | 윤종용 | Interrupt handler |
| US20020078287A1 (en) * | 2000-12-05 | 2002-06-20 | Noriaki Shinagawa | Data transfer control circuit with interrupt status register |
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|---|---|
| KR100660452B1 (en) | 2006-12-22 |
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