WO2007052421A1 - Dispositif d’affichage, circuit de pilotage de ligne de pilotage de signal de données et méthode de pilotage de dispositif d’affichage - Google Patents

Dispositif d’affichage, circuit de pilotage de ligne de pilotage de signal de données et méthode de pilotage de dispositif d’affichage Download PDF

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Publication number
WO2007052421A1
WO2007052421A1 PCT/JP2006/318850 JP2006318850W WO2007052421A1 WO 2007052421 A1 WO2007052421 A1 WO 2007052421A1 JP 2006318850 W JP2006318850 W JP 2006318850W WO 2007052421 A1 WO2007052421 A1 WO 2007052421A1
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WIPO (PCT)
Prior art keywords
signal line
data signal
source
display device
reference voltage
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Application number
PCT/JP2006/318850
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English (en)
Japanese (ja)
Inventor
Yukihiko Hosotani
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Sharp Kabushiki Kaisha
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Application filed by Sharp Kabushiki Kaisha filed Critical Sharp Kabushiki Kaisha
Publication of WO2007052421A1 publication Critical patent/WO2007052421A1/fr

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only

Definitions

  • Display device data signal line drive circuit, and display device drive method
  • the present invention relates to a signal generation circuit used for a display device such as a liquid crystal display device.
  • Liquid crystal display devices are actively used as display elements for televisions, graphic displays and the like.
  • a liquid crystal display device in which a switching element such as a thin film transistor (hereinafter referred to as TFT) is provided for each display pixel causes crosstalk between adjacent display pixels even when the number of display pixels increases. It is especially noticeable because it provides a superior display image.
  • TFT thin film transistor
  • Such a liquid crystal display device is mainly composed of a liquid crystal display panel and a drive circuit unit.
  • the liquid crystal display panel holds a liquid crystal composition between a pair of electrode substrates.
  • Polarizing plates are attached to the outer surfaces.
  • a TFT array substrate which is one electrode substrate, has a plurality of signal lines and scanning signal lines formed in a matrix on a transparent insulating substrate such as glass. Then, a switch element made of TFT connected to the pixel electrode is formed at each intersection of the signal line and the scanning signal line, and an alignment film is installed so as to cover almost the entire surface of the switch element. A TFT array substrate is formed.
  • the counter substrate which is another electrode substrate, is formed by sequentially laminating a counter electrode and an alignment film over the entire surface of a transparent insulating substrate such as glass like the TFT array substrate.
  • the scanning signal line driving circuit connected to each scanning signal line of the liquid crystal display panel thus configured, the signal line driving circuit connected to each signal line, and the counter electrode driving circuit connected to the counter electrode
  • the drive circuit unit is configured by COM.
  • liquid crystals require AC drive to prevent burn-in afterimages and display degradation
  • the drive method described below is also a type of AC drive frame inversion drive. Will be described.
  • TF1 In the first field (TF1), when the scanning voltage Vgh is applied to the gate electrode of the TFT of the display pixel to the scanning signal line driving circuit, this TFT is turned on, and the video signal from the signal line driving circuit is turned on.
  • the voltage Vsp is written to the pixel electrode via the TFT source electrode and drain electrode, and the pixel electrode holds the pixel potential V dp until the scanning voltage Vgh is applied in the next field (TF2).
  • the counter electrode Since the counter electrode is set to a predetermined counter potential VCOM by the counter electrode drive circuit COM, the liquid crystal composition held by the pixel electrode and the counter electrode has a potential difference between the pixel potential Vdp and the counter potential VCOM. In response, the image is displayed.
  • the scanning signal line drive circuit scanning voltage Vgh is applied to the gate electrode of the TFT of the display pixel in the second field (TF2), this TFT is turned on, and the signal line drive circuit power is reduced.
  • the video signal voltage Vsn is written to the pixel electrode and holds the pixel potential Vdn.
  • the liquid crystal composition responds according to the potential difference between the pixel potential Vdn and the counter potential VCOM, and an image is displayed.
  • the liquid crystal AC drive is realized by setting the video signal voltage Vsp in the first field and the video signal voltage Vsn in the second field to have opposite polarities.
  • Patent Document 1 Japanese Patent Publication “Japanese Patent Laid-Open No. 11 281957 (Publication Date: October 15, 1999)”
  • Patent Document 2 Japanese Patent Publication “JP 2004-206075 Publication (Published July 22, 2004)”
  • a level shift AVd caused by the parasitic capacitance Cgd is present in the pixel potential Vd when the scanning voltage Vgh falls. Arise.
  • This level shift AVd is defined as Clc for the liquid crystal capacitance of the pixel and AVg for the difference between the on-voltage and off-voltage in the scanning signal.
  • the scanning signal waveform has almost no waveform rounding immediately after the output of the scanning signal line driving circuit, but the waveform is rounded near the end of the scanning signal line due to the signal delay propagation characteristics of the scanning signal line. It becomes.
  • the level shift AVd does not become uniform over the entire surface of the display panel, and the source pull-in level differs between the input side and the termination side of the scanning signal line. This causes display deterioration such as flickering force on the display screen.
  • the counter voltage needs to be set between the source voltage during positive polarity driving and the source voltage during negative polarity driving.
  • the counter voltage is usually set at the center of the screen so that it is between the source voltage during positive polarity driving and the source voltage during negative polarity driving. Variations in brightness occur from time to time, causing flickering force generation.
  • the display panel has been increased in size, and in such a large-panel liquid crystal display device, the difference in the source pull-in level due to the rounding of the waveform of the scanning signal has increased, and the in-plane flicker has increased. The problem of force generation becomes more prominent.
  • Patent Document 1 discloses a technique for making the level shift ⁇ Vd uniform in the display surface by controlling the falling edge of the scanning signal and eliminating such a flickering force.
  • the method of Patent Document 1 requires a complicated circuit configuration in the scanning signal line driving circuit in order to control the falling edge of the scanning signal.
  • the present invention has been made in view of the above problems, and its object is to sufficiently reduce the occurrence of flickering force and the like due to fluctuations in pixel potential caused by parasitic capacitance.
  • a display device and a display method capable of obtaining a fine and high-quality display image may be realized without requiring a complicated circuit configuration.
  • the display device according to the present invention includes a plurality of scanning signal lines and a plurality of data signal lines provided to cross each other, and the scanning signal lines and the data signal lines.
  • a display panel having a pixel electrode connected to the intersection via a thin film transistor, a scanning signal line driving circuit for driving the scanning signal line, and a data signal line for driving the data signal line as a plurality of source drivers. And the display panel is divided into a plurality of drive regions driven by different source drivers, and the source signal output from the source driver in each of the drive regions is It is characterized in that it is adjusted to minimize the in-plane fretting force.
  • the display device includes a plurality of scanning signal lines and a plurality of data signal lines provided so as to intersect with each other, the scanning signal lines, and the data signal lines.
  • a display panel having pixel electrodes connected to each other through a thin film transistor, a scanning signal line driving circuit for driving the scanning signal lines, and data for driving the data signal lines, comprising a plurality of source drains
  • the display panel is divided into a plurality of drive regions driven by different source drivers, and the source drivers in the respective drive regions have different system reference voltages. It is characterized by being input.
  • the display panel is divided into a plurality of drive regions that are driven by different source drivers.
  • the source signal output by the source driver is adjusted to minimize the in-plane flickering force in each driving area, thus suppressing the in-plane flicking force on the display screen. High-definition and high-quality display images can be obtained.
  • FIG. 1 showing an embodiment of the present invention, is a block diagram showing a signal line drive circuit and a reference voltage generation circuit in a display device according to Embodiment 1.
  • FIG. 2 is a diagram showing a schematic configuration of a liquid crystal display device to which the present invention is applicable.
  • FIG. 3 is a circuit diagram showing a reference voltage generating circuit.
  • FIG. 4 is a block diagram showing a circuit for generating two systems of reference voltages.
  • FIG. 5 is a block diagram showing a signal line driver circuit in the display device according to the second embodiment.
  • FIG. 6 is a block diagram showing a circuit for correcting a gradation signal in the signal line driving circuit.
  • FIG. 7 is a timing chart showing a video signal and a gradation voltage correction signal Vrev input to the signal line driving circuit.
  • FIG. 8 is a timing chart showing a video signal and a gradation voltage correction signal Vrev input to the signal line driving circuit.
  • the liquid crystal display device shown in FIG. 2 is composed of a liquid crystal display panel 1 and a drive circuit unit, and the liquid crystal display panel holds a liquid crystal composition between a pair of electrode substrates.
  • Polarizing plates are attached to the outer surfaces.
  • One electrode substrate has a plurality of signal lines S (l), S (2), ⁇ S (i), SiN), on a transparent insulating substrate 10 such as glass.
  • the scanning signal lines G (1), G (2) G (j) to G (M) are formed in a matrix.
  • a switch element 12 made of TFT connected to the pixel electrode 13 is formed at each intersection between the signal lines and the scanning signal lines, and an alignment film (not shown) is formed so as to cover the entire surface thereof. 2) is installed to form a TFT array substrate.
  • the counter substrate which is another electrode substrate, is formed by sequentially laminating a counter electrode 14 and an alignment film (not shown) over the entire surface of a transparent insulating substrate 11 such as glass like the TFT array substrate. Made up of. Then, the scanning signal line driving circuit 30 connected to each scanning signal line of the liquid crystal display panel configured as described above, the signal line driving circuit 20 connected to each signal line, and the counter electrode connected to the counter electrode.
  • the drive circuit section is constituted by the electrode drive circuit COM.
  • the liquid crystal display device uses a plurality of source drivers 21A to 21D in cascade connection as a signal line driving circuit 20.
  • Each of the source drivers 21A to 21D receives the video signal and a plurality of types of reference voltages from the reference voltage generation circuit, selects one reference voltage according to the video signal, and outputs it to the signal line. Further, the above-described operation in the source drivers 21A to 21D is timing-controlled by a control signal such as a source start pulse signal or a source clock signal input by the control circuit 40 (see FIG. 2).
  • the reference voltage generation circuit 22A supplies the reference voltage to the source drivers 21A and 21B
  • the reference voltage generation circuit 22B supplies the reference voltage to the source drivers 21C and 21D.
  • FIG. 3 shows a configuration example of the reference voltage generation circuits 22A and 22B.
  • the reference voltage generation circuits 22A and 22B generate a plurality of reference voltages between Vref and GND by resistance division when the reference voltage Vrei3 ⁇ 4 is input.
  • the reference voltage generation circuits 22A and 22B have different resistance voltage division ratios.
  • the reference voltage generation circuit 22A generates a Va system reference voltage (VOa to Vna), and the reference voltage generation circuit 22B Generate system reference voltage (V Ob to Vnb).
  • the display panel can be AC driven by switching the polarity of the reference voltage Vref.
  • the reference voltage generation circuit 22A switches the reference voltages VHOa to VHna and the reference voltages VLOa to V Lna for AC driving. Can be generated. The same applies to the reference voltage generation circuit 22B.
  • Va system reference voltage and Vb system reference voltage minimize the in-plane flicker force in the region driven by the source driver to which each reference voltage is input. It is determined by taking the in-plane ⁇ into account for each gradation.
  • the Va system reference voltage generated by the reference voltage generating circuit 22 ⁇ is Input to source drivers 21A and 21B that drive the left half of the display screen (on the scanning signal input stage side).
  • the level shift ⁇ caused by the scan signal waveform rounding is small, and the Va system reference voltage is taken into account. Is set as a small value.
  • the Vb system reference voltage generated by the reference voltage generation circuit 22 is input to the source drivers 21C and 21D that drive the right half of the display screen (the end side of the scanning signal).
  • the level shift ⁇ caused by the waveform rounding of the scanning signal with a large rounding of the scanning signal is a large value at the terminal side of the scanning signal. Set as a value.
  • the reference voltages of different systems are supplied to the display area driven by the source drivers 21A and 21B and the display area driven by the source drivers 21C and 21D, respectively.
  • a configuration including two reference voltage generation circuits 22 ⁇ and 22 ⁇ is illustrated.
  • the method of supplying the reference voltages for a plurality of systems is not limited to this.
  • Fig. 4 shows a modification.
  • FIG. 4 shows a configuration in which two systems of reference voltages can be generated using one reference voltage generation circuit.
  • the reference voltage generation circuit 22C generates the Va system reference voltage. Further, the reference voltage output from the reference voltage generation circuit 22C is branched into two, and one of them is input to the level shift circuit 23.
  • the other reference voltage (Vb system) can be generated if the level is uniformly shifted with respect to the Va system reference voltage. That is, the level shift circuit 23 generates a Vb reference voltage by applying a level shift of ⁇ to the Va reference voltage.
  • the Va reference voltage directly generated by the reference voltage generation circuit 22C is input to the source drivers 21A and 21B, and the Vb reference voltage generated by the level shift in the level shift circuit 23 is obtained.
  • the flickering force of the display screen can be reduced as in the configuration of FIG.
  • the display panel display area is the same.
  • Each source driver is divided into a plurality of drive regions that are driven by different source drivers, and a reference voltage that can optimally improve the in-plane flick force in each drive region is given to each source driver. That is, in the first embodiment, a plurality of system reference voltages are generated by an external reference voltage generation circuit, and the reference voltages of each system are supplied to corresponding source drivers.
  • each of the reference voltages supplied to each source driver has n (n is an integer of n ⁇ l) reference voltages.
  • the reference voltage is set.
  • all n may have different values for each display panel display area, or only one of n may have a different value. Sometimes it becomes. It depends on conditions such as the size of the display panel. At least one of n forces is set to a different voltage.
  • the number of source drivers may be any number as long as it is two or more.
  • two drive regions are separated.
  • four drive regions can be separated.
  • the improvement level of the flicker force is further improved.
  • the number of source drivers is m
  • the number of reference voltage systems used to drive the display panel can be arbitrarily set between 2 and m.
  • the level of improvement increases as the number of reference voltage systems used increases.
  • the reference voltage generation circuit generates each reference voltage from a certain reference voltage (Vref) by resistance voltage division.
  • Vref reference voltage
  • the present invention is not limited to this, and other methods are used. You can generate a reference voltage! / ⁇ .
  • Embodiment 2 according to the present invention will be described below.
  • a plurality of source drivers 24 A to 24 D are used in cascade as the signal line driving circuit 20.
  • Each source driver 24A to 24D receives a video signal and a plurality of types of reference voltages from a reference voltage generation circuit, and responds to the video signal. Select one reference voltage and output to the signal line. Further, the above-described operation in the source drivers 24A to 24D is timing-controlled by a control signal such as a source start pulse signal or a source clock signal input by the control circuit 40 (see FIG. 2).
  • the grayscale voltage correction signal Vrev is input to each of the source drivers 24A to 24D.
  • the gradation voltage correction signal Vrev is a signal for correcting the gradation voltage for the source driver.
  • the gradation voltage correction is performed based on the gradation voltage correction signal Vrev. Is performed. That is, in the second embodiment, the power to which the reference voltage of the same system is input in all the source drivers is corrected to the optimized source voltage in each block and output in each source driver. This improves the in-plane fretting force.
  • the gradation voltage correction signal Vrev is independent of each data power to be a video signal, and notifies signal information for correcting the gradation voltage for each source driver.
  • the information power DZA conversion is performed on the input video signal.
  • the video signal input to the source driver is an n-bit digital signal, and a plurality of (2 n ) reference signals input to the source driver by switching processing according to the bit of the digital signal.
  • One reference voltage is selected from the voltages. The reference voltage thus selected is output to the signal line as a gradation signal corresponding to the video signal.
  • gradation voltage correction information is added to each source driver by the gradation voltage correction signal Vrev and is corrected by the output voltage correction circuit in the source driver.
  • the source driver output voltage is output.
  • Figure 6 shows the main configuration of the source driver for this purpose. Note that the source driver 24 shown in FIG. 6 is common to all of the source drivers 24A to 24D shown in FIG.
  • the source driver 24 includes a DZA conversion circuit 241 and an output voltage correction circuit 242 for each of the source signal lines from which the source voltage is output from the source dry circuit 24.
  • the video signal input to the source driver 24 is first converted into an analog gradation signal by the DZA conversion circuit 241.
  • the source driver 24 The adjustment signal is corrected by the output voltage correction circuit 242 and the corrected analog gradation signal is output to the source signal line.
  • the output voltage correction circuit 242 receives the analog gradation signal from the DZA conversion circuit 241 and the gradation voltage correction signal Vrev.
  • the output voltage correction circuit 242 corrects the input analog gradation signal to a source voltage optimized by level shifting, and the level shift amount ⁇ is determined by the gradation voltage correction signal Vrev. It is.
  • the gradation voltage correction signal Vrev is a parameter in which correction information optimized for the display panel is added to the base reference voltage, and is set according to the characteristics of the display panel.
  • the level shift amount ⁇ in the output voltage correction circuit 242 is set to an optimum value for suppressing the flicker force in each of the regions driven by the source drivers 24 to 24D. It is necessary to make it. This can be dealt with by changing the gradation voltage correction signal Vrev over time. This can be explained with reference to Fig. 7 as follows.
  • the source dryers 24A to 24D perform the above processing on the input video signal in a time-sharing manner for each source signal line. For this reason, the gradation voltage correction signal Vrev may be set to a value corresponding to the source driver 24A while processing is performed on the region driven by the source driver 24A. Similarly, while the processing is performed on the region driven by the source drys 24B to 24D, the gradation voltage correction signal Vrev is set to a value corresponding to the source drys 24B to 24D. In this way, even if the configuration of the source drivers 24A to 24D is the same, different voltage corrections are possible so as to suppress the optimum flickering force in each source driver, which is suitable for each drive region. Source voltage can be output. As a result, it is possible to perform a good display optimized for the display panel and having no flickering force.
  • the gradation voltage correction signal Vrev is input to the source driver as a signal set separately from the video signal. As shown in FIG. It may be input to the source driver with the pressure correction signal Vrev added. This is because, for example, gradation correction voltage information is added to the end of the video signal, and this decoded information is displayed in the figure. It is also possible to input to the 6 source output voltage correction circuit 242.
  • the display device includes a plurality of scanning signal lines and a plurality of data signal lines provided so as to intersect with each other, and an intersection portion between the scanning signal lines and the data signal lines.
  • a display panel having a pixel electrode connected thereto via a thin film transistor, a scanning signal line driving circuit for driving the scanning signal line, and a data signal line driving circuit for driving the data signal line comprising a plurality of source drivers,
  • the display panel is divided into a plurality of drive regions driven by different source drivers, and the source signal output from the source driver in each of the drive regions is a surface within each drive region. Adjusted to minimize internal flickering force.
  • the display device includes a plurality of scanning signal lines and a plurality of data signal lines provided so as to intersect with each other, and a thin film transistor at an intersection between the scanning signal line and the data signal line.
  • a display panel having pixel electrodes connected to each other, a scanning signal line driving circuit for driving the scanning signal line, and a data signal line driving circuit for driving the data signal line including a plurality of source drivers.
  • the display panel is divided into a plurality of drive regions driven by different source drivers, and different system reference voltages are input to the source drivers in the drive regions.
  • the display panel is divided into a plurality of drive regions that are driven by different source drivers.
  • the source signal output by the source driver is adjusted to minimize the in-plane flickering force in each driving area, thus suppressing the in-plane flicking force on the display screen. High-definition and high-quality display images can be obtained.
  • a reference voltage of a different system is input to each of the source drivers.
  • Each reference voltage can be configured to be set to a voltage that can minimize the in-plane flicking force in a drive region driven by a source driver to which the reference voltage is input.
  • the reference voltage set to a voltage that can minimize the in-plane flicking force in the drive region driven by each source driver is input to each source driver.
  • the in-plane flickering force in each driving region can be minimized.
  • the reference voltage input to each of the source drivers is configured to be generated by a different reference voltage generation circuit, or generated by the same reference voltage generation circuit.
  • a plurality of reference voltages can be obtained by branching into a plurality of levels and level-shifting the branched reference voltages.
  • the reference voltages of the different systems have n (n is an integer of n ⁇ 1) reference voltages, and at least one of the n reference voltages has different values. It can be configured to be set.
  • each source driver includes a DZA conversion unit that converts an input digital video signal into an analog gradation signal, and the analog gradation signal in each drive region.
  • a voltage correction unit that corrects the source output signal that can minimize the in-plane flickering force in the case can be provided.
  • the analog gradation signal is supplied to the voltage correction unit.
  • the analog gradation signal can be corrected to a source output signal that can minimize the in-plane flickering force in each drive region.
  • the in-plane flicking force in each drive region can be minimized.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

Selon l’invention, un panneau d’affichage est divisé en une pluralité de zones de pilotage. Chacune des zones de pilotage est pilotée par un pilote source différent (21A à 21D). Des tensions de référence de différents systèmes générées par des circuits (22A, 22B) de génération de tension de référence sont fournies aux pilotes source respectifs (21A à 21D). Chacune des tensions de référence est réglée à une valeur minimisant le scintillement en plan dans la zone de pilotage pilotée par le pilote source à laquelle la tension de référence est fournie. Ceci réduit les scintillements, entre autres, générés par la fluctuation d’un potentiel de pixel attribué à une capacité parasite et produit un dispositif d’affichage et une méthode d’affichage permettant d’obtenir une image d’affichage de hautes précision et qualité sans exiger de configuration de circuit complexe.
PCT/JP2006/318850 2005-11-07 2006-09-22 Dispositif d’affichage, circuit de pilotage de ligne de pilotage de signal de données et méthode de pilotage de dispositif d’affichage WO2007052421A1 (fr)

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Application Number Priority Date Filing Date Title
JP2005-322684 2005-11-07
JP2005322684 2005-11-07

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102637415A (zh) * 2011-07-22 2012-08-15 京东方科技集团股份有限公司 一种液晶显示装置及其驱动方法
JP2013101211A (ja) * 2011-11-08 2013-05-23 Seiko Epson Corp 電気光学装置および電子機器
JP5420894B2 (ja) * 2006-02-16 2014-02-19 株式会社カネカ 硬化性組成物

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0426818A (ja) * 1990-05-23 1992-01-30 Hitachi Ltd 液晶表示装置
JPH11133919A (ja) * 1997-10-27 1999-05-21 Advanced Display Inc 液晶表示装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0426818A (ja) * 1990-05-23 1992-01-30 Hitachi Ltd 液晶表示装置
JPH11133919A (ja) * 1997-10-27 1999-05-21 Advanced Display Inc 液晶表示装置

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5420894B2 (ja) * 2006-02-16 2014-02-19 株式会社カネカ 硬化性組成物
CN102637415A (zh) * 2011-07-22 2012-08-15 京东方科技集团股份有限公司 一种液晶显示装置及其驱动方法
JP2013101211A (ja) * 2011-11-08 2013-05-23 Seiko Epson Corp 電気光学装置および電子機器
US9449572B2 (en) 2011-11-08 2016-09-20 Seiko Epson Corporation Electro-optical device and electronic apparatus having compensation unit for performing voltage compensation

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