WO2007049356A1 - Composant a semiconducteur et son procede de fabrication - Google Patents

Composant a semiconducteur et son procede de fabrication Download PDF

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Publication number
WO2007049356A1
WO2007049356A1 PCT/JP2005/019931 JP2005019931W WO2007049356A1 WO 2007049356 A1 WO2007049356 A1 WO 2007049356A1 JP 2005019931 W JP2005019931 W JP 2005019931W WO 2007049356 A1 WO2007049356 A1 WO 2007049356A1
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Prior art keywords
chip
semiconductor
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Application number
PCT/JP2005/019931
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English (en)
Japanese (ja)
Inventor
Tomoko Higashino
Chuichi Miyazaki
Original Assignee
Renesas Technology Corp.
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Publication date
Application filed by Renesas Technology Corp. filed Critical Renesas Technology Corp.
Priority to PCT/JP2005/019931 priority Critical patent/WO2007049356A1/fr
Publication of WO2007049356A1 publication Critical patent/WO2007049356A1/fr

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    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K26/00—Working by laser beam, e.g. welding, cutting or boring
    • B23K26/36—Removing material
    • B23K26/40—Removing material taking account of the properties of the material involved
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K26/00—Working by laser beam, e.g. welding, cutting or boring
    • B23K26/50—Working by transmitting the laser beam through or within the workpiece
    • B23K26/53—Working by transmitting the laser beam through or within the workpiece for modifying or reforming the material inside the workpiece, e.g. for producing break initiation cracks
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B28—WORKING CEMENT, CLAY, OR STONE
    • B28D—WORKING STONE OR STONE-LIKE MATERIALS
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    • B28D5/0005—Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor by breaking, e.g. dicing
    • B28D5/0011—Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor by breaking, e.g. dicing with preliminary treatment, e.g. weakening by scoring
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01084—Polonium [Po]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Definitions

  • the present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a dicing technique for dividing a semiconductor wafer into semiconductor chips.
  • a measurement unit including a test element in a lattice area called a scribe area on a main surface of a semiconductor wafer (hereinafter referred to as wafer) is used.
  • the integrated circuit formed in each chip region is inspected for characteristics.
  • the wafer is cut along the scribe area, and each chip area is separated into semiconductor chips (hereinafter referred to as chips).
  • a cutting tool called a dicing blade having a disk shape with a width of several tens of meters (micrometers) is used. Therefore, the width of the scribe area provided on the wafer is currently set to a width of about 80 m to 200 m in consideration of tolerances at the time of cutting.
  • chipping chips
  • pure water is used for the purpose of cooling and cleaning the wafer. This pure water may enter the cutting surface force chip and corrode the Cu wiring.
  • the low dielectric constant film has poor adhesion to other interlayer insulation films, and the inside is porous, so it cannot be cut accurately with a dicing blade, or peeling occurs at the interface between films. May occur.
  • This method is a method of cutting a wafer by irradiating a laser beam along a scribe area of a single crystal silicon wafer and selectively forming a fractured layer inside the wafer.
  • this laser dicing method not only the above-mentioned problems can be improved, but also the wafer can be cut with a width of several ⁇ m, so that the width of the scribe area can be reduced to 10 ⁇ m or less. The effect of increasing the number of chips that can be obtained from wafers of the same size can also be expected.
  • Patent Document 1 Japanese Unexamined Patent Application Publication No. 2004-221286 discloses a method in which a laser beam is irradiated to a scribe area in which a dummy wiring layer is formed to form a molten region (fracture layer) inside the wafer.
  • the dummy wiring layer is formed for the purpose of making the laser irradiation region uniform and making it easier to absorb the laser.
  • Patent Document 1 Japanese Patent Application Laid-Open No. 2004-221286
  • a TEG for inspecting the characteristics of the integrated circuit formed in each chip region is arranged in the scribe area of the wafer.
  • a probe probe
  • the width of the TEG is required to be at least about several tens of meters. It is difficult to reduce.
  • the width of the scribe area is limited by the size of the TEG and cannot be reduced to a width that can be cut by a laser (10 ⁇ m or less), so even if the laser dicing method is introduced at present I can hardly expect an increase in the number of chips acquired.
  • a scribe area having a width of about several tens of ⁇ m is cut with a laser
  • the chip region is divided into TEGs when dividing each chip region by the expanding method.
  • a whisker-like conductor wire is formed. This is because the TEG is formed of a metal pattern, and a fracture layer is formed in a silicon region made of a material different from that of the TEG. Therefore, when extending by the expanding method, cracks running from the fractured layer are difficult to be transmitted to the TEG. Therefore, in order to separate the chip from the TEG, the laser must be scanned twice along both sides of the TEG per scribe area, resulting in a complicated cutting process. .
  • An object of the present invention is to provide a technique capable of increasing the number of chips that can be obtained from a wafer of the same size.
  • Another object of the present invention is to provide a technique for quickly cutting a wafer by a laser dicing method.
  • Another object of the present invention is to provide a technique for improving the mounting density of a package in which a plurality of chips are stacked.
  • the present invention includes a reader main body and a reader antenna connected to the reader main body, and for wireless IC tags that read data of a wireless IC tag using microwaves transmitted from the reader main body.
  • a reader wherein the reader antenna is a ceramic antenna.
  • the width of the scribe area can be cut with a laser while securing a region for arranging the TEG.
  • FIG. 1 is an overall plan view of a semiconductor wafer used in an embodiment of the present invention.
  • FIG. 2 is an enlarged plan view showing a chip region of the semiconductor wafer shown in FIG. 3 is an enlarged plan view showing a chip region of the semiconductor wafer shown in FIG.
  • FIG. 4 is a sectional view showing a semiconductor wafer cutting step according to an embodiment of the present invention.
  • FIG. 5 is a cross-sectional view showing a semiconductor wafer cutting step following FIG. 4.
  • FIG. 6 is a cross-sectional view showing a semiconductor wafer cutting step following FIG. 5.
  • FIG. 7 is a perspective view showing a semiconductor wafer cutting step continued from FIG. 5.
  • FIG. 8 is a perspective view showing a semiconductor wafer cutting process continued from FIGS. 6 and 7.
  • FIG. 8 is a perspective view showing a semiconductor wafer cutting process continued from FIGS. 6 and 7.
  • FIG. 9 is a cross-sectional view showing a semiconductor wafer cutting step following FIGS. 6 and 7.
  • FIG. 10 is a cross-sectional view showing a semiconductor wafer cutting step following FIGS. 8 and 9.
  • FIG. 11 is a perspective view showing a semiconductor wafer cutting step continued from FIGS. 8 and 9.
  • FIG. 11 is a perspective view showing a semiconductor wafer cutting step continued from FIGS. 8 and 9.
  • FIG. 12 is a cross-sectional view showing a semiconductor chip peeling step subsequent to FIGS. 10 and 11.
  • FIG. 12 is a cross-sectional view showing a semiconductor chip peeling step subsequent to FIGS. 10 and 11.
  • FIG. 13 is a cross-sectional view showing a semiconductor chip mounting process following FIG. 12.
  • FIG. 14 is a plan view showing a semiconductor chip mounting process following FIG. 12.
  • FIG. 15 is a cross-sectional view showing a step of mounting the semiconductor chip following FIG. 13 and FIG.
  • FIG. 16 is a cross-sectional view showing the mounting process of the semiconductor chip following FIG. 13 and FIG.
  • FIG. 17 is a cross-sectional view showing a step of mounting the semiconductor chip following FIG. 15 and FIG.
  • FIG. 18 is a plan view showing another example of a semiconductor chip mounting method.
  • FIG. 19 is a plan view showing another example of a semiconductor chip cutting method.
  • 20 is a cross-sectional view showing the vicinity of a corner portion of the semiconductor chip along the line A-B in FIG.
  • FIG. 21 is a plan view showing another example of the planar shape of the semiconductor chip.
  • FIG. 22 is a plan view showing another example of a semiconductor chip mounting method.
  • FIG. 23 is a plan view showing another example of a semiconductor chip mounting method.
  • a semiconductor wafer (hereinafter simply referred to as a wafer) 1 as shown in FIG. 1 is prepared.
  • This The wafer 1 is made of, for example, single crystal silicon having a diameter of 300 mm and a thickness force of 50 ⁇ m to 800 ⁇ m, and its main surface is partitioned in a lattice shape by a plurality of chip regions 1A ′.
  • An integrated circuit is built in each chip region 1A ′ by a well-known semiconductor manufacturing process.
  • the semiconductor manufacturing process includes a film forming process, an impurity ion implantation process, a photolithographic process, an etching process, a metallization process, a cleaning process, and an inspection process between the processes.
  • the quality of each chip region 1A ′ is determined by an electrical test using a probe.
  • a case where a memory circuit is formed in each chip region 1A ′ will be described.
  • FIG. 2 and 3 are partially enlarged plan views of the main surface of the wafer 1.
  • FIG. FIG. 2 is an enlarged plan view showing about four chip areas 1A ′
  • FIG. 3 is an enlarged plan view showing about one chip area 1A ′.
  • Each chip region 1A ' is separated from other chip regions 1A' by a grid-like scribe area SA extending in the X direction and the Y direction orthogonal thereto! .
  • the width of the scribe area was set to about 80 ⁇ m to 200 ⁇ m in consideration of the width of the dicing blade.
  • the width of the scribing area SA is determined by taking a dicing blade in both the X and Y directions in consideration of the diameter of the laser beam. It is set to a few meters narrower than the case of use.
  • the diameter of the laser beam is much narrower than the width of the dicing blade, so that the width of the scribe area SA can be greatly reduced.
  • the chip regions 1A 'separated from each other by the scribe area SA have a substantially rectangular planar shape, and a plurality of bonding pads constituting external connection terminals of the memory circuit are located near the short sides.
  • BP is arranged in a row.
  • the chip area 1A ' four corners are chamfered. Therefore, the area where the scribe area SA extending in the X direction and the scribe area SA extending in the Y direction intersect (the area that touches the corner of the chip area 1 A ′) is the width of the scribe area SA is another area.
  • the scribe area SA extending in the X direction and the scribe area SA extending in the Y direction intersect is the width of the scribe area SA is another area.
  • TEG2 is arranged in the above-mentioned intersection region of scribe area SA (region in contact with the corner of chip region 1A ').
  • This TEG2 is a memo formed in the chip area 1A '. It is configured to include a predetermined number of measuring elements for evaluating the characteristics of the re-circuit and a predetermined number of nodes electrically connected to these measuring elements via wiring. It is electrically connected to any one of the four chip areas 1A ′.
  • a probe is applied to the TEG2 pad to evaluate the characteristics of the memory circuit and determine the quality of each chip area 1A '.
  • the TEG2 pad needs a space enough to contact the probe, and therefore has a diameter of at least several tens of ⁇ m.
  • the width of the scribe area SA is set to about several ⁇ m. That is, the width of the scribe area SA is set narrower than the width of TEG2. Therefore, TEG2 cannot be placed in the scribe area SA as it is. Therefore, the corner area of chip area 1A 'is chamfered, and the width of scribe line SA in the area in contact with this corner area is made wider than in other areas, thereby securing a space for placing TEG2. .
  • TEG2 is arranged at a position several m away from the corner of chip area 1A '.
  • the width of the scribe area can be narrowed to a laser-cuttable width (less than 10 m) without being restricted by the TEG dimensions.
  • the interval between the extended chip areas 1A ′ can be reduced. This can increase the number of chips acquired.
  • the back surface of the wafer 1 is ground to reduce its thickness to about 50 to 60 m.
  • a backgrind tape for integrated circuit protection to the main surface of wafer 1 and grind the back side with a grinder.
  • the damaged layer generated in the wafer 1 by this grinding is removed by a method such as wet etching, dry polishing, or plasma etching.
  • the wafer 1 is placed on a flat glass substrate 3 as shown in FIG.
  • the wafer 1 is attached to the glass substrate 3 via a tape coated with an ultraviolet curable pressure sensitive adhesive.
  • a suction port penetrating the upper and lower surfaces of the glass substrate 3 may be provided, and the wafer 1 may be adhered to the glass substrate 3 by a vacuum suction method.
  • TEG2 and alignment mark are arranged in scribe area SA, the laser beam will be shielded by TEG2 and alignment mark, so that a fracture layer may be formed inside wafer 1. Have difficulty.
  • the TEG 2 and alignment mark chamfer the corner portion of the chip region 1A ′ and place it in the region in contact with the corner portion. It is possible to form a crushing layer in the interior of the UENO 1 even when the surface side force is irradiated.
  • any surface may be directed upward, but the case where the wafer 1 is placed on the glass substrate 3 with the back surface facing upward will be described below.
  • the pattern of the chip area 1A and the scribe area SA on the main surface of the wafer 1 is recognized, and the laser scanning area is determined based on the recognition data. To do. Since the wafer 1 is extremely thin, the pattern can be recognized not only from the main surface side but also from the back surface side.
  • the laser beam LB emitted from the laser generator 30 is irradiated onto the wafer 1 while scanning along the scribe line SA.
  • a laser generator 30 is disposed above the wafer 1 and the laser beam LB is irradiated from the back side of the wafer 1.
  • the laser generator 30 may be disposed below the glass substrate 3 and the main surface side of the wafer 1 may be irradiated with the laser beam LB that has passed through the glass substrate 3.
  • a YAG laser having a wavelength of 1064 nm is used, and the center of the wafer 1 in the thickness direction is aligned and irradiated. As a result, a fractured layer 31 is formed inside the wafer 1 along the scribe line SA.
  • the laser beam LB is scanned along the corner portion of the chip region 1A. At this time, the laser beam LB is irradiated to the gap between the chip region 1A ′ and TEG2. As a result, a crushing layer can be formed inside the wafer 1 along the corner portion, and TEG2 can be separated from the chip area 1A ′ when the chip areas 1A ′ are separated from each other in the later process. .
  • one surface of a die attach film 4 is attached to the back surface of the wafer 1 fixed to the glass substrate 3, and a dicing tape is attached to the other surface of the die attach film 4.
  • Paste 5 the wafer ring 6 is attached to the periphery of the dicing tape 5.
  • the wafer ring 6 is a jig for holding the dicing tape 5 and applying a horizontal tension to the dicing tape 5.
  • the die attach film 4 is a film-like adhesive having a thickness of 20 to about L 00 m that serves as an adhesive layer when a chip separated from the wafer 1 is mounted on a wiring board or another chip.
  • the dicing tape 5 has a tackiness by applying an ultraviolet curable pressure sensitive adhesive or the like on one side of a tape substrate made of polyolefin (PO), polyvinyl chloride (PVC) or the like.
  • PO polyolefin
  • PVC polyvinyl chloride
  • the tape is about 90m to 120m thick. Conventionally, when dicing tape 5 is used to cut a wafer with a dicing blade, the dicing tape 5 is pasted on the back surface of the wafer and used as it is!
  • the glass substrate 3 is removed from the wafer 1.
  • the adhesive is irradiated with ultraviolet rays. In this way, the pressure-sensitive adhesive is cured and the adhesive strength is reduced, so that the glass substrate 3 can be easily removed from the wafer 1.
  • FIGS. 8 and 9 the dicing tape 5 to which the wafer 1 is bonded is positioned horizontally on the support ring 11 of the pickup device 10 and bonded to the peripheral portion of the dicing tape 5.
  • the expanded wafer ring 6 is held by the expanding ring 12.
  • FIG. 8 is an external perspective view of the pick-up device 10
  • FIG. 9 is a schematic cross-sectional view showing the positional relationship between the wafer ring 6, the support ring 11 and the expanding ring 12.
  • a suction piece 13 for pushing the chip 1 upward is disposed.
  • the die attach film 4 on the back surface of the wafer 1 is also stretched together with the dicing tape 5 and separated in units of chips, so that the die attach of the same size as the chip 1 is placed on the back surface of the chip 1 that has been separated. Film 4 remains.
  • TEG2 arranged in the intersecting area of the scribe area SA (the area in contact with the corner of the chip area 1A ') is separated from the chip area 1A', and therefore does not remain in the chip 1. Therefore, the planar shape of the diced chip 1 is a rectangle with chamfered corners.
  • the suction piece 13 is disposed immediately below one chip 1 and the suction collet 14 is brought into close contact with the upper surface of the chip 1.
  • a suction port 14a in which the inside is depressurized, so that only one chip 1 to be peeled can be selectively sucked and held.
  • the dicing tape 5 is irradiated with ultraviolet rays. By rubbing in this way, the pressure-sensitive adhesive applied to the dicing tape 5 is cured and the adhesive strength is lowered, so that the die attach film 4 can be easily peeled off from the dicing tape 5.
  • the suction piece 13 is pushed upward, and the suction collet 14 is moved upward to peel off the chip 1 and the die attach film 4 from the dicing tape 5.
  • the chip 1 peeled from the dicing tape 5 is adsorbed and held by the adsorption collet 14, and conveyed to the next process (pellet attaching process). As shown in FIG. 13 and FIG. After being mounted on the wiring board 17A via the die attach film 4, it is electrically connected to the electrode 16 of the wiring board 17A via the Au wire 15.
  • the second chip 1 is peeled off from the dicing tape 5 in accordance with the procedure described above, and the pelletizing process is performed again. Be transported. Then, as shown in FIG. 15 and FIG. 16, after being mounted on the first chip 1 via the die attach film 4, it is electrically connected to the electrode 16 of the wiring board 17A via the Au wire 15. Is done. Next, as shown in Figure 17, The package 19 is completed by sealing the chip 1 and the Au wire 15 on the substrate 17A with the resin 18.
  • the package 19 shown in the figure is an example in which two chips 1 are stacked, but one or a plurality of chips 1 can be sequentially stacked on the second chip 1 in accordance with the procedure described above.
  • the corner portion of the chip region 1A ′ of the wafer 1 is chamfered, and the TEG 2 is arranged in the scribe area SA in the region in contact with the corner portion.
  • the width of the scribe area SA can be narrowed to a width that can be cut by a laser (10 m or less) while securing a region where the TEG 2 is arranged, so that it can be obtained from the wafer 1 having the same diameter.
  • the number of chips 1 can be increased.
  • the chip area 1A 'and TEG2 can be obtained by scanning the laser beam only once around the chip area 1A'. Therefore, it is possible to quickly cut the wafer and 1 with a laser.
  • the package 19 in which the chip 1 mounted on the wiring board 17 is sealed with the grease 18 is caused by the difference in thermal expansion coefficient between the wiring board 17 and the chip 1.
  • the fact that stress is easily applied to 1 contributes to a decrease in the reliability of the package 19.
  • the corner portion of chip 1 has a large thermal stress because the amount of expansion and contraction due to heat that the distance of the center force of chip 1 is long is maximized.
  • the chip 1 of the present embodiment has a corner portion that is chamfered, so that the distance from the center portion to the corner portion is substantially shorter than a chip of the same diameter that is not chamfered. Accordingly, the thermal stress concentrated on the corner portion of the chip 1 is reduced correspondingly, so that the reliability of the knock 19 can be improved.
  • the force for separating the chip 1 and the TEG 2 may be cut so that the TEG 2 remains in the corner portion of the chip 1 as shown in FIG. Chip 1 corner
  • the planar shape of chip 1 is apparently rectangular, but the planar shape of the region that substantially functions as chip 1 is chamfered at the corner as in the previous embodiment. It becomes a rectangle.
  • FIG. 20 is a cross-sectional view showing the vicinity of the corner portion of chip 1 along the line AB in FIG.
  • a one-dot chain line C in the figure indicates a chamfered area
  • the chip 1 is on the left side
  • the scribe area SA is on the right side.
  • a guard ring 20 having a metal layer force in the same layer as the wiring of the integrated circuit formed in the chip 1.
  • the guard ring 20 is formed so as to surround the entire peripheral portion of the chip 1, and prevents moisture and foreign matter from entering the inside of the chip 1 from the end of the chip 1.
  • the wafer 1 is cut so that the TEG2 remains in the corner portion of the chip 1, it is only necessary to scan the laser in the X direction and the Y direction in FIG. Compared to the first embodiment, the laser scanning distance is shortened, and the wafer 1 can be cut more quickly by the laser.
  • the package 19 in which the chip 1 mounted on the wiring board 17 is sealed with the resin 18 is attached to the chip 1 due to the difference in thermal expansion coefficient between the wiring board 17 and the chip 1. Stress tends to be applied, especially stress tends to concentrate on the corner of the chip 1 where the center force distance is long.
  • what is arranged at the corner of chip 1 is TEG2 and alignment marks. Since TEG2 and alignment mark are necessary wiring in the manufacturing process, the reliability of package 19 will not be reduced even if TEG2 and alignment mark are damaged by thermal stress after sealing is completed. .
  • the present invention is not limited to this, and the nonvolatile memory circuit in which the bonding pad is formed on one short side.
  • the present invention can be applied to cutting various wafers on which logic circuits having bonding pads formed on a plurality of sides are formed.
  • the wafer irradiated with the laser is attached to the dicing tape,
  • the chips are separated by stretching the dicing tape, but the method for separating the chips is not limited to this.
  • the chip may be singulated by bending the wafer from the scribe area.
  • the planar shape of the chip to be cut by the laser is not limited to a quadrangle whose corners are chamfered, but may be a polygon other than a quadrangle.
  • FIG. 21 is a plan view of the chip 1B cut so that the planar shape is an octagon.
  • FIG. 22 is a plan view in which the chip 1C cut so that the planar shape is circular is mounted on a circular wiring board 17C.
  • FIG. 23 is a plan view in which the circular chip 1C shown in FIG. 22 is mounted on the wiring board 17D in multiple stages.
  • the present invention can be applied to the manufacture of a semiconductor device having a semiconductor wafer cutting process using a laser.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Mechanical Engineering (AREA)
  • Optics & Photonics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Oil, Petroleum & Natural Gas (AREA)
  • Dicing (AREA)

Abstract

Selon l'invention, sur un plan principal d'une tranche (1) sont formées une pluralité de zones de puces (1A'), séparées l'une de l'autre par des zones de séparation (SA) présentant une largeur de plusieurs μm. Une forme plane de la zone de puces (1A') est rectangulaire avec des sections d'angle chanfreinées. La zone de séparation (SA) dans une zone en contact avec la section d'angle présente une largeur plus grande par comparaison avec les largeurs des autres zones, et elle possède, disposé sur elle, un groupe d'éléments de test (2). Afin de diviser la tranche (1) en puces, un procédé de découpe par laser est employé pour irradier la zone de séparation (SA) avec un faisceau laser et pour former une couche de cassure à l'intérieur de la tranche (1) le long de la ligne de séparation (SA).
PCT/JP2005/019931 2005-10-28 2005-10-28 Composant a semiconducteur et son procede de fabrication WO2007049356A1 (fr)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009076787A (ja) * 2007-09-21 2009-04-09 Fujitsu Microelectronics Ltd 半導体装置及びその製造方法、並びにその設計方法
JP2012156258A (ja) * 2011-01-25 2012-08-16 Toshiba Corp 半導体チップの製造方法および半導体装置
JP2018063986A (ja) * 2016-10-11 2018-04-19 株式会社ディスコ ウェーハの加工方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0217657A (ja) * 1988-07-05 1990-01-22 Mitsubishi Electric Corp 半導体集積回路
JP2002043528A (ja) * 2000-07-27 2002-02-08 Nec Microsystems Ltd 半導体ウェハ及び特性評価回路
JP2004079667A (ja) * 2002-08-13 2004-03-11 Seiko Epson Corp 半導体装置および半導体装置の製造方法
JP2004079746A (ja) * 2002-08-16 2004-03-11 Tokyo Seimitsu Co Ltd チップ製造方法
JP2005228892A (ja) * 2004-02-12 2005-08-25 Toshiba Corp 半導体ウェーハと半導体素子およびその製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0217657A (ja) * 1988-07-05 1990-01-22 Mitsubishi Electric Corp 半導体集積回路
JP2002043528A (ja) * 2000-07-27 2002-02-08 Nec Microsystems Ltd 半導体ウェハ及び特性評価回路
JP2004079667A (ja) * 2002-08-13 2004-03-11 Seiko Epson Corp 半導体装置および半導体装置の製造方法
JP2004079746A (ja) * 2002-08-16 2004-03-11 Tokyo Seimitsu Co Ltd チップ製造方法
JP2005228892A (ja) * 2004-02-12 2005-08-25 Toshiba Corp 半導体ウェーハと半導体素子およびその製造方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009076787A (ja) * 2007-09-21 2009-04-09 Fujitsu Microelectronics Ltd 半導体装置及びその製造方法、並びにその設計方法
JP2012156258A (ja) * 2011-01-25 2012-08-16 Toshiba Corp 半導体チップの製造方法および半導体装置
JP2018063986A (ja) * 2016-10-11 2018-04-19 株式会社ディスコ ウェーハの加工方法

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