WO2007027534A1 - Dispositif afficheur type a matrice active - Google Patents

Dispositif afficheur type a matrice active Download PDF

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Publication number
WO2007027534A1
WO2007027534A1 PCT/US2006/033314 US2006033314W WO2007027534A1 WO 2007027534 A1 WO2007027534 A1 WO 2007027534A1 US 2006033314 W US2006033314 W US 2006033314W WO 2007027534 A1 WO2007027534 A1 WO 2007027534A1
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WO
WIPO (PCT)
Prior art keywords
light emitting
subframe
subframes
driver element
voltage
Prior art date
Application number
PCT/US2006/033314
Other languages
English (en)
Inventor
Shinya Ono
Original Assignee
Eastman Kodak Company
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Eastman Kodak Company filed Critical Eastman Kodak Company
Priority to EP06790008.4A priority Critical patent/EP1920430B1/fr
Priority to US12/064,091 priority patent/US8013813B2/en
Publication of WO2007027534A1 publication Critical patent/WO2007027534A1/fr

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0876—Supplementary capacities in pixels having special driving circuits and electrodes instead of being connected to common electrode or ground; Use of additional capacitively coupled compensation electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2077—Display of intermediate tones by a combination of two or more gradation control methods
    • G09G3/2081—Display of intermediate tones by a combination of two or more gradation control methods with combination of amplitude modulation and time modulation

Definitions

  • the present invention relates to an active-type display device having a pixel circuit for each of a number of pixels and, more particularly, to such a device in which luminance is controlled by changing a light emitting period of a pixel using a pixel signal voltage.
  • organic electroluminescent (EL) display devices using a self light emitting organic EL element do not require a backlight as do liquid crystal display devices, EL display devices are advantageous for reducing the thickness of displays. For that reason, and because the viewing angle of EL display devices is not restricted, it is widely anticipated that development of EL display devices will lead to their becoming the next generation of display devices.
  • the organic EL element used in an organic EL display device also differs from a liquid crystal cell in that, while the display in each liquid crystal cell is controlled by an applied voltage, in an organic EL element, the luminance of each of light emitting element is controlled by the value of the current flowing through the element.
  • FIG 9 shows a pixel circuit in an organic EL display device of the active matrix system of the time division method of a conventional art, such as that disclosed in Japanese Patent Application No.2002-149113 (Page 24, FIG 8; Page 25, FIG 9).
  • a scanning line driving circuit 106 two scanning lines consisted of a first scanningline 101 and a second scanning line 102 extend to respective pixels.
  • Asource supply circuit 107 supplies a positive voltage VDD and a negative voltage Vss to the respective pixels.
  • a signal line driving circuit 108 supplies signal voltages to the respective pixels through a signal line 103.
  • the first scanning line 101 is connected with the gate of a switching element 109, and the n-channel switching element 109 turns on or off a connection of the signal line 103 with the gate of ap-channel driver element 104.
  • the second scanning line 102 is connected with the gate ofa discharge switch element 110, and the discharge switch element 110 turns on or off a connection of the positive source V DD with the gate of the driver element 104.
  • a capacitance 111 is connected in parallel.
  • One end of the driver element 104 is connected with the positive source V DD and the other end thereof is connected with the negative source Vss via a light emitting element 105.
  • the discharge switch element 110 when the discharge switch element 110 is turned on, both ends of the capacitance 111 are short-circuited for discharging.
  • the discharge switch element 110 When the discharge switch element 110 is turned off and the switching element 109 is turned on, a signal voltage of the signal line 103 is written in the capacitance 111, and, in accordance with the written voltage, the driver element 104 and, therefore, the light emitting element 105 are turned on or off.
  • the light emitting period in one frame is determined by a combination of emission off or on subframes which is assigned a weight of 0 to n bits, thus display gradations in accordance with luminance data obtained therefrom.
  • a problem of visibility called false contours is reduced for a bit having a comparatively longer light emitting period by arranging the bits by dividing and dispersing the light emitting period on the time axis.
  • the driver element 104 has a fimction as a switch for turning on or off the current flowing to the light emitting element 105.
  • a gate voltage of the driver element 104 is applied either an on-voltage sufficiently larger than a threshold voltage of the driver element 104 or an off-voltage sufficiently smaller than the threshold voltage. Because the impedance of the driver element 104 is sufficient smaller than the impedance ofthe light emitting element 105 when the driver element 104 is turned on, the value ofthe current flowing to the light emitting element 105 while the light emitting element 105 is emitting light is determined by the impedance ofthe light emitting element 105.
  • FIG 11 shows a pixel circuit in an organic EL display device ofthe active matrix system ofthe time division method of another conventional art (See, for example, Kageyama et al, "51.1 : A 2.5 inch OLED Display with a Three-TFT Pixel Circuit for Clamped Inverter Driving", SID04 DIGEST, p 1395, FIGS.3 and 4.).
  • a source supply circuit 207 supplies a positive source V DD (positive source voltage V DD ) and a negative source Vss (negative source voltage Vss) to the respective pixels.
  • a signal line driving circuit 208 supplies signal voltages to the respective pixels via a signal line 203.
  • the signal line 203 is connected with the gate of a driver element 204 via capacitance 211, and the source ofthe driver element 204 is connected with the positive source VDD-
  • the first scanning line 201 is connected with the gate of an n-channel first switching element 209, and the first switching element 209 turns on or off the connection between the gate and the drain ofthe p-channel driver element 204.
  • the second scanning line 202 is connected with the gate of an n-channel second switching element 210, and the second switching element 210 is provided between the drain ofthe driver element 204 and an anode ofthe light emitting element 205 for turning on or off the connection between the second switching element 210 and the driver element 204. Accordingly, in a state where the second switching element 210 is turned on, the current flowing to the driver element 204 flows to the light emitting element 205.
  • Such writing operation of the signal voltage is performed in parallel for pixels of respective columns within one row, and the operation is sequentially performed for respective rows (n rows in FIG 12).
  • a writing period of the signal voltage in all pixels is first executed, and after writing is complete all pixels enter into a light emitting period.
  • a triangular wave is applied as a reference voltage to the capacitance 211 through the signal line 203, and, during a period where the voltage of the triangular wave is lower than the signal voltage written in the pixels during the data writing period, the driver element 204 is turned on to cause the light emitting element 205 to emit light.
  • the threshold voltage of the driver element 204 can be compensated for, influence of variations of the threshold voltage of the driver element 204 can be further reduced than by the method shown in FIG 9.
  • duty ratio a ratio of the light emitting period in one frame(hereinafter referred to as duty ratio)
  • the present invention provides an active matrix-type display device having a pixel circuit in each of a number of pixels arranged in matrix, in which each pixel circuit includes a light emitting element which emits light using a driving current, a driver element for controlling supply of the driving current to the light emitting element, a capacitance in which a signal voltage is written from a signal line for applying a voltage corresponding to the written signal voltage to the gate of the driver element, and a gate potential control line for shifting potential of the capacitance to control gate potential of the driver element, wherein one frame is divided into a plurality of subframes, and in each of the subframes, at least three stages of signal voltage are written in the capacitance from the signal line, and in one of the subframes, after the signal voltage is written in, sub-subframes are formed by further dividing the subframe by changing the gate potential of the driver element by the gate potential control line, and the gate electrode voltage of the driver element in the sub-subframe is controlled by combining the signal voltage and the voltage of the gate potential
  • the sum of lengths of all subframe periods is preferably equal to the length of one frame period.
  • the sub-subframes, in one frame have a priority light emitting period for a second half sub-subframe in a first half subframe, and a priority light emitting period for the first half sub-subframe in the second half subframe.
  • the lengths of the subframes are preferably equal.
  • the driver element is preferably a field effect transistor.
  • the field effect transistor is preferably a thin film transistor.
  • the light emitting element is preferably an organic EL element.
  • a gate potential control line is provided on an electrode on a side not connected with a gate electrode of capacitance connected with a gate electrode of a driver element, and, by controlling the gate potential control line, a subframe is divided into sub-subframes, such that the number of the subframes is thus minimized. Then, still smaller sub-subframes are prepared by controlling relationship between the signal voltage written in one subframe and a control line voltage in a predetermined way, whereby the number of writings is reduced and reduction of speed and power consumption of a driving circuit is made possible.
  • by sequentially performing data writing and gate electrode control processing of the driver element by means of capacitance by scanning processing it is possible to ensure a duty ratio greater than 90%.
  • FIG 1 is a block diagram showing the configuration of one embodiment of the present invention.
  • FIG 2 A is a timing chart of the embodiment shown in FIG 1 ;
  • FIG 2B is another timing chart of the embodiment shown in FIG 1 ;
  • FIG 3 A is a block diagram showing a data writing state of the embodiment shown in FIG 1 ;
  • FIG 3B is ablock diagram showing a light emitting state of the embodiment shown in FIG 1
  • FIG 3C is block diagram showing another light emitting state of the embodiment shown in FIG 1 ;
  • FIG 4A is a block diagram showing a data writing state according to another embodiment of the present invention.
  • FIG 4B is a block diagram showing a light emitting state of the embodiment shown in FIG 4A;
  • FIG 4C is ablock diagram showing another light emitting state of the embodiment shown in FIG 4A;
  • FIG 5 is a table showing states of input signals and second scanning lines of the embodiment shown in FIG 4A;
  • FIG 6A is a block diagram showing example 1 of scanning line driving circuit utilized in the embodiment shown in FIG 4A;
  • FIG 6B is a block diagram showing example 2 of scanning line driving circuit utilized in the embodiment shown in FIG 4A;
  • FIG 7A is a table showing an example of application of the present invention to a 4 bit gradation display device
  • FIG 7B is a table showing another example of application of the present invention to a 4 bit gradation display device
  • FIG 7C is a table showing an example of application of the present invention to a 6 bit gradation display device
  • FIG 7D is a table showing another example of application of the present invention to a 6 bit gradation display device
  • FIGS. 8A, 8B, 8C and 8D are charts illustrating conditions enabling expressions by all gradations;
  • FIG 9 is a block diagram showing the configuration of a conventional pixel circuit 1;
  • FIG 10 is a timing chart of the conventional pixel circuit 1 ;
  • FIG 11 is a block diagram showing a make-up of another conventional pixel circuit 1;
  • FIG 12 is a timing chart of the another conventional pixel circuit 2
  • FIG 13 is a timing chart showing a state of light emitting in 6 bit gradations of the another conventional pixel circuit 2;
  • FIG 14 is a block diagram showing an example configuration of another pixel circuit
  • FIG 15A is a block diagram explaining operations of the pixel circuit shown in FIG 14;
  • FIG 15B is a block diagram explaining operations of the pixel circuit shown in FIG 14
  • FIG 15C is a block diagram explaining operations ofthe pixel circuit shown in FIG 14.
  • FIG 16 is a table explaining operations ofthe pixel circuit shown in FIG 14.
  • FIG 1 shows a display device in which the present invention is applied
  • FIG 2A shows a timing chart for explaining an operation thereof.
  • a source supply circuit 4 is connected with a positive source line 12 maintained at a voltage VQD and a negative source line 13 maintained at a voltage Vss, which extend to respective pixels.
  • signal lines 14 for supplying signal voltages corresponding to luminance signals of respective pixels extend along respective columns.
  • a first and second scanning lines 10, 11 for controlling seizure of signal voltages at respective pixels extend along respective rows.
  • Each of the pixels is provided with an n-channel switching element 15, a capacitance 16, a p-channel driver element 17, and a light emitting element 18.
  • the switching element 15 has the drain or the source being connected with the signal line 14, the source or the drain being connected with the gate of the driver element 17, and the gate being connected with the first scanning line 10. It should be noted that a p-channel switching element 15 maybe used.
  • One end of the capacitance 16 is connected with the gate of the driver element 17, and the other end of the capacitance 16 is connected with the second scanning line 11.
  • the source of the driver element 17 is connected with the positive source line 12, and the drain thereof is connected with an anode electrode of the light emitting element 18.
  • a cathode electrode of the light emitting element 18 is connected with the negative source line 13.
  • one frame is made up of a plurality of subftames, and one subframe thereof is divided into a data writing period and two sub-subframes, the sub-subframes being detenriined by a level of the second scanning line 11.
  • the subframes correspond to either State A or State B in FIG 5, depending on the level of the second scanning line 11.
  • the signal voltage of the signal line 14 is set at any one of Vo, VO-VDI, or VO-VDI-VDS by the signal line driving circuit 2 and, after the second scanning line 11 is set to a low voltage VL by a scanning line driving circuit 3, the first scanning line 10 is controlled by the scanning line driving circuit 3 such that the switching element 15 is in conductive state (FIG 3A). Thereafter, a pixel enters into a sub-subframe which is either in the State A or State B depending on the state of the second scanning line 11. Li other words, when the second scanning line 11 is set at V b the sub-subframe is in the State A, and when it is set at VH, the sub-subframe is in the State B (FIG 5).
  • V H , VL, V 0 , VD 1 , and V 02 are set such that the following below-noted relationships are satisfied when a threshold voltage of the driver element 17 is set at V t .
  • V t is set equal to 0.
  • Formula 1 V DD -Vo ⁇ -V t V DD -(Vo-V D1 ) >-V t
  • VDD V 0 -VD 1 -VD 2 ) - (V H -V L ) > -V t
  • V sg + V t > 0 is satisfied for the gate voltage of the driver element 17 if the voltage of the second scanning line 11 is VL (State A: priority sub-subframe which is turned on with priority), and the driver element 17 is turned on to cause the light emitting element 18 to emit light.
  • VL voltage of the second scanning line 11
  • VH voltage of the second scanning line 11
  • V sg + V t ⁇ 0 is applied to the driver element 17, the driver element 17 is turned off, and the light emitting element 18 does not emit light.
  • the time ratio of the sub-subframes can be controlled by controlling the duty ratio of the second scanning line 11. It is also possible that the sequence of the State A and State B can be altered in an arbitrary subframe as shown in FIG 2B.
  • the false contour can be reduced by approximation to the light emitting characteristic shown in FIG 13 as described in the non-patent art discussed above, without increasing the refreshing number as n + m times as described in the cited patent application. Furthermore, because a duty ratio of almost 100% can be secured by the method according to the present embodiment in conjunction with the related art method described above, which does not generate false contours, the current density of the light emitting element at the time of light emitting can be reduced enabling elongation of lifetime and reduction of power consumption of the light emitting element; both are clearly advantages.
  • FIGS.4Ato 4C show the configuration and operation of another embodiment of the present invention.
  • the gate of the driver element 17 is connected with one end of capacitance 19, other end thereof being maintained at a constant voltage supplied from a source supply circuit 4. Accordingly, as shown in FIG 4A, when a voltage V da i a is supplied from the signal line 14 to the gate of the driver element 17, the capacitance 19 is also charged.
  • FIG 7A shows an example of control in case of 4 bits (16 gradations).
  • four subframes l to 4 are prepared. Then, the subframe l having a total length of 4 units is divided into two sub-subframes, the first half thereof having a length of 3 units and the second half having a length of 1 unit (3:1), with the second half being the priority light emitting period; the subframe 2 having a total length of 4 units is divided into two sub-subframes, each of the first half and the second half thereof having a length of 2 units, respectively(2:2), with the second half being the priority light emitting period; the subframe 3 having a total length of 4 units is divided into two sub-subframes, each of the first half and the second half thereof having a length of 2 units, respectively(2:2), with the first half being the priority light emitting period; and the subframe 4 having a total length of 3 units is divided into two sub-subframes, the first half thereof having a length of 2 units and the second half having a length of
  • the subframe 1 having a total length of 7 units is divided into two sub-subframes, the first half thereof having a length of 6 units and the second half having a length of 1 unit(6: 1), with the second half being the priority light emitting period;
  • the subframe 2 having a total length of 6 units is divided into two sub-subframes, the first half thereof having a length of 4 units and the second half having a length of 2 units (4:2), with the second half being the priority light emitting period;
  • the subframe 3 having a total length of 6 units is divided into two sub-subframes, each of the first half and the second half thereof having a length of 3 units, respectively ⁇ :3), with the first half being the priority light emitting period;
  • the subframe 4 having a total length of 6 units is divided into two sub-subframes, the first half thereof having a length of 4 units and the second half having a length of 2 units (4:2), with the
  • the duty ratio of 0 to 100% can be realized by preparing 6 subframes and providing sub-subframes of 10:1, 9 : 2, 7:4, 6:4, 8:2, and 9:1.
  • FIG 7D other examples of make-up of sub-subframes which realize display of 6 bits (64 gradations) with 6 subframes are also available, such as shown in FIG 7D.
  • the number of subframes corresponding to the number of gradations necessary for display is determined in the following manner in accordance with the number of gradations of the sub-subframes.
  • the number of the gradations of a display device is set as n bits, and the number of the subframes is set asm.
  • the gradations expressed by respective subframes are configured as:
  • the number of subframes m is the minimum value of k which satisfies the above fomiula
  • the number of subframes of m expressed by k is the rninimum number for satisfying the above formula.
  • the number of subframes m is the minimum value of k which satisfies the above formula
  • the number of gradations desirably expressed is expressed, in this manner, utilizing the sub-subframes.
  • the frequency of the subframe does not change even if the duty ratio between two sub-subframes within one subframe is altered. Accordingly, display of larger gradations can be achieved while maintaining a small subframe display rate.
  • FIG 14 shows another example of pixel circuit make-up. Ih this example, an anode of the light emitting element 18 is connected with the positive source line 12, a cathode thereof is connected with the drain of the n-channel driver element 17, and the source of the driver element 17 is connected with the negative source line 13.
  • a switching element 21 for short-circuiting is provided between the drain and the gate of the driver element 17, and the gate of the switching element 21 for short-circuiting is connected with the first scanning line 10. Furthermore, a capacitance 16 is arranged between the gate of the driver element 17 and the source or drain of the switching element 15 (on a side which is not connected with the signal line 14). With this configuration, the switching element 15 and the switching element 21 for short-circuiting are turned on by setting the first scanning line 10 at H level as shown in FIGS. 15 A to 15C, a voltage higher by the threshold voltage V t than the voltage Vss of the negative source line 13 is written in the gate of the driver element 17, and a signal voltage is written in the connection of the switching element 15 with the capacitance 16.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Electroluminescent Light Sources (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of El Displays (AREA)

Abstract

S'agissant de l'exécution d'une expression de gradation par un procédé d'attaque à division temporelle, on supprime une fréquence opérationnelle de circuit d'attaque, et on élimine un temps d'émission non lumineuse pour augmenter le temps d'émission lumineuse. Chacun des différents circuits de pixels comprend un élément luminescent, un élément d'attaque pour la marche/l'arrêt d'un courant d'attaque de l'élément luminescent, un élément de commutation pour le contrôle de la connexion d'une électrode de grille de l'élément d'attaque avec une ligne de signal, et une capacité à laquelle une tension de signal fournie par la ligne de signal à l'électrode de grille de l'élément d'attaque est adressée.
PCT/US2006/033314 2005-08-30 2006-08-24 Dispositif afficheur type a matrice active WO2007027534A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP06790008.4A EP1920430B1 (fr) 2005-08-30 2006-08-24 Dispositif afficheur type a matrice active
US12/064,091 US8013813B2 (en) 2005-08-30 2006-08-24 Active matrix-type display device

Applications Claiming Priority (2)

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JP2005-250303 2005-08-30
JP2005250303A JP4773777B2 (ja) 2005-08-30 2005-08-30 アクティブマトリクス型表示装置

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BR112012009848B1 (pt) * 2009-10-30 2021-11-03 The University Of North Carolina At Chapel Hill Método de obtenção de células-tronco/progenitoras multipotentes de mamíferos capazes de se diferenciar em linhagens hepáticas e pancreáticas
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EP1920430B1 (fr) 2015-11-04
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