WO2006104150A1 - Dispositif a semi-conducteurs et son procede de production - Google Patents

Dispositif a semi-conducteurs et son procede de production Download PDF

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Publication number
WO2006104150A1
WO2006104150A1 PCT/JP2006/306306 JP2006306306W WO2006104150A1 WO 2006104150 A1 WO2006104150 A1 WO 2006104150A1 JP 2006306306 W JP2006306306 W JP 2006306306W WO 2006104150 A1 WO2006104150 A1 WO 2006104150A1
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Prior art keywords
semiconductor device
core
manufacturing
insulating film
oxide
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PCT/JP2006/306306
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English (en)
Japanese (ja)
Inventor
Takashi Fuyuki
Yukiharu Uraoka
Takio Hikono
Atsushi Miura
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National University Corporation NARA Institute of Science and Technology
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Application filed by National University Corporation NARA Institute of Science and Technology filed Critical National University Corporation NARA Institute of Science and Technology
Priority to JP2007510529A priority Critical patent/JP5110428B2/ja
Publication of WO2006104150A1 publication Critical patent/WO2006104150A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure

Definitions

  • the present invention relates to a method for manufacturing a semiconductor device using a core made of a metal oxide as a quantum dot and a semiconductor device.
  • Japanese Patent Application Laid-Open No. 11 45990 Japanese Patent Application Laid-Open No. 2003-086715
  • a quantum dot is formed using a caged protein supramolecule, which is called furitin, and the floating dot is used as a storage element.
  • a technique for fabricating a type MOSFET is disclosed.
  • ferritin is composed of a spherical protein outer shell portion having a diameter of 12 ⁇ m composed of 24 proteins, and a central portion of the outer shell portion, which is Fe in vivo. It has a structure with a core part with a diameter of about 6 to 7 nm that absorbs ions and holds them in the form of an oxide. It is called a cocoon-like protein supramolecule because it has an outer shell and a core. Ferritin has an active site that acidifies absorbed Fe ions, and Fe ions are stored as oxides of 5FeO ⁇ 9 ⁇ . Ferritin is not listed above.
  • Ni and Co can be stored in the core.
  • ferritin has a metal oxide in the core portion, and the outer shell has a structure in which 24 monomeric proteins are combined.
  • This ferritin has a feature that it is easy to form as a uniform film because of its self-assembling ability, and the protein in the outer shell is easily decomposed and removed by UV ozone heat treatment.
  • the self-assembly ability of ferritin is used to control the adsorption position of ferritin on the silicon substrate.
  • the metal oxide which is the core, is removed. Structures arranged in a dimensional matrix can be manufactured, and biotechnology can be applied to semiconductor manufacturing technology. At present, the application to a floating gate type MOSFET with a simple structure is being studied.
  • FIG. 13 and FIG. 14 are diagrams showing a manufacturing process of a floating gate type MOSFET using a ferritin core according to the prior art.
  • ferritin absorbs iron ions and accumulates them in the form of oxide 5Fe 2 O ⁇ 9 ⁇ .
  • This treatment produces nanoscale (about 6 nm) metal oxide particles.
  • the produced ferritin is adsorbed on a silicon substrate to produce a film in which each particle is arranged in a two-dimensional matrix.
  • the outer shell of ferritin is formed of biological proteins, and the uniform “nanoblock” can be formed on the silicon substrate by the self-assembling ability of the protein.
  • the two-dimensional matrix of ferritin nanoblocks formed on a silicon substrate is subjected to UV ozone treatment to destroy and remove the protein outer shell.
  • the protein outer shell is a combination of monomeric proteins, and when UV ozone treatment is applied, it is broken apart, while the core metal oxide is not affected by UV ozone treatment, so ferritin Only the protein portion of can be selectively removed. As a result, an ordered arrangement structure of nanodot inorganic materials in which only the metal oxides that are the cores are regularly arranged on the silicon substrate can be obtained.
  • the core which is an inorganic material of metal oxide, is subjected to a reduction treatment to impart conductivity (S1004).
  • the core obtained in the above S1003 treatment is an Fe 2 O insulator
  • plasma treatment is performed by mixing it with a reducing gas such as hydrogen gas or nitrogen gas.
  • a reducing gas such as hydrogen gas or nitrogen gas.
  • the core and these gases are brought into direct contact with each other, and the core force is deprived of oxygen directly.
  • a silicon oxide film or silicon nitride film is grown as an insulating film on the substrate on which the nanodot inorganic material ordered arrangement structure obtained by the processing of S1004 is formed, and further aluminum on the upper surface. Electrode is deposited.
  • a source and a drain are formed on a silicon substrate, and an aluminum electrode on the upper surface is etched to form a gate electrode.
  • Patent Document 1 Japanese Patent Application Laid-Open No. 11 45990
  • Patent Document 2 Japanese Patent Laid-Open No. 2003-086715
  • a method for fabricating an OSFET is provided.
  • a floating gate type MOSFET electrons flow from the source electrode to the drain electrode in the on state.
  • the electrons flowing through the channel part are partially insulated by the vertical electric field. Pass through the membrane.
  • the dot is a conductive object, it can hold charge as a quantum dot, and charge is accumulated in the dot. Even if the gate is closed after sufficient charge is retained in the dot The charges in the dots are blocked by the insulating film and held. Note that this state is such that the threshold voltage of the transistor is raised by the charge stored in the floating gate, and even if the transistor is operated at a low voltage, the charge is not released and remains held. Become.
  • each dot of the floating gate type MOSFET must have conductivity, but the ferritin core is an iron oxide FeO that is an insulator. So S10
  • Dots that have undergone the reduction treatment in S1004 are composed of Fe and FeO and are easily oxidized, so they are arranged on the substrate in a state that is not chemically stable.
  • an insulating oxide film such as SiO is grown on this dot by sputtering or CVD.
  • this insulating oxide film In the process of forming this insulating oxide film, an oxidation reaction takes place immediately and a core made of Fe or FeO is formed in the process of covering the dots by embedding the dots in the insulating oxide film.
  • the conductive core produced by reducing ferritin core which is an insulator, is oxidized again in the process of forming the insulating oxide film, and returns to the original insulating oxide. Will happen.
  • the present invention provides a new method for manufacturing a semiconductor device that uses ferritin and can maintain high-quality conductivity without deteriorating the conductivity of dots, and the manufacturing method. It is an object to provide a manufactured semiconductor device.
  • a method of manufacturing a semiconductor device of the present invention includes a substrate on which an insulating film is formed by using a core made of a metal oxide as an insulator as a two-dimensional matrix quantum dot. Forming a gate insulating film on the substrate on which the cores are arranged; forming an insulating film on the gate insulating film including the core; And an annealing process to reduce to a conductor.
  • the insulating film formed on the substrate is, for example, an oxide film or an oxynitride film.
  • the dot is left as ferritin-derived acid 5Fe O 9
  • a gate insulating film for example, Si film
  • an annealing process is performed on the entire surface, thereby proceeding with a reduction process of ferritin-derived oxide 5FeO ⁇ 9 ⁇ in the gate insulating film.
  • This treatment uses the standard free energy difference for oxide formation.
  • the standard free energy value of SiO is higher than the standard free energy value of Fe O
  • an annealing treatment causes an oxidation-reduction reaction in which Si in the gate insulating film takes O from Fe O, which is a dot, and the dots are reduced to Fe or FeO.
  • the annealing treatment power in the annealing treatment step is preferably a treatment for imparting conductivity to the core by reducing the core, which is a metal oxide, by an oxygen bonding force of the gate insulating film. .
  • the core is derived from a core of a cage protein supramolecular structure, and the dot forming step is arranged with a first step of arranging the cage protein supramolecular structure on a substrate in a two-dimensional matrix.
  • the outer shell of the protein of the rod-like protein supramolecular structure is removed. It is preferable to have a second step.
  • the rod-like protein supramolecular structure is preferably ferritin.
  • the core of ferritin is selected from iron oxides, nickel oxides, and cobalt oxides !, preferably any metal oxide! /.
  • the gate insulating film is preferably an oxide selected from silicon oxide and germanium oxide.
  • the annealing conditions are preferably as follows.
  • the annealing temperature should be in the range of 100 to 800 degrees.
  • the annealing pressure should be in the range of 0.01 to 2 atmospheres.
  • the annealing time should be in the range of 10 minutes to 10 hours.
  • the semiconductor device manufacturing method described above can be used for manufacturing a MOS capacitor semiconductor device. Further, the above-described method for manufacturing a semiconductor device can be used for manufacturing a floating gate MOS type semiconductor device. Furthermore, the method for manufacturing a semiconductor device described above includes the manufacture of a thin film semiconductor device using the substrate as an insulating substrate, the manufacture of a single electron device using one quantum dot, and the current using the arrangement of quantum dots. Can be used to manufacture a quantum effect device that can flow in the direction horizontal to the substrate.
  • An insulating film for example, a Si film
  • annealing is performed on the entire surface, so that the reduction process of the ferritin-derived oxide 5Fe O 9 ⁇ ⁇ proceeds in the gate insulating film, and Fe
  • the method for manufacturing a semiconductor device according to the present invention uses one quantum dot that is expected as a next-generation device that can be achieved not only by manufacturing a floating gate MOS semiconductor device. It is also useful for manufacturing single-electron devices and quantum effect devices that can flow current in a direction parallel to the substrate using an array of quantum dots.
  • the dot arrangement of the metal core can be determined by examining the cross section of the gate insulating film.
  • the method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device in which a metal oxide-core core that is an insulator is a quantum dot, and the electrical characteristics of the core are changed to an insulator-power conductor.
  • the reduction method and timing of reduction are devised, eliminating the disadvantage of quantum dot oxidation in the process of embedding quantum dots in the insulating film as seen in the prior art. It is a thing.
  • the semiconductor device manufactured by the method for manufacturing a semiconductor device of the present invention exhibits good electrical conductivity in terms of quantum dot electrical characteristics, and the breakdown and deterioration of the electrical characteristics of the quantum dots are small.
  • FIG. 1 and FIG. 2 are diagrams schematically showing a manufacturing process of a floating gate type MOSFET using the cage protein supramolecule according to the present invention. The manufacturing process will be explained step by step.
  • Sponge protein supramolecules exist in the living body, have a spherical protein outer shell with a diameter of about 12 nm, and have a core portion with a diameter of about 6 nm inside.
  • Various inorganic materials can be included in the core. Fe, Ni, Co etc. are mentioned.
  • the cage protein supramolecules By using the cage protein supramolecules, extremely homogeneous metal oxide particles can be obtained at the nano level.
  • the generated rod-like protein supramolecules are adsorbed on the substrate to form a film in which each particle is arranged in a two-dimensional matrix.
  • the outer shell of rod-like protein supramolecules is made of biological protein, and the uniform “nanoblock” can be formed on the substrate by the self-assembly ability of the protein.
  • UV ozonation is applied to the two-dimensional matrix nanoblocks of cage protein supramolecules formed on the silicon substrate to destroy and remove the protein outer shell.
  • the protein outer shell is a combination of 24 monomeric proteins, and it is broken apart by UV ozone treatment, while the metal oxide that is the core is not affected by UV ozone treatment. Therefore, only the protein portion of the rod-like protein supramolecule can be selectively removed to leave only the core. As a result, an ordered structure of nanodot inorganic materials in which only the metal oxides that are the cores are regularly arranged on the silicon substrate can be obtained.
  • a silicon film (Si) or a silicon silicate film (SiO 2) is grown by sputtering or CVD on a substrate on which dots as insulators are arranged, and an aluminum electrode is formed on the upper surface. Vapor deposition is formed.
  • the physical structure forming process (S105) of the floating nanodot gate device is performed.
  • a source and a drain are formed on a silicon substrate, and an aluminum electrode on the upper surface is etched to form a gate electrode.
  • a gate electrode is etched to form a gate electrode.
  • the structure of the floating nanodot gate device has been completed in terms of physical structure, but the electrical characteristics of the dot itself are insulators. Yes, it cannot function as a quantum dot because of the insulator provided in the insulating film. Therefore, the process of reducing the dots to make their electrical properties into conductors and forming them as quantum dots is the last step.
  • each dot which has been an insulator, is reduced by the annealing process so as to exhibit conductivity will be described later.
  • the structure of the floating gate MOSFET is physically built before the reduction process is applied to the dots derived from the molecular core (S104, S105). After that, annealing is performed to reduce each dot, which is an insulator, so that it exhibits conductivity, thereby completing a quantum dot.
  • the technology for manufacturing a floating gate MOSFET by such a manufacturing process is neither disclosed nor suggested in the prior art.
  • FIG. 3 is a diagram schematically showing the principle that each dot is reduced by an insulating film during the annealing process of the present invention. Note that the dots are emphasized and drawn so that they can be easily distributed. This is an expanded internal structure of the actual semiconductor device. /.
  • Reference numeral 110 denotes a semiconductor substrate. For example, a silicon substrate is used. A thermal oxide film 111 is provided on the surface of the semiconductor substrate 110.
  • iron oxide Fe 2 O 3
  • each dot 120 is embedded in the insulating film 130.
  • a silicon film (Si) is used.
  • each electrode as a floating gate MOSFET that is, a source electrode 141, a drain electrode 142, and a gate electrode 143 are provided.
  • each dot 120 which is an insulator, is included in the silicon insulating film 130 as described above.
  • FIG. 4 is a so-called acid-acid reaction curve of Ellingham, which shows the standard free energy of oxide formation. Only the graph for silicon and iron oxides is shown.
  • silicon oxide (SiO 2) is any iron oxide FeO, Fe 2 O, Fe 2 O
  • the present invention is an application of this newly discovered principle of reduction treatment as a method for manufacturing a semiconductor device.
  • a dot derived from the core of a rod-like protein supramolecule is reduced to form a quantum dot, which is a floating gate.
  • This is a function that demonstrates its function as a MOSFET.
  • dots that were initially iron oxide (Fe 2 O 3) by an annealing process (S106) are formed on the surrounding silicon film ( Si)
  • the reduction process is promoted by the change to Fe or FeO as the conductor.
  • the dots that were insulators can be modified to produce conductive quantum dots.
  • ferritin is a cage-like protein supramolecule that exists in the body, has a spherical protein outer shell with a diameter of 12 nm, and a core portion of acid iron iron (Fe 2 O 3) with a diameter of about 6 nm inside.
  • ferritin absorbs iron ions
  • iron ions are in the form of oxide 5Fe O 9 ⁇ ⁇ .
  • the pH of the solution was adjusted to 5.8 using MES-TRIS buffer. This is a technique for increasing the adsorption density of ferritin on the silicon oxynitrate film, which will be described later, by bringing the ⁇ of the solution close to the isoelectric point ( ⁇ 5.3) of ferritin.
  • Ferritin was prepared as a rod-like protein supramolecule by the above procedure.
  • ferritin was evenly adsorbed on a silicon substrate to produce a film arranged in a two-dimensional matrix.
  • the thermal acid solution on the RCA cleaned silicon substrate A film of 3 nm was formed, and the surface was subjected to UV ozone treatment for 10 minutes to make it hydrophilic. After that, the ferritin solution was immediately dropped on the substrate surface, and the outer shell of ferritin held for 10 minutes in a sealed container was formed of biological protein. Nano-level films can be formed.
  • ferritin is subjected to UV ozone treatment to destroy and remove the protein shell.
  • FIG. 6 is a diagram showing a result of observation of a sample obtained by two-dimensionally adsorbing ferritin on a silicon oxide film substrate and removing a protein portion, using a scanning electron microscope.
  • the adsorption density of the ferritin core was 4.5 ⁇ 10 11 Zcm 2 .
  • a gate insulating film was formed on the substrate on which the dots as insulators were arranged.
  • a silicon oxide film (Si) was grown.
  • a silicon oxide film was deposited by parallel plate type tetraethoxysilane plasma CVD (hereinafter TEOS-CVD). Deposition conditions are temperature 300 ° C, pressure 80Pa, high frequency power 225W, TEOS flow rate 3sccm, O flow rate 300sccm
  • the thickness of the silicon oxide film was approximately 17 nm.
  • a gate electrode was provided by an aluminum deposition method, and the physical structure of the floating gate MOSFET was built.
  • the floating gate MOSFET with a built-in physical structure was annealed at a processing temperature of 400 degrees and a processing time of 1 hour in a 9: 1 nitrogen (hydrogen) gas (forming gas) atmosphere.
  • a processing temperature of 400 degrees a processing temperature of 400 degrees
  • a processing time of 1 hour a processing time of 1 hour in a 9: 1 nitrogen (hydrogen) gas (forming gas) atmosphere.
  • FIG. 7 is a diagram showing the results of observation of the manufactured sample with a transmission electron microscope. A floating gate MOSFET with nano-level quantum dots has been fabricated!
  • the concentration of each component was measured using the X-ray photoelectron spectroscopy (XPS) of the dot part of the sample that was produced this time.
  • XPS X-ray photoelectron spectroscopy
  • FIGS. 8 and 9 are diagrams showing the measurement results of Fe2p and Ols spectra by XPS. For comparison, both before and after annealing are shown.
  • Fig. 8 (a) shows the Ols measurement results before annealing
  • Fig. 8 (b) shows the Ols measurement results after annealing
  • Fig. 9 (a) shows the Fe2p measurement results before annealing
  • Fig. 9 (b) shows the annealing.
  • the Fe2p measurement results after treatment are shown.
  • the peak detected around 71 leV is derived from the iron oxide Fe O.
  • the sample substrate is silicon oxide SiO
  • the dots embedded in the insulating film are iron oxide FeO.
  • the iron oxide is derived from FeO.
  • SiO is a component of insulating film.
  • the SiO peak increases as a result of the reduction treatment of ferric oxide.
  • the iron oxide Fe embedded in the insulating film by the annealing treatment of the present invention As described above, the iron oxide Fe embedded in the insulating film by the annealing treatment of the present invention.
  • the fabricated sample substrate can actually function as a MOS capacitor and can also function as a floating gate MOSFET.
  • FIG. 10 (a) is a diagram showing the capacitance-voltage characteristics of a sample MOS capacitor in which quantum dots are formed by the semiconductor manufacturing method of the present invention.
  • Fig. 10 (b) is a diagram showing the capacitance-voltage characteristics of a sample in which a dot derived from the ferritin core was not made.
  • sample substrate physically fabricated as a floating gate MOSFET through the process of S105 actually functions as a floating gate MOSFET as a result of the annealing process of S106.
  • FIG. 11 (a) is a diagram showing the input characteristics of a sample MOSFET in which quantum dots are formed by the semiconductor manufacturing method of the present invention.
  • Fig. 11 (b) shows the input characteristics of the MOSFET with a dot derived from the ferritin core!
  • a dot whose electrical characteristics derived from a ferritin core is an insulator changes its electrical characteristics into a conductor by annealing, It can be used as a quantum dot, and it has been confirmed that the semiconductor device operates as a MOS capacitor and as a floating gate MOSFET.
  • the semiconductor device to be manufactured is a MOS type semiconductor device
  • the semiconductor substrate is a silicon substrate.
  • the substrate may be a glass substrate.
  • the semiconductor device to be manufactured may be a thin film semiconductor device.
  • the present invention can be used in the field of LSI semiconductor devices and the field of manufacturing LSI semiconductor devices.
  • floating-gate MOS semiconductor devices single-electron devices that use one quantum dot, which is expected as the next-generation device, and quantum effect devices that can flow current in a direction parallel to the substrate using an array of quantum dots It is useful in the manufacturing field.
  • FIG. 1 A diagram schematically showing the fabrication process of a floating gate type MOSFET using rod-like protein supramolecules according to the present invention.
  • FIG.2 A schematic diagram showing the fabrication process of a floating gate type MOSFET using rod-like protein supramolecules according to the present invention.
  • FIG. 3 is a diagram schematically showing the principle that each dot is reduced by an insulating film during the annealing process of the present invention.
  • FIG. 6 Diagram showing the results of SEM observation of a sample in which ferritin was adsorbed two-dimensionally on a silicon oxide film substrate and the protein portion was removed.
  • FIG. 10 is a graph showing capacitance-voltage characteristics of a sample MOS capacitor in which quantum dots are formed by the semiconductor manufacturing method of the present invention.
  • FIG. 11 Sample MOSFE in which quantum dots are formed by the semiconductor manufacturing method of the present invention.
  • FIG. 14 A diagram for explaining a phenomenon in which the created conductive dots are oxidized again in the process of forming the insulating oxide film and returned to the original insulating oxide in the prior art.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Nanotechnology (AREA)
  • Chemical & Material Sciences (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Non-Volatile Memory (AREA)

Abstract

La présente invention décrit une structure de suite de points dans laquelle les cœurs ou les isolateurs uniquement sont placés dans l'ordre sur un substrat de silicium ; elle est obtenue en passant par un processus de production de super-molécule de protéine en forme de cage (S101), un processus de production de film (S102) utilisant une super-molécule de protéine en forme de cage et un processus pour retirer le revêtement de protéines d'une super-molécule de protéine en forme de cage (S103). Un film de silicium (Si) est ensuite cultivé sur un substrat à suite de points par un procédé CVD, une électrode d'aluminium est déposée à la vapeur sur sa surface supérieure et le film est soumis à un processus de préparation de structure de condenseur (104). Ensuite, une électrode d'aluminium est fournie et le produit est soumis à un processus de fabrication de structure physique, par exemple un dispositif de grille flottante (S105). Enfin, un traitement de recuisson (S106) est réalisé. Le traitement par recuisson réduit chaque point qui a été un isolateur au moyen d'un film de silicium pour le modifier afin de montrer de la conductivité. Un procédé de production de dispositif à semi-conducteurs et un semi-conducteur capable d'assurer la conductivité de manière constante sont donc fournis sans entraîner de détérioration de la conductivité des points.
PCT/JP2006/306306 2005-03-28 2006-03-28 Dispositif a semi-conducteurs et son procede de production WO2006104150A1 (fr)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008194815A (ja) * 2006-12-07 2008-08-28 Matsushita Electric Ind Co Ltd フェリチンを基板上に二次元配列させる方法
JP2008244025A (ja) * 2007-03-26 2008-10-09 Nara Institute Of Science & Technology 薄膜トランジスタの製造方法
WO2009104229A1 (fr) * 2008-02-19 2009-08-27 パナソニック株式会社 Elément de mémoire non volatile résistant et son procédé de fabrication
JP2011096714A (ja) * 2009-10-27 2011-05-12 Nara Institute Of Science & Technology 金属ナノ粒子を有する抵抗変化メモリ

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07106442A (ja) * 1993-09-29 1995-04-21 Oki Electric Ind Co Ltd 不揮発性半導体記憶装置
JP2003086715A (ja) * 2001-09-10 2003-03-20 Matsushita Electric Ind Co Ltd 半導体装置の製造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07106442A (ja) * 1993-09-29 1995-04-21 Oki Electric Ind Co Ltd 不揮発性半導体記憶装置
JP2003086715A (ja) * 2001-09-10 2003-03-20 Matsushita Electric Ind Co Ltd 半導体装置の製造方法

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008194815A (ja) * 2006-12-07 2008-08-28 Matsushita Electric Ind Co Ltd フェリチンを基板上に二次元配列させる方法
JP2008244025A (ja) * 2007-03-26 2008-10-09 Nara Institute Of Science & Technology 薄膜トランジスタの製造方法
WO2009104229A1 (fr) * 2008-02-19 2009-08-27 パナソニック株式会社 Elément de mémoire non volatile résistant et son procédé de fabrication
US7738280B2 (en) 2008-02-19 2010-06-15 Panasonic Corporation Resistive nonvolatile memory element, and production method of the same
JP2011096714A (ja) * 2009-10-27 2011-05-12 Nara Institute Of Science & Technology 金属ナノ粒子を有する抵抗変化メモリ

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