WO2006080116A1 - Thin film transistor and method for manufacture thereof, and thin film transistor substrate and method for manufacture thereof, and liquid crystal display device and organic el display device using said thin film transistor, and transparent electroconductive laminated substrate - Google Patents

Thin film transistor and method for manufacture thereof, and thin film transistor substrate and method for manufacture thereof, and liquid crystal display device and organic el display device using said thin film transistor, and transparent electroconductive laminated substrate Download PDF

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Publication number
WO2006080116A1
WO2006080116A1 PCT/JP2005/019417 JP2005019417W WO2006080116A1 WO 2006080116 A1 WO2006080116 A1 WO 2006080116A1 JP 2005019417 W JP2005019417 W JP 2005019417W WO 2006080116 A1 WO2006080116 A1 WO 2006080116A1
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Prior art keywords
electrode
thin film
substrate
film transistor
transparent
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PCT/JP2005/019417
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French (fr)
Japanese (ja)
Inventor
Kazuyoshi Inoue
Masato Matsubara
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Idemitsu Kosan Co., Ltd.
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Publication of WO2006080116A1 publication Critical patent/WO2006080116A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • H01L29/458—Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode

Definitions

  • the present invention relates to a thin film transistor (hereinafter sometimes referred to as TFT) and a manufacturing method thereof, a thin film transistor substrate and a manufacturing method thereof, and a liquid crystal display device and an organic EL display device using TFT.
  • TFT thin film transistor
  • a matrix type liquid crystal display device is configured so that a display material such as liquid crystal is filled between a TFT array substrate and a counter substrate, and a voltage is selectively applied to the display material for each pixel.
  • the TFT array substrate usually refers to a substrate on which a TFT or the like having a force such as a semiconductor thin film (hereinafter referred to as a semiconductor film) is disposed. Further, a counter electrode, a color filter, a black matrix, and the like are provided on the counter substrate.
  • a liquid crystal display device (Liquid Crystal Display, hereinafter abbreviated as LCD) using such a TFT array substrate is sometimes referred to as a TFT-LCD.
  • a substrate on which a TFT (thin film transistor) is formed is referred to as a thin film transistor substrate or a TFT substrate.
  • a TFT substrate In general, when used in a display device, a plurality of thin film transistors are often formed in an array, so it is often called a TFT array substrate.
  • a TFT array substrate is provided with a TFT and a pixel electrode constituting each pixel on an insulating substrate (typically a glass substrate) such as glass.
  • the TFT in each pixel also has a gate electrode, a source electrode, a drain electrode, and a semiconductor film force. These TFTs and pixel electrodes are arranged in an array.
  • This TFT array substrate is provided with an alignment film and a storage capacitor as necessary in addition to TFT and pixel electrodes on the substrate.
  • signal lines such as gate wirings and source wirings are arranged in the boundary region between the pixels. These signal lines are generally grouped together and run in parallel with each other. It is.
  • the display area of the TFT array substrate consists of an area representing each pixel of the image and a boundary area between the pixels. Outside the display area (outer periphery), input terminals and drive circuits for driving the TFTs are provided corresponding to the signal lines. In this description, an area outside the display area is referred to as an interface area for convenience.
  • TFTs, gates, sources, Z drains, and other common wires are first formed in an array on a glass substrate. Configure the display area.
  • the interface area is configured by arranging input terminals, spare wirings, drive circuits, and the like around the display area. In this way, a TFT array substrate is produced.
  • the gate electrode and the gate wiring are collectively referred to as a gate.
  • the source electrode and the source wiring are simply called a source.
  • the drain electrode and the drain wiring are collectively referred to as a drain.
  • the source and drain are referred to as source Z drain.
  • a conductive thin film hereinafter referred to as a conductive film
  • an insulating film It is necessary to dispose a thin film (hereinafter referred to as an insulating film).
  • a counter electrode is provided on the counter substrate, and a color filter and a black matrix are provided.
  • the two substrates are placed in a state where a gap necessary for injecting the liquid crystal material is provided between the two substrates. Fix the edges of the periphery together. After bonding the peripheral edges together, a liquid crystal material is injected into the gap that exists between the two substrates to make an LCD.
  • Various semiconductor devices and other elements are provided on TFT array substrates and counter substrates used in LCDs using thin film technology.
  • a semiconductor film, an insulating film, and a conductive film are formed.
  • an interlayer insulating film, a contact hole that penetrates the semiconductor film, etc. is further formed.
  • TFT-LCDs have been increased in size or definition. This As a result, it is necessary to use pure A1 or an electrically low-resistance alloy material mainly composed of A1 for TFT-LCD gate wiring and source Z drain wiring to prevent signal delay. Hope from the process.
  • the contact resistance is increased.
  • the (contact resistance) was very high, 1 ⁇ 10 to 1 ⁇ 12 ⁇ , and it was difficult to obtain good contact characteristics.
  • the first electrode that also has pure A1 or A1 alloy force and the second electrode that is made of a transparent conductive film such as ⁇ or ⁇ that becomes a pixel electrode are directly contacted through a contact hole that is opened in the insulating film. It was difficult to realize a TFT array substrate that employs the (connected) configuration.
  • the electrode made of the transparent material constituting the pixel electrode is referred to as the second electrode, and the other conductive material constituting the signal wiring (in many cases, made of A1 (or A1 alloy)) is used.
  • This electrode is called the first electrode.
  • the material constituting the second electrode is called a second electrode material, and the material constituting the first electrode is called a first electrode material.
  • Patent Document 1 For example, in order to obtain a good contact, a first electrode having a two-layer structure in which Cr, Ti, Mo, Cu, Ni, or the like is deposited on pure A1 or an Al alloy has been proposed.
  • Such technology can be found in Patent Document 1, Patent Document 2, and Patent Document 3 below.
  • At least one kind of group force including N, 0, Si, and C force is locally selected in the first electrode portion where the first electrode and the second electrode are in direct contact (connection).
  • impurities Such an impurity is added to the upper layer of the first electrode (that is, the connecting portion) to form a second layer to which the impurity is added, thereby forming a local two-layer structure.
  • Patent Document 4 Such a technique is found in Patent Document 4 below.
  • A1 contains 0.1 to 6 atomic% of at least one substance selected from the group consisting of Au, Ag, Zn, Cu, Ni, Sr, Sm, Ge, and BU as an alloy component.
  • the first electrode using an alloy There has been proposed a structure in which the first electrode is directly joined to the transparent electrode (second electrode). Such a technique can be found in Patent Document 5 below.
  • Patent Document 1 Japanese Patent Laid-Open No. 4253342
  • Patent Document 2 Japanese Patent Laid-Open No. 4-305627
  • Patent Document 3 JP-A-8-18058
  • Patent Document 4 JP-A-11-284195
  • Patent Document 5 Japanese Unexamined Patent Application Publication No. 2004-214606
  • the manufacturing method First, the second electrode having a force such as ITO and IZO (registered trademark) and the first having a pure A1 or A1 alloy force.
  • the contact resistance with the electrode was very high, IX 10E10 ⁇ 1 X 10 ⁇ 12 ⁇ , and good contact resistance could not be obtained
  • an alloy containing 0.1 to 6 atomic% of at least one selected from the group consisting of Au, Ag, Zn, Cu, Ni, Sr, Sm, Ge, and BU as an alloy component in A1 It is known as a conventional technique improved for use as a single electrode. When using this improved conventional technology, the contact resistance between the transparent electrode (second electrode) and the first electrode is about 10 ⁇ 2 ⁇ . ) Causes a battery reaction and dissolution of the electrode occurs. As a result, it is known that wiring breakage occurs.
  • the present invention has been made in view of such problems, and reduces the value of contact resistance (contact resistance) generated at the contact portion between the second electrode and the first electrode, and suppresses the battery reaction.
  • TFT that can be used, manufacturing method thereof, and TFT substrate and liquid using the TFT
  • An object is to realize a crystal display device.
  • the present invention uses, as the first electrode, an A1 wiring material containing Ni and one or more metals selected from ⁇ Mo, Nb, W, Zr ⁇ . Is one of its features.
  • an object of the present invention is to provide a TFT, a manufacturing method thereof, and a liquid crystal display device that can reduce the production cost and improve the productivity by using such an A1 wiring material. .
  • the present invention provides a method for producing a thin film transistor on a transparent insulating substrate in order to solve the above-mentioned problem, and uses the A1 alloy on the transparent insulating substrate as the first electrode.
  • a method for producing a thin film transistor characterized by being an A1 alloy containing
  • a thin film transistor produced by such a manufacturing method does not exhibit high contact resistance even when its drain source or the like is brought into direct contact with the transparent electrode!
  • the method of forming a thin film transistor on a transparent insulating substrate, and manufacturing the thin film transistor substrate includes: A step of forming at least one of a gate, a source, and a drain of the thin film transistor, which is a first electrode, using an A1 alloy; and an insulating film covering the first electrode and the substrate. Forming a contact hole by patterning the insulating film; forming a second electrode having a transparent electrode force on the insulating film; and connecting the second electrode and the first electrode to the first electrode.
  • the thin film transistor substrate produced by such a manufacturing method is a force that directly contacts the drain and source of the thin film transistor with the transparent electrode, and there is no high contact resistance. It can be used sufficiently for devices.
  • the present invention provides a thin film transistor provided on a transparent insulating substrate, At least one of a gate, a source, and a drain of the thin film transistor that is a first electrode formed on the transparent insulating substrate, and the first electrode is made of Ni, ⁇ Mo, Nb, W, Zr ⁇ A thin film transistor characterized by having an A1 alloy strength containing at least one selected metal.
  • the thin film transistor having such a configuration does not exhibit high contact resistance even when its drain or source is brought into direct contact with the transparent electrode.
  • the present invention provides a transparent insulating substrate, at least one of a gate, a source, and a drain as a first electrode formed on the transparent insulating substrate, the first electrode, and the transparent An insulating film formed to cover the insulating substrate, the insulating film having a predetermined contact hole, and a second electrode that is a transparent electrode formed on the insulating film.
  • the first electrode is made of A1 alloy force containing Ni and one or more metals selected from ⁇ Mo, Nb, W, Zr ⁇ , and the second electrode and the first electrode are It is a thin film transistor substrate that is electrically directly connected through a contact hole.
  • the present invention is the thin film transistor substrate according to the above (4), wherein the transparent electrode is made of any one of indium oxide, tin oxide, indium tin oxide, and zinc oxide.
  • the present invention provides a content ratio force of Ni and one or more metals selected from ⁇ Mo, Nb, W, Zr ⁇ in the A1 alloy constituting the first electrode.
  • the present invention relates to a content ratio force of Ni and one or more metals selected from ⁇ Mo, Nb, W, Zr ⁇ in the A1 alloy constituting the first electrode.
  • the content ratios shown in the constitutions of (6) and (7) are preferred and in the range. This content ratio is, of course, the total content ratio of the content ratio of “Ni” and the content ratio of one or more metals of ⁇ Mo, Nb, W, Zr ⁇ .
  • the present invention also provides a transparent insulating substrate and a first insulating layer formed on the transparent insulating substrate.
  • a gate, a source and a drain which are electrodes; an insulating film formed so as to cover the first electrode and the transparent insulating substrate; an insulating film provided with a predetermined contact hole; and formed on the insulating film
  • a second electrode made of a transparent electrode wherein the first electrode is made of an A1 alloy containing Ni and one or more metals selected from ⁇ Mo, Nb, W, Zr ⁇ .
  • a liquid crystal display device having at least a TFT array substrate in which the second electrode and the first electrode are electrically connected directly through the contact hole.
  • the contact resistance can be kept low while the thin film transistor and the transparent electrode are in direct contact with each other, so that a good display can be performed.
  • the first electrode is made of an A1 alloy containing at least Ni and at least one metal selected from ⁇ Mo, Nb, W, Zr ⁇ . Such a first electrode is formed by sputtering using an A1 alloy target containing Ni and one or more metals selected for ⁇ Mo, Nb, W, Zr ⁇ force. .
  • the A1 alloy target containing Ni and one or more metals selected from ⁇ Mo, Nb, W, Zr ⁇ can be prepared by various methods known in the art. For example, it is manufactured by a vacuum melting method, a spray forming method, or the like.
  • the first electrode is an A1 alloy containing at least Ni and one or more metals selected from ⁇ Mo, Nb, W, Zr ⁇ .
  • the first electrode is a drain, a source, or a gate, but in order to actually use it as a drain or the like, it must be patterned into a desired shape. This patterning is performed by etching a thin film of the A1 alloy having the above composition with a mixed acid of phosphoric acid, acetic acid and nitric acid.
  • the A1 alloy thin film itself is formed by sputtering using an A1 alloy target containing Ni and one or more metals selected from ⁇ Mo, Nb, W, Zr ⁇ . Is done.
  • the present invention provides a transparent insulating substrate, a gate, a source and a drain which are first electrodes formed on the transparent insulating substrate, the first electrode and the transparent insulating substrate.
  • An insulating film formed so as to cover the insulating film, the insulating film having a predetermined contact hole, and a second electrode made of a transparent electrode formed on the insulating film, wherein the first electrode Ni and an Al alloy containing at least one metal selected from ⁇ Mo, Nb, W, Zr ⁇ , and the second electrode and the first electrode are electrically directly connected through the contact hole.
  • Contact This is an organic EL display device having at least a TFT array substrate.
  • the present invention also provides a second electrode comprising a transparent insulating substrate, a first electrode formed on the transparent insulating substrate, and a transparent electrode formed on the transparent insulating substrate.
  • the first electrode is made of an Al alloy containing Ni and one or more metals selected from ⁇ Mo, Nb, W, Zr ⁇ , and the first electrode is It is a transparent conductive laminated substrate that is electrically connected directly to a second electrode that is a transparent electrode cover.
  • a thin film transistor is provided, and a substrate is also included in the present invention.
  • electrodes such as a gate, a drain, and a source are made of an Al alloy containing Ni and one or more metals selected from ⁇ Mo, Nb, W, Zr ⁇ . Since it is configured, it is possible to provide a thin film transistor capable of realizing a low contact resistance even when directly in contact with a transparent electrode.
  • the method for producing a thin film transistor substrate of the present invention includes:
  • the thin film transistor substrate according to the present invention includes a transparent insulating substrate, at least one of a gate, a source, and a drain as a first electrode formed on the transparent insulating substrate, and the first An insulating film formed so as to cover the electrode and the transparent insulating substrate, the insulating film having a predetermined contact hole, and a second electrode that is a transparent electrode formed on the insulating film;
  • the first electrode is made of A1 alloy containing Ni and one or more metals selected from ⁇ Mo, Nb, W, Zr ⁇ , the second electrode and the first electrode Are electrically connected directly through the contact hole, and thus there is an effect of obtaining a thin film transistor that can realize low contact resistance directly with IZO or the like.
  • the transparent electrode is made of indium oxide, tin oxide, indium tin oxide, or zinc oxide. Therefore, even if the first electrode (source, drain, gate) of the thin film transistor is directly connected to ITO, IZO, etc., a thin film transistor substrate capable of realizing a low contact resistance can be obtained.
  • the liquid crystal display device includes a transparent insulating substrate, a gate, a source, and a drain that are first electrodes formed on the transparent insulating substrate, the first electrode, and the transparent insulating material.
  • One electrode is made of an Al alloy alloy containing Ni and one or more metals selected from ⁇ Mo, Nb, W, Zr ⁇ , and the second electrode and the first electrode serve as the contact hole.
  • This is a liquid crystal display device having at least a TFT array substrate that is electrically directly connected through the TFT array substrate.
  • FIG. 1 (a) and FIG. 1 (b) are cross-sectional explanatory views showing a manufacturing process of a TFT array substrate (thin film transistor substrate) according to this example.
  • FIG. 2 (a) and FIG. 2 (b) are other cross-sectional explanatory views showing the manufacturing process of the TFT array substrate (thin film transistor substrate) according to this example.
  • FIG. 3 is still another cross-sectional explanatory view showing the manufacturing process of the TFT array substrate (thin film transistor substrate) according to the present embodiment.
  • FIG. 4 is a wiring conceptual diagram showing the appearance of Kelvin pattern wiring and the state of measurement in this example.
  • FIG. 1 to 3 are process cross-sectional explanatory views showing the TFT portion and the terminal portion of the TFT array substrate 100 according to the present invention in the order of the manufacturing process, and FIG. 1 (a), FIG. 1 (b), FIG. Fig. 2 (b) and Fig. 3 show the manufacturing process progressing!
  • 21 is a TFT portion
  • 22 is a terminal portion
  • 1 is a transparent insulating substrate
  • 2 is the first electrode of the first electrode (the first electrode of the TFT portion is a gate electrode).
  • 4 is a gate insulating film
  • 5 is a semiconductor layer a-Si film
  • 6 is a semiconductor layer n + a-Si film (see FIG. 1 (a) and FIG. 1 (b)).
  • 7 is the first layer of the first electrode (the first electrode of the TFT section is the source Z drain electrode), 9 is the interlayer insulating film, and 10 is the contact hole (FIG. 2 (a ) And Figure 2 (b)).
  • Reference numeral 11 denotes a second electrode (pixel electrode) (see FIG. 3).
  • the TFT portion 21 is provided near the intersecting portion of the gate wiring and the source wiring (both not shown) on the TFT array substrate 100, and constitutes a switching element that drives the liquid crystal, and has a terminal
  • the part 22 extends from the gate wiring and is arranged outside the display panel, and is a part for inputting an external force to the gate electrode.
  • an A1 alloy containing Ni and one or more metals selected from ⁇ Mo, Nb, W, Zr ⁇ using a sputtering method or the like on the transparent insulating substrate 1 (first electrode material) Is deposited.
  • etching is performed using phosphoric acid, nitric acid, and acetic acid-based etching solutions, and gate wiring (not shown) and gate electrode 2 (first electrode) are etched. ) And the terminal 22 are formed (see FIG. 1 (a)).
  • the gate insulating film 4 having a silicon nitride (SiNx) or oxide silicon (SiO 2) force is formed to a thickness of about 4000 using chemical vapor deposition (hereinafter simply referred to as CVD).
  • a semiconductor layer is formed.
  • Ni and ⁇ Mo, Nb which are the first electrode materials again using the sputtering method , W, Zr ⁇ , an Al alloy containing one or more metals selected from the group consisting of one or more metals, is formed to a thickness of about 3000 A, and patterning is performed to form the channel portion of the transistor and the source / drain electrode portion (ie, the first electrode) (See Figure 2 (a)).
  • the interlayer insulating film 9 can be formed by, for example, a silicon nitride film by a CVD method, an acrylic transparent resin, or a combination of both (see (b) of FIG. )reference).
  • an IZO film indium zinc oxide
  • IZO is a registered trademark.
  • the basic structure of the TFT array substrate is completed by patterning this transparent conductive film to form the pixel electrode (second electrode) 11.
  • the pixel electrode 11 is electrically connected directly to the gate electrode and the source Z drain electrode (that is, the first electrode) made of the first electrode material through the contact hole 10 provided in the interlayer insulating film 9. Has been.
  • the first electrode material A1 alloy is
  • the characteristic of this embodiment is that when the gate electrode and the terminal portion are formed by sputtering using the first electrode material, sputtering is performed in an atmosphere of pure Ar gas, and the first electrode is formed.
  • the film thickness is about 2000 A.
  • This A1 film is formed by performing sputtering using an A1 alloy target containing Ni and one or more metals selected from ⁇ Mo, Nb, W, Zr ⁇ . Further, the resistance value can be reduced by the subsequent heat treatment.
  • Table 1 shows the physical measurement results for various examples of the A1 film of the present embodiment.
  • Table 1 shows Example Example 2, Example 3, and Example 4, and Comparative Example 1, Comparative Example 2, and Comparative Example 3 for comparison. [0074] [Table 1]
  • the A1 alloy constituting the first electrode is an Al alloy containing 1.5 wt% Ni and 0.2 wt% W.
  • the specific resistance of this A1 alloy is 5.2 ⁇ cm. No change was observed when this Al alloy thin film was immersed in an aqueous TMAH (2.38 wt%) solution at room temperature for 5 minutes.
  • the A1 alloy constituting the first electrode is an Al alloy containing 1.5 wt% Ni and 0.5 wt% Mo.
  • the specific resistance of this A1 alloy is 4.8 ⁇ cm. No change was observed when this Al alloy thin film was immersed in an aqueous TMAH (2.38 wt%) solution at room temperature for 5 minutes.
  • the A1 alloy constituting the first electrode is an A1 alloy containing 1.5 wt% Ni and 0.8 wt% Nb.
  • the specific resistance of this A1 alloy is 5.8 ⁇ cm. No change was seen when this A1 alloy thin film was immersed in a room temperature TMAH (2.38 wt%) aqueous solution for 5 minutes.
  • the A1 alloy constituting the first electrode is an A1 alloy containing 1.5 wt% Ni and 0.5 wt% Zr.
  • the specific resistance of this A1 alloy is 5. ⁇ ⁇ cm.
  • A1 constituting the first electrode is pure A1.
  • the specific resistance of A1 is 2.1 ⁇ cm. Even if this A1 thin film was immersed in an aqueous TMAH (2.38 wt%) solution at room temperature for 5 minutes, no change was observed.
  • the A1 alloy constituting the first electrode is an A1 alloy containing 1.5 wt% Ni.
  • the specific resistance of this A1 alloy is 3. ⁇ ⁇ cm.
  • the A1 alloy constituting the first electrode is an A1 alloy containing 0.8 wt% Nd.
  • the specific resistance of this A1 alloy is 4.2 ⁇ cm.
  • the electrical resistance value (contact resistance value) of the contact surface portion between the first electrode and the second electrode, which is a transparent conductive film, applied to this embodiment is a sufficiently small value.
  • the minimum value of the contact resistance was about 380 ⁇ at the mouth of about 50 ⁇ m, indicating a good value.
  • Table 2 shows the results of the electrical resistance value (contact resistance value) of the contact surface with the second electrode made of a transparent conductive film such as IZO using the Kelvin pattern.
  • the first electrode in this patent is characterized in that it is made of an Al alloy containing one or more metals selected from Ni and ⁇ Mo, Nb, W, Zr ⁇ .
  • the second electrode made of a transparent conductive film is specifically composed of IZO or the like.
  • Table 2 shows Example 5, Example 6, Example 7, and Example 8, and Comparative Example 1, Comparative Example 2, and Comparative Example 3 (same as Table 1) for comparison. Has been.
  • the A1 alloy constituting the first electrode is an Al alloy containing 1.5 wt% Ni and 0.5 wt% W.
  • the specific resistance of this A1 alloy is 8.2 ⁇ cm.
  • This Al alloy thin film and a transparent conductive film with IZO force were provided on the substrate so as to cross each other in a cross shape, and contact resistance was measured by Kelvin noturn. This Kelvin pattern is shown in Fig. 4.
  • the specific resistance of the metal oxide of IZO was 380 ⁇ cm.
  • the measured value of contact resistance (contact resistance value) with the Kelvin pattern in Fig. 4 was 230 ⁇ , which was a sufficiently low value.
  • Example 6 the A1 alloy composing the first electrode is 1.5 wt% Ni and 0.8 w Mo. Al alloy containing t%. The specific resistance of this A1 alloy is 9.8 ⁇ cm.
  • This A1 alloy thin film and a transparent conductive film with IZO force were placed on the substrate so as to cross each other in a cross shape, and contact resistance was measured by Kelvinno ⁇ turn (see Fig. 4).
  • the specific resistance of the metal oxide of IZO was 380 ⁇ cm.
  • the measured value of contact resistance (contact resistance value) with the Kelvin pattern in Fig. 4 was 340 ⁇ , which was a sufficiently low value.
  • the A1 alloy constituting the first electrode is an Al alloy containing 1.5 wt% Ni and 0.8 wt% Nb.
  • the specific resistance of this A1 alloy is 5.8 ⁇ cm.
  • This Al alloy thin film and a transparent conductive film with IZO force were provided on the substrate so as to cross each other in a cross shape, and the contact resistance was measured by Kelvinno ⁇ turn (see Fig. 4).
  • the specific resistance of the metal oxide of IZO was 380 ⁇ cm.
  • the measured value of contact resistance (contact resistance value) using the Kelvin pattern in Fig. 4 was 280 ⁇ , which was a sufficiently low value.
  • the A1 alloy constituting the first electrode is an Al alloy containing 1.5 wt% Ni and 0.5 wt% Zr.
  • the specific resistance of this A1 alloy is 5. ⁇ ⁇ cm.
  • This Al alloy thin film and a transparent conductive film with ITO force were provided on the substrate so as to cross each other in a cross shape, and the contact resistance was measured by Kelvinno turn (see Fig. 4).
  • the specific resistance of the metal oxide of ITO was 220 ⁇ cm.
  • the measured value of contact resistance (contact resistance value) by the Kelvin pattern in Fig. 4 was 320 ⁇ , which was a sufficiently low value.
  • the first electrode is composed of pure A1.
  • the specific resistance of A1 is 2.1 ⁇ cm.
  • This Al thin film and a transparent conductive film with ITO force were provided on the substrate so as to cross in a cross shape, and contact resistance was measured using a Kelvin pattern (see Fig. 4).
  • the resistivity of the ITO metal oxide was 220 ⁇ cm.
  • the cherub in Figure 4 The measured value of contact resistance (contact resistance value) by the pattern is 1 ⁇ ⁇ or more, which is high for use in a display device.
  • the A1 alloy constituting the first electrode is an A1 alloy containing 1.5 wt% Ni.
  • the specific resistance of this A1 alloy is 3. ⁇ ⁇ cm.
  • This A1 alloy thin film and a transparent conductive film made of ITO were provided on the substrate so as to cross each other in a cross shape, and the contact resistance was measured by a Kelvin pattern (see Fig. 4).
  • the specific resistance of the ITO metal oxide was 220 ⁇ cm.
  • the measured value of contact resistance (contact resistance value) by the Kelvin pattern in Fig. 4 is 1 ⁇ ⁇ or more, which is high for use in a display device.
  • the A1 alloy constituting the first electrode is an A1 alloy containing 0.8 wt% Nd.
  • the specific resistance of this A1 alloy is 2.4 ⁇ cm.
  • This A1 alloy thin film and a transparent conductive film made of ITO were provided on the substrate so as to cross each other in a cross shape, and the contact resistance was measured using a Kelvin pattern (see Fig. 4).
  • the specific resistance of the metal oxide of ITO was 220 ⁇ cm.
  • the measured value of contact resistance (contact resistance value) by the Kelvin pattern in Fig. 4 is 1 ⁇ ⁇ or more, which is high for use in a display device.
  • the value of the contact resistance (contact resistance) generated between the transparent conductive film (second electrode) can be reduced.
  • the contact resistance value after heat treatment for 30 minutes at CX is about 650 ⁇ , and even after heat treatment at 300 ° CX for 60 minutes, the contact resistance value is about 900 ⁇ .
  • 1E8- Excellent heat resistance, extremely low compared to ⁇ 12 ⁇ .
  • the first electrode Ni and ⁇ Mo, Nb, W, Z The content of one or more metals selected from r ⁇ is preferably 0.05 to 5 wt%.
  • the content is more preferably 0.1 to 2 wt%.
  • the first electrode when the first electrode is manufactured using an A1 alloy containing Ni alone, a battery reaction occurs in an aqueous solution of T MAH (tetramethylammonium hydroxide), and the A1 wiring
  • T MAH tetramethylammonium hydroxide
  • the battery reaction can be suppressed by using an Al alloy containing one or more metals selected from Ni and ⁇ Mo, Nb, W, Zr ⁇ .
  • the gate electrode is formed by using a first electrode material Ni and an A1 alloy containing one or more metals selected from ⁇ Mo, Nb, W, Zr ⁇ using a sputtering method.
  • the terminal part 22 and the source Z drain electrode 7 may be formed by sputtering in an Ar gas atmosphere first.
  • A1 which is the base material of the material of the first electrode
  • Ni and ⁇ Mo, Nb, W, Zr ⁇ force A force using an A1 alloy containing one or more selected metals A1 alloy
  • the third element to be added is preferably Cu, Si, or a rare earth element in terms of suppressing hillocks and improving corrosion resistance. In order to take advantage of A1's low electrical resistance, it is preferable to keep the added amount so that the specific resistance of the first electrode does not exceed 10 ⁇ 'cm.
  • the third element “three” means that Ni is the first, the one or more metals selected from ⁇ Mo, Nb, W, Zr ⁇ are the second, and the third is the third. It is. It means "other elements”.
  • the first electrode material is Ni and an Al alloy containing one kind of metal selected from ⁇ Mo, Nb, W, Zr ⁇ , and the second electrode material.
  • IZO the case of using IZO has been described above, the effects according to the present invention are not limited to these electrode materials.
  • any of the materials such as In 2 O, SnO, and ZnO as the second electrode material such as In 2 O, SnO, and ZnO as the second electrode material
  • the present invention includes any transparent conductive laminated substrate in which the first electrode and the second electrode (transparent electrode) are provided without providing TFTs.
  • TFT array substrate formed by adopting any of the examples described in Embodiment 1 above, this is bonded to a counter substrate having a counter electrode, a color filter, etc., and a liquid crystal material is injected and held.
  • a TFT active matrix type liquid crystal display device (TFT LCD device) is manufactured (Embodiment 2).
  • the low-resistance wiring Ni and the Al alloy containing one or more metals selected from ⁇ Mo, Nb, W, Zr ⁇ are used for the wiring and electrodes of the TFT array substrate. It has a structure in which a pixel electrode made of an IZO transparent film is in direct contact with the A1 alloy without providing another metal layer mainly composed of components other than A1. Therefore, a high-performance liquid crystal display device with a high aperture ratio can be obtained.
  • the productivity of the liquid crystal display device of Embodiment 2 is greatly improved. If another metal layer is provided, V. Since the manufacturing process is not required, the liquid crystal display device of the second embodiment has excellent characteristics that it can be implemented (manufactured) at a lower cost than the prior art!
  • Embodiment 2 Although an example in which a liquid crystal display device is configured using a liquid crystal material is described in Embodiment 2, it is also preferable to configure an organic EL display device using an organic EL material.

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Abstract

A method, characterized in that it comprises a step of forming a first electrode (a source or the like) of a thin film transistor on a transparent insulating substrate using an Al alloy as a first electrode, a step of forming an insulating film over the first electrode and the substrate, a step of forming a contact hole in the insulating film and a step of forming a second electrode (a transparent electrode) on the insulating film and electrically connecting the second electrode with the first electrode directly via the above contact hole, wherein the above Al alloy comprises Ni and one or more types of metal selected from among Mo, Nb, W and Zr. The above method can be suitably used for reducing the contact resistance in the contacting region of a transparent electrode as a second electrode with a first electrode (gate, source, drain) and for inhibiting the galvanic cell reaction.

Description

明 細 書  Specification
薄膜トランジスタ及びその製造方法並びに薄膜トランジスタ基板及びその 製造方法並びに該薄膜トランジスタを用いた液晶表示装置及び有機 EL表示装 置並びに透明導電積層基板  THIN FILM TRANSISTOR AND ITS MANUFACTURING METHOD, THIN FILM TRANSISTOR SUBSTRATE, ITS MANUFACTURING METHOD, LIQUID CRYSTAL DISPLAY DEVICE, ORGANIC EL DISPLAY DEVICE, AND TRANSPARENT CONDUCTIVE LAMINATED SUBSTRATE USING THE THIN FILM TRANSISTOR
技術分野  Technical field
[0001] 本発明は、薄膜トランジスタ（以下、 TFTと称する場合もある）とその製造方法、薄 膜トランジスタ基板とその製造方法、さらに TFTを用いた液晶表示装置や有機 EL表 示装置に関する。  The present invention relates to a thin film transistor (hereinafter sometimes referred to as TFT) and a manufacturing method thereof, a thin film transistor substrate and a manufacturing method thereof, and a liquid crystal display device and an organic EL display device using TFT.
背景技術  Background art
[0002] マトリックス型液晶表示装置は、 TFTアレイ基板と対向基板との間に液晶などの表 示材料を充填し、この表示材料に対して画素ごとに選択的に電圧を印加するように 構成されている。ここで、 TFTアレイ基板とは、通常は、半導体薄膜 (以下、半導体膜 と称す)など力もなる TFT等が配置されている基板を言う。また、対向基板上には、対 向電極、カラーフィルタ及びブラックマトリックスなどが設けられている。このような TF Tアレイ基板を用いた液晶表示装置 (Liquid Crystal Display、以下 LCDと略記 する）を以下、 TFT— LCDと称する場合がある。  A matrix type liquid crystal display device is configured so that a display material such as liquid crystal is filled between a TFT array substrate and a counter substrate, and a voltage is selectively applied to the display material for each pixel. ing. Here, the TFT array substrate usually refers to a substrate on which a TFT or the like having a force such as a semiconductor thin film (hereinafter referred to as a semiconductor film) is disposed. Further, a counter electrode, a color filter, a black matrix, and the like are provided on the counter substrate. A liquid crystal display device (Liquid Crystal Display, hereinafter abbreviated as LCD) using such a TFT array substrate is sometimes referred to as a TFT-LCD.
[0003] TFTアレイ某板にっ ヽて  [0003] On the TFT array board
なお、 TFT (薄膜トランジスタ）が形成されている基板を薄膜トランジスタ基板、又は TFT基板と称する。一般に、表示装置に用いられる場合は、複数の薄膜トランジスタ がアレイ状に形成される場合が多 、ので、 TFTアレイ基板と呼ばれる場合も多 、。  A substrate on which a TFT (thin film transistor) is formed is referred to as a thin film transistor substrate or a TFT substrate. In general, when used in a display device, a plurality of thin film transistors are often formed in an array, so it is often called a TFT array substrate.
[0004] TFTアレイ基板は、ガラスなどカゝらなる絶縁性基板 (典型的にはガラス基板)上に各 画素を構成する TFT並びに画素電極が設けられている。各画素中の TFTは、ゲート 電極、ソース電極、ドレイン電極及び半導体膜力もなるものである。そして、これらの T FTや画素電極がアレイ状に配置されている。この TFTアレイ基板は、基板上に、 TF Tや画素電極の他に配向膜や必要に応じて蓄積容量などが設けられている。さらに 、各画素の間の境界領域には、ゲート配線やソース配線などの信号線が配置されて いる。これらの信号線は、一般に、複数本ずつまとめられ、互いに並行に張り巡らさ れている。 [0004] A TFT array substrate is provided with a TFT and a pixel electrode constituting each pixel on an insulating substrate (typically a glass substrate) such as glass. The TFT in each pixel also has a gate electrode, a source electrode, a drain electrode, and a semiconductor film force. These TFTs and pixel electrodes are arranged in an array. This TFT array substrate is provided with an alignment film and a storage capacitor as necessary in addition to TFT and pixel electrodes on the substrate. Furthermore, signal lines such as gate wirings and source wirings are arranged in the boundary region between the pixels. These signal lines are generally grouped together and run in parallel with each other. It is.
[0005] このように、 TFTアレイ基板の表示領域は、画像の各画素を表す領域と、画素間の 境界領域と、カゝらなるものである。この表示領域の外側（外周）には、上記各信号線に 対応してそれぞれ入力端子や、各 TFTを駆動する駆動回路などが設けられて ヽる。 本説明では、この表示領域の外側の領域を、便宜上、インターフェース領域と呼ぶこ とにする。  As described above, the display area of the TFT array substrate consists of an area representing each pixel of the image and a boundary area between the pixels. Outside the display area (outer periphery), input terminals and drive circuits for driving the TFTs are provided corresponding to the signal lines. In this description, an area outside the display area is referred to as an interface area for convenience.
[0006] このような TFTアレイ基板を用いた液晶表示装置を作製するには、まず、ガラス基 板上に、 TFT、ゲート、ソース Zドレイン、及びその他の共通配線、をアレイ状に作製 して表示領域を構成する。さらに、表示領域の周辺に、入力端子、予備配線及び駆 動回路などを配置してインターフェース領域を構成する。このよう〖こして TFTアレイ基 板を作製している。  [0006] In order to manufacture a liquid crystal display device using such a TFT array substrate, TFTs, gates, sources, Z drains, and other common wires are first formed in an array on a glass substrate. Configure the display area. In addition, the interface area is configured by arranging input terminals, spare wirings, drive circuits, and the like around the display area. In this way, a TFT array substrate is produced.
[0007] なお、本説明では、ゲート電極とゲート配線とをあわせて単にゲートと言う。また、ソ ース電極とソース配線とをあわせて単にソースと言う。また、ドレイン電極とドレイン配 線とをあわせて単にドレインと言う。さらに、ソース及びドレインをソース Zドレインと表 している。  In this description, the gate electrode and the gate wiring are collectively referred to as a gate. The source electrode and the source wiring are simply called a source. The drain electrode and the drain wiring are collectively referred to as a drain. Furthermore, the source and drain are referred to as source Z drain.
[0008] このとき、表示領域、インターフェース領域、の各領域の機能を発揮可能な状態に 置くために (稼働状態にするために）は、導電性薄膜 (以下、導電膜と称す)や絶縁 性薄膜 (以下、絶縁膜と称す)を配設する必要がある。また、対向基板上には対向電 極を設けるとともにカラーフィルタ、ブラックマトリックスを設ける。  [0008] At this time, in order to put the functions of the display area and the interface area into a functionable state (in order to bring them into operation), a conductive thin film (hereinafter referred to as a conductive film) or an insulating property is used. It is necessary to dispose a thin film (hereinafter referred to as an insulating film). A counter electrode is provided on the counter substrate, and a color filter and a black matrix are provided.
[0009] このようにして、 TFTアレイ基板と対向基板とをそれぞれ作製した後、 2枚の基板の 間に液晶材料が注入するために必要な隙間を開けた状態で、 2枚の基板をその周 辺の縁を貼り合わせて固定する。周囲の縁部を貼り合わせた後、 2枚の基板の間に 存在する隙間に液晶材料を注入して LCDを作製する。  [0009] In this way, after the TFT array substrate and the counter substrate are respectively fabricated, the two substrates are placed in a state where a gap necessary for injecting the liquid crystal material is provided between the two substrates. Fix the edges of the periphery together. After bonding the peripheral edges together, a liquid crystal material is injected into the gap that exists between the two substrates to make an LCD.
[0010] LCDに用いられる TFTアレイ基板や対向基板には、薄膜技術を利用して種々の 半導体装置、その他の素子などが設けられている。これらの半導体装置には、半導 体膜や絶縁膜、導電膜が形成されており、各膜の間の絶縁又は電気的接続をとるた めに層間絶縁膜や半導体膜を貫通するコンタクトホール等がさらに形成されている。  [0010] Various semiconductor devices and other elements are provided on TFT array substrates and counter substrates used in LCDs using thin film technology. In these semiconductor devices, a semiconductor film, an insulating film, and a conductive film are formed. In order to establish insulation or electrical connection between the films, an interlayer insulating film, a contact hole that penetrates the semiconductor film, etc. Is further formed.
[0011] TFT— LCDにおいては、近年、大型化あるいは高精細化が進められている。これ に伴い、 TFT— LCDのゲート配線やソース Zドレイン配線には信号の遅延を防止す るために、純 A1あるいは A1を主成分とする電気的に低抵抗な合金材料を用いること が特性上及びプロセス上からは望まし 、。 [0011] In recent years, TFT-LCDs have been increased in size or definition. this As a result, it is necessary to use pure A1 or an electrically low-resistance alloy material mainly composed of A1 for TFT-LCD gate wiring and source Z drain wiring to prevent signal delay. Hope from the process.
[0012] し力し、透明性の画素電極となる ITOや IZOなどからなる第 2電極と、これら純 A1あ るいは A1合金カゝらなる第 1電極とを直接コンタクトさせると、そのコンタクト抵抗 (接触 抵抗）は 1Ε10〜1Ε12 Ωと非常に高くなつてしまい、良好なコンタクト特性を得ること は困難であった。 [0012] When the second electrode made of ITO, IZO, or the like, which becomes a transparent pixel electrode, is in direct contact with the first electrode made of pure A1 or A1 alloy cover, the contact resistance is increased. The (contact resistance) was very high, 1Ε10 to 1Ε12 Ω, and it was difficult to obtain good contact characteristics.
[0013] したがって、絶縁膜に開口したコンタクトホールを介して純 A1又は A1合金力もなる 第 1電極と、画素電極となる ΙΤΟや ΙΖΟなどの透明性導電膜からなる第 2電極とを直 接コンタクト (接続)する構成を採用した TFTアレイ基板を実現することは困難であつ た。  Therefore, the first electrode that also has pure A1 or A1 alloy force and the second electrode that is made of a transparent conductive film such as の or ΙΤΟ that becomes a pixel electrode are directly contacted through a contact hole that is opened in the insulating film. It was difficult to realize a TFT array substrate that employs the (connected) configuration.
[0014] 第 1雷極 第 2雷極  [0014] First Thunder Pole Second Thunder Pole
なお、本説明では、画素電極を構成する透明材料カゝらなる電極を第 2電極と呼び、 それ以外の信号配線を構成する導電材料 (多くの場合、 A1 (又は A1合金)からなる） カゝらなる電極を第 1電極と呼ぶ。そして、第 2電極を構成する材料を第 2電極材料、第 1電極を構成する材料を第 1電極材料と呼ぶ。  In this description, the electrode made of the transparent material constituting the pixel electrode is referred to as the second electrode, and the other conductive material constituting the signal wiring (in many cases, made of A1 (or A1 alloy)) is used. This electrode is called the first electrode. The material constituting the second electrode is called a second electrode material, and the material constituting the first electrode is called a first electrode material.
[0015] 己 良された従 の枝術  [0015] Skilled obedience branch
上述した問題を解決する方法として、従来から種々の手法が提案されて 、る。  Various methods have been proposed for solving the above problems.
[0016] たとえば、良好なコンタクトを得るために、純 A1又は A1合金上に Cr、 Ti、 Mo、 Cu、 Ni、等を成膜する 2層構造の第 1電極が提案されている。このような技術は、下記特 許文献 1、特許文献 2、特許文献 3において見られる。  [0016] For example, in order to obtain a good contact, a first electrode having a two-layer structure in which Cr, Ti, Mo, Cu, Ni, or the like is deposited on pure A1 or an Al alloy has been proposed. Such technology can be found in Patent Document 1, Patent Document 2, and Patent Document 3 below.
[0017] また、第 1の電極と第 2の電極が直接コンタクト (接続)する箇所の、第 1電極部分に 、局所的に、 N、 0、 Si及び C力もなる群力も選択される少なくとも一種の不純物を添 加する手法が知られている。このような不純物を、前記第 1電極の上層（すなわち、接 続する箇所）に添加して、前記不純物を添加した第 2層を形成し、局所的な 2層構造 をなすものである。このような技術は、下記特許文献 4において見られる。  [0017] In addition, at least one kind of group force including N, 0, Si, and C force is locally selected in the first electrode portion where the first electrode and the second electrode are in direct contact (connection). There is a known method of adding impurities. Such an impurity is added to the upper layer of the first electrode (that is, the connecting portion) to form a second layer to which the impurity is added, thereby forming a local two-layer structure. Such a technique is found in Patent Document 4 below.
[0018] また、 A1に、合金成分として Au、 Ag、 Zn、 Cu、 Ni、 Sr、 Sm、 Ge、 BUりなる群から 選択される少なくとも一種の物質を 0. 1〜6原子％含有させた合金を用いて第 1電極 を構成し、この第 1電極を透明電極 (第 2電極)と直接接合する構成が提案されている 。このような技術は、下記特許文献 5において見られる。 [0018] Further, A1 contains 0.1 to 6 atomic% of at least one substance selected from the group consisting of Au, Ag, Zn, Cu, Ni, Sr, Sm, Ge, and BU as an alloy component. The first electrode using an alloy There has been proposed a structure in which the first electrode is directly joined to the transparent electrode (second electrode). Such a technique can be found in Patent Document 5 below.
[0019] 特許文献 1 :特開平 4 253342号公報 Patent Document 1: Japanese Patent Laid-Open No. 4253342
特許文献 2：特開平 4— 305627号公報  Patent Document 2: Japanese Patent Laid-Open No. 4-305627
特許文献 3 :特開平 8— 18058号公報  Patent Document 3: JP-A-8-18058
特許文献 4：特開平 11― 284195号公報  Patent Document 4: JP-A-11-284195
特許文献 5：特開 2004— 214606号公報  Patent Document 5: Japanese Unexamined Patent Application Publication No. 2004-214606
発明の開示  Disclosure of the invention
発明が解決しょうとする課題  Problems to be solved by the invention
[0020] 以上述べたように、従来の改良されて 、な 、製造方法にお!、ては、 ITOや IZO (登 録商標）など力もなる第 2電極と純 A1又は A1合金力もなる第 1電極とのコンタクト抵抗 が I X 10E10〜1 X 10Ε12 Ωと非常に高く、良好なコンタクト抵抗が得られなかった [0020] As described above, in the conventional improvement, the manufacturing method! First, the second electrode having a force such as ITO and IZO (registered trademark) and the first having a pure A1 or A1 alloy force. The contact resistance with the electrode was very high, IX 10E10 ~ 1 X 10Ε12 Ω, and good contact resistance could not be obtained
[0021] 一方、良好なコンタクトを得るため (接触抵抗を低減するため）に、第 1電極を材料 の異なる 2層構造とする従来の改良された技術を採用する場合は、 2種の材料を同 一の薬液 (エッチング液)を用いて、且つ、同時にエッチングをすることは極めて困難 であるので、 2種類の薬液による 2度のエッチング工程を必要とする。したがって、製 造工程の複雑化を招!、て 、た。 [0021] On the other hand, in order to obtain a good contact (in order to reduce the contact resistance), when adopting the conventional and improved technique in which the first electrode has a two-layer structure made of different materials, two kinds of materials are used. Since it is extremely difficult to perform etching simultaneously using the same chemical solution (etching solution), two etching steps using two types of chemical solutions are required. Therefore, the manufacturing process is complicated!
[0022] また、 A1に合金成分として Au、 Ag、 Zn、 Cu、 Ni、 Sr、 Sm、 Ge、 BUりなる群から 選択される少なくとも一種を 0. 1〜6原子％含有させた合金を第 1電極として用いるこ とが改良された従来の技術として知られている。この改良された従来の技術を採用す る場合は、透明電極 (第 2電極）と第 1電極のコンタクト抵抗は、 10Ε2 Ω程度と小さな コンタクト抵抗を実現できる力 エッチング工程で使用する薬液 (エッチング液）にて 電池反応が生じ、電極の溶解が起きてしまう。その結果、配線の断線が生じること、が 知られている。  [0022] In addition, an alloy containing 0.1 to 6 atomic% of at least one selected from the group consisting of Au, Ag, Zn, Cu, Ni, Sr, Sm, Ge, and BU as an alloy component in A1 It is known as a conventional technique improved for use as a single electrode. When using this improved conventional technology, the contact resistance between the transparent electrode (second electrode) and the first electrode is about 10Ε2 Ω. ) Causes a battery reaction and dissolution of the electrode occurs. As a result, it is known that wiring breakage occurs.
[0023] 本発明は、係る課題に鑑みなされたものであり、第 2電極と第 1電極とのコンタクト部 において発生するコンタクト抵抗 (接触抵抗)の値を低減し、且つ、電池反応を抑制 することが可能な TFT及びその製造方法並びに該 TFTを用いた TFT基板及び液 晶表示装置を実現することを目的とする。この目的を達成するために、本発明は、第 1電極を、 Niと、及び、 {Mo、 Nb、 W、 Zr}とから選ばれた一種以上の金属を含有す る A1配線材料を用いることをその特徴の一つとする。 [0023] The present invention has been made in view of such problems, and reduces the value of contact resistance (contact resistance) generated at the contact portion between the second electrode and the first electrode, and suppresses the battery reaction. TFT that can be used, manufacturing method thereof, and TFT substrate and liquid using the TFT An object is to realize a crystal display device. In order to achieve this object, the present invention uses, as the first electrode, an A1 wiring material containing Ni and one or more metals selected from {Mo, Nb, W, Zr}. Is one of its features.
[0024] さらに、本発明は、このような A1配線材料を用いて生産コストの低下及び生産性の 向上を図ることができる TFTとその製造方法及び液晶表示装置を提供することを目 的とする。 Furthermore, an object of the present invention is to provide a TFT, a manufacturing method thereof, and a liquid crystal display device that can reduce the production cost and improve the productivity by using such an A1 wiring material. .
課題を解決するための手段  Means for solving the problem
[0025] (1)本発明は、上記課題を解決するために、透明絶縁性基板上で薄膜トランジスタ を製造する方法において、前記透明絶縁性基板上に、 A1合金を用いて、第 1電極で ある前記薄膜トランジスタのゲート、ソース及びドレインのうちの少なくとも一つを形成 する工程、を含み、前記 A1合金は、 Niと、 {Mo、 Nb、 W、 Zr}から選択された一種以 上の金属と、を含む A1合金であることを特徴とする薄膜トランジスタの製法である。  [0025] (1) The present invention provides a method for producing a thin film transistor on a transparent insulating substrate in order to solve the above-mentioned problem, and uses the A1 alloy on the transparent insulating substrate as the first electrode. Forming at least one of a gate, a source, and a drain of the thin film transistor, wherein the A1 alloy is Ni, and one or more metals selected from {Mo, Nb, W, Zr}, A method for producing a thin film transistor, characterized by being an A1 alloy containing
[0026] このような製法 (製造方法）によって作成される薄膜トランジスタは、そのドレインゃソ ースなどを透明電極と直接接触させても高 、接触抵抗を示すことがな!、。  [0026] A thin film transistor produced by such a manufacturing method (manufacturing method) does not exhibit high contact resistance even when its drain source or the like is brought into direct contact with the transparent electrode!
[0027] (2)また、本発明の請求項 2に係る薄膜トランジスタ基板の製造方法は、透明絶縁 性基板上に薄膜トランジスタを形成し、薄膜トランジスタ基板を製造する方法にぉ ヽ て、前記透明絶縁性基板上に、 A1合金を用いて、第 1電極である前記薄膜トランジス タのゲート、ソース及びドレインのうちの少なくとも一つを形成する工程と、前記第 1電 極及び前記基板を覆って絶縁膜を成膜する工程と、該絶縁膜にパターユングを施し コンタクトホールを形成する工程と、前記絶縁膜上に透明電極力 なる第 2電極を形 成して該第 2電極と第 1電極とを前記コンタクトホールを介して電気的に直接接続す る工程と、を少なくとも含み、前記 A1合金は、 Niと、 {Mo、 Nb、 W、 Zr}から選択され た一種以上の金属と、を含む A1合金であることを特徴とする薄膜トランジスタ基板の 製法である。  [0027] (2) Further, in the method for manufacturing a thin film transistor substrate according to claim 2 of the present invention, the method of forming a thin film transistor on a transparent insulating substrate, and manufacturing the thin film transistor substrate, includes: A step of forming at least one of a gate, a source, and a drain of the thin film transistor, which is a first electrode, using an A1 alloy; and an insulating film covering the first electrode and the substrate. Forming a contact hole by patterning the insulating film; forming a second electrode having a transparent electrode force on the insulating film; and connecting the second electrode and the first electrode to the first electrode. A step of electrically connecting directly through a contact hole, wherein the A1 alloy includes Ni and one or more metals selected from {Mo, Nb, W, Zr}. Thin, characterized by It is a process for the preparation of the transistor substrate.
[0028] このような製法 (製造方法）によって作成される薄膜トランジスタ基板は、その中の薄 膜トランジスタのドレインやソースなどを透明電極と直接接触している力 そこに高い 接触抵抗は表れず、表示装置等に十分に使用可能である。  [0028] The thin film transistor substrate produced by such a manufacturing method (manufacturing method) is a force that directly contacts the drain and source of the thin film transistor with the transparent electrode, and there is no high contact resistance. It can be used sufficiently for devices.
[0029] (3)また、本発明は、透明絶縁性基板上に設けられた薄膜トランジスタにおいて、 前記透明絶縁性基板上に形成された第 1電極である前記薄膜トランジスタのゲート、 ソース及びドレインの少なくとも一つと、を備え、前記第 1電極は、 Niと、 {Mo、 Nb、 W、 Zr}から選択された一種以上の金属と、を含む A1合金力 なることを特徴とする 薄膜トランジスタである。 (3) Further, the present invention provides a thin film transistor provided on a transparent insulating substrate, At least one of a gate, a source, and a drain of the thin film transistor that is a first electrode formed on the transparent insulating substrate, and the first electrode is made of Ni, {Mo, Nb, W, Zr} A thin film transistor characterized by having an A1 alloy strength containing at least one selected metal.
[0030] このような構成の薄膜トランジスタは、そのドレインやソースなどを透明電極と直接接 触させても高 、接触抵抗を示すことがな 、。  [0030] The thin film transistor having such a configuration does not exhibit high contact resistance even when its drain or source is brought into direct contact with the transparent electrode.
[0031] (4)また、本発明は、透明絶縁性基板と、前記透明絶縁性基板上に形成された第 1 電極であるゲート、ソース及びドレインの少なくとも一つと、該第 1電極及び前記透明 絶縁性基板を覆うように形成された絶縁膜であって、所定のコンタクトホールが設けら れている絶縁膜と、該絶縁膜上に形成された透明電極である第 2電極と、を少なくと も含み、前記第 1電極は、 Niと、 {Mo、 Nb、 W、 Zr}から選択された一種以上の金属 と、を含む A1合金力 なり、前記第 2電極と前記第 1電極とが前記コンタクトホールを 介して電気的に直接接続されてなる薄膜トランジスタ基板である。  [0031] (4) Further, the present invention provides a transparent insulating substrate, at least one of a gate, a source, and a drain as a first electrode formed on the transparent insulating substrate, the first electrode, and the transparent An insulating film formed to cover the insulating substrate, the insulating film having a predetermined contact hole, and a second electrode that is a transparent electrode formed on the insulating film. The first electrode is made of A1 alloy force containing Ni and one or more metals selected from {Mo, Nb, W, Zr}, and the second electrode and the first electrode are It is a thin film transistor substrate that is electrically directly connected through a contact hole.
[0032] このような構成によって、薄膜トランジスタのドレインやソースなどを透明電極と直接 接触させつつ、低い接触抵抗が実現されており、表示装置等に十分に使用可能な 薄膜トランジスタ基板が得られる。  [0032] With such a configuration, a low-contact resistance is realized while the drain, source, and the like of the thin film transistor are in direct contact with the transparent electrode, and a thin film transistor substrate that can be sufficiently used for a display device or the like is obtained.
[0033] (5)また、本発明は、前記透明電極が酸化インジウム、酸化すず、酸化インジウム すず及び酸化亜鉛の 、ずれかからなる上記 (4)記載の薄膜トランジスタ基板である。  (5) The present invention is the thin film transistor substrate according to the above (4), wherein the transparent electrode is made of any one of indium oxide, tin oxide, indium tin oxide, and zinc oxide.
[0034] (6)また、本発明は、前記第 1電極を構成する A1合金中の、 Ni及び、 {Mo、 Nb、 W 、 Zr}から選ばれた一種以上の金属の含有比率力 0. l〜5wt%であることを特徴と する上記（3)記載の薄膜トランジスタである。  [0034] (6) Further, the present invention provides a content ratio force of Ni and one or more metals selected from {Mo, Nb, W, Zr} in the A1 alloy constituting the first electrode. The thin film transistor according to (3) above, wherein the content is 1 to 5 wt%.
[0035] (7)また、本発明は、前記第 1電極を構成する A1合金中の、 Ni及び、 {Mo、 Nb、 W 、 Zr}から選ばれた一種以上の金属の含有比率力 0. l〜5wt%であることを特徴と する上記 (4)記載の薄膜トランジスタ基板である。  [0035] (7) Further, the present invention relates to a content ratio force of Ni and one or more metals selected from {Mo, Nb, W, Zr} in the A1 alloy constituting the first electrode. The thin film transistor substrate according to (4) above, wherein the content is 1 to 5 wt%.
[0036] このような（6) (7)の構成に示した含有比率が好ま 、範囲である。この含有比率は もちろん、「Ni」の含有比率と、 {Mo、Nb、W、 Zr}のいずれか一種以上の金属の含 有比率と、の合計の含有比率である。  [0036] The content ratios shown in the constitutions of (6) and (7) are preferred and in the range. This content ratio is, of course, the total content ratio of the content ratio of “Ni” and the content ratio of one or more metals of {Mo, Nb, W, Zr}.
[0037] (8)また、本発明は、透明絶縁性基板と、前記透明絶縁性基板上に形成された第 1 電極であるゲート、ソース及びドレインと、該第 1電極及び前記透明絶縁性基板を覆 つて形成された絶縁膜であって、所定のコンタクトホールが設けられた絶縁膜と、該 絶縁膜上に形成された透明電極からなる第 2電極と、を少なくとも含み、前記第 1電 極が Niと、 {Mo、 Nb、 W、 Zr}から選ばれた一種以上の金属と、を含む A1合金からな り、前記第 2電極と前記第 1電極とが前記コンタクトホールを介して電気的に直接接 続されてなる TFTアレイ基板を少なくとも有する液晶表示装置である。 [0037] (8) The present invention also provides a transparent insulating substrate and a first insulating layer formed on the transparent insulating substrate. A gate, a source and a drain which are electrodes; an insulating film formed so as to cover the first electrode and the transparent insulating substrate; an insulating film provided with a predetermined contact hole; and formed on the insulating film And a second electrode made of a transparent electrode, wherein the first electrode is made of an A1 alloy containing Ni and one or more metals selected from {Mo, Nb, W, Zr}. A liquid crystal display device having at least a TFT array substrate in which the second electrode and the first electrode are electrically connected directly through the contact hole.
[0038] このような構成によれば、薄膜トランジスタと透明電極とを直接接触させつつ、接触 抵抗を低く抑えることができるので、良好な表示を行うことができる。  [0038] According to such a configuration, the contact resistance can be kept low while the thin film transistor and the transparent electrode are in direct contact with each other, so that a good display can be performed.
[0039] 前記第 1電極は、 Niと、 {Mo、 Nb、 W、 Zr}から選ばれた一種以上の金属と、を少 なくとも含む A1合金かなる。そして、このような第 1電極は、 Niと、 {Mo、 Nb、 W、 Zr} 力も選ばれた一種以上の金属と、を含む A1合金ターゲットを用いて、スパッタリングに より形成されるちのである。  [0039] The first electrode is made of an A1 alloy containing at least Ni and at least one metal selected from {Mo, Nb, W, Zr}. Such a first electrode is formed by sputtering using an A1 alloy target containing Ni and one or more metals selected for {Mo, Nb, W, Zr} force. .
[0040] 前記 Niと、 {Mo、 Nb、 W、 Zr}から選ばれた一種以上の金属と、を含む A1合金ター ゲットは、従来力 知られている種々の手法で作成することができる。たとえば、真空 溶解方法、スプレイフォーミング法、等により製造されるものである。  [0040] The A1 alloy target containing Ni and one or more metals selected from {Mo, Nb, W, Zr} can be prepared by various methods known in the art. For example, it is manufactured by a vacuum melting method, a spray forming method, or the like.
[0041] 前記第 1電極は、 Niと、 {Mo、 Nb、 W、 Zr}から選ばれた一種以上の金属と、を少 なくとも含む A1合金である。この第 1電極は、ドレインやソース、ゲートであるが、実際 にドレイン等として使用するには、所望の形状にパター-ングする必要がある。このパ ターニングは、上記組成の A1合金の薄膜を、燐酸 酢酸 硝酸の混合酸によりエツ チングすることによって実行される。もちろん、この A1合金の薄膜自体は、上述したよ うに、 Niと、 {Mo、 Nb、 W、 Zr}から選ばれた一種以上の金属と、含む A1合金ターゲ ットを用いて、スパッタリングにより形成される。  [0041] The first electrode is an A1 alloy containing at least Ni and one or more metals selected from {Mo, Nb, W, Zr}. The first electrode is a drain, a source, or a gate, but in order to actually use it as a drain or the like, it must be patterned into a desired shape. This patterning is performed by etching a thin film of the A1 alloy having the above composition with a mixed acid of phosphoric acid, acetic acid and nitric acid. Of course, as described above, the A1 alloy thin film itself is formed by sputtering using an A1 alloy target containing Ni and one or more metals selected from {Mo, Nb, W, Zr}. Is done.
[0042] (9)また、本発明は、透明絶縁性基板と、前記透明絶縁性基板上に形成された第 1 電極であるゲート、ソース及びドレインと、該第 1電極及び前記透明絶縁性基板を覆 つて形成された絶縁膜であって、所定のコンタクトホールが設けられた絶縁膜と、該 絶縁膜上に形成された透明電極からなる第 2電極と、を少なくとも含み、前記第 1電 極力 Niと、 {Mo、 Nb、 W、 Zr}から選ばれた一種以上の金属と、を含む A1合金から なり、前記第 2電極と前記第 1電極とが前記コンタクトホールを介して電気的に直接接 続されてなる TFTアレイ基板を少なくとも有する有機 EL表示装置である。 [0042] (9) Further, the present invention provides a transparent insulating substrate, a gate, a source and a drain which are first electrodes formed on the transparent insulating substrate, the first electrode and the transparent insulating substrate. An insulating film formed so as to cover the insulating film, the insulating film having a predetermined contact hole, and a second electrode made of a transparent electrode formed on the insulating film, wherein the first electrode Ni and an Al alloy containing at least one metal selected from {Mo, Nb, W, Zr}, and the second electrode and the first electrode are electrically directly connected through the contact hole. Contact This is an organic EL display device having at least a TFT array substrate.
[0043] このような構成によれば、薄膜トランジスタと透明電極とを直接接触させつつ、接触 抵抗を低く抑えることができるので、良好な表示を行うことができる有機 EL装置が得 られる。 [0043] According to such a configuration, since the contact resistance can be kept low while the thin film transistor and the transparent electrode are in direct contact with each other, an organic EL device capable of performing good display can be obtained.
[0044] (10)また、本発明は、透明絶縁性基板と、前記透明絶縁性基板上に形成された第 1電極と、前記透明絶縁性基板上に形成された透明電極からなる第 2電極と、を具備 し、前記第 1電極が、 Niと、 {Mo、 Nb、 W、 Zr}から選ばれた一種以上の金属と、を 含む A1合金カゝらなり、前記第 1電極が、前記透明電極カゝらなる第 2電極と電気的に直 接接続されてなる透明導電積層基板である。  (10) The present invention also provides a second electrode comprising a transparent insulating substrate, a first electrode formed on the transparent insulating substrate, and a transparent electrode formed on the transparent insulating substrate. The first electrode is made of an Al alloy containing Ni and one or more metals selected from {Mo, Nb, W, Zr}, and the first electrode is It is a transparent conductive laminated substrate that is electrically connected directly to a second electrode that is a transparent electrode cover.
[0045] このような構成によれば、第 1電極と、透明電極である第 2電極と、を直接接触させ てもその間の接触抵抗の値を小さくすることができる透明導電積層基板が得られる。  [0045] According to such a configuration, it is possible to obtain a transparent conductive multilayer substrate that can reduce the value of the contact resistance between the first electrode and the second electrode, which is a transparent electrode, even if they are in direct contact with each other. .
[0046] このように、薄膜トランジスタを設けて 、な 、基板も本発明に含まれる。  [0046] Thus, a thin film transistor is provided, and a substrate is also included in the present invention.
発明の効果  The invention's effect
[0047] 以上述べたように、本発明によれば、ゲート、ドレイン、ソースなどの電極を、 Ni及び 、 {Mo、 Nb、 W、 Zr}から選ばれた一種以上の金属を含む A1合金で構成したので、 透明電極と直接接触させても低い接触抵抗を実現できる薄膜トランジスタを提供する ことができる。  [0047] As described above, according to the present invention, electrodes such as a gate, a drain, and a source are made of an Al alloy containing Ni and one or more metals selected from {Mo, Nb, W, Zr}. Since it is configured, it is possible to provide a thin film transistor capable of realizing a low contact resistance even when directly in contact with a transparent electrode.
[0048] また、特に本発明の薄膜トランジスタ基板の製法は、  [0048] In particular, the method for producing a thin film transistor substrate of the present invention includes:
(1)透明絶縁性基板上に、 Ni及び、 {Mo、 Nb、 W、 Zr}から選ばれた一種以上の 金属を含む A1合金を用いて、第 1電極であるゲート、ソース及びドレインのうちの少な くとも一つを形成する工程と、  (1) On the transparent insulating substrate, using A1 alloy containing Ni and one or more metals selected from {Mo, Nb, W, Zr}, among the gate, source and drain as the first electrode Forming at least one of
(2)前記第 1電極及び前記基板を覆って絶縁膜を成膜する工程と、  (2) forming an insulating film covering the first electrode and the substrate;
(3)該絶縁膜にパターユングを施しコンタクトホールを形成する工程と、 (3) patterning the insulating film to form a contact hole;
(4)前記絶縁膜上に透明膜電極からなる第 2電極を形成して該第 2電極と第 1電極 とを前記コンタクトホールを介して電気的に直接接続する工程と、 (4) forming a second electrode made of a transparent film electrode on the insulating film, and electrically connecting the second electrode and the first electrode directly through the contact hole;
を少なくとも含むものであるので、第 1電極を IZOなどと直接的に低コンタクト抵抗が 実現できる薄膜トランジスタ基板を容易にうると ヽぅ効果を奏する。  Therefore, it is easy to obtain a thin film transistor substrate that can realize low contact resistance directly with IZO or the like for the first electrode.
[0049] また、 A1合金のみを用い、他の金属層との 2層構造等を取っていないので、パター ユング時のエッチングが 1回で済む。そのために、成膜 (配線材料種類の低減)並び にエッチング工程の簡略化、
Figure imgf000011_0001
、う効果を奏 する。 [0049] Also, since only the A1 alloy is used and the two-layer structure with other metal layers is not taken, Etching during Jung can be done only once. Therefore, film formation (reduction of wiring material types) and simplification of etching process,
Figure imgf000011_0001
This has the effect.
[0050] また、特に本発明に係る薄膜トランジスタ基板は、透明絶縁性基板と、前記透明絶 縁性基板上に形成された第 1電極であるゲート、ソース及びドレインの少なくとも一つ と、該第 1電極及び前記透明絶縁性基板を覆うように形成された絶縁膜であって、所 定のコンタクトホールが設けられている絶縁膜と、該絶縁膜上に形成された透明電極 である第 2電極と、を少なくとも含み、前記第 1電極は Niと、 {Mo、 Nb、 W、 Zr}から選 ばれた一種以上の金属と、を含む A1合金カゝらなり、前記第 2電極と前記第 1電極とが 前記コンタクトホールを介して電気的に直接接続されてなるものであるので、 IZOなど と直接的に低コンタクト抵抗が実現できる薄膜トランジスタをうるという効果を奏する。  [0050] In particular, the thin film transistor substrate according to the present invention includes a transparent insulating substrate, at least one of a gate, a source, and a drain as a first electrode formed on the transparent insulating substrate, and the first An insulating film formed so as to cover the electrode and the transparent insulating substrate, the insulating film having a predetermined contact hole, and a second electrode that is a transparent electrode formed on the insulating film; The first electrode is made of A1 alloy containing Ni and one or more metals selected from {Mo, Nb, W, Zr}, the second electrode and the first electrode Are electrically connected directly through the contact hole, and thus there is an effect of obtaining a thin film transistor that can realize low contact resistance directly with IZO or the like.
[0051] また、 A1のみを用いて、他の金属層との 2層構造等を採用する必要がないので、パ ターニング時のエッチングが 1回で済むために、成膜 (配線材料種類の低減)並びに エッチング工程の簡略化、ひ 、ては生産性向上並びにコスト低減と!/、う効果を奏する  [0051] In addition, since it is not necessary to use only A1 and adopt a two-layer structure with other metal layers, etc., film formation (reduction of wiring material types) can be performed only once during patterning. ) And the simplification of the etching process, thus improving productivity and reducing costs!
[0052] また、本発明に係る薄膜トランジスタ基板は、前記透明電極が酸化インジウム、酸 化すず、酸化インジウムすず及び酸化亜鉛のいずれかからなるものである。したがつ て、薄膜トランジスタの第 1電極 (ソースやドレイン、ゲート）を、 ITOや IZOなどと直接 接続させても、低 ヽコンタクト抵抗を実現できる薄膜トランジスタ基板が得られる。 [0052] In the thin film transistor substrate according to the present invention, the transparent electrode is made of indium oxide, tin oxide, indium tin oxide, or zinc oxide. Therefore, even if the first electrode (source, drain, gate) of the thin film transistor is directly connected to ITO, IZO, etc., a thin film transistor substrate capable of realizing a low contact resistance can be obtained.
[0053] また、本発明に係る液晶表示装置は、透明絶縁性基板と、前記透明絶縁性基板上 に形成された第 1電極であるゲート、ソース及びドレインと、該第 1電極及び前記透明 絶縁性基板を覆って形成された絶縁膜であって、所定のコンタクトホールが設けられ ている絶縁膜と、該絶縁膜上に形成された透明電極からなる第 2電極と、を少なくとも 含み、前記第 1電極が、 Niと、 {Mo、 Nb、 W、 Zr}から選ばれた一種以上の金属と、 を含む A1合金カゝらなり、前記第 2電極と前記第 1電極とが前記コンタクトホールを介し て電気的に直接接続されてなる TFTアレイ基板を少なくとも有する液晶表示装置で ある。したがって、薄膜トランジスタの第 1電極 (ソースやドレイン、ゲート）を、 IZOや I TOなどと直接接続させても、低いコンタクト抵抗が実現できる薄膜トランジスタを用い た液晶表示装置である。この薄膜トランジスタはこのような構成を採用しているので、 高開口率を実現しやすぐ高性能な表示特性を有する。その結果、従来装置よりも生 産性が向上し、低い製造コストを実現することができる優れた液晶表示装置をうるとい う効果を奏する。 In addition, the liquid crystal display device according to the present invention includes a transparent insulating substrate, a gate, a source, and a drain that are first electrodes formed on the transparent insulating substrate, the first electrode, and the transparent insulating material. An insulating film formed over the conductive substrate, the insulating film having a predetermined contact hole, and a second electrode made of a transparent electrode formed on the insulating film, One electrode is made of an Al alloy alloy containing Ni and one or more metals selected from {Mo, Nb, W, Zr}, and the second electrode and the first electrode serve as the contact hole. This is a liquid crystal display device having at least a TFT array substrate that is electrically directly connected through the TFT array substrate. Therefore, use a thin film transistor that can achieve low contact resistance even if the first electrode (source, drain, gate) of the thin film transistor is directly connected to IZO, ITO, etc. A liquid crystal display device. Since this thin film transistor employs such a structure, it realizes a high aperture ratio and has high-performance display characteristics. As a result, it is possible to obtain an excellent liquid crystal display device that is more productive than conventional devices and can realize a low manufacturing cost.
図面の簡単な説明  Brief Description of Drawings
[0054] [図 1]図 1(a)及び図 1(b)は本実施例による TFTアレイ基板 (薄膜トランジスタ基板)の 製造工程を示す断面説明図である。  [0054] FIG. 1 (a) and FIG. 1 (b) are cross-sectional explanatory views showing a manufacturing process of a TFT array substrate (thin film transistor substrate) according to this example.
[図 2]図 2(a)及び図 2(b)は本実施例による TFTアレイ基板 (薄膜トランジスタ基板)の 製造工程を示す別の断面説明図である。  [FIG. 2] FIG. 2 (a) and FIG. 2 (b) are other cross-sectional explanatory views showing the manufacturing process of the TFT array substrate (thin film transistor substrate) according to this example.
[図 3]本実施例による TFTアレイ基板 (薄膜トランジスタ基板)の製造工程を示すさら に別の断面説明図である。  FIG. 3 is still another cross-sectional explanatory view showing the manufacturing process of the TFT array substrate (thin film transistor substrate) according to the present embodiment.
[図 4]本実施例におけるケルビンパターンの配線の外観及び測定の様子を示す配線 概念図である。  FIG. 4 is a wiring conceptual diagram showing the appearance of Kelvin pattern wiring and the state of measurement in this example.
符号の説明  Explanation of symbols
[0055] 1 透明絶縁性基板 [0055] 1 Transparent insulating substrate
2 ゲート電極  2 Gate electrode
4 ゲート絶縁膜  4 Gate insulation film
5 半導体層 a— Si膜  5 Semiconductor layer a—Si film
6 半導体層 n+a— Si膜  6 Semiconductor layer n + a—Si film
7a ドレイン電極  7a Drain electrode
7b ソース電極  7b Source electrode
9 層間絶縁膜  9 Interlayer insulation film
10 コンタクトホーノレ  10 Contact Honoré
11 画素電極  11 Pixel electrode
21 TFT咅  21 TFT
22 端子部  22 Terminal
100 TFTアレイ基板  100 TFT array substrate
発明を実施するための最良の形態 [0056] 以下、添付図面を参照しつつ、本発明の実施の形態について詳細に説明する。 BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
[0057] 実施の形餱 1 [0057] Implementation form 1
図 1〜図 3は本発明に係わる TFTアレイ基板 100の TFT部及び端子部を製造ェ 程順に示す工程断面説明図であり、図 l (a)、図 l (b)、図 2 (a)、図 2 (b)、図 3の順に 製造工程が進んで!/、く様子が示されて!/ヽる。  1 to 3 are process cross-sectional explanatory views showing the TFT portion and the terminal portion of the TFT array substrate 100 according to the present invention in the order of the manufacturing process, and FIG. 1 (a), FIG. 1 (b), FIG. Fig. 2 (b) and Fig. 3 show the manufacturing process progressing!
[0058] これらの図において、 21は TFT部であり、 22は端子部であり、 1は透明性絶縁基 板であり、 2は第 1電極 (TFT部の第 1電極はゲート電極)の第 1層である。また、 4は ゲート絶縁膜であり、 5は半導体層 a— Si膜であり、 6は半導体層 n+a— Si膜である（ 図 1(a)及び図 1(b)参照)。 In these drawings, 21 is a TFT portion, 22 is a terminal portion, 1 is a transparent insulating substrate, and 2 is the first electrode of the first electrode (the first electrode of the TFT portion is a gate electrode). One layer. Further, 4 is a gate insulating film, 5 is a semiconductor layer a-Si film, and 6 is a semiconductor layer n + a-Si film (see FIG. 1 (a) and FIG. 1 (b)).
[0059] 次に、 7は第 1電極 (TFT部の第 1電極はソース Zドレイン電極）の第 1層であり、 9 は層間絶縁膜であり、 10はコンタクトホールである（図 2(a)及び図 2(b)参照)。 Next, 7 is the first layer of the first electrode (the first electrode of the TFT section is the source Z drain electrode), 9 is the interlayer insulating film, and 10 is the contact hole (FIG. 2 (a ) And Figure 2 (b)).
[0060] そして、 11は第 2電極 (画素電極)である（図 3参照）。 [0060] Reference numeral 11 denotes a second electrode (pixel electrode) (see FIG. 3).
[0061] TFT部 21は、 TFTアレイ基板 100上の互いに直交するゲート配線とソース配線（ 共に図示せず)の交差部近傍に設けられ、液晶を駆動するスイッチング素子を構成 する部分であり、端子部 22はゲート配線を延在して表示パネルの外側に配置され、 ゲート電極に外部力も信号を入力するための部分である。  [0061] The TFT portion 21 is provided near the intersecting portion of the gate wiring and the source wiring (both not shown) on the TFT array substrate 100, and constitutes a switching element that drives the liquid crystal, and has a terminal The part 22 extends from the gate wiring and is arranged outside the display panel, and is a part for inputting an external force to the gate electrode.
[0062] 以下、本実施の形態の TFTアレイ基板 100の製造工程を図面に基づき説明する。  Hereinafter, the manufacturing process of the TFT array substrate 100 of the present embodiment will be described with reference to the drawings.
[0063] まず、透明性絶縁基板 1上にスパッタリング法などを用いて、 Ni、及び、 {Mo、 Nb、 W、 Zr}から選ばれた一種以上の金属を含む A1合金 (第 1電極材料)を成膜する。  [0063] First, an A1 alloy containing Ni and one or more metals selected from {Mo, Nb, W, Zr} using a sputtering method or the like on the transparent insulating substrate 1 (first electrode material) Is deposited.
[0064] 次に、フォトリソグラフィ法にてレジストパターユングを行った後、燐酸、硝酸及び酢 酸系のエッチング液を用いてエッチングし、ゲート配線（図示せず)及びゲート電極 2 (第 1電極)並びに端子部 22の端子を形成する（図 1 (a)参照)。  [0064] Next, after performing resist patterning by a photolithography method, etching is performed using phosphoric acid, nitric acid, and acetic acid-based etching solutions, and gate wiring (not shown) and gate electrode 2 (first electrode) are etched. ) And the terminal 22 are formed (see FIG. 1 (a)).
[0065] 次に、化学的気相成長法 (以下、単に CVDと呼ぶ)等を用いて窒化シリコン (SiNx )又は酸ィ匕シリコン (SiO )力もなるゲート絶縁膜 4を厚さ約 4000 る。  Next, the gate insulating film 4 having a silicon nitride (SiNx) or oxide silicon (SiO 2) force is formed to a thickness of about 4000 using chemical vapor deposition (hereinafter simply referred to as CVD).
2 A成膜す  2 A film
[0066] 次に、半導体層を成膜する。この半導体層をパターユングすることによって、半導 体層 a— Si膜 5 (厚さ 1500A)低抵抗の半導体層 n+a— Si膜 6 (厚さ約 300A)を順 次形成する。（図 1 (b)参照)。  [0066] Next, a semiconductor layer is formed. By patterning this semiconductor layer, a semiconductor layer a—Si film 5 (thickness 1500 A) and a low resistance semiconductor layer n + a—Si film 6 (thickness about 300 A) are sequentially formed. (See Figure 1 (b)).
[0067] さらに、スパッタリング法を用いてふたたび第 1電極材料である、 Ni及び、 {Mo、 Nb 、 W、 Zr}から選ばれた一種以上の金属を含む Al合金を約 3000 A成膜し、パター- ングを行ってトランジスタのチャネル部並びにソース/ドレイン電極部（すなわち第一 電極)を形成する（図 2 (a)参照)。 [0067] Furthermore, Ni and {Mo, Nb which are the first electrode materials again using the sputtering method , W, Zr}, an Al alloy containing one or more metals selected from the group consisting of one or more metals, is formed to a thickness of about 3000 A, and patterning is performed to form the channel portion of the transistor and the source / drain electrode portion (ie, the first electrode) (See Figure 2 (a)).
[0068] 次に、層間絶縁膜 9を形成したのち、パターユングを行いコンタクトホール 10を形成 する（図 2 (b)参照）。コンタクトホール 10はゲート端子部及び TFTのドレイン電極 7a に接続するように形成される。ここで、層間絶縁膜 9は、たとえば CVD法による窒化シ リコン膜、又はアクリル系の透明性榭脂などのいずれか一方、あるいは両方の組み合 わせで形成することができる（図 2の (b)参照)。  Next, after forming the interlayer insulating film 9, patterning is performed to form the contact hole 10 (see FIG. 2B). The contact hole 10 is formed so as to be connected to the gate terminal portion and the TFT drain electrode 7a. Here, the interlayer insulating film 9 can be formed by, for example, a silicon nitride film by a CVD method, an acrylic transparent resin, or a combination of both (see (b) of FIG. )reference).
[0069] 最後に透明導電膜としてスパッタリング法を用い IZO膜 (酸化インジウム亜鉛)を厚 さ約 1000 A成膜する (IZOは登録商標)。そして、この透明導電膜をパターユングし て画素電極 (第 2電極） 11を形成することによって TFTアレイ基板が基本的な構成が 完成する。  [0069] Finally, an IZO film (indium zinc oxide) is formed to a thickness of about 1000 A using a sputtering method as a transparent conductive film (IZO is a registered trademark). The basic structure of the TFT array substrate is completed by patterning this transparent conductive film to form the pixel electrode (second electrode) 11.
[0070] ここで、画素電極 11は層間絶縁膜 9に設けられたコンタクトホール 10を介して第 1 電極材料からなるゲート電極、ソース Zドレイン電極 (すなわち、第 1電極）と電気的 に直接接続されている。  Here, the pixel electrode 11 is electrically connected directly to the gate electrode and the source Z drain electrode (that is, the first electrode) made of the first electrode material through the contact hole 10 provided in the interlayer insulating film 9. Has been.
[0071] 本実施の形態において特徴的なことは、第 1電極材料である A1合金が  [0071] What is characteristic in the present embodiment is that the first electrode material A1 alloy is
•Niと、  • Ni,
• {Mo、 Nb、 W、 Zr}から選ばれた一種以上の金属と、  • One or more metals selected from {Mo, Nb, W, Zr},
を含む A1合金であることである。さらに、本実施の形態で特徴的なことは、この第 1電 極材料を用いてスパッタリングによってゲート電極及び端子部を形成する際に、純 Ar ガスの雰囲気中でスパッタリングを行い、第 1電極を約 2000 Aの厚さで成膜すること である。  A1 alloy containing Further, the characteristic of this embodiment is that when the gate electrode and the terminal portion are formed by sputtering using the first electrode material, sputtering is performed in an atmosphere of pure Ar gas, and the first electrode is formed. The film thickness is about 2000 A.
[0072] なお、この A1膜は、 Ni、及び、 {Mo、 Nb、 W、 Zr}から選ばれた一種以上の金属を 含む A1合金ターゲットを用いてスパッタリングを行うことによって形成される。また、そ の後の熱処理により抵抗値を低減することができる。  [0072] This A1 film is formed by performing sputtering using an A1 alloy target containing Ni and one or more metals selected from {Mo, Nb, W, Zr}. Further, the resistance value can be reduced by the subsequent heat treatment.
[0073] 本実施の形態の A1膜の種々の例についての物理計測結果が表 1に示されている。 [0073] Table 1 shows the physical measurement results for various examples of the A1 film of the present embodiment.
表 1には、実施例 実施例 2、実施例 3、実施例 4と、比較のための比較例 1、比較 例 2、比較例 3が示されている。 [0074] [表 1] Table 1 shows Example Example 2, Example 3, and Example 4, and Comparative Example 1, Comparative Example 2, and Comparative Example 3 for comparison. [0074] [Table 1]
Figure imgf000015_0001
Figure imgf000015_0001
実施例 1 Example 1
実施例 1においては、第 1電極を構成する A1合金は、 Niを 1. 5wt%、 Wを 0. 2wt %含有する Al合金である。この A1合金の比抵抗は 5. 2 μ Ω cmである。この Al合金 の薄膜を、室温の TMAH (2. 38wt%)水溶液に 5分間浸漬しても変化は見られな かった。  In Example 1, the A1 alloy constituting the first electrode is an Al alloy containing 1.5 wt% Ni and 0.2 wt% W. The specific resistance of this A1 alloy is 5.2 μΩcm. No change was observed when this Al alloy thin film was immersed in an aqueous TMAH (2.38 wt%) solution at room temperature for 5 minutes.
[0075] また、この A1合金薄膜上に ITOを積層した後、室温の TMAH (2. 38wt%)水溶 液に 5分間浸漬しても変化は見られな力つた。 ITOの代わりに IZOを積層して同様に 室温の TMAH (2. 38wt%)水溶液に 5分間浸漬した力 同様に変化は見られなか つた o  [0075] In addition, after laminating ITO on the A1 alloy thin film, even if it was immersed in a TMAH (2.38 wt%) aqueous solution at room temperature for 5 minutes, no change was observed. IZO layered instead of ITO, and similarly immersed in a TMAH (2.38 wt%) aqueous solution at room temperature for 5 minutes.
[0076] ¾細12  [0076] ¾fine 12
実施例 2においては、第 1電極を構成する A1合金は、 Niを 1. 5wt%、 Moを 0. 5w t%含有する Al合金である。この A1合金の比抵抗は 4. 8 μ Ω cmである。この Al合金 の薄膜を、室温の TMAH (2. 38wt%)水溶液に 5分間浸漬しても変化は見られな かった。  In Example 2, the A1 alloy constituting the first electrode is an Al alloy containing 1.5 wt% Ni and 0.5 wt% Mo. The specific resistance of this A1 alloy is 4.8 μΩcm. No change was observed when this Al alloy thin film was immersed in an aqueous TMAH (2.38 wt%) solution at room temperature for 5 minutes.
[0077] また、この A1合金薄膜上に ITOを積層した後、室温の TMAH (2. 38wt%)水溶 液に 5分間浸漬しても変化は見られな力つた。 ITOの代わりに IZOを積層して同様に 室温の TMAH (2. 38wt%)水溶液に 5分間浸漬した力 同様に変化は見られなか つた o [0077] Moreover, after laminating ITO on this A1 alloy thin film, TMAH (2.38 wt%) Even after being immersed in the solution for 5 minutes, there was no change. IZO layered instead of ITO, and similarly immersed in a TMAH (2.38 wt%) aqueous solution at room temperature for 5 minutes.
[0078] 実施例 3  [0078] Example 3
実施例 3においては、第 1電極を構成する A1合金は、 Niを 1. 5wt%、 Nbを 0. 8wt %含有する A1合金である。この A1合金の比抵抗は 5. 8 μ Ω cmである。この A1合金 の薄膜を、室温の TMAH (2. 38wt%)水溶液に 5分間浸漬しても変化は見られな かった。  In Example 3, the A1 alloy constituting the first electrode is an A1 alloy containing 1.5 wt% Ni and 0.8 wt% Nb. The specific resistance of this A1 alloy is 5.8 μΩcm. No change was seen when this A1 alloy thin film was immersed in a room temperature TMAH (2.38 wt%) aqueous solution for 5 minutes.
[0079] また、この A1合金薄膜上に ITOを積層した後、室温の TMAH (2. 38wt%)水溶 液に 5分間浸漬しても変化は見られな力つた。 ITOの代わりに IZOを積層して同様に 室温の TMAH (2. 38wt%)水溶液に 5分間浸漬した力 同様に変化は見られなか つた o  [0079] In addition, after laminating ITO on this A1 alloy thin film, even if immersed in a TMAH (2.38 wt%) aqueous solution at room temperature for 5 minutes, no change was observed. IZO layered instead of ITO, and similarly immersed in a TMAH (2.38 wt%) aqueous solution at room temperature for 5 minutes.
[0080] 実飾 14  [0080] Decoration 14
実施例 4においては、第 1電極を構成する A1合金は、 Niを 1. 5wt%、 Zrを 0. 5wt %含有する A1合金である。この A1合金の比抵抗は 5. δ μ Ω cmである。この A1合金 の薄膜を、室温の TMAH (2. 38wt%)水溶液に 5分間浸漬した場合、一部に溶解 が見られた。  In Example 4, the A1 alloy constituting the first electrode is an A1 alloy containing 1.5 wt% Ni and 0.5 wt% Zr. The specific resistance of this A1 alloy is 5. δ μΩcm. When this A1 alloy thin film was immersed in an aqueous TMAH (2.38 wt%) solution at room temperature for 5 minutes, some dissolution was observed.
[0081] また、この A1合金薄膜上に ITOを積層した後、室温の TMAH (2. 38wt%)水溶 液に 5分間浸漬しても変化は見られな力つた。 ITOの代わりに IZOを積層して同様に 室温の TMAH (2. 38wt%)水溶液に 5分間浸漬した力 同様に変化は見られなか つた o  [0081] In addition, after laminating ITO on this A1 alloy thin film, even if immersed in a TMAH (2.38 wt%) aqueous solution at room temperature for 5 minutes, no change was observed. IZO layered instead of ITO, and similarly immersed in a TMAH (2.38 wt%) aqueous solution at room temperature for 5 minutes.
[0082] 比較例 1  [0082] Comparative Example 1
比較例 1においては、第 1電極を構成する A1は、純 A1である。この A1の比抵抗は 2 . 1 μ Ω cmである。この A1薄膜を、室温の TMAH (2. 38wt%)水溶液に 5分間浸漬 しても変化は見られな力つた。  In Comparative Example 1, A1 constituting the first electrode is pure A1. The specific resistance of A1 is 2.1 μΩcm. Even if this A1 thin film was immersed in an aqueous TMAH (2.38 wt%) solution at room temperature for 5 minutes, no change was observed.
[0083] また、この A1薄膜上に ITOを積層した後、室温の TMAH (2. 38wt%)水溶液に 5 分間浸漬した場合、水溶液に溶解した。また、 ITOの代わりに IZOを積層して同様に 室温の TMAH (2. 38wt%)水溶液に 5分間浸漬しても、同様に溶解が見られた。 [0084] 比較例 2 [0083] Further, when ITO was laminated on the A1 thin film, it was dissolved in an aqueous solution of TMAH (2.38 wt%) at room temperature for 5 minutes, and then dissolved in the aqueous solution. In addition, even when IZO was laminated instead of ITO and immersed in a TMAH (2.38 wt%) aqueous solution at room temperature for 5 minutes, dissolution was similarly observed. [0084] Comparative Example 2
比較例 2においては、第 1電極を構成する A1合金は、 Niを 1. 5wt%含有する A1合 金である。この A1合金の比抵抗は 3. δ μ Ω cmである。この A1合金の薄膜を、室温の TMAH (2. 38wt%)水溶液に 5分間浸漬した場合、溶解が見られた。  In Comparative Example 2, the A1 alloy constituting the first electrode is an A1 alloy containing 1.5 wt% Ni. The specific resistance of this A1 alloy is 3. δ μΩcm. When this A1 alloy thin film was immersed in an aqueous TMAH (2.38 wt%) solution at room temperature for 5 minutes, dissolution was observed.
[0085] また、この A1合金薄膜上に ITOを積層した後、室温の TMAH (2. 38wt%)水溶 液に 5分間浸漬した場合も、水溶液に溶解した。また、 ITOの代わりに IZOを積層し て同様に室温の TMAH (2. 38wt%)水溶液に 5分間浸漬しても、同様に溶解が見 られた。  [0085] Further, even when ITO was laminated on the A1 alloy thin film and then immersed in a TMAH (2.38 wt%) aqueous solution at room temperature for 5 minutes, it was dissolved in the aqueous solution. Also, when IZO was laminated instead of ITO and immersed in a TMAH (2.38 wt%) aqueous solution at room temperature for 5 minutes, dissolution was observed in the same manner.
[0086] 比較例 3  [0086] Comparative Example 3
比較例 3においては、第 1電極を構成する A1合金は、 Ndを 0. 8wt%含有する A1 合金である。この A1合金の比抵抗は 4. 2 μ Ω cmである。この A1合金薄膜を、室温の TMAH (2. 38wt%)水溶液に 5分間浸漬した場合、溶解が見られた。  In Comparative Example 3, the A1 alloy constituting the first electrode is an A1 alloy containing 0.8 wt% Nd. The specific resistance of this A1 alloy is 4.2 μΩcm. When this A1 alloy thin film was immersed in a TMAH (2.38 wt%) aqueous solution at room temperature for 5 minutes, dissolution was observed.
[0087] また、この A1合金薄膜上に ITOを積層した後、室温の TMAH (2. 38wt%)水溶 液に 5分間浸漬した場合も、水溶液に溶解した。また、 ITOの代わりに IZOを積層し て同様に室温の TMAH (2. 38wt%)水溶液に 5分間浸漬しても、同様に溶解が見 られた。 [0087] Further, even when ITO was laminated on the A1 alloy thin film and then immersed in a TMAH (2.38 wt%) aqueous solution at room temperature for 5 minutes, it was dissolved in the aqueous solution. Also, when IZO was laminated instead of ITO and immersed in a TMAH (2.38 wt%) aqueous solution at room temperature for 5 minutes, dissolution was observed in the same manner.
[0088] 以上述べたように、本実施例で示した例によれば、 TMAH水溶液に浸漬しても全 てが溶解してしまうことはない。薄膜トランジスタの製造を安定的に実行することがで きると考えられる。一部溶解した実施例 4においても透明電極を積層した場合は、変 ィ匕がなぐ円滑に製造を行うことができると考えられる。  [0088] As described above, according to the example shown in the present example, even when immersed in the TMAH aqueous solution, everything is not dissolved. It is considered that the thin film transistor can be manufactured stably. Also in Example 4 where a part was dissolved, it is considered that when the transparent electrode is laminated, the production can be smoothly performed without any change.
[0089] 本実施の形態に適用した、第 1電極と、透明導電膜である第 2電極とのコンタクト表 面部の電気抵抗値 (コンタクト抵抗値）は、十分に小さな値となる。たとえば、第 1電極 として Moを利用した A1合金を利用した場合は、コンタクト抵抗値のも最小値は約 50 μ m口で約 380 Ωと低く良好な値を示した。ケルビンパターンによる IZOなどの透明 導電膜からなる第 2電極とのコンタクト表面部の電気抵抗値 (コンタクト抵抗値)の結 果が表 2に示されている。  The electrical resistance value (contact resistance value) of the contact surface portion between the first electrode and the second electrode, which is a transparent conductive film, applied to this embodiment is a sufficiently small value. For example, when the A1 alloy using Mo as the first electrode was used, the minimum value of the contact resistance was about 380 Ω at the mouth of about 50 μm, indicating a good value. Table 2 shows the results of the electrical resistance value (contact resistance value) of the contact surface with the second electrode made of a transparent conductive film such as IZO using the Kelvin pattern.
[0090] [表 2] 表 2 [0090] [Table 2] Table 2
Figure imgf000018_0001
Figure imgf000018_0001
なお、本特許における第 1電極とは、 Ni、及び、 {Mo、 Nb、 W、 Zr}から選ばれた一 種以上の金属を含む Al合金カゝらなることを特徴とする。また、透明導電膜からなる第 2電極は、具体的には、 IZOなどカゝら構成される。 The first electrode in this patent is characterized in that it is made of an Al alloy containing one or more metals selected from Ni and {Mo, Nb, W, Zr}. The second electrode made of a transparent conductive film is specifically composed of IZO or the like.
[0091] さて、表 2には、実施例 5、実施例 6、実施例 7、実施例 8と、比較のための比較例 1 、比較例 2、比較例 3 (表 1と同じ)が示されている。  [0091] Table 2 shows Example 5, Example 6, Example 7, and Example 8, and Comparative Example 1, Comparative Example 2, and Comparative Example 3 (same as Table 1) for comparison. Has been.
[0092] 実飾 15  [0092] Decoration 15
実施例 5においては、第 1電極を構成する A1合金は、 Niを 1. 5wt%、 Wを 0. 5wt %含有する Al合金である。この A1合金の比抵抗は 8. 2 μ Ω cmである。この Al合金 薄膜と、 IZO力 なる透明導電膜を基板上に十字形に交差するように設け、ケルビン ノターンによる接触抵抗の計測を行った。このケルビンパターンの様子が図 4に示さ れている。  In Example 5, the A1 alloy constituting the first electrode is an Al alloy containing 1.5 wt% Ni and 0.5 wt% W. The specific resistance of this A1 alloy is 8.2 μΩcm. This Al alloy thin film and a transparent conductive film with IZO force were provided on the substrate so as to cross each other in a cross shape, and contact resistance was measured by Kelvin noturn. This Kelvin pattern is shown in Fig. 4.
[0093] IZOの金属酸化物の比抵抗は、 380 μ Ω cmであった。そして図 4におけるケルビ ンパターンによる接触抵抗 (コンタクト抵抗値)の計測値は、 230 Ωであり、十分に低 い値となった。  [0093] The specific resistance of the metal oxide of IZO was 380 μΩcm. The measured value of contact resistance (contact resistance value) with the Kelvin pattern in Fig. 4 was 230 Ω, which was a sufficiently low value.
[0094] 実施例 6  [0094] Example 6
実施例 6においては、第 1電極を構成する A1合金は、 Niを 1. 5wt%、 Moを 0. 8w t%含有する Al合金である。この A1合金の比抵抗は 9. 8 μ Ω cmである。この A1合金 薄膜と、 IZO力 なる透明導電膜を基板上に十字形に交差するように設け、ケルビン ノ《ターンによる接触抵抗の計測を行った (図 4参照)。 In Example 6, the A1 alloy composing the first electrode is 1.5 wt% Ni and 0.8 w Mo. Al alloy containing t%. The specific resistance of this A1 alloy is 9.8 μΩcm. This A1 alloy thin film and a transparent conductive film with IZO force were placed on the substrate so as to cross each other in a cross shape, and contact resistance was measured by Kelvinno << turn (see Fig. 4).
[0095] IZOの金属酸化物の比抵抗は、 380 μ Ω cmであった。そして図 4におけるケルビ ンパターンによる接触抵抗 (コンタクト抵抗値)の計測値は、 340 Ωであり、十分に低 い値となった。 [0095] The specific resistance of the metal oxide of IZO was 380 μΩcm. The measured value of contact resistance (contact resistance value) with the Kelvin pattern in Fig. 4 was 340 Ω, which was a sufficiently low value.
[0096] 実施例 7 [0096] Example 7
実施例 7においては、第 1電極を構成する A1合金は、 Niを 1. 5wt%、 Nbを 0. 8wt %含有する Al合金である。この A1合金の比抵抗は 5. 8 μ Ω cmである。この Al合金 薄膜と、 IZO力 なる透明導電膜を基板上に十字形に交差するように設け、ケルビン ノ《ターンによる接触抵抗の計測を行った (図 4参照)。  In Example 7, the A1 alloy constituting the first electrode is an Al alloy containing 1.5 wt% Ni and 0.8 wt% Nb. The specific resistance of this A1 alloy is 5.8 μΩcm. This Al alloy thin film and a transparent conductive film with IZO force were provided on the substrate so as to cross each other in a cross shape, and the contact resistance was measured by Kelvinno << turn (see Fig. 4).
[0097] IZOの金属酸化物の比抵抗は、 380 μ Ω cmであった。そして図 4におけるケルビ ンパターンによる接触抵抗 (コンタクト抵抗値)の計測値は、 280 Ωであり、十分に低 い値となった。  [0097] The specific resistance of the metal oxide of IZO was 380 μΩcm. The measured value of contact resistance (contact resistance value) using the Kelvin pattern in Fig. 4 was 280 Ω, which was a sufficiently low value.
[0098] 実施例 8  [0098] Example 8
実施例 8においては、第 1電極を構成する A1合金は、 Niを 1. 5wt%、 Zrを 0. 5wt %含有する Al合金である。この A1合金の比抵抗は 5. δ μ Ω cmである。この Al合金 薄膜と、 ITO力もなる透明導電膜を基板上に十字形に交差するように設け、ケルビン ノ《ターンによる接触抵抗の計測を行った (図 4参照)。  In Example 8, the A1 alloy constituting the first electrode is an Al alloy containing 1.5 wt% Ni and 0.5 wt% Zr. The specific resistance of this A1 alloy is 5. δ μΩcm. This Al alloy thin film and a transparent conductive film with ITO force were provided on the substrate so as to cross each other in a cross shape, and the contact resistance was measured by Kelvinno turn (see Fig. 4).
[0099] ITOの金属酸化物の比抵抗は、 220 μ Ω cmであった。そして図 4におけるケルビ ンパターンによる接触抵抗 (コンタクト抵抗値)の計測値は、 320 Ωであり、十分に低 い値となった。  [0099] The specific resistance of the metal oxide of ITO was 220 μΩcm. The measured value of contact resistance (contact resistance value) by the Kelvin pattern in Fig. 4 was 320 Ω, which was a sufficiently low value.
[0100] 比較例 1  [0100] Comparative Example 1
比較例 1においては、表 1と同様に、第 1電極を構成するのは純 A1である。この A1 の比抵抗は 2. 1 μ Ω cmである。この Al薄膜と、 ITO力もなる透明導電膜を基板上に 十字形に交差するように設け、ケルビンパターンによる接触抵抗の計測を行った（図 4参照)。  In Comparative Example 1, as in Table 1, the first electrode is composed of pure A1. The specific resistance of A1 is 2.1 μΩcm. This Al thin film and a transparent conductive film with ITO force were provided on the substrate so as to cross in a cross shape, and contact resistance was measured using a Kelvin pattern (see Fig. 4).
[0101] ITOの金属酸化物の比抵抗は、 220 μ Ω cmであった。そして図 4におけるケルビ ンパターンによる接触抵抗 (コンタクト抵抗値)の計測値は、 1Μ Ω以上であり、表示 装置に用いるには高 、値である。 [0101] The resistivity of the ITO metal oxide was 220 μΩcm. And the cherub in Figure 4 The measured value of contact resistance (contact resistance value) by the pattern is 1 以上 Ω or more, which is high for use in a display device.
[0102] 比較例 2 [0102] Comparative Example 2
比較例 2においては、第 1電極を構成する A1合金は、 Niを 1. 5wt%含有する A1合 金である。この A1合金の比抵抗は 3. δ μ Ω cmである。この A1合金薄膜と、 ITOから なる透明導電膜を基板上に十字形に交差するように設け、ケルビンパターンによる接 触抵抗の計測を行った (図 4参照)。  In Comparative Example 2, the A1 alloy constituting the first electrode is an A1 alloy containing 1.5 wt% Ni. The specific resistance of this A1 alloy is 3. δ μΩcm. This A1 alloy thin film and a transparent conductive film made of ITO were provided on the substrate so as to cross each other in a cross shape, and the contact resistance was measured by a Kelvin pattern (see Fig. 4).
[0103] ITOの金属酸化物の比抵抗は、 220 μ Ω cmであった。そして図 4におけるケルビ ンパターンによる接触抵抗 (コンタクト抵抗値)の計測値は、 1Μ Ω以上であり、表示 装置に用いるには高 、値である。  [0103] The specific resistance of the ITO metal oxide was 220 μΩcm. The measured value of contact resistance (contact resistance value) by the Kelvin pattern in Fig. 4 is 1Μ Ω or more, which is high for use in a display device.
[0104] 比較例 3  [0104] Comparative Example 3
比較例 3においては、第 1電極を構成する A1合金は、 Ndを 0. 8wt%含有する A1 合金である。この A1合金の比抵抗は 2. 4 μ Ω cmである。この A1合金薄膜と、 ITO力 らなる透明導電膜を基板上に十字形に交差するように設け、ケルビンパターンによる 接触抵抗の計測を行った (図 4参照)。  In Comparative Example 3, the A1 alloy constituting the first electrode is an A1 alloy containing 0.8 wt% Nd. The specific resistance of this A1 alloy is 2.4 μΩcm. This A1 alloy thin film and a transparent conductive film made of ITO were provided on the substrate so as to cross each other in a cross shape, and the contact resistance was measured using a Kelvin pattern (see Fig. 4).
[0105] ITOの金属酸化物の比抵抗は、 220 μ Ω cmであった。そして図 4におけるケルビ ンパターンによる接触抵抗 (コンタクト抵抗値)の計測値は、 1Μ Ω以上であり、表示 装置に用いるには高 、値である。  [0105] The specific resistance of the metal oxide of ITO was 220 μΩcm. The measured value of contact resistance (contact resistance value) by the Kelvin pattern in Fig. 4 is 1Μ Ω or more, which is high for use in a display device.
[0106] 以上述べたように、本実施例で示した例によれば、透明導電膜 (第 2電極）との間に 生じる接触抵抗 (コンタクト抵抗)の値を小さな値にすることができる。  As described above, according to the example shown in the present embodiment, the value of the contact resistance (contact resistance) generated between the transparent conductive film (second electrode) can be reduced.
[0107] また本実施の形態で上述した製造方法で製造した TFTアレイ基板に対して、 230 。C X 30分の熱処理を行った後の同コンタクト抵抗値は約 650 Ω、さらに 300°C X 60 分の熱処理を行った後も同コンタクト抵抗値は約 900 Ωと、従来技術の場合の値で ある 1E8〜： ίΕ12 Ωに比べると極めて低ぐ優れた耐熱性を有していた。  Further, 230 for the TFT array substrate manufactured by the manufacturing method described above in the present embodiment. The contact resistance value after heat treatment for 30 minutes at CX is about 650 Ω, and even after heat treatment at 300 ° CX for 60 minutes, the contact resistance value is about 900 Ω. 1E8-: Excellent heat resistance, extremely low compared to ίΕ 12 Ω.
[0108] なお、表 1における成膜条件のパラメータ値は、装置によってそれぞ固有に最適化 されるものであって、この値に限定されるものではない。また、表 1や 2における組成 は、例示であり、この糸且成に限定されるものではない。  [0108] Note that the parameter values of the film formation conditions in Table 1 are uniquely optimized by the apparatus, and are not limited to these values. The compositions in Tables 1 and 2 are examples and are not limited to these yarns.
[0109] また。良好なコンタクト抵抗をうるためには、第 1電極の Ni、及び、 {Mo、 Nb、 W、 Z r}から選ばれた一種以上の金属の含有量は、それぞれ 0. 05〜5wt%にすることが 好ましい。 [0109] Also. To obtain good contact resistance, the first electrode Ni and {Mo, Nb, W, Z The content of one or more metals selected from r} is preferably 0.05 to 5 wt%.
[0110] これは、以下の事項を考慮した結果である。  [0110] This is a result of considering the following matters.
[0111] .まず、含有量が 0. 05wt%未満では、 IZOと A1界面のコンタクト抵抗を抑制するの が難しぐさらに、電池反応抑制効果力 、さくなるためである。  [0111] First, if the content is less than 0.05 wt%, it is difficult to suppress the contact resistance at the interface between IZO and A1, and the effect of suppressing the battery reaction becomes small.
[0112] ·次に、含有量が 5wt%超では、電極全体の抵抗値が高くなり、 A1を用いることによ る配線の低抵抗ィ匕のメリットを享受できないためである。  [0112] Next, if the content exceeds 5 wt%, the resistance value of the entire electrode becomes high, and the merit of low resistance of wiring by using A1 cannot be enjoyed.
[0113] なお、含有量は、 0. l〜2wt%とすることがより一層好ましい。  [0113] The content is more preferably 0.1 to 2 wt%.
[0114] 以上述べたように、 Ni単独を含有する A1合金を用いて第 1電極を製造した場合、 T MAH (テトラメチルアンモ -ゥムハイド口オキサイド）水溶液中で電池反応を起きし、 A1配線の金属自身が溶解し、断線する場合がある。これに対して、 Ni、及び、 {Mo、 Nb、 W、 Zr}から選ばれた一種以上の金属を含む A1合金を用いることにより電池反 応を抑えることができる。  [0114] As described above, when the first electrode is manufactured using an A1 alloy containing Ni alone, a battery reaction occurs in an aqueous solution of T MAH (tetramethylammonium hydroxide), and the A1 wiring The metal itself may melt and break. On the other hand, the battery reaction can be suppressed by using an Al alloy containing one or more metals selected from Ni and {Mo, Nb, W, Zr}.
[0115] なお、本実施の形態では、スパッタリング法を用いて第 1電極材料の Ni及び、 {Mo 、 Nb、 W、 Zr}から選ばれた一種以上の金属を含む A1合金を用いてゲート電極 2及 び端子部 22並びにソース Zドレイン電極 7を形成する際に、まず Arガス雰囲気中で スパッタリングをして成膜してもよ 、。  [0115] In the present embodiment, the gate electrode is formed by using a first electrode material Ni and an A1 alloy containing one or more metals selected from {Mo, Nb, W, Zr} using a sputtering method. 2 and the terminal part 22 and the source Z drain electrode 7 may be formed by sputtering in an Ar gas atmosphere first.
[0116] また、第 1電極の材料の母体となる A1としては、 Ni及び、 {Mo、 Nb、 W、 Zr}力 選 ばれた一種以上の金属を含む A1合金を用いている力 当該 A1合金に、さらに第三 元素を添加することも好まし 、。  [0116] Further, as A1 which is the base material of the material of the first electrode, Ni and {Mo, Nb, W, Zr} force A force using an A1 alloy containing one or more selected metals A1 alloy In addition, it is also preferable to add a third element.
[0117] 添加する第三元素は、ヒロック抑制や耐食性の向上といった点から Cuや Si、あるい は希土類元素が望ましい。その添加量は、 A1の電気的低抵抗というメリットを活かす ために、第 1電極の比抵抗が 10 Ω 'cmを超えない程度の添カ卩量に抑えるのが好 ましい。なお、第三元素の「三」とは、 Niを第一、 {Mo、 Nb、 W、 Zr}から選ばれた一 種以上の金属を第二、とみなし、それらに続く第三番目という意味である。ようするに その他の元素と 、う意味である。  [0117] The third element to be added is preferably Cu, Si, or a rare earth element in terms of suppressing hillocks and improving corrosion resistance. In order to take advantage of A1's low electrical resistance, it is preferable to keep the added amount so that the specific resistance of the first electrode does not exceed 10 Ω'cm. The third element “three” means that Ni is the first, the one or more metals selected from {Mo, Nb, W, Zr} are the second, and the third is the third. It is. It means "other elements".
[0118] ただし、本実施の形態のように、 Ni及び、 {Mo、 Nb、 W、 Zr}から選ばれた一種以 上の金属を用いた場合には、純 A1と比較して、ヒロックの発生防止効果、さらに耐食 性も向上する効果を有する。 [0118] However, as in this embodiment, when one or more metals selected from Ni and {Mo, Nb, W, Zr} are used, hillocks are compared with pure A1. Prevention of occurrence and corrosion resistance Has the effect of improving the properties.
[0119] このため、特に耐ヒロック性に優れる第三元素を添加しなくても極めて信頼性の高 V、TFTアレイを実現できる可能性が高 、ことも本実施の形態の大きな特長である。  [0119] For this reason, it is highly possible that a highly reliable V and TFT array can be realized without adding a third element that is particularly excellent in hillock resistance. This is a major feature of this embodiment.
[0120] なお、以上述べたきた実施の形態 1では、第 1電極材料として Ni及び、 {Mo、 Nb、 W、 Zr}から選ばれた一種の金属を含む Al合金、そして第 2電極材料として IZOを用 V、た場合にっ 、て説明してきたが、本発明に係る効果はこれらの電極材料に限られ ない。  [0120] In the first embodiment described above, the first electrode material is Ni and an Al alloy containing one kind of metal selected from {Mo, Nb, W, Zr}, and the second electrode material. Although the case of using IZO has been described above, the effects according to the present invention are not limited to these electrode materials.
[0121] たとえば、第 2の電極材料として In O、 SnO、 ZnOなどの材料中、いずれかの材  [0121] For example, any of the materials such as In 2 O, SnO, and ZnO as the second electrode material
2 3 2 2  2 3 2 2
料をベースとした他の種類の透明性酸ィ匕導電膜を用いた場合でも同様の効果を奏 する。  The same effect can be obtained even when other types of transparent acid-oxide conductive films based on the material are used.
[0122] なお、上記説明では、基板上に TFTを設け、その TFTのソース'ドレイン等として第 1電極を利用した。しかし、上記組成の第 1電極は TFTの端子として利用する以外の 用途に用いてもカゝまわない。他の電子部品の端子や配線として利用しても、上で説 明した作用 ·効果を奏することは言うまでもない。そのため、本件の発明としては、 TF Tを設けずに、第 1電極と、第 2電極 (透明電極)とが設けられた透明導電積層基板で あれば、本発明に含まれる。  In the above description, a TFT is provided on the substrate, and the first electrode is used as the source and drain of the TFT. However, the first electrode with the above composition can be used for purposes other than as a TFT terminal. Needless to say, even if it is used as a terminal or wiring for other electronic components, the effects and effects described above can be obtained. Therefore, the present invention includes any transparent conductive laminated substrate in which the first electrode and the second electrode (transparent electrode) are provided without providing TFTs.
[0123] ¾施の 2 (m^^ m )  [0123] ¾2 (m ^^ m)
上述した実施の形態 1で説明したいずれかの実施例を採用して形成した TFTァレ ィ基板を用い、これと対向電極やカラーフィルタなど有する対向基板を貼り合わせ、 さらに液晶材料を注入挾持して TFTアクティブマトリックス型の液晶表示装置 (TFT LCD装置)を製造する (実施の形態 2)。  Using a TFT array substrate formed by adopting any of the examples described in Embodiment 1 above, this is bonded to a counter substrate having a counter electrode, a color filter, etc., and a liquid crystal material is injected and held. A TFT active matrix type liquid crystal display device (TFT LCD device) is manufactured (Embodiment 2).
[0124] すなわち本実施の形態 2においては、 TFTアレイ基板の配線や電極に低抵抗配線 である Ni及び、 {Mo、 Nb、 W、 Zr}から選ばれた一種以上の金属を含む Al合金が用 いられており、また A1以外を主成分とする別の金属層を設けることなく IZO透明膜か らなる画素電極が上記 A1合金と直接コンタクトした構造を有している。したがって、高 開口率で高性能な液晶表示装置を得ることができる。 [0124] That is, in the second embodiment, the low-resistance wiring Ni and the Al alloy containing one or more metals selected from {Mo, Nb, W, Zr} are used for the wiring and electrodes of the TFT array substrate. It has a structure in which a pixel electrode made of an IZO transparent film is in direct contact with the A1 alloy without providing another metal layer mainly composed of components other than A1. Therefore, a high-performance liquid crystal display device with a high aperture ratio can be obtained.
[0125] 特に、従来装置に比べて、別の金属層を設ける必要がないので、本実施の形態 2 の液晶表示装置はその生産性が大きく向上している。さらに、別の金属層を設けると V、う製造工程が不要となるので、本実施の形態 2の液晶表示装置は従来技術に比べ て低コストで実施 (製造)することができると!/、う優れた特質を有する。 In particular, since it is not necessary to provide another metal layer as compared with the conventional device, the productivity of the liquid crystal display device of Embodiment 2 is greatly improved. If another metal layer is provided, V. Since the manufacturing process is not required, the liquid crystal display device of the second embodiment has excellent characteristics that it can be implemented (manufactured) at a lower cost than the prior art!
なお、本実施の形態 2では液晶材料を用いて液晶表示装置を構成する例を示した が、有機 EL材料を用いて有機 EL表示装置を構成することも好ま ヽ。  Note that although an example in which a liquid crystal display device is configured using a liquid crystal material is described in Embodiment 2, it is also preferable to configure an organic EL display device using an organic EL material.

Claims

請求の範囲 The scope of the claims
[1] 透明絶縁性基板上で薄膜トランジスタを製造する方法にぉ 、て、  [1] In a method for manufacturing a thin film transistor on a transparent insulating substrate,
前記透明絶縁性基板上に、 A1合金を用いて、第 1電極である前記薄膜トランジスタ のゲート、ソース及びドレインのうちの少なくとも一つを形成する工程、  Forming at least one of a gate, a source, and a drain of the thin film transistor as the first electrode on the transparent insulating substrate using an A1 alloy;
を含み、  Including
前記 A1合金は、  The A1 alloy is
Niと、  Ni,
{Mo、 Nb、 W、 Zr}から選択された一種以上の金属と、  One or more metals selected from {Mo, Nb, W, Zr},
を含む A1合金であることを特徴とする薄膜トランジスタの製法。  A method for producing a thin film transistor, characterized by being an A1 alloy containing
[2] 透明絶縁性基板上に薄膜トランジスタを形成し、薄膜トランジスタ基板を製造する 方法において、 [2] In a method of manufacturing a thin film transistor substrate by forming a thin film transistor on a transparent insulating substrate,
前記透明絶縁性基板上に、 A1合金を用いて、第 1電極である前記薄膜トランジスタ のゲート、ソース及びドレインのうちの少なくとも一つを形成する工程と、  Forming at least one of a gate, a source, and a drain of the thin film transistor, which is a first electrode, using an A1 alloy on the transparent insulating substrate;
前記第 1電極及び前記基板を覆って絶縁膜を成膜する工程と、  Forming an insulating film covering the first electrode and the substrate;
該絶縁膜にパターユングを施しコンタクトホールを形成する工程と、  Forming a contact hole by patterning the insulating film;
前記絶縁膜上に透明電極からなる第 2電極を形成して該第 2電極と第 1電極とを前 記コンタクトホールを介して電気的に直接接続する工程と、  Forming a second electrode made of a transparent electrode on the insulating film and electrically connecting the second electrode and the first electrode directly through the contact hole;
を少なくとも含み、  Including at least
前記 A1合金は、  The A1 alloy is
Niと、  Ni,
{Mo、 Nb、 W、 Zr}から選択された一種以上の金属と、  One or more metals selected from {Mo, Nb, W, Zr},
を含む A1合金であることを特徴とする薄膜トランジスタ基板の製法。  A method for producing a thin film transistor substrate, which is an A1 alloy containing
[3] 透明絶縁性基板上に設けられた薄膜トランジスタにおいて、 [3] In the thin film transistor provided on the transparent insulating substrate,
前記透明絶縁性基板上に形成された第 1電極である前記薄膜トランジスタのゲート 、ソース及びドレインの少なくとも一つと、  At least one of a gate, a source and a drain of the thin film transistor which is a first electrode formed on the transparent insulating substrate;
を備え、前記第 1電極は、  The first electrode comprises:
Niと、  Ni,
{Mo、 Nb、 W、 Zr}から選択された一種以上の金属と、 を含む Al合金力もなることを特徴とする薄膜トランジスタ。 One or more metals selected from {Mo, Nb, W, Zr}, A thin film transistor characterized in that it also has an Al alloying force.
[4] 透明絶縁性基板と、 [4] a transparent insulating substrate;
前記透明絶縁性基板上に形成された第 1電極であるゲート、ソース及びドレインの 少なくとも一つと、  At least one of a gate, a source and a drain as a first electrode formed on the transparent insulating substrate;
該第 1電極及び前記透明絶縁性基板を覆うように形成された絶縁膜であって、所 定のコンタクトホールが設けられて 、る絶縁膜と、  An insulating film formed to cover the first electrode and the transparent insulating substrate, the insulating film having a predetermined contact hole; and
該絶縁膜上に形成された透明電極である第 2電極と、  A second electrode which is a transparent electrode formed on the insulating film;
を少なくとも含み、  Including at least
前記第 1電極は、  The first electrode is
Niと、  Ni,
{Mo、 Nb、 W、 Zr}から選択された一種以上の金属と、  One or more metals selected from {Mo, Nb, W, Zr},
を含む A1合金からなり、  Made of A1 alloy containing,
前記第 2電極と前記第 1電極とが前記コンタクトホールを介して電気的に直接接続 されてなる薄膜トランジスタ基板。  A thin film transistor substrate in which the second electrode and the first electrode are electrically connected directly through the contact hole.
[5] 前記透明電極が酸化インジウム、酸化すず、酸化インジウムすず及び酸化亜鉛の いずれかからなる請求項 4記載の薄膜トランジスタ基板。 5. The thin film transistor substrate according to claim 4, wherein the transparent electrode is made of any one of indium oxide, tin oxide, indium tin oxide, and zinc oxide.
[6] 前記第 1電極を構成する A1合金中の、 Ni及び、 {Mo、 Nb、 W、 Zr}から選ばれた 一種以上の金属の含有比率が、 0. l〜5wt%であることを特徴とする請求項 3記載 の薄膜トランジスタ。 [6] The content ratio of Ni and one or more metals selected from {Mo, Nb, W, Zr} in the A1 alloy constituting the first electrode is 0.1 to 5 wt%. The thin film transistor according to claim 3.
[7] 前記第 1電極を構成する A1合金中の、 Ni及び、 {Mo、 Nb、 W、 Zr}から選ばれた 一種以上の金属の含有比率が、 0. l〜5wt%であることを特徴とする請求項 4記載 の薄膜トランジスタ基板。  [7] The content ratio of Ni and one or more metals selected from {Mo, Nb, W, Zr} in the A1 alloy constituting the first electrode is 0.1 to 5 wt%. The thin film transistor substrate according to claim 4, wherein the thin film transistor substrate is a thin film transistor substrate.
[8] 透明絶縁性基板と、 [8] a transparent insulating substrate;
前記透明絶縁性基板上に形成された第 1電極であるゲート、ソース及びドレインと、 該第 1電極及び前記透明絶縁性基板を覆って形成された絶縁膜であって、所定の コンタクトホールが設けられた絶縁膜と、  A gate, a source and a drain, which are first electrodes formed on the transparent insulating substrate, and an insulating film formed to cover the first electrode and the transparent insulating substrate, provided with a predetermined contact hole An insulating film formed,
該絶縁膜上に形成された透明電極からなる第 2電極と、  A second electrode made of a transparent electrode formed on the insulating film;
を少なくとも含み、 前記第 1電極が Including at least The first electrode
Niと、  Ni,
{Mo、 Nb、 W、 Zr}から選ばれた一種以上の金属と、  One or more metals selected from {Mo, Nb, W, Zr},
を含む A1合金からなり、  Made of A1 alloy containing,
前記第 2電極と前記第 1電極とが前記コンタクトホールを介して電気的に直接接続 されてなる TFTアレイ基板を少なくとも有する液晶表示装置。  A liquid crystal display device having at least a TFT array substrate in which the second electrode and the first electrode are electrically directly connected through the contact hole.
[9] 透明絶縁性基板と、 [9] a transparent insulating substrate;
前記透明絶縁性基板上に形成された第 1電極であるゲート、ソース及びドレインと、 該第 1電極及び前記透明絶縁性基板を覆って形成された絶縁膜であって、所定の コンタクトホールが設けられた絶縁膜と、  A gate, a source and a drain, which are first electrodes formed on the transparent insulating substrate, and an insulating film formed to cover the first electrode and the transparent insulating substrate, provided with a predetermined contact hole An insulating film formed,
該絶縁膜上に形成された透明電極からなる第 2電極と、  A second electrode made of a transparent electrode formed on the insulating film;
を少なくとも含み、  Including at least
前記第 1電極が  The first electrode
Niと、  Ni,
{Mo、 Nb、 W、 Zr}から選ばれた一種以上の金属と、  One or more metals selected from {Mo, Nb, W, Zr},
を含む A1合金からなり、  Made of A1 alloy containing,
前記第 2電極と前記第 1電極とが前記コンタクトホールを介して電気的に直接接続 されてなる TFTアレイ基板を少なくとも有する有機 EL表示装置。  An organic EL display device having at least a TFT array substrate in which the second electrode and the first electrode are electrically directly connected through the contact hole.
[10] 透明絶縁性基板と、 [10] a transparent insulating substrate;
前記透明絶縁性基板上に形成された第 1電極と、  A first electrode formed on the transparent insulating substrate;
前記透明絶縁性基板上に形成された透明電極からなる第 2電極と、  A second electrode comprising a transparent electrode formed on the transparent insulating substrate;
を具備し、  Comprising
前記第 1電極が、  The first electrode is
Niと、  Ni,
{Mo、 Nb、 W、 Zr}から選ばれた一種以上の金属と、  One or more metals selected from {Mo, Nb, W, Zr},
を含む A1合金からなり、  Made of A1 alloy containing,
前記第 1電極が、前記透明電極カゝらなる第 2電極と電気的に直接接続されてなる透 明導電積層基板。  A transparent conductive laminated substrate, wherein the first electrode is electrically connected directly to a second electrode such as the transparent electrode cover.
PCT/JP2005/019417 2005-01-26 2005-10-21 Thin film transistor and method for manufacture thereof, and thin film transistor substrate and method for manufacture thereof, and liquid crystal display device and organic el display device using said thin film transistor, and transparent electroconductive laminated substrate WO2006080116A1 (en)

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