WO2006056153A1 - Composant a semi-conducteur pourvu d'une puce a semi-conducteur et de contacts externes et procede de fabrication dudit composant - Google Patents

Composant a semi-conducteur pourvu d'une puce a semi-conducteur et de contacts externes et procede de fabrication dudit composant Download PDF

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Publication number
WO2006056153A1
WO2006056153A1 PCT/DE2005/001922 DE2005001922W WO2006056153A1 WO 2006056153 A1 WO2006056153 A1 WO 2006056153A1 DE 2005001922 W DE2005001922 W DE 2005001922W WO 2006056153 A1 WO2006056153 A1 WO 2006056153A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor
chip
flip
semiconductor component
contacts
Prior art date
Application number
PCT/DE2005/001922
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German (de)
English (en)
Inventor
Michael Bauer
Original Assignee
Infineon Technologies Ag
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Filing date
Publication date
Application filed by Infineon Technologies Ag filed Critical Infineon Technologies Ag
Publication of WO2006056153A1 publication Critical patent/WO2006056153A1/fr

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49894—Materials of the insulating layers or coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10954—Other details of electrical connections
    • H05K2201/10977—Encapsulated connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01—Tools for processing; Objects used during processing
    • H05K2203/0104—Tools for processing; Objects used during processing for patterning or coating
    • H05K2203/013—Inkjet printing, e.g. for printing insulating material or resist
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05—Patterning and lithography; Masks; Details of resist
    • H05K2203/0548—Masks
    • H05K2203/0557—Non-printed masks
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/13—Moulding and encapsulation; Deposition techniques; Protective layers
    • H05K2203/1333—Deposition techniques, e.g. coating
    • H05K2203/1366—Spraying coating
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the invention relates to a semiconductor device with a semiconductor chip on a wiring substrate and with external contacts. These external contacts are arranged on an underside of the semiconductor component and allow the semiconductor component to be applied by surface mounting to a higher-level circuit carrier. For this purpose, the external contacts are arranged on the underside of the semiconductor components, as is the case with flip-chip contacts and / or with BGA packages.
  • the gap between the semiconductor device with BGA package or with flip chip structure and the übergeord ⁇ Neten circuit substrate is filled by an underfill material after Ober ⁇ surface mounting.
  • a slow dispensing process is used.
  • a correspondingly large area is to be reserved on the higher-order circuit carrier so that corresponding tools can introduce the underfill material into the intermediate space between the semiconductor component and the higher-level circuit carrier.
  • This space requirement as well as the slow dispensing process adversely affect the production throughput.
  • this filling is limited to underfilling materials which are able, with the aid of the capillary action, to fill the gap between the underside of the body Fill semiconductor device and the parent circuit carrier.
  • the object of the invention is to specify a semiconductor component, with which it is possible to perform a surface mounting, without the intermediate spaces zwi ⁇ tween the external contacts of the parent circuit board are then filled.
  • a semiconductor device is provided with a semiconductor chip on a wiring substrate, wherein the wiring substrate has a wiring structure on its top side and / or on its bottom side. At least one semiconductor chip is arranged on the upper side of the wiring substrate and is electrically connected to the wiring structure via connecting elements.
  • the wiring substrate has an underside, on which outer contact surfaces are arranged, which are electrically connected to the wiring structure and / or the connecting elements via through-contacts through the wiring substrate.
  • the outer contact surfaces have external contacts which are surrounded by an insulating thermal compensation layer which has an underfill material, external contact peaks protruding out of the compensation layer.
  • Another aspect of the invention provides a semiconductor component with a semiconductor chip, the semiconductor chip having flip-chip contacts as external contacts of the semiconductor component.
  • the semiconductor device can be mounted on a higher-level circuit board.
  • the flip-chip contacts are surrounded by an insulating thermal compensation layer on the active upper side of the semiconductor chip, wherein the compensation layer has an underfill material.
  • flip-chip contact tips protrude from the compensating layer as external contact tips from the compensating layer.
  • Such an inventive component has the advantage that a surface mounting is cheaper and faster Kunststoff ⁇ feasible.
  • the application of the compensation layer to the underside of the wiring substrate or to the upper side of the semiconductor chip with flip chip contacts between the external contacts or the flip chip contacts arranged there also enables a fast process flow, especially since these surfaces are fully coated for surface coating prior to surface mounting Compensation mass are available.
  • another advantage is decisive that the application height can be adapted to the outer contact heights or to the heights of the flip-chip contacts in an arbitrary manner, so that an individual application height is required without changing the corresponding technology. Rather, only appropriate process parameters for the application of the compensation layer are adapted to the outer contact heights.
  • the outer contact tips or the flip-chip contact tips are distributed uniformly on the lower side of the semiconductor component.
  • this uniform arrangement corresponds to the BGA package technology or flip-chip technology
  • the external contacts for the surface mounting of the semiconductor component according to the invention are not completely available, but merely a spherical segment which protrudes from the compensation layer. Nevertheless, this ball section of an external contact or a flip-chip contact is completely sufficient to achieve a reliable surface mounting on the higher-level circuit carrier.
  • the outer contact tips or the flip-chip contact tips can preferably have a surface grid that can be surface-mounted. This external grid is matched in its arrangement ent ⁇ speaking contact pads on the parent circuit carrier.
  • the semiconductor device according to the invention can be brought without difficulty to the parent circuit board.
  • the outer contact tips have a height h at which they come out of the compensating layer. protrude. This height h is less than or equal to the thickness d of the compensation layer. If the thickness of the compensation layer is equal to the height h of the outer contact tips, the outer contacts of the semiconductor component are surrounded by the compensation layer only up to half their total height H.
  • the outer contact tips or the flip-chip contact tips form a spherical segment shape with a spherical segment height h k of only a few. This slight elevation relative to the cover layer is sufficient to ensure reliable surface mounting on a higher-level circuit carrier and at the same time to fill up the intermediate spaces between circuit carrier and semiconductor component with the aid of the compensating layer.
  • the thickness d of the compensation layer is preferably between 35 ⁇ m ⁇ d ⁇ 500 ⁇ m. This order of magnitude of the layer thickness of the compensation layer thus extends from flip-chip technology to external contacts in BGA technology.
  • the connecting elements arranged between the semiconductor chip and the wiring substrate can in turn also have flip-chip contacts.
  • the active upper side of the semiconductor chip is arranged opposite the upper side of the wiring substrate, wherein the wiring substrate has a corresponding arrangement of contact connection surfaces which corresponds to the arrangement of the flip-chip contacts of the semiconductor chip.
  • through contacts through the wiring substrate can be arranged such that they also correspond to the arrangement of the flip-chip contacts of the semiconductor chip, in which case the wiring structure of the wiring substrate is arranged on the underside.
  • the connecting elements may also have bonding wires.
  • the active upper side of the semiconductor chip is remote from the upper side of the wiring substrate and has on its upper side contact surfaces, which are electrically connected via bonding wires to contact connection surfaces of the wiring substrate.
  • the wiring structure is arranged on the upper side of the wiring substrate and is connected to corresponding through-contacts which, in turn, are electrically connected to external contact surfaces.
  • a solder-stop resist layer is arranged between the underside of the wiring substrate and the compensation layer.
  • a solder resist coating layer is used in cases where the wiring structure of the wiring substrate is disposed on the lower side or on the same side as the outer contact surfaces.
  • the solder resist lacquer layer ensures that the material of the external contacts only wets the external contact surfaces and the wiring structure remains protected from the external contact material.
  • Such a solder resist coating layer may also improve the adhesion between the leveling layer and the wiring substrate.
  • the underfill material of the compensating layer may have a filler content of 30% by volume to 95% by volume, preferably of 70% by volume to 85% by weight of the remainder of the plastic.
  • Filler content can thus be arbitrarily increased, especially since a low viscosity of the molten underfill material, as occurs at low filler content, is not required for this Aus ⁇ same layer.
  • the underfill material has ceramic particles as filler in order to ensure thermal equilibration.
  • a method for producing a semiconductor device at a plurality of semiconductor device positions has the following procedural steps. First, a benefit is produced with the following process steps. First, a wiring substrate having a plurality of semiconductor device positions, which have wiring substrates with wiring patterns, through-contacts and external contact areas on the underside of the wiring substrate, is manufactured. Subsequently, the wiring carrier with semiconductor chips is produced in the semiconductor component positions by connecting connecting elements to contact pads of the wiring substrate. Finally, the semiconductor chips and the connecting elements are embedded in a plastic housing composition while forming a coplanar upper side on the wiring carrier.
  • This method has the advantage that a cheap and fast process flow is possible. Furthermore, this method is inline-capable. Furthermore, the method has the advantage that a surface mount customizable application level of the leveling layer is possible without changing the devices for application. Only corresponding process parameters have to be adapted in order to realize individual application heights for individual compensation layer thicknesses. Fer ⁇ ner is when using suitable self-curing or curable by UV radiation curing materials as Unter Reichllmaterial a leveling layer possible, which can renounce further thermally stressing process steps, such as curing and Trock ⁇ NEN on a parent circuit board.
  • the compensation layer for a plurality of semiconductor components can be applied in flip-chip technology. Only the separating tools when separating the semiconductor wafer and when separating a benefit into individual Halbleiterbau ⁇ parts differ.
  • the individual semiconductor components in their semiconductor component positions on the use or on the semiconductor wafer are tested for their functionality via the external contact tips even before the semiconductor wafer is terminated with flip-chip contacts or the external contacts. Only after marking the semiconductor component positions which did not pass the functional test, the wafer or the groove is then separated, and only the semiconductor components which are functional are processed further.
  • the compensation layer is applied by means of dispensing, with the outer contact tips or the flip-chip contact tips being omitted. This has the advantage that a Nach ⁇ treatment is not required.
  • the application of the compensating layer takes place by means of spraying through a protective mask. In this case, the regions are protected by the protective mask from applying the compensating layer, which have external contacts or flip-chip contacts. All other areas are covered with a leveling layer.
  • the compensating layer can be effected by means of a jet printing method with the exception of the outer contact tips or flip-chip contact tips.
  • the jet printing method corresponds to the ink jet printing method and can be applied to the underside of a wiring substrate or to the active upper side by similar jet print heads as in inkjet printing between the external contacts or the flip chip contacts. side of a semiconductor chip, which is already covered with flip-chip contacts are applied. Since the outer contact tips are left completely free in this method, the semiconductor device can be used directly after the jet printing process with a separation of the benefit or the semiconductor wafer for surface mounting.
  • a further preferred possibility of applying the Aus ⁇ gleichs Mrs is to perform a stencil printing process while protecting the outer contact tips.
  • the stencil printing method differs from the above-mentioned spraying method by a protective mask in that the stencil printing method distributes a mass of underfilling material in the molten state with the aid of a doctor blade on the upper side of a stencil, wherein the surfaces which do not have any external contacts or Wear flipchip contacts, covered with the leveling layer.
  • a dipping method Another way to apply the leveling layer is to use a dipping method.
  • the outer contact tips or flip-chip contact tips are also covered by the underfill material and are freed from the underfill material in a subsequent process step.
  • This process step can be carried out with a laser ablation technique, with a friction or grinding technique or with sputtering or etching techniques.
  • Figure 1 shows a schematic cross section through a
  • FIG. 2 shows a schematic diagram of a jet printing method for applying an insulating thermal compensating layer to an underside of a wiring substrate
  • FIG. 3 shows a schematic diagram of a spray method for applying an insulating thermal compensation layer to an underside of a wiring substrate.
  • FIG. 1 shows a schematic cross section through a semiconductor component 1 of an embodiment of the invention.
  • This semiconductor device 1 is constructed using BGA technology (ball grid array).
  • BGA technology ball grid array
  • the compensation layer 11 of underfill material 12 according to the invention can also be applied to the undersides of semiconductor components by flip-chip technology.
  • Such semiconductor components 1 have external contacts 10 on their underside 14, the arrangement of the external contacts 10 corresponding to the arrangements of connection surfaces on the superordinated circuit carrier.
  • the compensating layer 11 according to the invention between the external contacts 10 of the surface-mountable semiconductor components 1 it is possible to provide underfilling of the gap between a surface-mountable semiconductor component 1 and a superimposed semiconductor device 1. ordered circuit carrier completely dispense.
  • the exemplary semiconductor component 1 shown in FIG. 1 has a semiconductor chip 2 on a wiring substrate 3. On its underside 7, the wiring substrate 3 has a wiring structure 5, via which through contacts 9 are connected to external contact surfaces 8 on the underside 7 of the wiring substrate 3.
  • the semiconductor chip 2 in turn has contact surfaces 21, which are connected via connecting elements 6, which are formed in this embodiment of the invention as flip-chip contacts 16, with the through-contacts 9 via corresponding pads 17 on the upper side 4 of the wiring substrate 3.
  • the semiconductor chip 2 and the connecting elements 6 to the wiring substrate 3 are embedded in a common Kunststoffgeffeu ⁇ semasse 18 having a planar or planar upper side 19 of the semiconductor device 1.
  • this upper side 19 can also be formed directly from the rear side 22 of the semiconductor chip 2.
  • the wiring structure 5 forms outer contact surfaces 8, on which outer contacts 10 are arranged. These external contacts 10 protrude with external contact tips 13 from the compensating layer 11, which forms the underside 14 of the semiconductor component 1.
  • the balancing tips 13 have a spherical segment shape 15 with a spherical segment height h k of a few micrometers. However, this spherical segment height h k may be greater than or equal to the thickness d of the compensating layer 11.
  • the thickness d of the compensation layer 11 is between 35 and 500 microns.
  • the compensation layer 11 surrounds the external contacts 10, which have a height H, so that the external contacts 10 are supported so far be that breaks between the external contacts 10 and basedWalletflachen 8 are avoided.
  • the leveling layer 11 may comprise an underfill material 12 of a UV-curable plastic.
  • the compensating layer 11 can be cured after its application to the underside 7 of the wiring substrate 3, which is not possible with conventional underfilling techniques, especially since these Underfill materials are applied only after Oberflä ⁇ chenmontage the semiconductor devices and thus represent the semiconductor devices themselves a mask against a curing exposure or irradiation.
  • FIG. 2 shows a schematic diagram of a jet printing method for applying an insulating thermal compensation layer 11 to a lower side 7 of a wiring substrate 3.
  • Components having the same functions as in FIG. 1 are identified by the same reference symbols and are not discussed separately.
  • a jet pressure nozzle 23 which operates like an inkjet printer, is directed onto the underside 7 of the wiring substrate with the jet pressure nozzle 23, thereby filling the intermediate spaces 24 between the external contacts 10 with the underfill material 12 and leaves the tips of the outer contacts 10 free of Unter Schollmaterial 12th
  • FIG. 3 shows a schematic diagram of an alternative process in the form of a spraying process for applying an insulating thermal compensating layer 11 to a substrate.
  • a spray nozzle 25 is directed to the bottom 7 of the wiring substrate 3, wherein the wiring substrate 3 has the external contacts 8 on its bottom side 7.
  • This spray nozzle 25 applies the underfill material 12 in a planar manner and a protective mask 20 protects the positions of the outer contacts 10 from coating their outer contact tips 13 through the spray nozzle 25.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

Composant (1) à semi-conducteur pourvu d'une puce (2) à semi-conducteur et de contacts externes (10) et procédé de fabrication dudit composant. Sur la face inférieure (7) du composant (1) à semi-conducteur, entre les contacts externes (10), est placée une couche de compensation (11) qui supporte les contacts externes (10) et remplace l'apport d'une matière de remplissage inférieure lors du montage de surface.
PCT/DE2005/001922 2004-11-23 2005-10-26 Composant a semi-conducteur pourvu d'une puce a semi-conducteur et de contacts externes et procede de fabrication dudit composant WO2006056153A1 (fr)

Applications Claiming Priority (2)

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