Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04J—MULTIPLEX COMMUNICATION
  • H04J3/00—Time-division multiplex systems
  • H04J3/02—Details
  • H04J3/06—Synchronising arrangements
  • H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
  • H04J3/0632—Synchronisation of packets and cells, e.g. transmission of voice via a packet network, circuit emulation service [CES]
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L1/00—Arrangements for detecting or preventing errors in the information received
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L1/00—Arrangements for detecting or preventing errors in the information received
  • H04L1/20—Arrangements for detecting or preventing errors in the information received using signal quality detector
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L7/00—Arrangements for synchronising receiver with transmitter
  • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
  • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04R—LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; ELECTRIC HEARING AIDS; PUBLIC ADDRESS SYSTEMS
  • H04R1/00—Details of transducers, loudspeakers or microphones
  • H04R1/10—Earpieces; Attachments therefor ; Earphones; Monophonic headphones
  • H04R1/1041—Mechanical or electronic switches, or control elements
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04R—LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; ELECTRIC HEARING AIDS; PUBLIC ADDRESS SYSTEMS
  • H04R1/00—Details of transducers, loudspeakers or microphones
  • H04R1/10—Earpieces; Attachments therefor ; Earphones; Monophonic headphones
  • H04R1/1008—Earpieces of the supra-aural or circum-aural type
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04R—LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; ELECTRIC HEARING AIDS; PUBLIC ADDRESS SYSTEMS
  • H04R2420/00—Details of connection covered by H04R, not provided for in its groups
  • H04R2420/07—Applications of wireless loudspeakers or wireless microphones

Definitions

• This invention relates to apparatus and methods for transmission and reception of digital data communication signals. More particularly, this invention relates to the synchronization of received digital data communication signals. Description of Related Art
• a playback system that uses a standard sigma delta audio digital to analog converter has to maintain the audio clocks that demand the audio pulse code modulation samples periodically to sustain a smooth playback.
• the transmitter's audio clock is different from the receiver's audio clock and thus the rate of production of the digital data versus the consumption of the digital data becomes a problem.
• the transmitter's clock may be oversupplying the digital data at a faster rate than the receiver can consume the digital or alternately, the transmitter's clock may be undersupplying the digital data at a slower rate and thus starving the receiver of digital data symbols.
• An example of a digital data communications system is a wireless infrared digital audio headphone, as shown in Fig. 1.
• the transmitter 10 acquires digitally encoded audio signals, which are then formatted with synchronization, control, and error signals.
• the formatted encoded data modulates a transmit signal employing a pulse positioned modulation.
• the modulated signal is used to control the radiation of a light signal from the light emitting diode (LED) 15.
• the light signal 20 is broadcast to the headphones 25.
• the headphones 25 have a photodetector 40.
• the photodetector 40 are generally placed on the outer sides of the headphones 25 to receive the light signal 20.
• the detected electrical signals of the photodetector 40 are transferred to the receiver 30, which demodulates and reformats the encoded audio signals for transfer to the speakers 35a and 35b.
• the speakers 35a and 35b are placed in close proximity to the ears of the person 45 wearing the headphones 25.
• Wireless transmission of digital data is often accomplished by sending serially formatted frames of the digital data.
• the frame as shown in section 5.4.2 has a Preamble Field (PA), Start Flag Field (FA), a Data Field (DD), and a Stop Flag Field (STO).
• PA Preamble Field
• FA Start Flag Field
• DD Data Field
• STO Stop Flag Field
• the receiver uses the Preamble Field to synchronize the clocking system of the receiver to the in coming message.
• a phase lock loop oscillator is used to synchronize the receiver to the Preamble Field.
• the receiver begins to detect the Start Flag Field to establish symbol synchronization. If the Start Flag Field is correct, the receiver then begins to interpret the data symbols of the Data Field and will continue to interpret the data symbols until the Stop Flag Field is received.
• second frame AD1 is sampled and converted to symbols of the digital data.
• the frame of the interleaved and encoded data is
• a transmission signal RF TO which is broadcast from the transmitter 10 by the LED 15 through the atmosphere to the photodiode 40 of
• the receiver recovers the transmitted signal and restores the frames of the symbols of received data RF RO.
• the second frame of data is interleaved and encoded with the error correction codes ECCE1 and the
• the received data RF RO is deinterleaved and has error correction and detection applied to the received to recover the frames of symbols of the original digital data ECCDO.
• the interleaved and encoded frame of data ECCE1 modulates the transmission signal RF T1 , which is transmitted.
• the transmitted signal RF T1 is received and the frames RF R1 recovered.
• the third frames of symbols are interleaved and encoded for error correction and detection to form the frames ECCE2 and a fourth sampling of the analog signal is converted to the frames of symbols ADO of a second grouping of frames.
• the frames of symbols of the original data ECCDO are converted to an analog signal ADO for application to the
• the "Serial Infrared Physical Layer Specification” details the encoding of the data in section 5.4.1.
• the digital data is transmitted using a four-pulse position modulation.
• a dual-bit data structure is encoded by positioning a pulse within a symbol.
• the symbol is divided into four time positions of the time duration of the symbol with each position representing the coding of the dual-bit data structure.
• Stop Flag Field is each unique codes that have symbol streams that cannot be confused with the four-pulse position modulation of the dual-bit data structure.
• the synchronization of the receiver employing a phase lock loop is subject to jitter in pulling the frequency of the local receiver to match the frequency of the transmitted data. Further any drift in the local oscillator causes the local oscillator to have to be re-locked periodically. Without periodic relocking of the local oscillator to the signal, there can be errors with the data reception. Further, multipath reception problems cause the received timing data to fluctuate with the differences in the delay of the paths.
• U.S. Patent 5,457,718 teaches a compact phase recovery scheme using digital circuits.
• the phase recovery circuit is essentially a fully integrated digital filter, which interacts with a phase comparator to provide a phase lock loop and data retiming function.
• the digital filter provides a data retiming function by sending the output of the four bit counter to a digital delay element interposed between the data signal input and the input to the phase comparator.
• the digital filter determines from a multitude of binary phase decisions the polarity of phase correction required, and feeds this back to the delay element.
• the delay element then adjusts the phase of the incoming data with respect to the phase of the local clock.
• U.S. Patent 5,887,040 provides a high speed digital data retiming apparatus, in which, binary data can be retimed in a stable manner, even if static skew due to a delay difference between the retiming clock pulse and the data is present and a dynamic skew due to the characteristic variation according to time and temperature.
• the external clock pulses are delayed by means of a delaying section, so that system performance is independent of the pattern of data. If the data phases show a continuous difference (wandering) for more than a certain period of time, an elastic buffer absorbs the wandering, and therefore, no data is lost.
• U.S. Patent 5,886,552 (Chai, et al.) describes a data retiming circuit, which is capable of more effectively retiming an externally inputted data by using a plurality of clocks from a voltage controlled oscillator of a phase- locked loop.
• U.S. Patent 5,608,357 (Ta, et al.) teaches a data retiming system for retiming incoming data and eliminating jitter.
• the data retiming system includes a local clock; a phase aligner for receiving the incoming data and producing a recovered clock from the incoming data, and then producing retimed incoming data by retiming the incoming data with the recovered clock; and a buffer memory for removing jitter from the retimed incoming data by storing the retimed incoming data to the buffer memory in accordance with the recovered clock and reading the stored data from the buffer memory in accordance with the local clock.
• the data retiming system provides reliable operation even at very high data rates.
• An object of this invention is to provide a communication system that synchronizes data received and recovered from a transmission medium to the data transmitted to the transmission medium.
• Another object of this invention is provide a communication system in which the data received and recovered from a transmission medium has neither under-run or overrun of the data due to differences in the transmission clocking and the reception clocking.
• a data communication system has a transmitter and a receiver.
• the transmitter includes a frame formatter and a transmission device.
• the frame formatter encodes digital data into series of symbols.
• the encoding of the digital data includes interleaving the digital data and providing error detection and correction codes with the digital data.
• the transmission device is in communication with the frame formatter to receive the series of symbols and transmits a modulated signal composed of the series of symbols.
• the receiver is in communication with the transmitter for acquiring the modulated signal, restoring the modulated signal, reconstructing the symbols of the digital data from the modulated signal and synchronizing the digital data to a first reference signal.
• the receiver has an amplification and conditioning circuit connected to receive, restore, and sample the modulated signal.
• the modulated signal is sampled at a multiple of the first reference signal such that transitions representing boundaries between bits of the digital data within the modulated signal are detected and the digital data is reconstructed and synchronized to the second reference signal.
• the amplification and conditioning circuit has reconstructed and synchronized the digital data, the digital data is transferred to a buffer data retention circuit where the reconstructed digital data is retained.
• the buffer retention circuit has at least one buffer circuit for retaining groupings of the symbols.
• the digital data is transferred from the buffer retention circuit to a data correction and deinterleaving circuit for reorganizing the digital data to an original sequence of symbols.
• the data correction and deinterleaving circuit further corrects any error created in the transmission of the modulated signal.
• the reorganized and corrected digital data is replaced within the buffer retention circuit.
• a boundary marker signal detection circuit is in communication with the amplification and conditioning circuit to receive the reconstructed digital data. From the reconstructed digital data, the boundary marker signal detection circuit extracts a marker signal indicating a boundary of symbols of the digital data. The marker signal provides an indication of the timing of the digital data as broadcasted by the transmitter.
• the receiver has a jitter management unit to synchronize the digital data to the first reference signal.
• the jitter management unit has a first-in- first-out (FIFO) data retention device, which receives the reconstructed digital data at the rate of the first reference signal from the buffer retention circuit and transmits the synchronized digital data for further processing at a rate approximating that of a second reference signal, which approximates the timing of the digital data within the transmitter.
• FIFO first-in- first-out
• the jitter management unit has a variable reference signal generator connected to the FIFO data retention device to provide the second reference signal for synchronization of the digital data.
• the buffer data retention circuit transfers the digital data to the FIFO data retention device until the FIFO data retention device contains a first amount of digital data ( approximately one half of the capacity of the FIFO data retention device), where upon the FIFO data retention device begins to transmit the digital data. Further, the buffer data retention circuit must transfer all symbols of the digital data present between two marker signals to prevent overrun of the digital data. To accomplish this full transfer of all symbols between two markers, the buffer data retention device transfers the first and second symbols of a frame between two markers essentially simultaneously. This prevents any overrun of the data as transferred to the FIFO data retention circuit.
• the jitter management unit has a generator control circuit connected to receive a marker signal extracted from the modulated signal by the boundary marker signal detection circuit.
• the generator control circuit is further in communication with the FIFO data retention device to receive an occupation signal indicating an amount of digital data present within the FIFO data retention device. From the marker signal and the occupation signal, the generator control circuit creates a generator control signal to cause an adjustment of the variable reference signal generator such that the second reference signal synchronizes the digital data to a timing at which the digital data is transmitted.
• the generator control circuit causes the generator control signal to indicate that there is to be no adjustment by the variable reference signal generator to the second reference signal, if the occupation signal indicates that the FIFO data retention device contains a second amount (approximately half the capacity of the FIFO data retention device) of the digital data. However, if the occupation signal indicates that the FIFO data retention device contains less than the second amount of the digital data, generator control circuit sets the generator control signals to cause adjustment by the variable reference signal generator to the second reference signal to increase the contents of the FIFO data retention device until it contains the second amount of digital data.
• the generator control circuit causes the generator control signal to indicate that the variable reference signal generator should cause adjustment to the second reference signal to decrease the contents of the FIFO data retention device until it contains the second amount of digital data.
• FIG. 1 is a diagram of a communications system of the prior art.
• Fig. 2 is a timing diagram of ideal transmission of digital data through a communications system of the prior art.
• FIG. 3 is a diagram of the communication system of this invention.
• Fig. 4 is a block diagram of the transmitter of the communication system of this invention.
• Fig. 5 is a diagram of the frame structure of the digital data of the communication system of this invention.
• Fig. 6 is a block diagram of the receiver of the communication system of this invention.
• Figs. 7a - 7d are flow diagrams describing the method for synchronizing data received by a receiver to prevent overrun or under-run of the digital data to during transmission of the digital data to the receiver of this invention.
• Fig. 8a is a timing diagram illustrating the synchronization of the digital data in a communication system of this invention.
• Fig. 8b is a timing diagram illustrating the relationship of the marker signal with synchronization signal and the start signal of the communication system of this invention.
• Fig. 9 is a timing diagram illustrating the transfer of data to the FIFO data retention device of this invention.
• the communication system of this invention is applicable either to wired or wireless digital audio communication and provides isochronous timing of the digital data for high quality audio playback. Both the transmitter and receiver will use their own local clocks for the communication.
• the receiver contains a jitter management unit that consists a first-in- first-out (FIFO) data retention device or buffer, a standard VCXO (Voltage controlled crystal oscillator) and a VCXO control logic unit. This jitter management unit tracks the transmitter's audio clock by making use of the FIFO buffer status only and is simple to implement or integrate into any digital audio systems that separates the playback from the source.
• FIFO first-in- first-out
• VCXO Voltage controlled crystal oscillator
• the FIFO buffer is analogous to a container and the producer
• receiver pours in digital data symbols of the analog audio signal at a rate that is equivalent to the receiver's clock period.
• This container is empty at the beginning and the consumer (player) will not start until the digital data symbols have reached a threshold level. Once the digital data symbols reach the threshold level, the consumer begins to consume the digital data symbols. If theoretically the producer and consumer operate at the same rate, then the level of the FIFO buffer or container will be at the threshold level always because what gets in also gets out at the same rate.
• the level of the container or FIFO buffer increases. As this increase in the level of the FIFO buffer continues, the FIFO buffer will overflow and an overrun of the digital data symbols will cause a loss in the digital data. Alternately, if the producer happens to be slower than the consumer and the digital data symbols are transferred to the FIFO buffer more slowly and the consumer is still extracting the digital data at a faster rate, the level of the container or FIFO buffer decreases.
• the FIFO buffer will empty and an under-run of the digital data symbols will cause the playback to stop until the producer provides more of the digital data symbols, thus causing distortion during the playback of the isochronous digital data symbols.
• the consumer can adjust the rate at which the digital data symbols are removed from the FIFO buffer. If a central region between an upper limit and a lower limit are designated a "comfort zone,” the consumer does not change the rate at which the digital samples are removed from the FIFO buffer. However, when the level of the amount of data present within the FIFO buffer exceeds either the upper limit or the lower limit, the consumer must now either increase or decrease the rate of consumption of the digital data symbols from the FIFO buffer.
• the FIFO buffer will exceed the upper limit and the amount of digital data symbols in the FIFO buffer are no longer in the "comfort zone".
• the consumer will increase the consumption rate to match the rate of transfer of the producer and attempts to have the amount of digital data symbols present in the FIFO buffer approach the comfort zone again.
• the consumer increments the rate of transfer from the FIFO buffer while monitoring the level of the amount of digital data present in the FIFO buffer at periodic intervals.
• the consumer increments the rate of consumption of the digital data in steps to a stage that the amount of data present in the FIFO buffer starts to fall, then the consumer stops incrementing the rate of transfer and waits for the level of the amount of digital data symbols in the FIFO buffer to enter the comfort zone. If however, the producer is transferring the digital data at a rate that is much larger than the consumer can anticipate, the FIFO buffer may enter into a hard upper region. Once the amount of digital data symbols present in the FIFO buffer has entered into the hard upper region, the consumer must then increment the transfer rate much faster. This acceleration and deceleration by the consumer of the transfer rate will leads to the consumer's speed being close to the producer's speed.
• the consumption rate of the digital data symbols from the FIFO buffer by the consumer will not be exactly the same as the transfer rate of the producer but the consumer will ultimately have a consumption rate that is in the soft region or comfort zone and there will be little acceleration or deceleration of the consumption rate.
• An analog signal such as human speech or music is sampled and converted into digital data symbols 50 representing the samples of the analog signal.
• the digital data symbols 50 are transferred to the transmitter 100, which serializes and formats the digital data symbols and provides error detection and correction codes.
• the encoded digital data symbols are then used to modulate a transmission signal such as a fundamental frequency for an RF wireless transmission or a light signal for an infrared transmission.
• the modulated signal 150 is transferred to the receiver 200, which recovers, restores, deserializes, and synchronizes the digital data symbols.
• the receiver 200 further converts the digital data symbols to the analog signal 250 for transfer to the speakers of the headphones 260.
• the transmitter 100 of this invention is shown in Fig. 4.
• the digital data symbols 50 are transferred to the data input register 105.
• the digital data register 105 synchronizes the digital data symbols with the data clock provided by the transmitter clock generator 135.
• the digital data symbols are transferred from the data input register 105 to the error detection and correction coding circuit 110 where the digital data symbols are encoded with error detection and correction codes to provide a level of recovery for potential corruption of the transmitted digital data symbols.
• the digital data symbols with their attendant error correction codes are then transferred to the interleave circuit 115.
• the transmission of digital data symbols often have corruption of the transmission that occurs such that temporally adjacent digital data symbols maybe corrupted.
• the digital data symbols are interleaved such that digital data symbols of the same error correction code are no longer temporally adjacent, thus permitting correction of any of the corruption at the receiver of the digital data symbols.
• the interleaved digital data symbols with the error correction codes are then transferred to the frame formatting circuit 120.
• the frame formatting circuit serializes the interleaved digital data symbols and then generates the necessary synchronization field and a start pattern that are appended to the serialized interleaved digital data symbols with the attendant error correction codes as shown in Fig. 5.
• Each frame 160a, .uß., 16On begins with a synchronization pattern 163.
• the synchronization pattern 163 is a unique series of timing pulses that in a receiver of the prior art would be used to synchronize a phase locked loop.
• a start sequence 165 indicating that the pattern of signals that follows represents the packets 167a, ..., 167n digital data symbols.
• the start sequence 165 provides a reference timing referenced to the transmitter clock 135 of Fig. 4.
• the error correction coding 169 is used to repair and recover any of the digital data symbols corrupted in the transmission.
• the formatted digital data symbols are transferred from the frame formatter 120 to the transmit signal modulator 125.
• the modulation scheme is usually a four-pulse position modulation scheme, but any appropriate modulation scheme is in keeping with the intention of this invention.
• the transmitter clock generator 135 provides that necessary timing to create the four-pulse position modulation.
• the modulated transmit signal is transferred to the transmit driver 130 which sends the modulated signal 150 to a transducer such as an LED which conveys the modulated signal to a transmission medium such as the atmosphere or a cabling such as a fiberoptic cable.
• a transducer such as an LED which conveys the modulated signal to a transmission medium such as the atmosphere or a cabling such as a fiberoptic cable.
• the modulated signal impinges upon a transducer 195.
• the transducer 195 In the case of an infrared system the transducer 195 would be a PIN diode receiving a light signal. In the case of an RF system the radio frequency wave, the transducer 195 would be an antenna.
• the electrical signal developed by the transducer 195 is then transferred to the amplification and conditioning circuit 205.
• the amplification and conditioning circuit 205 restores the amplitude of the modulated signal, removes any extraneous noise, and demodulates the signal to recover the digital data symbols.
• the restored and conditioned modulated signal is sampled using a clock that a multiple factor (n) of a receive clock fi.
• the receive clock fi and its multiple nfi are generated by the receiver clock generator 220, which has a fundamental frequency approaching that of the transmitter clock generator 135 of Fig. 4.
• the transmitter clock generator 135 and the receiver clock generator 220 each have a frequency of 12.288 MHz +/- 50 ppm. The differences in the frequency due to the tolerance and the differences in the phase between the two clock generators causes the overrun and under-run of the digital data symbols as discussed above.
• provided by the receiver clock generator 220 is used to detect the transitions of the modulated signal and allows the determination of the synchronization pattern 163 and the start pattern 165 of the modulated signal, as shown in Fig. 5.
• the amplification and conditioning circuit 205 detects the packets 167a, ..., 167n of the interleaved digital data symbols and extracts the packets of the interleaved digital data symbols from the modulated signal.
• the multiple n of the multiple frequency clock nfi is optimally from approximately 5 times to approximately 6 times the frequency of the receiver clock f
• the fully recovered frame of the packets of the interleaved digital data symbols are transferred from the amplification and conditioning circuit 205 to the start/stop detection circuit 225.
• the start/stop detection circuit 225 interprets the synchronization pattern and the start pattern to develop a marker signal 242.
• the marker signal 242 is timed to demarcate the boundaries of the beginning of each frame of the packets 167a, ..., 167n of the interleaved digital data symbols. This timing is equivalent to the periodicity of the transmitter clock generator 135 of Fig. 4.
• the recovered packets of the interleaved digital data symbols are transferred from the amplification and conditioning circuit 205 to the buffer control circuit 210.
• the buffer control circuit 210 places the packets of the interleaved digital data symbols in the buffer 215.
• the buffer control circuit 210 directs the placement and movement of the packets of the digital data symbols into and out of the buffer 215.
• the buffer control circuit 210 extracts the packets of the interleaved digital data symbols from the buffer 215 for transfer to the deinterleave and error detection and correction circuit 230.
• the deinterleave and error detection and correction circuit 230 rearranges the order of the packets of digital data symbols to their original order.
• the packets of digital data symbols are then examined for errors that may occur during the transmission of the modulated signal and then corrected to restore the digital data symbols as transmitted.
• the deinterleaved and corrected packets of digital data symbols are then returned to the buffer 215 by the buffer control circuit 210.
• the packets of digital data symbols must be transferred isochronously to insure that the audio analog signal 250 applied to the headphones 260. To insure this, the packets of digital data symbols must be consumed at the rate at which they were generated using the transmitted clock. Since the frequency and phase of the receiver clock 220 varies from the transmitter clock 135 of Fig. 4, the packets of digital data symbols must be resynchronized to match the transmitter clock to insure the isochronous transfer to the packets of digital data symbols. The packets of digital data symbols are transferred from the buffer 215 to the jitter management unit 235 for the resynchronization to the transmitter clock.
• the buffer control circuit 210 conveys the packets of digital data symbols from the buffer 215 to the FIFO buffer 236.
• the packets of digital data symbols are transferred from the buffer 215 to the FIFO buffer 236 at the rate determined by the frequency U of the receiver clock generator 220.
• the FIFO buffer 236 is structured to have the digital data symbols written at one frequency (WCLK) and read at another frequency (RCLK).
• the receiver clock generator 220 is connected to the write clock terminal WCLK of the FIFO buffer 236 to provide the timing for the transfer of the digital data symbols to the FIFO buffer 236.
• the digital data symbols are transferred in isochronous order from the FIFO buffer 236 at the frequency f 2 to the digital-to-analog converter 245.
• the digital data symbols are converted by the digital-to-analog converter 245 to the audio analog signal 250.
• the audio analog signal 250 is transmitted to the speakers of the headphones 260.
• the voltage-controlled oscillator (VCXO) 239 is connected to the read clock terminal RCLK of the FIFO buffer 236 to provide the frequency f 2 with the Read Clock 242.
• the read clock RCLK as controlled by the frequency f 2 acts as the consumer control for the FIFO buffer 236 as described above.
• the frequency f 2 is controlled through the VCXO by the control voltage 242.
• the control voltage 242 is the output of a second digital-to-analog converter 238, which is controlled by the voltage control word 243.
• the voltage control word 243 is generated by the VCO management circuit 237 and is dependent on the FIFO level indication signals 240 and the marker signal 242.
• the FIFO level indication signals 240 provide a signal denoting the level of the FIFO 236 such that the consumer regulation by the adjustment of the frequency of the VCXO 239 can be determined by the VCO management circuit 237.
• the FIFO level indication signals 240, the frequency f 2 is to be adjusted to maintain the amount of digital data symbols present in FIFO buffer in the region between the levels indicated by the Lower Level LL1 and the Upper Limit 1 UL1 signals.
• the digital data symbols 50 are then placed in the data input register 105 of the transmitter 100.
• the symbols of the frame are encoded with an error correction code ECCEO by the ECC generator 110 and
• a second frame AD1 is sampled and converted to symbols of
• the frame formatter 120 formats the frame of the encoded and
• AD2 is converted to the digital data.
• the analog signal is sampled and a new set of digital data symbols is created and transferred to the data input register 105.
• a new set of digital data symbols is created and transferred to the data input register 105.
• the data is encoded with an error correction code ECCEn by the
• the frame formatter 120 formats the encoded and interleaved data to create the frames for transmission.
• the formatted frames modulate the transmit signal with in the transmit signal modulator 125, which is used by the transmit driver 130 to convey the modulated signal 150 to the transmission medium.
• the quality of the transmission medium maybe such that the
• modulated signal 150 is attenuated and interfered with to cause corruption of the modulated signal 150.
• the receiver 200 recovers the modulated signal and restores the frames of the symbols of received data RF RO during the
• the transducer 195 acquires the modulated signal 150 from
• the transmission medium converts the modulated signal 150 to an electrical signal that is applied to the amplification and conditioning circuit 205.
• the amplification and conditioning circuit 205 restores, samples, and recovers the digital data symbols RF RO, which are placed in the buffer 215.
• the deinterleave and error detection and correction circuit 230 is deinterleaved by the deinterleave and error detection and correction circuit 230 to recover the frames of symbols of the original digital data ECCDO.
• the transmitted signal RF T1 is received and the frames RF R1 recovered.
• the frames of symbols of the original data ECCDO are placed in the FIFO buffer 236 of the jitter
• the frames of the digital data symbols are extracted and the digital data symbols have error detection and correction applied to them.
• the digital data symbols are then transferred to the FIFO buffer 236 where they are synchronized to their original isochronous transmission timing.
• the digital data symbols are then applied to the digital-to-analog converter 245 for transmission to the headphones 260.
• the start/stop detection circuit 225 is connected to the buffer control circuit 210 such that the marker signal 242 is transmitted to the buffer control circuit 210.
• the buffer 210 is formed of multiple frame buffers into which one frame is placed upon receipt and recovery of the frames of digital data symbols. When a frame of digital data symbols (for instance frame ECCDO) have been deinterleaved and corrected and returned to the buffer 215, they are ready to be placed in the FIFO buffer 236.
• a frame of digital data symbols for instance frame ECCDO
• the marker signal is created at the completion of the synchronization signal and the start signal for each frame of the digital data symbols.
• the marker occurs at the beginning boundary of a frame of digital data symbols, the marker is synchronized to the transmitter clock and can be used as an indication of the synchronicity of the transmitter and receiver clock.
• the frames of digital data symbols have a fixed number of frames, the timing between the marker signals is also fixed and locked to a frequency that is a sub-multiple of the transmitter clock.
• the buffer control circuit 210 upon receipt of a marker signal 242, the buffer control circuit 210 initiates the transfer of the frame of digital data symbols to the FIFO buffer 236. Since there is no real indication or control of the difference between the frequency of the transmitter clock generator 135 of Fig. 3 and the frequency f
• the remaining digital data symbols S3, .nos., Sn of the frame are transferred serially at the frequency fi of the receiver clock generator 220.
• the VCO management circuit 237 activates the Start VCO signal 244, to start the VCXO 239 to provide the Read Clock signal 242 to the FIFO buffer 236, to begin the streaming of the digital data symbols DAO of Fig. 9 to the digital-to-analog converter 245.
• FIFO buffer 236 until the completion of the frame.
• the next marker signal 242 indicates the detection of the start pattern
• the first two symbols S1 and S2 of the second frame are transferred to the FIFO buffer 236.
• the remaining digital data symbols S3 and Sn are then transferred to FIFO buffer
• the transfer of the digital data symbols from the FIFO buffer 236 continues with no change in the frequency f 2 of the VCXO 239 while the amount of digital data symbols retained in the FIFO buffer 236 remains between the, Lower Level LL1 and the Upper Limit 1 UL1.
• the FIFO indicator signals 240 are appropriately activated to indicate the level.
• the VCO management circuit 237 increments or decrements the voltage control word 243 to cause to cause the digital-to-analog converter 238 to increase or decrease the VCO control voltage 242.
• the VCXO 239 will then increase or decrease the frequency f 2 of the Read Clock signal 241.
• the VCO management circuit 237 increments the voltage control word 243 such that the digital-to-analog converter causes the VCO control voltage 246 to increase, thus causing the frequency f 2 to increase. This causes the rate of consumption of the digital data symbols from the FIFO buffer 236 to increase.
• the VCO management circuit 237 monitors the activity of the FIFO indicator signals 240 to determine a gradient of the change in the amount of digital data symbols present within the FIFO buffer 236.
• the VCO management circuit 237 increments the voltage control word 243 to cause the frequency f 2 to increase again to increase the rate of consumption. Alternately, if the Upper Limit UL1 of the FIFO indicator signals 240 indicates that the amount of data present within the FIFO buffer 236 no longer exceeds the Upper Limit UL1, but the half full indicator ⁇ A F is activated, the VCO management circuit 237 does not change the voltage control word 243 and the frequency f 2 maintains a constant rate of consumption.
• the VCO management circuit 237 decrements the voltage control word 243 to cause the frequency f 2 to decrease to reduce the rate of consumption of the digital data symbols from the FIFO buffer 236.
• the VCO management circuit 237 changes the voltage control word 243 by a double factor such that the frequency f 2 of the VCXO 239 increases by a double increment. This causes the consumption from the
• the VCO management circuit 237 monitors the gradient of the change of the amount of digital data symbols present within the FIFO buffer 236. If the gradient of the change of the amount of the digital data symbols is too large, the VCO management circuit 237 decreases the voltage control word 243 to cause the frequency f 2 to decrease. This slows the consumption rate of the digital data symbols from the FIFO buffer 236.
• the VCO management circuit 237 decrements the voltage control word 243 such that the digital-to-analog converter causes the VCO control voltage 246 to decrease, thus causing the frequency f 2 to decrease. This causes the rate of consumption of the digital data symbols from the FIFO buffer 236 to fall.
• the VCO management circuit 237 monitors the activity of the FIFO indicator signals 240 to determine a gradient of the change in the amount of digital data symbols present within the FIFO buffer 236.
• the VCO management circuit 237 decrements the voltage control word 243 to cause the frequency f 2 to decrease again to decrease the rate of consumption. Alternately, if the Lower Limit LL1 of the FIFO indicator signals 240 indicates that the amount of data present within the FIFO buffer 236 no longer exceeds the Lower Limit LL1 , but the half full indicator Vz F is activated, the VCO management circuit 237 does not change the voltage control word 243 and the frequency f 2 maintains a constant rate of consumption.
• the VCO management circuit 237 decrements the voltage control word 243 to cause the frequency f 2 to decrease to reduce the rate of consumption of the digital data symbols from the FIFO buffer 236.
• the VCO management circuit 237 changes the voltage control word 243 by a double factor such that the frequency f 2 of the VCXO 239 decreases by a double decrement. This causes the consumption from the FIFO buffer 236 to decrease at a faster rate to cause the amount of digital data symbols present within the FIFO buffer 236 to fall toward the half full level.
• the VCO management circuit 237 monitors the gradient of the change of the amount of digital data symbols present within the FIFO buffer 236. If the gradient of the change of the amount of the digital data symbols is too large, the VCO management circuit 237 decreases the voltage control word
• the VCO management circuit 237 constantly monitors the FIFO indicator signals 240 to determine the amount of digital data symbols present within the FIFO buffer 236 and the gradient of the change in consumption of the digital data symbols. From the FIFO indicator signals 240 and the calculated gradient, the VCO management circuit 237 adjusts the voltage control word 243 to cause the frequency f 2 of the Read Clock 241 to maintain the level of the amount of digital data symbols within FIFO buffer 236 at approximately the half full level (Y 2 F).
• the number of bits n of the voltage control word 243 provided to the digital-to-analog converter 238 essentially determines the sensitivity of the jitter management unit 235.
• the voltage control word 238 has 3 bits allowing eight increment of the control voltage 242 from the digital-to-analog converter 238. The sensitivity would be improved by selecting 8 bits for the voltage control word
• the number of FIFO level indication signals 240 could be increased to provide a finer grained indication of the FIFO level indication signals 240.
• the buffer control circuit 210 destroys the recovered data and placed appropriate null characters within the buffer 215.
• the null characters when transferred to the FIFO buffer 236, act to flush the FIFO buffer 236.
• the VCO management circuit 237 interprets this as an error (Empty indicator E is activated) and causes the VCXO 239 to stop the Read Clock 241 thus deactivating the digital-to-analog converter 245 causing the audio analog signal 250 to be muted.
• the digital data symbols are then transferred as above described.
• Figs. 7a -7d for a discussion of the method for the communication of digital data symbols of this invention.
• the steps for the method of communications for the digital data symbols are performed at essentially three different rates - the rate (f t ) established by the transmitter clock 300, the rate (fi) established by the receiver clock 400, and the rate (f 2 ) established by the jitter management clock 500.
• the steps for the transmitting of the digital data symbols of the method of communications begins by sampling an analog signal to acquire (Box 305) the digital data symbols.
• An error detection and correction code is generated (Box 310) and appended to the digital data symbols.
• the digital data symbols are then interleaved (Box 315) to allow the error and detection codes to be enhanced by preventing corruption of adjacent data within the digital data symbols.
• the interleaved digital data symbols with the attendant error detection and correction codes are serialized and formatted (Box 320) as described in Fig. 5.
• the serialized and formatted digital data symbols then modulate (Box 325) a transmission signal.
• the serialized and formatted digital data symbols are encoded using a four-pulse position modulation scheme, as described above.
• the modulated signal is transmitted (Box 330) to a transmission medium such as the atmosphere for conveyance to a receiver.
• the steps for transmitting the digital data symbols within the modulated signal (Boxes 305 - 330) are all synchronized by the frequency f t of the transmit clock 300.
• the modulated signal is received (Box 405), amplified, conditioned, sampled, and decoded (Box 410) to recover the digital data symbols.
• the sampling of the modulated signal has a sampling rate that is a factor n times the frequency f 2 of the receiver clock 400. This sampling allows the determination of the transitions within the modulated signal, which are then decoded to recover the digital data symbols.
• the recovered digital data symbols are then placed (Box 425) within a buffer, which retains the digital data symbols for further processing. Simultaneously, the recovered digital data symbols are examined to detect (Box 415) the synchronization field and start pattern embedded within the framed of the recovered digital data symbols. Upon detection of the synchronization field and the start pattern, a frame marker is generated (Box 420) to demarcate the beginning of a frame of the digital data symbols.
• the digital data symbols are extracted from the buffer and deinterleaved (Box 430) to recover the correct order of the digital data symbols.
• the deinterleaved digital data symbols then have an error detection and correction process applied (Box 435) to correct any errors that may have occurred during the transmission of the modulated signal.
• a check for the occurrence of the frame marker signal is performed
• a read address counter x is initiated (Box 445) to control the transfer of the frame of digital data symbols from the buffer to a FIFO buffer.
• the FIFO buffer is tested (Box 450) for the presence of any digital data symbols in the FIFO buffer. At the beginning of a transfer of the digital data symbols, there are no digital data symbols present in the FIFO buffer.
• the digital data symbols pointed to by the read address counter x are transferred (Box 455) from the buffer to the FIFO buffer.
• the FIFO buffer is then tested (Box 460) if the FIFO buffer has reached a threshold ( 1 A full). If the threshold level has not been reached, the read address counter x is incremented (Box 465) to point to the next address and the next digital data symbol is transferred (Box 465) to the FIFO buffer.
• the FIFO buffer is then tested again (Box 460).
• the read address counter x is initialized (Box 445) and, since the FIFO buffer is not now empty, the next frame of digital data symbols is transferred from the buffer to the FIFO buffer. Because the frequency f t of the transmit clock 300 is not exactly equal in period or phase to the frequency fi of the receive clock 400, all of the digital data symbols of the frame must be transferred from the buffer to the FIFO buffer in the period of time between two of the frame markers. In the preferred embodiment of this method, two of the digital data symbols are transferred from the buffer to the FIFO buffer essentially simultaneously. The number of digital data symbols to be transmitted simultaneously is determined by the frequency f t of the transmit clock 300 versus the frequency fi of the receive clock 400. Therefore, any number of digital data symbols maybe transferred simultaneously and still be in keeping with the intent of this invention.
• the read address counter y is initialized (Box 502) to point to the first digital data symbol of the frame being transferred to the FIFO buffer.
• the digital data symbols pointed to by the read address counter y is transferred (Box 504) from the FIFO buffer.
• the digital data symbols are transferred to a digital-to-analog converter for conversion to an audio analog signal that is applied to speakers.
• the amount of digital data symbols present within the FIFO buffer is tested if it is greater than the Upper Limit 1 (UL1) (Box 506) or less than the Lower Limit 1 (LL1) (Box 508). If the amount of digital data symbols present within the FIFO buffer is neither greater than the Upper Limit 1 (UL1) (Box 506)
• a gradient of the consumption of the digital data symbols from the FIFO buffer versus the supplying of the digital data symbols to the FIFO buffer is tested (Box 510). If the gradient indicates the net rate that the amount of digital data symbols present within the FIFO buffer are being consumed or supplied to the FIFO buffer. If the rate of consumption or the rate of supply is too great, the frequency f 2 of the jitter management clock 400 is increased or decreased incrementally (f 2 +/- ⁇ ) (Box 512) to decrease the gradient.
• the frequency f 2 of the jitter management clock 500 is held constant.
• the read address y is incremented (Box 514) and the amount of digital data symbols present within the FIFO buffer is tested (Box 516) if the FIFO buffer is empty. If it is not empty, the set of next digital data symbols are transferred (Box 504) from the FIFO buffer. As long as the amount of digital data symbols present within the FIFO buffer are less than the Upper Limit 1 (UL1) (Box 506) or the Lower Limit 1 (LL.1), the frequency f 2 of the jitter management clock 500 is held constant. [0086] The read address y is incremented (Box 514) and the amount of digital data symbols present within the FIFO buffer is tested (Box 516) if the FIFO buffer is empty. If it is not empty, the set of next digital data symbols are transferred (Box 504) from the FIFO buffer. As long as the amount of digital data symbols present within the FIFO buffer are less than the Upper
• the read address counter y is incremented (Box 514) and the digital data symbols are transferred (Box 504) until no more digital data symbols are being transferred from the buffer to the FIFO buffer and the FIFO buffer is empty.
• the method returns to start the process of receiving (Box 405) the modulated signal.
• the jitter management clock 500 has a frequency f2 less than the frequency f t of the transmit clock 300 and must be raised to increase the consumption rate of the digital data symbols from the FIFO buffer.
• the amount of digital data symbols present in the buffer is first tested (Box 518) greater than the Upper Limit 2 (UL2). If the amount of digital data symbols is not greater than the Upper Limit 2 (UL2), the gradient of the consumption of the digital data symbols from the FIFO buffer versus the supplying of the digital data symbols to the FIFO buffer is tested (Box 520).
• the frequency f 2 of the jitter management clock 400 is increased incrementally (f 2 + j) (Box 522) to increase the rate of consumption of the digital data symbols. If the gradient of the consumption indicates rate of supply is too great, the frequency f 2 of the jitter management clock 400 is increased by a larger increment (f 2 + k) (Box 524) to decrease the gradient and increase the rate of consumption more rapidly.
• the jitter management clock 500 has a frequency f 2 greater than the frequency f t of the transmit clock 300 and must be lowered to decrease the consumption rate of the digital data symbols from the FIFO buffer.
• the amount of digital data symbols present in the buffer is first tested (Box 532) less than the Lower Limit 2 (LL2). If the amount of digital data symbols is not less than the Lower Limit 2 (LL2), the gradient of the consumption of the digital data symbols from the FIFO buffer versus the supplying of the digital data symbols to the FIFO buffer is tested (Box 534).
• the frequency f 2 of the jitter management clock 400 is decreased incrementally (f 2 - j) (Box 522) to decrease the rate of consumption of the digital data symbols. If the gradient of the consumption indicates rate of supply is too great, the frequency f 2 of the jitter management clock 400 is decreased by a larger increment (f 2 - k) (Box 536) to decrease the gradient and decrease the rate of consumption more rapidly.
• FIFO buffer is again tested (Box 540). If the gradient indicates the rate of consumption or the rate of supply is not too great, the frequency h of the jitter management clock 400 is decreased by an even larger increment (f 2 - 1) (Box 542) to decrease the rate of consumption of the digital data symbols more drastically the decrease the amount of digital data symbols within the FIFO buffer to prevent an overrun. If the gradient of the consumption indicates rate of supply is too great, the frequency f 2 of the jitter management clock 400 is decreased still more dramatically (f 2 - m) (Box 544) to decrease the gradient and decrease the rate of consumption even more rapidly.
• a frame marker is tested (Box 440) and no frame marker is detected, the received data is corrupted and invalid.
• the buffer is cleared of the data and the data is flushed (Box 480) from the FIFO buffer to eliminate the corrupted data.
• the digital data symbols must be streamed isochronously. To prevent distortion and undesirable tones, the digital data symbols must be set to values that null the audio signal.
• the buffer and FIFO buffer as described maybe implemented as a random access memory with the control of the access being provided by a group of state machines.
• the group of state machines implements the circuit functions as described above.
• An arbitrator circuit resolves any simultaneous conflicts of access for writing and reading to the random access memory. For instance the simultaneous transfer of the two sets of data symbols within a frame are accomplished by two state machines operating independently but essentially simultaneously, with the arbitrator circuit determining which state machine writes the data to the FIFO buffer.

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