Classifications

• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
  • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
  • B23K3/00—Tools, devices, or special appurtenances for soldering, e.g. brazing, or unsoldering, not specially adapted for particular methods
  • B23K3/06—Solder feeding devices; Solder melting pans
  • B23K3/0607—Solder feeding devices
  • B23K3/0623—Solder feeding devices for shaped solder piece feeding, e.g. preforms, bumps, balls, pellets, droplets
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
  • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
  • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L24/10—Bump connectors ; Manufacturing methods related thereto
  • H01L24/11—Manufacturing methods
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
  • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
  • B23K2101/00—Articles made by soldering, welding or cutting
  • B23K2101/36—Electric or electronic devices
  • B23K2101/40—Semiconductor devices
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L2224/02—Bonding areas; Manufacturing methods related thereto
  • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
  • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
  • H01L2224/0554—External layer
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L2224/02—Bonding areas; Manufacturing methods related thereto
  • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
  • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
  • H01L2224/0554—External layer
  • H01L2224/0556—Disposition
  • H01L2224/05567—Disposition the external layer being at least partially embedded in the surface
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L2224/02—Bonding areas; Manufacturing methods related thereto
  • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
  • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
  • H01L2224/0554—External layer
  • H01L2224/05573—Single external layer
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L2224/02—Bonding areas; Manufacturing methods related thereto
  • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
  • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
  • H01L2224/0554—External layer
  • H01L2224/05599—Material
  • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/0001—Technical content checked by a classifier
  • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

Definitions

• the present invention relates generally to a method of making bumps on a semiconductor device and, more particularly, to a bump making method, which makes bumps on a semiconductor device using a fluid, thus minimizing an error rate of the bumps, reducing investment costs, and allowing bumps to be easily made on a small amount of semiconductor devices as well as a large amount of semiconductor devices.
• a semiconductor device has several tens of semiconductor chips.
• Each of the semiconductor chips is provided with under ball metallurgy on which a bump is made to ensure a superior electrical connection, when the semiconductor chip is connected to a substrate.
• a passivation film is formed on an upper surface of a wafer other than under ball metallurgy so as to protect a pattern formed on the wafer.
• a three-layered metal film comprising titanium (Ti), tungsten (W), and gold (Au), that is, an upper barrier metal is deposited on the under ball metallurgy and the passivation film through a metal deposition process.
• a photoresist is applied to the upper barrier metal such that the under ball metallurgy is not electrically connected to each other.
• part of the upper barrier metal is eliminated through a photolithography process including an exposure step, a development step, an upper-barrier-metal etching step, and a stripping step.
• the upper barrier metal remains on only the under ball metallurgy.
• the upper-barrier-metal etching step is sequentially executed three times.
• the upper barrier metal is made only on the under ball metallurgy, a screen mask is laminated on the semiconductor device, and solder paste is applied to the under ball metallurgy using a squeezer.
• the upper barrier metal serves as a medium which enhances the coupling force between the under ball metallurgy and the solder paste.
• solder paste After the solder paste has been applied to the under ball metallurgy, flux is applied to the solder paste. In the case of using solder paste containing flux, an additional flux application process is not required.
• the flux is a kind of solvent which serves to neatly connect the under ball metallurgy to the solder paste, and prevents the formation of oxides, when the under ball metallurgy is connected to the solder paste, thus ensuring reliable connection.
• a reflow process is carried out.
• the solder paste is heated to a predetermined temperature in the reflow process, the solder paste is shaped into a ball due to the flux. Thereby, bumps are made on the under ball metallurgy.
• a flux cleaning process is executed to remove flux residue and impurities from the wafer. Therefore, the wafer having the bumps at predetermined positions is obtained.
• the conventional electroplating method is executed as follows. First, a wafer having under ball metallurgy is prepared. A passivation layer is formed on an upper surface of the wafer other than the under ball metallurgy. Next, an upper barrier metal is deposited on the under ball metallurgy and the passivation layer through a metal deposition process. Subsequently, a photoresist is applied to an upper surface of the upper barrier metal, and parts of the photoresist disposed on the under ball metallurgy are eliminated through an exposure operation and a development operation, so that parts of the upper barrier metal disposed on the under ball metallurgy are exposed to the outside. At this time, photoresist residue remaining on the upper barrier metal is eliminated through an etching operation.
• a plated part is formed in an empty space above the under ball metallurgy through an electrolytic plating operation. Solder, Au, Ni, and others are used as a material for the plated part. After the plated part has been formed as such, surplus photoresist is stripped and eliminated. Thereafter, the upper barrier metal is etched so that parts of the upper barrier metal other than parts provided under the plated parts are eliminated. In this case, since the upper barrier metal is a three-layered metal film, the etching process is sequentially performed three times.
• a dipping operation is carried out. That is, the semiconductor device having the plated parts is dipped into a flux bath so that flux is applied to the plated parts.
• predetermined heat is applied to the plated parts through a reflow process, so that each plated part is shaped into a ball due to the flux.
• bumps are made on the under ball metallurgy.
• a flux cleaning process is executed. That is, a cleaning liquid is supplied to the semiconductor device to remove flux residue and impurities from the semiconductor device. Consequently, a semiconductor device having bumps at predetermined positions is obtained.
• the conventional bump making methods have the following problems. That is, the screen printing method is problematic in that the solder paste may be non-uniformly applied due to the operational irregularity of the squeezer and print conditions when the solder paste is applied using the screen mask, so that solder bridging or a height difference may occur between neighboring terminals, or insufficient solder may be applied, thus causing a defective bump, therefore considerably reducing productivity.
• the electroplating method has a problem in that many processes are required to make a bump, so that it usually takes 30 to 40 minutes to make the bump, thus increasing the bump manufacturing time.
• the electroplating method has another problem in that expensive plating equipment is needed, so that bump manufacturing costs are increased.
• the electroplating method has a further problem in that a plating time, an applied current, a voltage, etc. are changed depending on a position of the semiconductor device, so that the plated amount is changed. Thereby, bumps made on an edge of the wafer become small. As such, the shape of the bumps becomes irregular. Further, if the difference in plated amount is large, an open failure may occur when the semiconductor device is connected to the substrate. [Technical Solution]
• an object of the present invention is to provide a method, which makes bumps on a semiconductor device using a fluid, thus minimizing an error rate of the bumps, reducing investment costs, and allowing bumps to be easily made on a small amount of semiconductor devices as well as a large amount of semiconductor devices.
• the present invention provides a method of making a bump on under ball metallurgy provided on a semiconductor device to enhance electrical connection, including a bump making step to make the bump having a predetermined diameter by jetting a molten metal compound onto the semiconductor device at a predetermined speed, and a reflow step to shape the bump into a ball by heating the bump made at the bump making step.
• FIG. 1 is a block diagram to illustrate a method of making a bump on a semiconductor device, according to the present invention
• FIG. 2 is a view to illustrate a wafer positioning operation in the bump making method, according to the present invention
• FIG. 3 is a view to illustrate the operation of making a bump by jetting a molten metal compound, according to the present invention.
• FIG. 4 is a view to illustrate the state where a bump is shaped into a ball through a reflow process of the bump making method, according to the present invention.
• FIG. 1 is a block diagram to illustrate a method of making a bump on a semiconductor device, according to the present invention
• FIG. 2 is a view to illustrate a wafer positioning operation in the bump making method, according to the present invention
• FIG. 3 is a view to illustrate the operation of making a bump by jetting a molten metal compound, according to the present invention
• FIG. 4 is a view to illustrate the state where a bump is shaped into a ball through a reflow process of the bump making method, according to the present invention.
• the bump making method according to the present invention includes a bump making step 100 and a reflow step 200.
• a molten metal compound is supplied to a semiconductor device 10 at a predetermined speed, thus making a bump 50 having a predetermined diameter.
• a fluid supply unit 30 jets a predetermined amount of molten metal compound 40 having a predetermined size onto a predetermined position of the semiconductor device 10 at a predetermined speed, so that the bump 50 is made on under ball metallurgy 20.
• the molten metal compound 40 is selected from the group comprising a mixture of tin and lead, a mixture of tin, silver, and copper, and a mixture of tin and copper. Elements contained in each of the mixtures are melted and mixed with each other in predetermined proportions.
• the semiconductor device 10 is moved such that preset position coordinates of the semiconductor device 10 are sequentially and precisely located under the fluid supply unit 30.
• the bump making step 100 includes a bump positioning step 110 and a wafer positioning step 120 that are preliminary steps and are executed before the molten metal compound 40 is supplied to the semiconductor device 10, so that the molten metal compound 40 is precisely supplied to a predetermined position on the semiconductor device 10 to make the bump 50.
• the bump positioning step 110 columns and rows of bumps 50 to be made on the semiconductor device 10 are established. That is, in order to make the bumps 50 at precise positions, accurate position coordinates of the under ball metallurgy 20 provided on the semiconductor device 10 are set and programmed.
• the wafer positioning step 120 is executed so as to precisely make the bumps 50 at the preset position coordinates.
• an initial position A of an object on which the bumps 50 are made, namely, the semiconductor device 10 is detected.
• the position of the semiconductor device 10 is adjusted so that the initial position A is precisely located at a predetermined position.
• the reflow step 200 is executed.
• the bump 50 provided on the under ball metallurgy 20 is heated to a predetermined temperature.
• the heated bump 50 is shaped into a ball due to surface tension, so that a desired bump 50 is obtained.
• the bumps of the semiconductor wafer are made as follows. That is, the fluid supply unit 30 supplies the molten metal compound 40 to the under ball metallurgy 20 of the wafer 10, in the form of a ball having a predetermined diameter, thus making the bump 50. Therefore, an error rate and equipment costs are considerably reduced, and productivity is dramatically increased. Further, even when a small amount of semiconductor device 10 is produced, profit is high. It is possible to make bumps 50 of various sizes by replacing the nozzle of the fluid supply unit 30 with another one depending on the diameter of a bump to be made, so that workability and productivity are superior, and manufacturing costs are considerably reduced. [Industrial Applicability]
• the present invention provides a bump making method, which makes bumps on a semiconductor device using a fluid, thus minimizing an error rate of the bumps, reducing investment costs, and allowing bumps to be easily made on a small amount of semiconductor devices as well as a large amount of semiconductor devices.

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• Engineering & Computer Science (AREA)
• Manufacturing & Machinery (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Mechanical Engineering (AREA)
• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Wire Bonding (AREA)

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Citations (4)

• 2004
  • 2004-09-07 KR KR1020040071290A patent/KR100554913B1/ko active IP Right Grant
• 2005
  • 2005-09-05 WO PCT/KR2005/002932 patent/WO2006028341A1/en active Application Filing
  • 2005-09-05 CN CNA200580030019XA patent/CN101019222A/zh active Pending
  • 2005-09-05 JP JP2007529719A patent/JP2008518428A/ja active Pending

Patent Citations (4)

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