TWI544594B - 半導體封裝及其製造方法 - Google Patents
半導體封裝及其製造方法 Download PDFInfo
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- TWI544594B TWI544594B TW103116031A TW103116031A TWI544594B TW I544594 B TWI544594 B TW I544594B TW 103116031 A TW103116031 A TW 103116031A TW 103116031 A TW103116031 A TW 103116031A TW I544594 B TWI544594 B TW I544594B
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- semiconductor package
- solder
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Classifications
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H01L21/565—Moulds
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
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- H01L2224/03828—Applying flux
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- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
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- H—ELECTRICITY
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Description
本揭露涉及一種半導體封裝結構。
晶圓等級封裝(WLP)指在一晶圓等級下封裝一積體電路(IC)的技術,其取代在個別封裝中組裝每一個別晶粒之封裝的傳統製程。WLP之一個特徵在於完成之積體電路封裝與經切割後之個別封裝的尺寸實際相同。此外,從開始至客戶端裝運,WLP提供半導體製程的簡化。
焊接結構在WLP中被廣泛地採用以用於外部的電連接。範圍係從手工焊接方法至焊接機的方法。使用具有焊接材料的助焊材料是眾所周知的。助焊材料滿足多項功能。通常助焊材料的主要功能是確保第一成分的導電材料,例如一個支撐基板,例如印刷電路板(PCB)橫跨焊接互連以與一第二成分,如電子組件,有良好的電傳導。
為形成一個成功的互連,通常需要施加助焊材料。許多
不同的替代方案已被使用。已知,例如,採用固體助焊材料在焊接材料內。通常此焊接材料將以線狀或其他固體形式中出現,並整合助焊材料流過焊接材料。當焊材熔化加熱時,如果焊接過程是一個可接受的標準,助焊劑被活化時,將得到互連形成。焊接膠(solder pastes)材料。焊接膠通常為均質、,穩定的焊材顆粒懸浮於助焊介質中所組成。
回流焊接係用於PCB的自動化製造,其中電子組件是表面安裝(surface mounted)在一焊接膠材料之前已經使用下述方法如絲網或網板印刷或點膠在PCB之上。然後,在PCB進行到足夠高的溫度,使焊材液化,並加入組件至PCB上。熱量可以通過以下方式提供,例如,紅外線,加熱的傳送帶或對流構件。
根據本發明之一面向,一種半導體封裝,其包含:一基板;一保護層,其在該基板上;具有一頂表面之一後鈍化互連(PPI),其位於該保護層上;及一導電結構,其與該PPI電連接,其中該PPI之該頂表面包含:一第一區域,其接收該導電結構;及一第二區域,其環繞該第一區域,其中該第二區域包含金屬衍生物,其由該第一區域之材料所轉變。
根據本發明之另一面向,一種半導體封裝,其包含:一基板;一保護層,其在該基板上;具有一頂表面之一後鈍化互連(PPI),其位於該保護層上;及一導電結構,其與該PPI電連接,其中該PPI之該頂表面包含:一第一區域,其電連接至
該導電結構;及一第二區域,其環繞該第一區域,其中該第二區域包含金屬衍生物,其具有大於約1微米之厚度,及其中該第一區域包含金屬。
根據本發明之另一面向,一種製造一半導體封裝之方法,其包含:在一後鈍化互連(PPI)之一第二區域中圖案化一金屬衍生物;在該PPI之一第一區域中形成一助焊層,其中該第一區域係由該第二區域所環繞;在該助焊層上置放一焊接球;及在該焊接球與該PPI之間形成電連接。
100‧‧‧半導體封裝結構
101‧‧‧基板
103‧‧‧保護層
105‧‧‧PPI層
107‧‧‧導電結構
1051‧‧‧第一區域
1052‧‧‧第二區域
1055‧‧‧金屬衍生物
1055A‧‧‧金屬衍生物區域
1057‧‧‧頂表面
200‧‧‧半導體封包
200A‧‧‧半導體封裝
201‧‧‧外部元件
301'‧‧‧開口
301A‧‧‧硬光罩層
301B‧‧‧硬光罩層
301C‧‧‧硬光罩層
3013‧‧‧底表面
3015‧‧‧底表面
302‧‧‧助焊層
303‧‧‧第二助焊層
303A‧‧‧氧電漿
303B‧‧‧氧電漿
303C‧‧‧氧電漿
305A‧‧‧第二模板
305B‧‧‧第二模板
305C‧‧‧第二模板
307‧‧‧導電結構
307A‧‧‧導電結構
307B‧‧‧導電結構
307C‧‧‧導電結構
本揭露之特徵可由下列說明書內容以及相應圖示充分表達。然而本揭露所屬技術領域中具有通常知識者應瞭解,如業界的一般做法,本揭露圖式上某些特徵並無按照相對比例繪製。事實上,本揭露圖式上某些特徵之尺寸會任意放大或縮小,以達到清楚的說明效果。
圖1係根據本揭露一些實施例之半導體封裝之一部分之一截面圖。
圖2A係根據本揭露一些實施例之半導體封裝之一部分之一頂視圖。
圖2B係根據本揭露一些實施例之半導體封裝之一部分之一頂視圖。
圖3A至3C係根據本揭露一些實施例所述之製造方法所準備之半導體封裝之一部分之一截面圖。
圖4A至4C係根據本揭露一些實施例所述之製造方法所準
備之半導體封裝之一部分之一截面圖。
圖5A至5C係根據本揭露一些實施例所述之製造方法所準備之半導體封裝之一部分之一截面圖。
圖6A至6C係根據本揭露一些實施例所述之製造方法所準備之半導體封裝之一部分之一截面圖。
圖7A至7B係根據本揭露一些實施例所述之製造方法所準備之半導體封裝之一部分之一截面圖。
圖8A至8B係根據本揭露一些實施例所述之製造方法所準備之半導體封裝之一部分之一截面圖。
圖9A至9B係根據本揭露一些實施例所述之製造方法所準備之半導體封裝之一部分之一截面圖。
圖10至16係根據本揭露一些實施例所述之製造方法所準備之半導體封裝之一部分之一截面圖。
示例性實施例的揭露可由相應圖示充分表達,圖示視為完整說明之一部分。在此揭露之實施例中,任何方向或定向的參考僅用於方便說明,但不限制本發明之範疇。相對用詞,如「低於」、「上方的」、「水平的」、「垂直的」、「之上」、「之下」、「上」、「下」、「頂」、「底」,及其同類用語(如「水平地」、「向下地」、「向上地」等)應參照下述揭示內容或所討論之圖示中。相對用詞僅用於方便說明且不將裝置建構成或操作成特定的定向。除非特定明確地表達,用詞如「附著的」、「附加的」、「連接的」及「互連的」指一種關係,其中結構係
彼此直接地或間接地透過連結結構及可移動的或剛性的附著件兩者或關係而安置或附著。此外,本案所請發明之特徵及好處係參照較佳的實施例來做說明。據此,本案所請發明不應限於此較佳的實施例,其解釋一些可能非限制的組合特徵,其可單獨存在或與其他特徵結合。本發明之範疇係由所附之申請專利範圍來定義。
在圖示中,使用參考標號以指定不同觀點之相同或相似元件,且本案所請發明之示例性實施例係如後所顯示及描述。圖示不全然依比例繪製,且在一些例子中,圖示會任意放大及/或簡化,以達到清楚的說明效果。本揭露所屬技術領域中具有通常知識者將基於本案所請發明之下述示例性實施例而了解本案所請發明之許多可能的應用及多樣性。
傳統四L(4L)焊接球安裝操作包含四道微影操作,名為用於一第一介電層之一第一微影,用於一後鈍化互連(post-passivation interconnect,縮寫為PPI)層之一第二微影,用於一第二介電層或一保護層之一第三微影,及用於一凸塊下金屬層(under bump metallization,UBM)之一第四微影。在UBM層形成之後,一導電凸塊或一焊接球係安放於其上以完成一外部連接結構。
在前述4L外部連接結構中,第二介電層之一圖案即UBM創造一凹陷結構以容納隨後的導電凸塊或焊接球。在此情況之下,即便在一回流操作之後,導電凸塊或焊接球之位置係限制於由UBM所形成之一區域內。然而,4L外部連接結構之製造成本超過替代的2L外部連接結構。因此,當前的趨勢逐
漸採用2L外部連接結構,其中僅一第一介電層及一PPI層被使用。
在2L外部連接結構中,焊接球限制之缺乏會造成球偏移(ball shift)及其它增生問題,例如低封包良率及低可靠度。球偏移現象造成電路徑被截斷及相鄰導電跡線分布之污染。此外,一較小的球偏移能導致在焊接球,模製化合物與環境底膠填充之間的三介面處的機械性脆弱之點。該脆弱之點容易產生橫跨焊接球而傳播之裂紋。
一些解決方式係經提供以解決在一2L設定中球偏移的問題。例如,先在一PPI層中形成一凹陷以容納焊接球。然而,不僅PPI層的附加圖案化產生額外的費用,球偏移的問題依然會損害經封裝元件之可靠度。本揭露之一些實施例在一2L設定中提供一半導體封裝結構,其中一表面處理係經使用以將焊接球空間地限制並放置於PPI上。PPI之表面之一部分係經轉變成金屬衍生物區,藉此避免焊接球之污染,且因此達成焊接球之空間限制。本揭露之一些實施例亦在一2L設定中提供用於製造半導體封裝結構之方法。
在描述及請求本揭露中,以下用語將根據下述定義而使用。
在此所使用之用語,「助焊材料」指加快焊接處理的物質。在一些實施例中,助焊材料包含還原劑,如木炭。在一些實施例中,助焊材料包含腐蝕性材料。在一些實施例中,助焊材料減少熔化的焊接材料的表面張力並更容易地造成熔化的焊接材料外流及濕潤(wet)一物件。在一些實施例中,助
焊材料係以松香為基底。
在此所使用之用語,「氣相沉積」指使用將被沉積之一材料之氣相或該材料之前導物以沉積材料於一基板的過程。「氣體沉積過程包含任何過程如,但不限於,化學氣相沉積(CVD)及物理氣相沉積(PVD)。氣相沉積方法之例子包含熱燈絲CVD、rf-CVD、雷射CVD(LCVD),共形鑽石塗佈處理,金屬有機CVD(MOCVD)、濺鍍、熱氣化PVD、離子化金屬PVD(IMPVD)、電子束PVD(EBPVD)、反應PVD、原子層沉積(ALD)、電漿強化CVD(PECVD)、高密度電漿CVD(HDPCVD)、低壓CVD(LPCVD)及其他態樣。
在此所使用之用語,「模製化合物」指由合成材料所形成之化合物。模製化合物可包含多孔環氧樹脂、酚系硬化劑、矽石、觸媒、色料、脫模劑或其他態樣。形成一模製化合物之材料具有一高導熱性,一低吸濕速率,在板安裝之溫度中之一高彎曲強度或其組合。
在此所使用之用語,「電性互連」指在IC結構內在晶粒上或周圍所配置的導電線或膜。在一些實施例中,電性互連係重分布層(RDL)。RDL係用於一扇入或一扇出過程。在一些實施例中,電性互連係由導電材料,如金、銀、銅、鎳、鎢、鋁、及/或其合金所形成。
在此所使用之用語,「圖案化」或「經圖案化」在本揭露中描述形成在一表面上之一預定圖案之一操作。圖案化操作包含不同步驟及過程,且根據實施例之特徵而變化。在一些實施例中,一圖案化操作圖案化一已存在之膜或層。圖案化
操作包含形成一光罩於已存在之膜或層上並以蝕刻或其他移除過程來移除膜或層之未在光罩下之部分。光罩係一光阻或一硬光罩。在一些實施例中,一圖案化操作直接地形成一圖案化層於一表面上。圖案化操作包含形成一光敏感膜於表面上,執行一光微影過程及一顯影過程。存留的光敏感膜可被移除或保留及整合至封裝中。
上面概括的問題和需要,可以通過本揭露的實施例來解決。圖1是在一2L的設置中一半導體封裝100的一部分的的橫截面圖。一元件基板101包括一半導體基板,如矽晶圓,矽晶粒,半導體於絕緣體上(SOI)基板,或包括半導體材料之任何結構。相互連接以執行一個或多個功能的半導體元件,如電晶體,電容器,電阻器,二極體,光電二極體,保險絲等等,係形成在基板101的表面上。一介電層或一保護層103被佈置在基板101上,以提供在某些預定的區域來自基板101的電連接的電絕緣性。在一些實施例中,保護層103由非摻雜矽酸鹽玻璃(USG),氮化矽,氮氧化矽,氧化矽,及其組合中選出的非有機材料形成。在另一實施例中,雖然也可以使用其他相對軟,往往是有機的,介電材料,保護層103係由聚合物層,如環氧樹脂,聚酰亞胺,苯並環丁烯(BCB),聚苯並噁唑(PBO)等等形成。
參見圖1,一PPI層105係放置於保護層103上。在一些實施例中,PPI層105係由一導電材料所形成,其包含,但不限於,例如銅、鋁、銅合金、鎳或其他移動導電材料。在其他實施例中,PPI層105電性連接在基板101中之半導體元件至一隨後
形成的導電結構107。PPI層105亦作用成一電源線、重分布線(re-distribution line,RDL)、電感器、電容器、或任何保護組件。在一些實施例中,PPI層105具有小於約30微米之厚度,例如介於約2微米與約25微米之間。在其他實施例中,PPI層105具有一頂表面1057,其在保護層103之相對側。導電結構107係藉由連接至PPI層105之頂表面1057而電耦合至PPI層105。
在一些實施例中,PPI層105之頂表面1057包含電連接至導電結構107之一第一區域1051,及環繞第一區域1051而不電連接至導電結構107之一第二區域1052。區別第一區域1051與第二區域1052之特徵係第二區域1052包含一金屬衍生物層,其在PPI層105之頂表面1057處,然而,無金屬衍生物層位在第一區域1051內。第二區域1052之濕潤性質係相對於導電結構107而終止,其通常為冶金材料,且第二區域1052之不沾濕性質係由位在其處之一金屬衍生物1055所造成。考量金屬衍生物1055之表面能與導電結構107之表面能,在金屬衍生物1055與導電結構107兩者介面之間的接觸對彼此施加一排斥力。換言之,導電結構107對金屬衍生物1055之一接觸角(未顯示)係至少大於90度,顯示一低濕潤(wetting)能力。
在一些實施例中,導電結構107包含一銅層、一銅合金層、一鎳層、一鎳合金層,一焊接層或其組合。在導電結構107中之焊接層可包含一無鉛的預焊接層,SnAg,或一焊接材料,其包含錫、鉛、銀、銅、鎳、鉍或其組合之合金。在某些實施例中,導電結構107係一焊接球或一焊接膠。例如,因環境及健康理由,在焊接成分中鉛的使用已經證實為不良的。
因此,在一些實施例中,焊接球係從焊接成分中去除鉛之需求。此無鉛焊接成分通常包含錫、銅、銀(通常重量比為95.5%的錫,重量比為4%的銀,重量比為0.5%之銅)。鉍亦可與錫、銻及銀一起使用,其重量比約在1%至4.5%之範圍。
參見圖1,雖然未顯示在如半導體封裝結構100中所說明之最終產物,但在一回流操作之前,一助焊材料係預先放置於導電結構107與PPI層105之第一區域1051之間。通常可知提供達成多個功能的一助焊材料係值得嚮往的。特別是,提供表面活化之助焊材料更是值得嚮往的。據此觀點,可知在助焊材料內包含一活化劑成分將會移除從一金屬表面經氧化之材料,藉此允許較佳的焊接至金屬互連。在一些實施例中,活化劑係經添加以分解及移除任何氧化物膜,其存在於焊接將被實現的部分中,且活化劑通常為有機化合物,其含有鹵化物,典型上為胺的氫鹵化,如二乙胺鹽酸鹽或弱無鹵化物有機酸。
在一些實施例中,金屬衍生物1055擁有約1微米至3微米之一厚度T。所述厚度T之範圍超過在PPI層105之頂表面1057處之原生氧化物或氮化物之一厚度(未顯示),其取決於實現封裝操作之週遭環境。在一些實施例中,PPI層105係由導電材料所形成,導電材料包含,但不限於,銅、鋁、銅合金、鎳或其他移動式導電材料,且封裝操作係在一含氧環境中執行,金屬衍生物1055包含導電材料氧化物。在其他實施例中,PPI層105係由導電材料所形成,且封裝操作係在一含氮環境中執行,金屬衍生物1055包含導電材料氮化物。
參見圖2A,圖2A係根據本揭露之一些實施例之顯示於圖1之半導體封裝結構100之一頂視圖。為簡化說明,共用相同於圖1之的元件符號之元件在此不再贅述。在圖2A中,僅顯示導電結構107及金屬衍生物1055從一頂視觀點,且顯示於圖1中位在下方之PPI層105、保護層103及基板101係由導電結構107及金屬衍生物1055所覆蓋。在一些實施例中,因導電結構107係一焊接球,具有焊接球之一直徑D之一圓形面積比PPI層105之表面1057處之第一區域1051(以虛線顯示)之面積大。第一區域1051以外之面積係第二區域1052,其由金屬衍生物1055所定義。在其他實施例中,第一區域1051之輪廓不限制為如圖2A所示之圓形,其他輪廓,如正方形、四邊形或具有不規則邊界之形狀均在本揭露所能思及之範疇內。
參見圖2B,圖2B係根據本揭露之一些實施例之顯示於圖1之半導體封裝結構100之一頂視圖。為簡化說明,共用相同於圖1之的元件符號之元件在此不再贅述。在圖2B中,導電結構107、金屬衍生物1055及PPI層105從一頂視觀點顯示,且顯示於圖1中位在下方之保護層103及基板101係由導電結構107、金屬衍生物1055及PPI層105所覆蓋。考量金屬衍生物1055係非導電的,故藉此增加PPI層105之電阻,由金屬衍生物1055所定義之第二區域1052係減縮至比顯示於圖2A之區域小之一面積,其環繞第一區域1051。在其他實施例中,金屬衍生物1055之輪廓不限制為如圖2B所示之圓形,其他輪廓,如正方形、四邊形或具有不規則邊界之形狀均在本揭露所能思及之範疇內。又在其他實施例中,金屬衍生物1055之輪廓不限制為如圖2B
所示之固體形狀,金屬衍生物1055之不連續的圖案,如放射圖案或螺旋圖案均在本揭露所能思及之範疇內。
圖3A至圖9B顯示操作一用於製造一半導體封裝之方法。在圖3A至圖9B中討論之三種替代方案,即在圖3A至圖9B中顯示三種實施例之操作。使用圖3A、4A、5A、6A、7A及7B討論一第一操作;使用圖3B、4B、5B、6B、8A及8B討論一第二操作;及使用圖3C、4C、5C、6C、9A及9B討論一第三操作。參見圖3A,一硬光罩層301A係放置於本揭露之圖1中之一堆疊上,堆疊包含一基板101、一保護層103及一PPI層105。在圖3A中,一光阻301A係經圖案化於PPI層105之最上端以遮蔽PPI層105之一部分。然而,在其他實施例中,一介電層係用以遮蔽PPI層105之部分。介電材料包含氮化矽、碳化矽、碳氮化矽、碳氧化矽、四乙基氧化矽烷(TEOS)、氧化矽、前述材料所形成的多層、及/或由PECVD技術所造成前述材料的結合或高密度電漿CVD(HDPCVD)、或相似材料。
參見圖3B,一硬光罩層301B係放置於本揭露之圖1中之一堆疊(101、103、105)上。在一些實施例中,硬光罩層301B係經使用以獲得如圖2A所示之一半導體封裝結構,其中金屬衍生物1055係環繞第一區域1051而形成的包覆。在一些實施例中,硬光罩層301B係放置於PPI層105上之一第一模板以遮蔽PPI層105之一部分。在某些實施例中,在硬光罩層301B之一底表面3013與PPI層105之頂表面1057之間的間隙G係少於10微米。
參見圖3C,一硬光罩層301C係放置於本揭露之圖1中之一堆疊(101、103、105)上。在一些實施例中,硬光罩層301C係
經使用以獲得如圖2B所示之一半導體封裝結構,其中金屬衍生物1055係環繞第一區域1051而僅在特定區域處形成。在一些實施例中,硬光罩層301C係放置於PPI層105上之一第一模板以遮蔽PPI層105之一部分。在某些實施例中,在硬光罩層301C之一底表面3013與PPI層105之頂表面1057之間的間隙G'係少於10微米。然而,在其他實施例中,一塗佈層(未顯示)係形成於硬光罩層301C之底表面3015處,且所述塗佈層之厚度足以接觸PPI層105之頂表面1057。如此,當一第一底部塗佈模板用以作為一硬光罩層301C時,間隙G'可被消除。在一些實施例中,塗佈層係似鑽石碳薄膜,且第一模板係由不鏽鋼所形成。
參見圖4A及圖5A,採用一表面處理操作以在PPI層105之一第二區域1052中形成一金屬衍生物1055。在一些實施例中,金屬衍生物1055係形成於一靠近表面區域處,但不被硬光罩層301A所覆蓋,硬光罩層301A係放置於PPI層105之頂表面1057上,且所述靠近表面區域係第二區域1052。例如,採用氧電漿303A以將第二區域1052從導電材料轉變成導電材料氧化物。在一些實施例中,氧電漿源不限於一低頻電漿源。其他電漿源,如射頻(RF)電漿源、微波(MW)遠端電漿源、直流(DC)電漿源、感應式耦合電漿源(ICP)、電子迴旋共振電漿源(ECR)及其他類型電漿設備及處理亦能被採用。透過例行實驗,本揭露所屬技術領域中具有通常知識者能選擇適合的電漿設備與條件,如所需的電漿功率、處理時間、氧氣流及腔室內壓力以藉由如前所述之氧電漿轉變將導電材料之所欲厚度轉變成導電材料氧化物。
如圖4A所示之一些實施例中,氧電漿303A係產生於一反應離子蝕刻系統中,反應離子蝕刻系統具有約0.1W/cm2至約0.6W/cm2之功率密度及約1MHz至約60MHz之RF頻率。氧氣流約6至180SCCM,且氧偏壓約1至25mTorr。約15至300秒的處理時間足以使得PPI層105之靠近表面區域變成導電材料氧化物,其具有如圖5A所示之約1.5微米的所欲厚度T。
參見圖4B及圖5B,採用一表面處理操作以在PPI層105之一第二區域1052中圖案化一金屬衍生物1055。在一些實施例中,金屬衍生物1055係形成於一靠近表面區域處,但不被硬光罩層301B所覆蓋,硬光罩層301B係放置於PPI層105之頂表面1057上,且所述靠近表面區域係第二區域1052。例如,採用氧電漿303B以將第二區域1052從導電材料轉變成導電材料氧化物。如圖5B所示,金屬衍生物1055係形成於第二區域1052處,亦在第一區域之一部分處。在一些實施例中,因在圖4B中之硬光罩層301B係一模板,其不與PPI層105之頂表面1057產生物理接觸,故氧電漿303B接著與第一區域1051之一部分反應並在其處形成一金屬衍生物區域1055A。在某些實施例中,金屬衍生物區域1055A之厚度T'係金屬衍生物區域1055之厚度T的約0.1至約0.5倍。參見圖4A之揭露內容,在圖4B中所採用之氧電漿303B先前已記載於本揭露中,故在此不再贅述。
如圖4B所示之一些實施例中,氧電漿303A係產生於一反應離子蝕刻系統中,反應離子蝕刻系統具有約0.1至0.6W/cm2之功率密度及約1MHz至約60MHz之RF頻率。氧氣流約6至180SCCM,且氧偏壓約1至25mTorr。約15至300秒的處理時間
足以使得PPI層105之靠近表面區域變成導電材料氧化物,其具有如圖5B所示之約1.8微米的所欲厚度T。
參見圖4C及圖5C,採用一表面處理操作以在PPI層105之一第二區域1052中圖案化一金屬衍生物1055。在一些實施例中,金屬衍生物1055係形成於一靠近表面區域處,但不被硬光罩層301C所覆蓋,硬光罩層301C係放置於PPI層105之頂表面1057上,且所述靠近表面區域係第二區域1052。例如,採用氧電漿303C以將第二區域1052從導電材料轉變成導電材料氧化物。如圖5C所示,金屬衍生物1055係形成於第二區域1052處,亦在第一區域之一部分處。
參見圖4C及圖5C,在一些實施例中,因硬光罩層301C係一模板,其不物理接觸PPI層105之頂表面1057,故氧電漿303C接著與第一區域1051之一部分反應並在其處形成一金屬衍生物區域1055A。在某些實施例中,金屬衍生物區域1055A之厚度T'係金屬衍生物區域1055之厚度T的約0.1至約0.5倍。參見圖4A之揭露內容,在圖4C中所採用之氧電漿303C先前已記載於本揭露中,故在此不再贅述。
仍參見圖4C及圖5C,在一些實施例中,因硬光罩層301C係一底塗佈模板(未顯示),其與PPI層105之頂表面1057產生物理接觸,故氧電漿303C被阻隔於第一區域1051,且在其處不形成一金屬衍生物區域1055A(未在圖5C中說明)。換言之,僅在第二區域1052中之金屬衍生物1055形成於PPI層105之靠近表面區域上,而在第一區域中之金屬衍生物區域1055A不形成於PPI層105之靠近表面區域上。
如圖4C所示之一些實施例中,氧電漿303C係產生於一反應離子蝕刻系統中,反應離子蝕刻系統具有約0.1至0.6W/cm2之功率密度及約1MHz至約60MHz之RF頻率。氧氣流約6至180SCCM,且氧偏壓約1至25mTorr。約15至300秒的處理時間足以使得PPI層105之靠近表面區域變成導電材料氧化物,其具有如圖5C所示之約2微米的所欲厚度T。
參見圖6A、6B及6C,一助焊層302係藉由一圖案化操作而形成於PPI層105之第一區域1051上。在如圖6A至圖6C所示一些實施例中,一第二模板(305A、305B、305C)係放在PPI層105上且在其處遮蔽第二區域1052。一刮板(未顯示)接著將助焊層材料散佈在第二模板(305A、305B、305C)之開口以形成助焊層302。在某些實施例中,第二模板(305A、305B、305C)不限於位在PPI層105之頂表面1057上方,而是直接放在PPI層105之頂表面1057上。在其他實施例中,第二模板(305A、305B、305C)係一底塗佈模板,其物理接觸PPI層105之頂表面1057。參見圖3C之揭露內容,底塗佈模板之結構及材料先前已記載於本揭露中,故在此不再贅述。
圖7A至圖9B顯示在本揭露所提供之一些實施例中一焊接球置放操作及一隨後回流操作。共用相同於圖1之的元件符號之元件在此不再贅述。圖7A顯示一導電結構307A,如一焊接球,其位在助焊層302上,隨後係顯示於圖3A、圖4A、圖5A、圖6A中之操作。圖7B顯示在圖7A中在半導體封裝結構上執行一回流操作後之一最終結構。在一些實施例中,回流操作包含加熱半導體封裝結構至約攝氏250度的溫度並保持在所述溫
度2分鐘。在完成回流操作之後,助焊層302消失且導電結構307A係電連接至PPI層105。
圖8A顯示一導電結構307B,如一焊接球,其位在助焊層302上,隨後係顯示於圖3B、圖4B、圖5B、圖6B中之操作。圖8B顯示在圖8A中在半導體封裝結構上執行一回流操作後之一最終結構。在一些實施例中,回流操作包含加熱半導體封裝結構至約攝氏230度的溫度並保持在所述溫度1.5分鐘。在完成回流操作之後,助焊層302消失且導電結構307B係電連接至PPI層105。
圖9A顯示一導電結構307C,如一焊接球,其位在助焊層302上,隨後係顯示於圖3C、圖4C、圖5C、圖6C中之操作。圖9B顯示在圖9A中在半導體封裝結構上執行一回流操作後之一最終結構。在一些實施例中,回流操作包含加熱半導體封裝結構至約攝氏260度的溫度並保持在所述溫度1分鐘。在完成回流操作之後,助焊層302消失且導電結構307C係電連接至PPI層105。
圖10至圖15顯示根據本揭露之一些實施例一種製造一半導體封包200之方法。共用相同於前揭之圖示的元件符號之元件在此不再贅述。參見圖10,一第一助焊層302形成於PPI層105之頂表面1057上。在一些實施例中,使用一第一模板301A以形成一第一助焊層302。如圖10所示,當一刮板(未顯示)散佈助焊膠橫跨一開口301'時,第一模板301A之開口301'具有一寬度W1,其允許助焊膠經放置於頂表面1057之下方。在其他實施例中,第一助焊層302之圖案化係由一螢幕列印操作或使
用光阻或硬光罩層之一光微影操作而實現。
參見圖11,未被第一助焊層302所覆蓋之PPI層105之頂表面1057之一部分係經轉變成一未沾濕層,其由金屬衍生物1055,如導電材料氧化物或氮化物所組成。在一些實施例中,半導體封裝200A係放置於一含氧環境中且受制於一第一溫度熱處理。例如,第一溫度係約攝氏100至250度,且在含氧環境中之氧氣與PPI層105之靠近表面區域反應約10分鐘之期間以形成一層金屬衍生物1055。在一些實施例中,氧化操作包含將氧氣流至一腔室中,其容納半導體封裝200A於50SCCM流速中及於第一溫度之範圍內之溫度。在一些實施例中,金屬衍生物1055擁有約1微米之厚度T。
然而,在其他實施例中,半導體封裝200A係受制於在一RIE腔室中之一氧電漿處理,及在該腔室中之溫度係控制在一第一溫度。例如,第一溫度約為攝氏150至200度。在一些實施例中,在圖11中所採用之氧電漿處理係可參見圖4A及其前述記載,在此不再贅述。在圖11所顯示之一些實施例中,氧電漿係產生於具有約0.1至0.6W/cm2之一功率密度及約1MHz至60MHz之一RF頻率的一RIE系統中。氧氣流速約為6至180SCCM,且氧偏壓約為1至25mTorr。在第一溫度下,約15至300秒的處理時間足以使得PPI層105之靠近表面區域變成導電材料氧化物,其具有所欲厚度T。在其他實施例中,無需在第一溫度下控制一RIE腔室溫度而執行氧電漿處理。
如圖10及圖11所示,當金屬衍生物1055形成於PPI層105之頂表面1057上,助焊層302之寬度從一寬度W1轉變成一寬度
W2。在一些實施例中,寬度W2比寬度W1大。例如,助焊層302由松香所組成,其係有機酸(樹脂酸,主要是樅酸,用海松酸,異海松酸,新樅酸,二氫樅酸及脫氫松香酸)之混合物。助焊層302在熔融狀態將液態的、離子的及輕微的反應劑轉變成金屬氧化物。助焊層302當受制第一溫度(約攝氏150至200度)時,傾向軟化且能夠從銅中融解表面氧化物的較薄層而無需額外的添加劑。因松香之軟化現象,其受限於大於約攝氏70度之溫度,在圖11中之助焊層302的寬度W2比在圖10中之助焊層302的寬度W1大。
參見圖11及圖12,第一助焊層302係被移除且在PPI層105之頂表面1057之一第一區域1051被暴露。在一些實施例中,第一助焊層302係被助焊移除器移除,如不含鹵素的有機溶劑,胺系化合物,沒有氨基基團之螯合劑或在鹼性環境中之水。相比於如圖10所示之第一助焊層302之寬度W1,在圖12中之第一區域1051之寬度W2反映如圖11所示在第一溫度處理後之第一助焊層302之一維度。因此,第一區域1051之寬度W2比如圖10所示之第一助焊層302之寬度W1大。在一些實施例中,在未由第一助焊層所覆蓋之PPI之頂表面之部分轉變成金屬衍生物1055之前,第一區域1051之一面積比由圖10中之第一助焊層302所覆蓋之面積大。
參見圖13,具有一寬度W1之一第二助焊層303係形成於PPI層105之頂表面1057上。在一些實施例中,第二助焊層303係使用一第二模板305A而形成。如圖13所示,當一刮板(未顯示)將助焊膠橫跨開口301'而散佈時,第二模板305A之一開口
301'具有一寬度W1,其允許助焊膠被放置於頂表面1057上。在其他實施例中,第二助焊層303之圖案化係由一螢幕列印操作或使用光阻或硬光罩層之一光微影操作而實現。在一些實施例中,第一區域1051之寬度W2比第二助焊層303之寬度W1大。然而,在其他實施例中,第二助焊層303之寬度W1能等於第一區域1051之寬度W2。
在如圖10至圖13及圖15中之操作顯示執行於圖14中之半導體封裝結構之一回流操作的一最終結構之後,圖14顯示的一導電結構307,如放置於第二助焊層303上之一焊接球。在一些實施例中,回流操作包含加熱半導體封裝結構至約攝氏230至270度之一第二溫度並保持在所述溫度1.5分鐘。在回流操作完成之後,第二助焊層303消失,且導電結構307係電連接至PPI層105。在一些實施例中,第二溫度係範圍為約攝氏230至270度之一焊接回流溫度。與先前所討論之第一溫度相比,在一些實施例中,應用約攝氏130至220度之第一溫度係以加速氧化操作及造成第一助焊層302軟化。
圖16顯示一半導體封裝,其包含如圖1所示之一半導體封裝結構100及經由導電結構307電連接至堆疊(101、103、105)之一外部元件201。如圖16所示之半導體封裝包含執行另一回流操作以形成在外部元件201與導電結構307之間之一電連接。在一些實施例中,回流操作包括加熱半導體封裝至約攝氏230至270度之一第二溫度並保持在所述溫度1.5分鐘。在一些實施例中,外部元件201包含,但不限於,一PCB板、一記憶體元件、一CPU、或具有電I/O之其他元件。
本揭露之一些實施例提供一種半導體封裝。該半導體封裝包含一基板,一保護層,其在該基板上,具有一頂表面之一後鈍化互連(PPI),其位於該保護層上,及一導電結構,其與該PPI電連接。該PPI之該頂表面包含一第一區域,其接收該導電結構;及一第二區域,其環繞該第一區域。該第二區域包含金屬衍生物,其由該第一區域之材料所轉變。
在本揭露之一些實施例中,該第二區域之該金屬衍生物包含金屬氧化物或金屬氮化物。
在本揭露之一些實施例中,該半導體封裝之該PPI包含一電源線,一重分布線,一電感器,一電容器,或保護組件。
在本揭露之一些實施例中,該半導體封裝之該PPI包含導電材料,且其中該第二區域之該金屬衍生物包含導電材料氧化物。
在本揭露之一些實施例中,該導電結構包含一焊料凸塊。
在本揭露之一些實施例中,該半導體封裝進一步包含電連接至該導電結構之一外部元件。
本揭露之一些實施例提供一種半導體封裝。該半導體封裝包含一基板,一保護層,其在該基板上,具有一頂表面之一後鈍化互連(PPI),其位於該保護層上,及一導電結構,其與該PPI電連接。該PPI之該頂表面包含:一第一區域,其電連接至該導電結構,及一第二區域,其環繞該第一區域。該第二區域包含金屬衍生物,其具有大於約1微米之厚度,及該導電結構在該第二區域係不沾濕的。
在本揭露之一些實施例中,該半導體封裝之該金屬衍生物包含氧化物或氮化物。
在本揭露之一些實施例中,該半導體封裝之該PPI包含一電源線,一重分布線,一電感器,一電容器,或保護組件。
在本揭露之一些實施例中,該半導體封裝之該PPI包含導電材料,且其中該第二區域之該金屬衍生物包含導電材料氧化物。
在本揭露之一些實施例中,該導電結構包含一焊料凸塊。
在本揭露之一些實施例中,該半導體封裝進一步包含電連接至該導電結構之一外部元件。
本揭露之一些實施例提供一種製造一半導體封裝之方法。該方法包含在一後鈍化互連(PPI)之一第二區域中圖案化一金屬衍生物;在該PPI之一第一區域中形成一助焊層,其中該第一區域係由該第二區域所環繞;在該助焊層上置放一焊接球;及在該焊接球與該PPI之間形成電連接。
在本揭露之一些實施例中,製造一半導體封裝之該方法之該在該PPI之該第二區域中圖案化該金屬衍生物進一步包含在該PPI上方形成一光罩層。
在本揭露之一些實施例中,製造一半導體封裝之該方法之該在該PPI上形成該光罩層包含在該PPI上放置一第一模板。
在本揭露之一些實施例中,製造一半導體封裝之該方法之該在該PPI之該第二區域中圖案化該金屬衍生物包含一氧氣電漿表面處理。
在本揭露之一些實施例中,製造一半導體封裝之該方法之該在該PPI之該第一區域中形成該助焊層包含在該PPI上放置一第二模板。
在本揭露之一些實施例中,製造一半導體封裝之該方法之該在該PPI上方形成該光罩層進一步包含在該PPI之上形成一光罩層。
在本揭露之一些實施例中,製造一半導體封裝之該方法之該在該焊接球與該PPI之間形成電連接包含一回流操作。
本揭露之一些實施例提供提供一種製造一半導體封裝之方法。該方法包含形成覆蓋一後鈍化互連(PPI)之一頂表面之一部分的一第一助焊層;將未由該第一助焊層所覆蓋之該PPI之該頂表面之一部分轉變成一金屬衍生物層;移該除第一助焊層,藉此暴露該PPI之一第一區域;在該PPI之該第一區域上形成一第二助焊層;在該助焊層上置放一焊接球;及在該焊接球與該PPI之間形成電連接。
在本揭露之一些實施例中,製造一半導體封裝之該方法之該形成覆蓋該PPI之一頂表面之一部分的該第一助焊層包含在該PPI上放置一第一模板。
在本揭露之一些實施例中,製造一半導體封裝之該方法之該將未由該第一助焊層所覆蓋之該PPI之該頂表面之一部分轉變成該金屬衍生物層包含加熱該半導體封裝至一第一溫度。
在本揭露之一些實施例中,製造一半導體封裝之該方法之該在該焊接球與該PPI之間形成電連接包含加熱該半導體封
裝至一第二溫度,且其中該第二溫度大於該第一溫度。
在本揭露之一些實施例中,在將未由該第一助焊層所覆蓋之該PPI之該頂表面之該部分轉變成一金屬衍生物層之前,由該第一助焊層所覆蓋之該PPI之該頂表面之該部分之一面積小於該第一區域之一面積。
在本揭露之一些實施例中,製造一半導體封裝之該方法之該將未由該第一助焊層所覆蓋之該PPI之該頂表面之一部分轉變成該金屬衍生物層包含將氧氣流進容納該半導體封裝之一腔室
在本揭露之一些實施例中,製造一半導體封裝之該方法之該將未由該第一助焊層所覆蓋之該PPI之該頂表面之一部分轉變成該金屬衍生物層包含一氧電漿表面處理。
在本揭露之一些實施例中,製造一半導體封裝之該方法之該在該PPI之該第一區域上形成該第二助焊層包含在該PPI上放置一第二模板。
儘管本揭露之技術內容及其優點已詳細揭示,然而本揭露所屬技術領域中具有通常知識者應瞭解,在不背離支柱附申請專利範圍所界定之本揭露精神和範圍內,本揭露之教示及揭示可作種種之替換及修飾。例如,上文揭示之許多裝置或結構可以不同之方法實施或以其它結構予以取代,或者採用上述二種方式之組合。
此外,本申請案之範疇並不限於說明書中所載之過程、機器、製程、合成物、構件、方法、步驟之特定的實施例。本揭露所屬技術領域中具有通常知識者應從本發明之揭示瞭
解實施相同於在此揭露之對應實施例之功能或達到實質相同於在此揭露之對應實施例之結果的當前存在的或將來發展之過程、機器、製程、合成物、構件、方法、步驟之特定的實施例可根據本發明而被使用。據此,所附之申請專利範圍包含前述範疇,如過程、機器、製程、合成物、構件、方法或步驟。
100‧‧‧半導體封裝結構
101‧‧‧基板
103‧‧‧保護層
105‧‧‧PPI層
107‧‧‧導電結構
1051‧‧‧第一區域
1052‧‧‧第二區域
1055‧‧‧金屬衍生物
1057‧‧‧頂表面
Claims (10)
- 一種半導體封裝,其包含:一基板;一保護層,其在該基板上;具有一頂表面之一後鈍化互連(post-passivation interconnect,PPI),其位於該保護層上;及一導電結構,其與該PPI電連接,其中該PPI之該頂表面包含:一第一區域,其接收該導電結構;及一第二區域,其環繞該第一區域,其中該第二區域包含金屬衍生物,其由該第一區域之材料所轉變;該金屬衍生物之厚度介於1微米至3微米之間。
- 如請求項1之半導體封裝,其中該第二區域之該金屬衍生物包含金屬氧化物或金屬氮化物。
- 如請求項1之半導體封裝,其中該PPI包含一電源線,一重分布線,一電感器,一電容器,或保護組件。
- 如請求項3之半導體封裝,其中該PPI包含導電材料,且其中該第二區域之該金屬衍生物包含導電材料氧化物。
- 如請求項1之半導體封裝,其中該第二區域具有大於1微米之厚度,及其中該第一區域包含金屬。
- 一種製造一半導體封裝之方法,其包含:在一後鈍化互連(post-passivation interconnect,PPI)之一第二區域中圖案化一金屬衍生物,該金屬衍生物之厚度介於1 微米至3微米之間;在該PPI之一第一區域中形成一助焊層,其中該第一區域係由該第二區域所環繞;在該助焊層上置放一焊接球;及在該焊接球與該PPI之間形成電連接。
- 如請求項6之製造一半導體封裝之方法,其中該在該PPI之該第二區域中圖案化該金屬衍生物進一步包含在該PPI上方形成一光罩層。
- 如請求項7之製造一半導體封裝之方法,其中該在該PPI上方形成該光罩層包含在該PPI上放置一第一模板。
- 如請求項6之製造一半導體封裝之方法,其中該在該PPI之該第二區域中圖案化該金屬衍生物包含一氧氣電漿表面處理。
- 如請求項6之製造一半導體封裝之方法,其中該在該PPI之該第一區域中形成該助焊層包含在該PPI上放置一第二模板。
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US9543263B2 (en) | 2017-01-10 |
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