WO2006024193A1 - Procede et systeme pour transfert de donnees - Google Patents

Procede et systeme pour transfert de donnees Download PDF

Info

Publication number
WO2006024193A1
WO2006024193A1 PCT/CN2004/001003 CN2004001003W WO2006024193A1 WO 2006024193 A1 WO2006024193 A1 WO 2006024193A1 CN 2004001003 W CN2004001003 W CN 2004001003W WO 2006024193 A1 WO2006024193 A1 WO 2006024193A1
Authority
WO
WIPO (PCT)
Prior art keywords
burst
signal
data transfer
master device
bus
Prior art date
Application number
PCT/CN2004/001003
Other languages
English (en)
French (fr)
Inventor
Jenya Chou
Minliang Sun
Original Assignee
Magima Digital Information Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Magima Digital Information Co., Ltd. filed Critical Magima Digital Information Co., Ltd.
Priority to PCT/CN2004/001003 priority Critical patent/WO2006024193A1/zh
Priority to EP04762138A priority patent/EP1811393B1/en
Priority to AT04762138T priority patent/ATE425495T1/de
Priority to US11/661,439 priority patent/US7543093B2/en
Priority to DE602004019990T priority patent/DE602004019990D1/de
Publication of WO2006024193A1 publication Critical patent/WO2006024193A1/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines

Definitions

  • the present invention relates to a data transfer method and a data transfer system. More particularly, it relates to a method and system for efficiently and efficiently transferring data between a master device and a slave device using a bus in an architecture having multiple master devices. Background technique
  • Processing units in the system may include various devices such as a central processing unit (CPU), digital signal processor (DSP), and memory.
  • CPU central processing unit
  • DSP digital signal processor
  • memory Especially in a system-on-a-chip, it is often necessary to integrate a large number of devices on the same chip at the same time. Due to various considerations such as area and cost, such systems often share resources between processing units in a shared bus manner.
  • a request is made to the bus, and a device that requires data transfer is called a master device; and a target device that the master device requires data transfer with is called a slave device.
  • a multi-device system there may be two or more master and slave devices.
  • only one master device can use the system bus at the same time.
  • the master device Before the master device uses the system bus, it often sends out a bus usage request. After the bus is arbitrated and authorized, the master device can start to control the bus. Then, the master device issues the address and data, sends the data to the corresponding address of the slave device through the bus or reads the data from the corresponding address of the slave device, until the data transfer operation between the master device and the slave device is completed. bus.
  • each time the master uses the bus it always issues a single address, so only a single data whose destination is the same address of the same slave can be sent.
  • the bus use request is issued again, and arbitration is again performed by the bus.
  • a data transmission system as disclosed in a Chinese patent (Patent No. 86108261).
  • the data transfer system is used to transfer data from the I/O (input/output) device to the main memory, the data is first sent by the I/O device 16 through the data bus 40 to the input buffer 30, and then at the address indicated by the address register. Store the data in the buffer. At this time, the address register 28 and the count register are respectively updated.
  • address register 28 When data is written in the forward direction, address register 28 is incremented by one, and count register 32 is decremented by one. When data is read back, address register 28 is decremented by one, and count register 32 is still decremented by one. In this data transfer system, if the master device needs to continuously send multiple data, the first bus request is sent from the master device to the completion of all the numbers.
  • the bursty data transfer method is an improvement to this single data transfer method.
  • This method of data transmission can continuously transmit a large amount of data, but there are still some drawbacks, because bursty data transmission requires data to be at consecutive addresses. That is to say, if the master device reads the operation, the data to be read should be on consecutive adjacent addresses of the same slave device. If the master device writes, the transmitted data must be consecutive neighbors sent to the same slave device. On the address. If the address of the received data is not continuous, the master device is also required to issue a bus usage request again, and the bus arbiter re-arbitrates.
  • the present invention proposes a new bus system in which a data burst operation is performed by means of a stream burst.
  • An object of the present invention is to provide a data transfer method and a data transfer system in which stream burst data transfer is employed to effectively improve bus use efficiency.
  • a data transfer method comprising: performing a data transfer operation between a master device and a slave device via a bus, the data transfer operation including a stream burst data transfer operation, the method comprising the steps of:
  • the master device authorized by arbitration performs a stream burst data transfer operation and simultaneously sends a bus control signal to the bus, the stream burst including at least one segment burst;
  • the CONT signal indicates that a segment burst in a stream burst does not end
  • the LAST signal indicates a stream burst End
  • the intermediate signal represents the end of a segmented burst in a stream burst, and the stream burst has not ended
  • bus control signal is an intermediate signal, detecting whether there is a new higher level bus request from another master device
  • step a The master device authorized by arbitration preferentially performs data transfer operations; h.
  • the bus control signal is a LAST signal, the operation of step a is returned.
  • a data transfer system for performing a data transfer operation between a master device and a slave device via a bus, the data transfer operation including a stream burst data transfer operation, the system Includes:
  • a judging device configured to determine, by the master device, which one of a CONT signal, a LAST signal, and an intermediate signal, wherein the CONT signal indicates that a segment burst in a stream burst does not end,
  • the LAST signal represents the end of a stream burst, the intermediate signal represents the end of a segmented burst in a stream burst, and the burst has not ended;
  • a detecting device configured to detect, when the determining device determines that the bus control signal is an intermediate signal, whether a host device other than the current master device issues a new higher level bus request;
  • Arbitration means arbitration means for arbitrating the next segment burst request in the current burst operation of the master device and the higher level bus request of the other master device measured by the detecting means;
  • the data transfer operating means performs the data transfer operation between the authorized master device and the slave device via the bus according to the arbitration result of the arbitration device.
  • data is transmitted in the form of a stream burst, and data transmitted by the stream burst does not require address continuity, and thus can be transmitted in a large amount without being restricted by non-adjacent data transfer addresses or different target slave devices. Data, which improves the efficiency of the bus.
  • the corresponding priority levels are respectively set corresponding to the segment bursts in the stream burst, not only during the same stream burst operation, but also according to The priority level is processed in sequence to process the segmentation burst; and, in the process of a stream burst operation, if a new stream burst has a higher priority segment burst to issue a bus usage request, Give priority to respond.
  • the present invention preferably ensures that a data transfer operation having a higher priority level can obtain a priority response in this manner.
  • FIG. 1 is a block diagram showing a bus system according to an embodiment of the present invention.
  • Figure 2 is a schematic diagram showing the assignment of slave addresses of the bus system shown in Figure 1;
  • Figure 3 is a block diagram showing an arbiter of the bus system shown in Figure 1;
  • Figure 4 is a flow chart showing a stream burst form data transfer operation in accordance with the present invention;
  • Figure 5 is a timing diagram showing signals in an uninterrupted data transfer operation in accordance with one embodiment of the present invention;
  • FIG. 6 is a timing diagram showing signals in an interrupted data transfer operation in accordance with one embodiment of the present invention.
  • FIG 7 is a block diagram showing a data transfer system for executing the flow of the data transfer operation shown in Figure 4; detailed description
  • the bus system of the present invention includes a master device and a slave device, and has an arbiter for arbitrating bus usage requests of the master device.
  • the arbitrator arbitrates and grants to the master device
  • the master device reads and writes to the slave device through the bus in a Stream Burst manner.
  • the sequence of signals that the master sends a bus request to the arbiter includes a sequence of ordered control signals to indicate the operational status of the data transfer.
  • the data signal sequence sent by the master device may include multiple single data (Single Data), and may also include multiple bursts of discontinuous destination addresses (Burst), and multiple single data addresses of different slave devices. And sudden.
  • the sequence of data signals sent by the master device in the present invention is defined as a stream burst. Each stream burst contains at least one segmented burst.
  • a segmentation burst can be a single piece of data or a burst.
  • a burst is a sequence of consecutive and aligned data, and the length is an
  • the data transmission operation status that the control signal sent by the master device can mark includes at least the following categories: one segment burst does not end; one stream burst has ended; one stream burst does not end and one segment burst has End.
  • the corresponding control signals are CONT, LAST and intermediate signals. Wherein, the CONT signal indicates that one segment burst in one stream burst does not end; the LAST signal indicates the end of a stream burst; the intermediate signal indicates the end of a segment burst in a stream burst, and the stream The hair is not over yet.
  • the third class data transfer operation state can be further divided into two categories: , a stream burst does not end and the current segment burst has ended, and the next segment burst and the current segment burst access are the same slave device; the other is a stream burst. The end and the current segmentation burst have ended, and the next segment burst and the current segment burst access are different slave devices.
  • the intermediate signals are respectively a SAME signal and a DIFF signal, wherein the SAME signal indicates the end of one segment burst in one stream burst, and the next slave device is predicted to be the same slave burst as the segment burst access. And the access request has the same level; the DIFF signal indicates the end of one segment burst in one stream burst, and predicts that the next segment burst and the segment burst access have different levels of different slave devices or access requests.
  • the signal sequence in which the master device issues a bus usage request to the arbiter also includes a control signal to set a certain level for the bus usage request.
  • the level control signals are configured by software according to the priority level of the corresponding transfer operation of the segment bursts, and are sequentially transmitted in the order of the corresponding data transfer operations.
  • the priority level of the bus usage request is determined by the level control signal, and the bus arbiter can determine the order of the response requests directly based on the level of the bus usage request.
  • the arbiter will enter the arbitration state according to the control signal completed by the flag segment burst, and will arbitrate when the arbiter finds other higher level bus requests; The arbitration state is terminated when no other higher-level bus request is found, and the original burst transmission operation is continued.
  • the bus can respond to a segment burst that is not in the stream burst and has a higher priority during a stream burst operation, and after the segment burst operation with the higher priority level ends Return to the original stream burst operation site and continue the original stream burst operation.
  • a bus system of the present invention includes a bus 101, and a master device A 102, a master device B 103, a slave device A 104, a slave device B 105, and a slave device C 106 are respectively connected to a bus 101, and data is shared by a bus. Transfer operation.
  • a bus arbiter 107 is provided on the bus 101 to be coupled to the master device A 102 and the master device B 103, respectively, for arbitrating the bus usage request of the master device.
  • the number of the request slave device that the master device sends to the arbiter 107 is indicated by the MDstnum signal.
  • An exemplary description is made with three slave devices, and Table 1 shows the separate encoding of the three slave devices. Table 1
  • the present invention has no limitation on the number of master devices and slave devices. Accordingly, the encoding of the MDstnum signal can also be adjusted according to the number of slave devices actually used.
  • the address assignment of the three slave devices is shown in Figure 2, slave device A is 00 - 7F, slave device B is 80-1FFF, and slave device C is 2000-FFFF.
  • the bus request signal line MReq[l:0] of the master device and the control signal line MLast[l:0] are connected to the arbiter 107, respectively.
  • Fig. 1 in order to clearly show the MLast signal line and the MReq signal line, other signal lines are omitted.
  • each signal line is provided with a special connection line for each signal to realize the transmission of each signal.
  • the signal transmission can also be implemented by a bus pipeline method or the like. Lose.
  • Bus Usage Request Signal MReq includes four types, namely IDLE, REQ, CREQ and LREQ, whose decoding and meaning are shown in Table 2. Table 2
  • the REQ signal is a general read/write request, and LREQ and CREQ are higher in priority than REQ. Therefore, if the MReq issued by the master device A 102 and the master device B 103 is CREQ or LREQ, the response can be obtained more quickly than the REQ.
  • the LREQ request is a special type of request, which requests an atomic operation of a read and write operation. Since the read and write operations need to be performed continuously, the bus will not respond to other LREQs during an LREQ response, so It is set to a request with a higher priority.
  • the bus use request signal MReq can be flexibly set by programming or the like at each data transfer, so the priority level of the bus request issued by the master device can be determined according to the actual demand at each data transfer.
  • the IDLE type request is set in this embodiment to prevent the MReq signal line from being disturbed by the outside world due to the unstable state in the floating state when there is no bus request signal, thereby ensuring the stability of the system on the one hand.
  • the bus usage request signal MReq can be set to a certain level as needed, and the encoding can be changed accordingly, as will be readily understood and implemented by those skilled in the art.
  • the control signal used to transmit the control signal line MLa S t[l:0] marks the state of the data transfer operation requested by the master device.
  • four states are defined for the data transfer operation, including CONT, SAME, DIFF, and LAST, the encoding and meanings of which are shown in Table 3.
  • the CONT signal indicates that a segmented burst is still in the process of transmission, so the data transfer address corresponding to the CONT signal is continuous, neither receiving a new address nor re-arbitrating.
  • the LAST signal indicates that a complete stream burst has been transferred. In this case, if the data transfer operation is to be performed, the arbiter 107 is required to re-arbitrate the bus use request. Both the SAME and DIFF signals indicate that a segmented burst has been transmitted and a stream burst has not yet ended.
  • the SAME signal is used to predict the next segmented burst and the same slave device as the segmented burst access, except that the address and the segment burst may be discontinuous, and the next segment burst Same as the level of the burst access request of this segment, that is, both REQ or CREQ.
  • the DIFF signal is used to predict that the next segment burst and the segment burst access are different slave devices, or the next segment burst and the segment burst access request are not of the same level.
  • the address range returned by the arbitration site is within the same device address range, so all requests of the level REQ in a stream burst can only access the same slave. device.
  • control signal MLast can also be adjusted according to the type of data transfer operation state actually required.
  • the data that can be transmitted by the stream burst data transmission method of the present invention includes data in a single data and burst form.
  • the stream burst mode does not require that the address of the data transfer be always continuous, that is, the data in the form of single data and bursts may not be at consecutive addresses.
  • the corresponding slave device is required to receive data in burst form.
  • Table 4 and Table 7 illustrate the data transfer form of the stream burst by way of example.
  • This request in Table 4 is issued to slave B 105.
  • the signal sequence for this request will be viewed from device B 105 as a stream burst consisting of one segmented burst, and this segmented burst includes 8 consecutive address data.
  • table 5
  • This request in Table 5 is issued to slave A 104.
  • the signal sequence of this request will be formed from device A 104 as a stream burst consisting of 4 segment bursts, each of which includes 2 consecutive address data.
  • Table 6
  • the signal sequence for this request in Table 6 is a stream burst consisting of 4 segment bursts, each segment burst comprising 2 consecutive address data.
  • the level of the access request of the second segment burst and the first segment burst is different, so the MLast signal at the end of the first segment burst is DIFF; similarly, The fourth segment burst and the third segment burst access request The level is different, so the MLast signal at the end of the third segment burst is DIFF.
  • the second segment burst and the third segment burst have the same level of access requests, and both access slave C 106, so the MLast signal at the end of the second segment burst is SAME.
  • the signal sequence for this request in Table 7 is a stream burst consisting of 4 segment bursts, each segment burst comprising 2 consecutive address data.
  • the second segment burst and the first segment burst have the same level of access requests, and both access slave B 105, so the MLast signal at the end of the first segment burst is SAME; the second The level of access requests for the segmentation burst and the third segment burst are different, and the slave devices accessed are different, so the MLast signal at the end of the second segment burst is DIFFo, here, the third score
  • the segment burst access request level is CREQ, not REQ, so it can access different slave devices with its previous segment burst; and the fourth segment burst and the third segment burst access request The level is the same, but the slave devices accessed are different, so the MLast signal at the end of the third segment burst is also DIFF.
  • the arbiter 107 Corresponding to the hierarchical level of the bus request, the arbiter 107 also sets different arbitration opportunities for the arbitration of the bus usage request. There are two arbitration opportunities in this embodiment, namely CREQ arbitration timing and REQ arbitration timing. At the REQ arbitration occasion, the arbiter 107 can arbitrate various types of bus requests issued by the respective master devices, including CREQ, REQ, and LREQ; and in the CREQ arbitration timing, the arbiter 107 can only issue CREQ and LREQ for each master device. Wait for a higher priority bus request to arbitrate.
  • a decoder 1071, a buffer 1072, and an arbitration state machine 1073 are provided in the arbiter 107.
  • the decoder 1071 is configured to decode the request signals such as the MReq signal, the MLast signal, and the MDstnum signal sent by the selected master device after arbitration, and send them to the corresponding master device and the slave device.
  • the arbitration state machine 1073 is used to select the appropriate arbitration opportunity to arbitrate the bus usage request issued by the master device and decide to respond to the device.
  • the arbitration state machine 1073 further includes a shield 1074 and a controller 1075.
  • the arbiter 107 first detects the MReq signal, and if it finds that there is an LREQ request, it immediately checks to see if the bus 101 is in a latched (LOCK) state. Generally, an LREQ is being performed on the bus 101. When reading and writing atomic operations, bus 101 automatically enters the latched state. If the bus 101 is in the latched state at this time, the current LREQ read request will be ignored.
  • LOCK latched
  • the MLast signal requested by each bus is decoded by the decoder 1071 to produce an ALast signal.
  • the ALast signal also includes four types of DIFF, SAME, LAST, and CONT.
  • the bus 101 continues the data transfer operation, and the arbiter 107 does not perform a new arbitration.
  • the arbiter 107 When the ALast signal is DIFF or SAME, a stream burst does not end. At this time, the arbiter 107 will issue a higher level arbitration enable signal ACREQ-arb signal. If there is no CREQ request or LREQ request in the MReq signal, but only the REQ request or IDLE exists, the arbiter 107 does not arbitrate the bus request issued by the master device, and the stream burst is not interrupted, but continues to use the bus 101. Perform data transfer operations. If there is a CREQ request or an LREQ request in the MReq signal, the arbitrator 107 will enter the CREQ arbitration opportunity.
  • the arbiter 107 When the ALast signal is LAST, a complete stream burst has ended. At this time, the arbiter 107 will simultaneously issue a higher level arbitration enable signal ACREQ-arb signal and a lower level arbitration enable signal AREQ_arb signal. If there is no REQ request, CREQ request, and LREQ request in the MReq signal, the arbiter 107 enters a wait state; if there is no CREQ request or LREQ request in the MReq signal, but only the REQ request exists, the arbiter 107 enters the REQ arbitration occasion; If there is a CREQ request or an LREQ request in the MReq signal, the arbiter 107 will enter the CREQ arbitration occasion.
  • the arbiter 107 will use a general algorithm to arbitrate requests with priority levels CREQ and LREQ, select a CREQ request or an LREQ request from it, and transmit an authorization signal to the master device that issued the request.
  • the data transfer operation starts after the authorization signal.
  • the arbiter uses a general algorithm to arbitrate the REQ request sent by each master device, select a REQ request from it, and transmit an authorization signal to the master device that issued the request, then the master device starts data transmission. .
  • the general algorithm herein refers to a single-loop arbitration algorithm or other arbitration algorithm known to those skilled in the art, and details are not described herein.
  • the mask 1074 is set corresponding to each MReq signal sent to the arbiter 107.
  • Each of the shields 1074 is provided with one
  • the controller 1075 in the arbiter 107 sets the CREQ-En signal terminal, and performs a logical operation operation on the MReq of the input terminal after the CREQ-En signal, and then requests the REQ level.
  • the signal is masked off, and the CREQ or LREQ level request letter is sent. The number is completely passed.
  • both the AGrant and AMnum signals indicate the signals sent by the arbiter 107 after being arbitrated by the decoder 1071, both of which are shared for use by all the master devices.
  • the AGrant indicates the signal that the arbiter 107 responds to the master device and the slave device, and the AMnum signal is used to indicate the code number of the master device authorized by the arbiter 107 to use the bus.
  • the code numbers of the master device A 102 and the master device B 103 are 1 and 2, respectively.
  • the decoder 1071 also sends out an ASNum signal to indicate the target slave of the data transfer operation.
  • the MLast signal sent by the master device that is performing the data transfer operation is LAST; before the end of a segment burst, the MLast signal sent by the master device that is performing the data transfer operation is SAME or DIFF.
  • the arbiter 107 After the arbitration by the arbiter 107, if the ALast signal is a LAST, SAME or DIFF signal, then the arbiter 107 enters the arbitration state accordingly. That is, after each stream burst and segmentation burst ends, the arbiter 107 will enter the arbitration state.
  • the AGrant signal appears to be in a valid state, which is shared between the master device and the slave device.
  • LREQ and CREQ have higher priority levels than REQ, and therefore, when one stream burst is not ended, but only one segment burst ends, the arbiter 107 re-arbitrates, if other masters If the bus request MReq signal sent by the device is LREQ or CREQ level, then it can participate in arbitration; if the other host device issues a bus request MReq signal at the REQ level, the request will be ignored and the original flow will continue. The next burst of bursts.
  • the bus request of the other master device participates in the bus arbitration, and after the arbitration obtains the bus use authorization of the arbiter, the stream burst of the current master device
  • the unfinished operation will be pushed into the buffer 1072 of the arbiter 107.
  • the bus will return to the site to re-arbitrate.
  • Figure 4 depicts the flow of data transfer operations in the form of a stream burst.
  • step 401 in the state where there is no data transfer operation, if there is a master device issuing a bus use request, the arbiter 107 arbitrates all bus requests in step 402. After the arbitration, the process proceeds to step 403. A bus requesting arbitration is authorized, and the corresponding master device starts to occupy the bus for data transfer operation, and the master device issues the bus control signal MLast.
  • Step 404 and step 403 are performed synchronously. In this step, when the arbiter 107 selects the bus request, accordingly, the decoder 1071 in the arbiter 107 will send the decoded ALast signal.
  • Steps 405, 406, 407 and step 408 All of them are judged by the control signal ALast, and it is judged which one of the four types listed in this embodiment.
  • the arbiter 107 performs synchronization. If it is determined in step 405 that ALast is a CONT signal indicating that a segmentation burst has not ended, then step 410 is entered to continue the data transmission operation of the current segmentation burst. If the result of the determination in step 406 is that the ALAST is the SAME signal or the judgment result of the step 407 is the DIFF signal, it indicates that the current stream burst has not ended yet, but one segment burst has been transmitted.
  • step 412 is also required to detect if a new higher level bus request has been made. If the condition of step 412 is satisfied, the arbiter arbitrates the next segment burst request in the current stream burst with the new higher level bus request in step 413. After arbitration here, if the condition of step 414 is not met, then step 416 is entered and the current stream burst data transfer operation continues. If the condition of step 414 is satisfied and the bus authorization is obtained for the other master devices, the data transfer operation of the other master devices is performed first in step 415.
  • step 416 After the data transfer operation of the other master devices ends, the process proceeds to step 416 to return to the scene of the original stream burst, and the next segment burst data transfer operation in the original stream burst is continued. If the ALast signal is determined to be LAST via step 408, the current stream burst ends and the arbiter returns to the state of step 402 to arbitrate all bus requests.
  • Example 1 The following is a further explanation of the data transfer operation in the form of a stream burst in two examples.
  • Example 1
  • Figure 5 shows the timing diagram for each signal in an uninterrupted data transfer.
  • the MAdd signal indicates the address of the data transfer; the MData signal indicates the transmitted data; and the MCmd signal is the forward transfer command, which is a low read high write in this embodiment. It can be seen from Figure 12 that this is a complete stream burst with a total of three segment bursts.
  • the MLast signal before the end of the first segment burst is SAME, that is, the destination address of the data transfer is no longer continuous, but it is still in the same slave device. Therefore, in the second segment burst, the MDstnum signal is the same as the first segment burst, both slave A (its code is 0), and the Madd signal is 0x20, with the first segment burst target address. Discontinuous.
  • the third segment burst is a segmented burst of the CREQ level, and the MLast signal before the end of the second segment burst is DIFF, so the target address of the third segment burst is at slave C (its code For 2), the slave segment destination address is different from the second segment.
  • the AGnmt signal and the AMnum signal are signals from the arbiter 107.
  • the MLast signal before the end of the first segmentation burst is SAME, indicating that the data transfer destination address of the next segment burst is still in the same slave device, so the AGrant signal remains in the active state (in this embodiment, the high level is high).
  • the status is active), indicating that the arbiter 107 still responds to the master device.
  • the MLast signal before the bundle is DIFF, indicating that the data transfer destination address of the next segment burst is at a different slave device, and the arbitrator 107 cannot know the MLast signal within one clock cycle after the DIFF signal because arbitration judgment is required.
  • the target slave device so that it cannot respond to the master device, so the AGmnt signal is in the low state for the first clock cycle of the segmented burst after the DIFF signal, and the arbiter is in the next clock cycle. 107
  • the master device After receiving the MDstnum signal from the master device, the master device responds, and the AGrant signal is again in a high state until the stream burst ends completely.
  • the AMnum signal continues to be 1, which is the master device in this example with Master A being the current burst.
  • Example two
  • FIG. 6 shows the timing diagram of each signal in an interrupted data transfer.
  • MReq1, MLastl, MAddl, MDatal, MDstnum1, MCmdl represent the request signal of the data transfer operation performed by the master device A; and MReq2, MLast2, MAdd2, MData2, MDstnum2, MCmd2 represent the master device B.
  • the ALast signal is the signal sent by the arbiter 107 in response to MLastl and MLast2.
  • the primary stream burst transfer operation of the master device A in FIG. 6 is exactly the same operation as the master device in FIG. 5, but since the master device A is subjected to a higher level of other master devices during the current stream burst transfer operation
  • the interrupt caused by the bus request the timing of the stream burst of the master device A also produces some changes.
  • the bus request for master device A in Figure 6 is a complete stream burst, including four segment bursts.
  • master device A in Figure 6 has a delay in the third segment burst because the third segment burst of master A is interrupted by a CREQ request from master B.
  • MLastl is the SAME, and the arbiter 107 enters the arbitration state, but the request MReq2 issued by the master device B at this time is the REQ level.
  • the REQ level request is specified.
  • a stream burst cannot be interrupted, so master A will continue to perform the second segment burst operation of the current stream burst.
  • the MLast1 signal is DIFF before the end of the second segment burst of the master device A, the arbiter 107 enters the arbitration state, and the request MReq2 issued by the master device B at this time is the CREQ level, and the third segment burst of the master device A
  • the arbiter 107 arbitrates both the CREQ level bus requests of the master device A and the master device B.
  • the request of the master device B in this example is authorized by the bus of the arbiter 107, so that the third segment burst at the master device A will be temporarily suspended, and the bus 101 first processes the bus request of the master device B.
  • the third segment burst operation of the master device A is pushed into the buffer 1072 of the arbiter 107 for temporary storage. After the bus request of master device B has been processed, the bus will return to the site, if there are no other new bus usage requests at this time. If arbitration is required, the third segment burst operation of the master device A is continued. It can also be seen from the figure that MAddl and MDatal have a delay in the third segment burst, and are waiting for the data transfer operation of the master device B during the delay period.
  • the AMmim signal of the arbiter 107 is 1 in the stream burst operation of the master device A, indicating that the master device performing the data transfer operation is the master device A; and after the bus use request authorization of the master device B, the AMmim signal also becomes 2, The master device indicating that the data transfer operation is in progress is the master device 8. After the bus request of the master device B is completed, the AMmim signal returns to 1, indicating that the bus returns to the original stream burst scene of the master device A, and continues the data transfer operation of the original stream burst.
  • Figure 7 is a block diagram showing a data transfer system for executing the flow of the data transfer operation shown in Figure 4;
  • the data transfer system is configured to perform a data transfer operation between the master device and the slave device via a bus, and the data transfer operation includes a stream burst data transfer operation.
  • the data transmission system includes a determining means 701 for determining which of the CONT signal, the LAST signal, the SAME signal and the DIFF signal is generated by the master device, and detecting means 702 for determining
  • the device 701 determines that the bus control signal is a SAME signal or a DIFF signal, it detects whether a host device other than the current master device issues a new higher level bus request; the arbitration device 703, the stream burst data for the current master device The next segment burst request in the transfer operation is arbitrated with a higher level bus request of the other master device measured by the detecting device; and the data transfer operation device 704 passes the arbitration result according to the arbitration device 703
  • the bus 101 performs the data transfer operation between the authorized master device and the slave device.
  • the arbitration device 703 can employ the arbiter shown in FIG.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Exchange Systems With Centralized Control (AREA)
  • Small-Scale Networks (AREA)

Description

数据传送方法和数据传送系统 技术领域
本发明涉及一种数据传送方法和数据传送系统。 尤其涉及一种在具有多主 设备的体系结构中， 利用总线在主设备与从设备之间快速有效地传送数据的方 法和系统。 背景技术
为了实现快速实时的信号处理， 计算机系统尤其是多处理器系统常常配置 了多个快速功能处理单元， 以便于同时进行相应的控制及数据处理。 系统中的 处理单元可能包括中央处理单元 （CPU) 、 数字信号处理器 （DSP) 和存储器 等各种设备。 特别是在片上系统中， 往往需要把大量的设备同时集成于同一块 芯片上。 出于面积和成本等各方面的考虑， 这种系统中常常以共享总线的方式 来实现各处理单元之间的资源共享。 在设备之间的数据传送中， 向总线发出请 求， 要求进行数据传送的设备称为主设备； 而主设备要求与之进行数据传送的 目标设备则称为从设备。 在多设备系统中， 主设备和从设备可能会存在两个或 两个以上。 为防止有多个设备同时使用系统总线而造成数据冲突， 在同一时间 内， 只能有一个主设备在使用系统总线。 主设备在使用系统总线前， 往往是先 发出总线使用请求， 待总线仲裁并授权后， 主设备才能开始控制总线。 然后， 主设备发出地址和数据， 通过总线将数据送往从设备的相应地址或从从设备的 对应地址处读取数据， 直到主设备与从设备之间的数据传送操作已全部完成才 会释放总线。
一般地， 主设备每次使用总线时， 总是发出单一的地址， 因而只能发送目 标是同一从设备同一地址的单一的数据。 当主设备需要发送目标是同一从设备 的不同地址或不同从设备的数据时， 就要再次发出总线使用请求， 并由总线再 次做出仲裁。如一件中国专利（专利号为 86108261 )揭示的一种数据传送系统。 采用该数据传送系统将数据从 I/O (输入 /输出）器件送入主存储器时， 先由 I/O 器件 16通过数据总线 40把数据送入输入缓冲器 30，然后在地址寄存器指示的 地址将数据存入缓冲器。 此时地址寄存器 28和计数寄存器分别进行更新动作。 正向写入数据时， 地址寄存器 28加 1， 计数寄存器 32减 1 ; 而反向读出数据 时， 地址寄存器 28减 1， 计数寄存器 32仍是减 1。 在这种数据传送系统中， 若主设备需要连续发出多个数据， 从主设备发出第一个总线请求到完成全部数
- 1 - 确 认 本 据的传送， 就可能需要消耗几个仲裁周期， 造成了总线使用效率低下， 数据传 送延时过长等弊病。
突发式的数据传送方式是对这种单一的数据传送方式所做出的改进。 这种 数据传送方式可以一次连续地发送大量的数据， 但也还是存在着一定的缺陷， 因为突发式的数据传送要求数据必须是在连续的地址上。 也就是说， 若是主设 备读操作， 则需要读取的数据应该在同一从设备的连续相邻的地址上， 若是主 设备写操作， 则发送的数据必须是送往同一从设备的连续相邻的地址上。 若接 收数据的地址不连续， 则同样需要主设备再次发出总线使用请求， 由总线仲裁 器再次进行仲裁。
为了克服上述缺陷， 本发明提出了一种新的总线系统， 其中采用流突发的 方式来进行数据传送操作。 发明内容
本发明的目的在于提供一种数据传送方法和数据传送系统， 其中采用流突 发式的数据传送以有效提高总线使用效率。
根据本发明的一个方面， 提供一种数据传送方法， 包括经由总线在主设备 与从设备之间进行数据传送操作， 所述数据传送操作包含流突发数据传送操 作， 所述方法包括如下步骤：
a. 对主设备发出的总线使用请求进行仲裁；
b .经仲裁获得授权的主设备进行流突发数据传送操作并同时向总线发出总 线控制信号， 所述流突发包含至少一个分段突发；
c 判断所述总线控制信号是 CONT信号、 LAST信号和中间信号中的哪一 种信号， 其中， CONT信号表示一个流突发中的一个分段突发没有结束， LAST 信号表示一个流突发的结束， 中间信号表示一个流突发中的一个分段突发的结 束， 而该流突发尚未结束；
d. 当判断所述总线控制信号是 CONT信号时， 继续当前流突发数据传送操 作的分段突发的数据传送操作；
e. 当判断所述总线控制信号是中间信号时， 检测是否有其它主设备发出的 新的较高级别的总线请求；
f. 当检测到其它主设备有新的较高级别的总线请求时， 对该请求与当前主 设备的流突发数据传送操作中的下一个分段突发请求进行仲裁；
g. 经仲裁获得授权的主设备优先进行数据传送操作； h. 当判断所述总线控制信号是 LAST信号时， 返回步骤 a的操作。
根据本发明的另一方面， 提供一种数据传送系统， 用以经由总线在主设备 与从设备之间进行数据传送操作， 所述数据传送操作包含流突发数据传送操 · 作， 所述系统包括：
判断装置，用以判断所述主设备发出的总线控制信号是 CONT信号、 LAST 信号和中间信号中的哪一种信号， 其中， CONT信号表示一个流突发中的一个 分段突发没有结束， LAST信号表示一个流突发的结束， 中间信号表示一个流 突发中的一个分段突发的结束， 而该琉突发尚未结束；
检测装置， 用以当所述判断装置判断所述总线控制信号是中间信号时， 检 测除当前主设备以外的其它主设备是否发出新的较高级别的总线请求；
仲裁装置，对当前主设备的流突发数据传送操作中的下一个分段突发请求 与所述检测装置测得的其它主设备的较高级别的总线请求进行仲裁的仲裁装 置； 以及 '
数据传送操作装置，根据所述仲裁装置的仲裁结果经由所述总线在获得授 权的主设备与从设备之间进行所述的数据传送操作。
一方面，本发明中以流突发形式传送数据，流突发传送的数据不要求地址连续， 因此可以不受不相邻的数据传送地址或不同目标从设备的限制，而一次性地发送大 量数据， 从而较好地提高了总线的使用效率。
另一方面， 在流突发数据传送操作中， 由于对应于流突发中的分段突发分别设 定了相应的优先权级别， 因此， 不但在同一个流突发操作过程中， 可根据优先权级 别的高低来先后处理分段突发； 并且， 在一个流突发操作进行过程中， 若有新的流 突发中有优先级别较高的分段突发发出总线使用请求， 也能优先做出响应。本发明 以这种方式较好地保证了具有较高优先级别的数据传送操作能够得到优先响应。 附图说明
以下附图为对本发明示例性实施例的辅助说明， 结合以下附图对本发明实 施例的阐述， 是为了进一步披露本发明的特征所在， 但并不限制本发明。 本发 明的其它的目的、 特点和优点在以下的描述中将变得更加清楚。 附图中相同的 符号代表实施例中相应的元件或步骤， 其中：
图 1是表示根据本发明的一个实施例的总线系统的结构图；
图 2是表示图 1所示总线系统的从设备地址分配示意图；
图 3是表示图 1所示总线系统的一个仲裁器的结构图； 图 4是表示根据本发明的流突发形式数据传送操作的流程图； 图 5是表示根据本发明的一个实施例的无中断的数据传送操作中各信号的 时序图；
图 6是表示根据本发明的一个实施例的有中断的数据传送操作中各信号的 时序图； 和
图 7是表示执行图 4所示数据传送操作流程的一个数据传送系统的方框图。 具体实施方式
本发明的总线系统包括主设备和从设备， 并有一仲裁器， 用以对主设备的 总线使用请求做出仲裁。 当仲裁器仲裁之后授权给主设备， 主设备以流突发 (Stream Burst)的方式通过总线向从设备进行读写操作。 主设备向仲裁器发出总 线请求的信号序列中包括一连串有序的控制信号， 用以标志数据传送的操作状 态。 其中主设备发出的数据信号序列可以包含多个单一数据 （Single Data) ， 也'可以包含多个目标地址不连续的分段突发 (Burst), 以及多个目标地址在不同 从设备的单一数据和突发。 本发明中主设备发出的数据信号序列定义为流突发 形式。 每个流突发至少包含一个分段突发。 分段突发可能是一个单一数据， 也 可能是一个突发。 其中的突发是指一连串地址连续和对齐的数据， 且长度是 2 的整数次幂。
主设备所发出的控制信号可以标志的数据传送操作状态至少包括如下几类：一 个分段突发没有结束；一个流突发已经结束；一个流突发并未结束而一个分段突发 己经结束。 其对应的控制信号分别为 CONT、 LAST和中间信号。 其中， CONT信 号表示一个流突发中的一个分段突发没有结束； LAST 信号表示一个流突发的结 束； 中间信号表示一个流突发中的一个分段突发的结束， 而该流突发尚未结束。本 发明的一个实施例中，为了满足在同一个流突发中的分段突发可以访问不同的从设 备， 对于上述第三类数据传送操作状态， 还可再分为两类： 一类是， 一个流突发并 未结束而当前的分段突发已经结束，且下一个分段突发和当前的分段突发访问的是 同一个从设备； 另一类是一个流突发并未结束而当前的分段突发已经结束，且下一 个分段突发和当前的分段突发访问的是不同的从设备。因此， 上述中间信号又分别 为 SAME信号和 DIFF信号， 其中， SAME信号表示一个流突发中的一个分段突发 结束， 预告下一个分段突发和本分段突发访问同样的从设备且访问请求的等级相 同； DIFF信号表示一个流突发中的一个分段突发的结束， 预告下一个分段突发和 本分段突发访问不同的从设备或者访问请求的等级不同。 主设备向仲裁器发出总线使用请求的信号序列中还包括用以对总线使用请求 设定了一定的等级的控制信号。这些等级控制信号按照所对应的分段突发的传送操 作的优先级别而由软件配置而定，并按照所对应的数据传送操作的先后顺序依次传 送。总线使用请求的优先级别由等级控制信号来决定，而总线仲裁器可直接根据总 线使用请求的级别来确定响应请求的先后次序。流突发的每一个分段突发结束时仲 裁器将会根据标志分段突发完成的控制信号进入仲裁状态，当仲裁器发现有其他较 高级别的总线请求时就进行仲裁；当仲裁器未发现有其他较高级别的总线请求时就 结束仲裁状态， 而继续原流突发的传送操作。这样， 总线可以在一个流突发操作过 程中对不在此流突发之内而优先级别较高的分段突发做出响应，并在该具有较高优 先级别的分段突发操作结束后返回原流突发操作现场， 继续原流突发操作。
图 1表示根据本发明的一个实施例的总线系统的结构图。 参照图 1， 本发 明的总线系统包括总线 101， 主设备 A 102、 主设备 B 103、 从设备 A 104、 从 设备 B 105和从设备 C 106分别与总线 101相连， 以共享总线的方式进行数据 传送操作。总线 101上设有总线仲裁器 107分别与主设备 A 102和主设备 B 103 相耦连， 用以对主设备的总线使用请求作出仲裁。
在本实施例中， 以 MDstnum信号来表示主设备送给仲裁器 107的请求从 设备的号码。 以三个从设备做示例性的说明， 表 1表示对这三个从设备的分别 编码。 表 1
Figure imgf000007_0001
而本发明对于主设备与从设备的数量并无限制， 相应地， MDstnum信号的 编码也可根据实际使用的从设备的数量做调整。 三个从设备的地址分配如图 2 所示， 从设备 A为 00 - 7F, 从设备 B为 80-1FFF, 从设备 C为 2000-FFFF。
主设备的总线请求信号线 MReq[l :0]与控制信号线 MLast[l :0]分别与仲裁 器 107相连。 图 1中为了清晰地表现出 MLast信号线和 MReq信号线， 而省略 了其他的信号线。 本实施例中各信号线是以对每一个信号设置专门的连线来实 现各信号的传输， 在其他实施例中也可以总线流水线方式等来实现各信号的传 输。
总线请求信号线 MReq[l :0]在主设备需要进行数据传送操作时，向仲裁器发 出总线使用请求。 总线使用请求信号 MReq包括四种类型， 即 IDLE、 REQ, CREQ和 LREQ， 其译码和含义如表 2所示。 表 2
Figure imgf000008_0001
总线使用请求信号 MReq中， REQ信号为一般的读写请求， 而 LREQ和 CREQ比 REQ优先级要高。 因此， 如果主设备 A 102和主设备 B103发出的 MReq为 CREQ或 LREQ, 较之 REQ往往能更快速地获得响应。
其中， LREQ的请求是一类比较特殊的请求， 它请求的是一个读写操作的 原子操作， 由于该读写操作需要连续进行， 在一个 LREQ响应期间， 总线将不 能响应其他的 LREQ, 因此将其设为一种优先级别较高的请求。
总线使用请求信号 MReq可以在每一次数据传送时由编程等方式灵活设 定， 因此主设备发出的总线请求的优先权等级可以在每一次数据传送时按实际 需求而决定。
本实施例中设置 IDLE类型的请求是为了防止在没有总线请求信号时 MReq 信号线由于在悬浮状态的不稳定情况下而受到外界干扰， 从而从一方面保证了 系统的稳定。
后文将对分等级的总线请求的使用作进一步说明。
在其它实施例中， 总线使用请求信号 MReq可以按需要设定一定的等级， 其编码也可随之改变， 对此本技术领域人员易于理解和实现。
控制信号线 MLaSt[l :0]用来传送的控制信号标志了主设备要求进行的数据 传送操作的状态。 本实施例中， 为数据传送操作定义了四种状态， 包括 CONT、 SAME, DIFF和 LAST, 其编码和含义如表 3所示。 表 3
Figure imgf000009_0001
在数据传送操作中， 以 CONT信号来表示一个分段突发还在传送过程中， 因此 CONT信号所对应的数据传送地址还是连续的， 既不需要接收新的地址， 也不需要重新做仲裁。 而 LAST信号则表示一个完整的流突发已经传送完成， 此时 若要进行数据传送操作，就需要仲裁器 107重新对总线使用请求做仲裁。 而 SAME和 DIFF信号均表示一个分段突发已经传送完成， 而一个流突发尚未 结束。 其不同之处主要在于， SAME信号是用来预告下一个分段突发和本分段 突发访问同样的从设备， 只是地址和本分段突发可能不连续， 并且下一个分段 突发和本分段突发访问请求的等级相同， 即都为 REQ或 CREQ。 DIFF信号则 是用来预告下一个分段突发和本分段突发访问不同的从设备， 或者是下一个分 段突发和本分段突发访问请求的等级不相同。
在本实施例中， 只是出于使实施更为简单的考虑， 规定仲裁现场返回的地 址范围在同一设备地址范围内， 因此一个流突发中所有等级为 REQ的请求都 只能访问相同的从设备。
类似地， 控制信号 MLast的编码也可根据实际需要的数据传送操作状态的 种类做调整。
本发明的流突发数据传送方式可传送的数据包括单一数据和突发形式的数 据。 流突发方式并不要求数据传送的地址是始终连续， 也就是说， 这些单一数 据和突发形式的数据可以不是在连续地址上。 而对于每一个以突发形式的数据 传送操作， 要求相应的从设备能够接收突发形式的数据。
表 4一表 7以示例来说明流突发这种数据传送形式。 表 4
Figure imgf000010_0001
表 4中的这个请求是向从设备 B 105发出的。 这个请求的信号序列将被从 设备 B 105看成是由一个分段突发构成的流突发， 而这个分段突发包括 8个连 续地址的数据。 表 5
Figure imgf000010_0002
表 5中的这个请求是向从设备 A 104发出的。 这个请求的信号序列将被从 设备 A 104着成是由 4个分段突发构成的流突发， 其中每个分段突发都包括 2 个连续地址的数据。 表 6
Figure imgf000010_0003
表 6中的这个请求的信号序列是由 4个分段突发构成的一个流突发， 每 个分段突发包括了 2个连续地址的数据。 在这个流突发中， 第二个分段突发和 第一个分段突发的访问请求的等级有所不同， 因此第一个分段突发结束时的 MLast信号是 DIFF; 类似地， 第四个分段突发和第三个分段突发的访问请求的 等级有所不同， 因此第三个分段突发结束时的 MLast信号是 DIFF。而第二个分 段突发和第三个分段突发的访问请求的等级相同， 并且都是访问从设备 C 106, 因此第二个分段突发结束时的 MLast信号是 SAME。 表 7
Figure imgf000011_0001
表 7中的这个请求的信号序列是由 4个分段突发构成的一个流突发， 每个 分段突发包括了 2个连续地址的数据。 第二个分段突发和第一个分段突发的访 问请求的等级相同， 并且都是访问从设备 B 105， 因此第一个分段突发结束时 的 MLast信号是 SAME; 第二个分段突发和第三个分段突发的访问请求的等级 不相同， 且访问的从设备也不同， 因此第二个分段突发结束时的 MLast信号是 DIFFo 在这里， 第三个分段突发的访问请求等级为 CREQ, 而非 REQ， 所以可 以与它之前的分段突发访问不同的从设备； 而第四个分段突发和第三个分段突 发的访问请求的等级相同， 但访问的从设备不同， 因此第三个分段突发结束时 的 MLast信号也是 DIFF。
与总线请求的分等级相对应， 仲裁器 107对总线使用请求的仲裁也设定了 不同的仲裁时机。本实施例中仲裁时机有两种， 分别为 CREQ仲裁时机和 REQ 仲裁时机。 在 REQ仲裁时机， 仲裁器 107可以对各个主设备发出的各类总线 请求进行仲裁， 包括 CREQ、 REQ和 LREQ; 而在 CREQ仲裁时机里， 仲裁器 107只能对各个主设备发出的 CREQ和 LREQ等优先级别较高的总线请求做出 仲裁。
参见图 3，仲裁器 107中设有解码器 1071、缓冲器 1072和仲裁状态机 1073。 其中， 解码器 1071用来对仲裁后选中的主设备送来的 MReq信号、 MLast信号 和 MDstnum信号等请求信号进行解码并送给相应的主设备和从设备。 仲裁状 态机 1073用来选择合适的仲裁时机对主设备发出的总线使用请求进行仲裁并 决定做出响应的设备。 仲裁状态机 1073还进一步包括屏蔽器 1074和控制器 1075。
仲裁器 107先检测 MReq信号， 若发现存在 LREQ请求， 则立即查看总线 101是否处于锁存 （LOCK)状态。 一般地， 在总线 101正在进行一个 LREQ的 读写原子操作时， 总线 101会自动进入锁存状态。 若此时总线 101是在锁存状 态， 则当前的 LREQ的读请求将被忽略掉。
在仲裁器 107中进行仲裁后，各总线请求的 MLast信号经解码器 1071解码 产生的信号为 ALast信号。在本实施例中根据 MLast信号的类型，同样地， ALast 信号也包括 DIFF、 SAME、 LAST和 CONT四类。
当 ALast信号为 CONT时， 总线 101继续数据传送操作， 而仲裁器 107并 不进行新的仲裁。
当 ALast信号为 DIFF或 SAME时， 一个流突发并未结束。 此时， 仲裁器 107将发出一个较高级仲裁允许信号 ACREQ一 arb信号。如果 MReq信号中不存 在 CREQ请求或 LREQ请求， 而只存在 REQ请求或者为 IDLE, 则仲裁器 107 不对主设备发出的总线请求做仲裁， 此时流突发并不中断， 而是继续使用总线 101进行数据传送操作。 如果 MReq信号中存在 CREQ请求或 LREQ请求， 仲 裁器 107将进入 CREQ仲裁时机。
当 ALast信号为 LAST时， 一个完整的流突发己经结束。 此时， 仲裁器 107 将同时发出一个较高级仲裁允许信号 ACREQ—arb信号和一个较低级仲裁允许 信号 AREQ_arb信号。如果 MReq信号中不存在 REQ请求、 CREQ请求和 LREQ 请求， 则仲裁器 107进入等待状态； 如果 MReq信号中不存在 CREQ请求或 LREQ请求，而只存在 REQ请求，则仲裁器 107进入 REQ仲裁时机；如果 MReq 信号中存在 CREQ请求或 LREQ请求， 仲裁器 107将进入 CREQ仲裁时机。
在 CREQ仲裁时机内， 仲裁器 107将采用一般算法对优先级别为 CREQ和 LREQ的请求进行仲裁， 从中选出一个 CREQ请求或 LREQ请求， 并对发出该 请求的主设备传送授权信号， 主设备接到授权信号后开始数据传送操作。
在 REQ仲裁时机内， 仲裁器采用一般算法， 公平地对各个主设备发出的 REQ请求进行仲裁， 从中选出一个 REQ请求， 并对发出该请求的主设备传送 授权信号， 则主设备开始数据传送。
这里的一般算法， 指单循环仲裁算法或其他为本技术领域人员公知的仲裁 算法， 在此不再赘述。
在 CREQ仲裁时机内 REQ级别的请求将被忽略掉。 屏蔽器 1074对应于送 往仲裁器 107的每一个 MReq信号而设置。 每一个屏蔽器 1074设有一个
CREQ-En信号端， 进入 CREQ仲裁时机后， 仲裁器 107中的控制器 1075将 CREQ-En信号端置位， 通过把 CREQ-En信号与输入端的 MReq进行逻辑运算 操作后， 将 REQ级别的请求信号屏蔽掉， 而使 CREQ或 LREQ级别的请求信 号完整通过。
本实施例中， AGrant和 AMnum信号都表示仲裁器 107仲裁后经解码器 1071 送出的信号， 二者都为所有主设备共享使用。 其中 AGrant表示仲裁器 107对 主设备和从设备做出响应的信号， AMnum信号用来指出仲裁器 107授权使用 总线的主设备的编码代号。 在本实施例中， 主设备 A 102和主设备 B 103的编 码代号分别为 1和 2。 解码器 1071同时送出的还有 ASNum信号， 用来指出数 据传送操作的目标从设备。
在一个流突发结束前， 正在进行数据传送操作的主设备送出的 MLast信号 为 LAST; 在一个分段突发结束前， 正在进行数据传送操作的主设备送出的 MLast信号为 SAME或 DIFF。经仲裁器 107做出仲裁后， ALast信号若为 LAST、 SAME或 DIFF信号， 则相应地， 仲裁器 107进入仲裁状态。 也就是说， 在每 一个流突发和分段突发结束后， 仲裁器 107都将进入仲裁状态。 在仲裁结束并 授权主设备占有总线进行数据传送操作时， AGrant信号表现为有效状态， 该信 号为各主设备和从设备所共享。
在一个流突发未结束， 而一个分段突发结束时， 正在进行数据传送操作的 主设备以外的其他主设备可能由于发出较高优先级别的请求而通过仲裁获得 总线使用权。 在本实施例中， LREQ和 CREQ具有比 REQ更高优先权级别， 因 此， 在一个流突发未结束， 而仅仅是一个分段突发结束时， 由于仲裁器 107重 新进行仲裁，若其他主设备发出的总线请求 MReq信号为 LREQ或 CREQ级另 lj， 则可以参与仲裁；若其他主设备此时发出的总线请求 MReq信号仅仅是 REQ级 别， 则该请求将被忽略掉， 而继续进行原流突发的下一个分段突发。
若在一个流突发未结束， 而一个分段突发结束时， 其他主设备的总线请求参与 了总线仲裁， 并在仲裁之后获得了仲裁器的总线使用授权，则当前主设备的流突发 中未完成的操作将压入仲裁器 107的缓冲器 1072中。 在其他主设备的数据传送操 作完成后， 总线将返回现场重新进行仲裁判断。
图 4描述了一次流突发形式的数据传送操作流程。
从步骤 401幵始， 在没有数据传送操作的状态下， 如果有主设备发出总线 使用请求， 步骤 402中仲裁器 107对所有总线请求进行仲裁。 仲裁后进入步骤 403， 参与仲裁的一总线请求获得授权， 对应的主设备开始占用总线进行数据 传送操作， 同时该主设备发出总线控制信号 MLast。 步骤 404与步骤 403为同 步进行， 该步骤中， 当仲裁器 107选中该总线请求， 相应地， 仲裁器 107中的 解码器 1071将送出解码后的 ALast信号。 步骤 405、 406、 407以及步骤 408 均为对控制信号 ALast进行判断，判断是本实施例中所列四种类型中的哪一类。 在数据传送过程中， 由仲裁器 107同步进行。若在步骤 405中， 判断得出 ALast 为 CONT信号， 表示一个分段突发还未结束， 则进入步骤 410， 继续当前分段 突发的数据传送操作。若步骤 406的判断结果为 ALast为 SAME信号或者步骤 407的判断结果为 DIFF信号， 均表示当前流突发尚未结束， 但一个分段突发已 经传送完成。 此时仲裁器 107进入仲裁状态， 即步骤 411， 但同时还需要进行 步骤 412检测是否有新的较高级别的总线请求提出。 若步骤 412条件满足， 则 仲裁器在步骤 413中将当前的流突发中下一个分段突发请求与新的较高级别的 总线请求一起进行仲裁。 此处仲裁之后， 若不满足步骤 414的条件， 则进入步 骤 416， 当前流突发数据传送操作继续进行。 若满足步骤 414的条件， 为其他 主设备获得总线授权， 则先在步骤 415中进行其他主设备的数据传送操作。 在 其他主设备的数据传送操作结束后， 即进入步骤 416返回至原流突发的现场， 继续进行原流突发中的下一个分段突发数据传送操作。 若 ALast信号经过步骤 408判断为 LAST, 则当前流突发结束， 仲裁器回到步骤 402的状态， 对所有 总线请求做仲裁。
以下以两个示例对流突发形式的数据传送操作做进一步解释。 示例一：
图 5所示为一次无中断的数据传送中各信号的时序图。
其中， MAdd信号表示数据传送的地址； MData信号表示传送的数据； MCmd 信号为正向传送命令， 本实施例中为低读高写。 从图 12中可以看出这是一个 完整的流突发， 共包含三个分段突发。
第一个分段突发结束前的 MLast信号为 SAME, 即数据传送的目标地址不 再连续， 但仍旧在同一个从设备内。 因此第二个分段突发中， MDstnum信号同 第一个分段突发相同， 都为从设备 A (其代码为 0 ) ， 而 Madd信号为 0x20， 与第一个分段突发目标地址不连续。第三个分段突发为 CREQ级别的分段突发， 而第二个分段突发结束前的 MLast信号为 DIFF, 因此第三个分段突发的目标 地址在从设备 C (其代码为 2 ) ， 与第二个分段突发目标地址在不同的从设备。
AGnmt信号和 AMnum信号为仲裁器 107发出的信号。 在第一个分段突发 结束前的 MLast信号为 SAME, 表示下一个分段突发的数据传送目标地址仍旧 在同一从设备， 因此 AGrant信号维持有效状态 （在本实施例中以高电平状态 为有效状态） ， 表示仲裁器 107对该主设备仍旧有响应。 在第二个分段突发结 束前的 MLast信号为 DIFF， 指示下一个分段突发的数据传送目标地址是在不 同的从设备， 仲裁器 107在 DIFF信号之后的一个时钟周期内因为需要进行仲 裁判断而无法得知 MLast信号和目标从设备， 也就无法对主设备做出响应， 所 以 AGmnt信号在 DIFF信号后的分段突发的第一个时钟周期内为低电平状态， 而在之后的一个时钟周期内仲裁器 107从主设备获取 MDstnum信号后对主设 备做出响应， AGrant信号又重新为高电平状态，直至该流突发完全结束。 AMnum 信号持续为 1， 即该示例中以主设备 A为本次流突发传送的主设备。 示例二：
图 6所示为一次有中断的数据传送中各信号的时序图。 为了便于说明， 图中以 MReql , MLastl , MAddl , MDatal , MDstnum 1 , MCmdl表示主设备 A进行的数据传送操作的请求信号； 而以 MReq2， MLast2 , MAdd2， MData2, MDstnum2 , MCmd2表示主设备 B进行的数据传送操作的请求信号。 ALast信 号是仲裁器 107对 MLastl和 MLast2做出响应后送出的信号。
图 6中的主设备 A的一次流突发传送操作是与图 5中的主设备完全一样 的操作，但由于主设备 A在本次流突发传送操作期间受到其他主设备的较高级 别的总线请求引起的中断， 主设备 A的流突发的时序也相应产生了一些变化。 与图 5中的主设备相同， 图 6中的主设备 A的总线请求为一个完整的流突发， 包括四个分段突发。 但图 6中的主设备 A在第三个分段突发却产生了延时， 其 原因就是主设备 A的第三个分段突发被主设备 B的一个 CREQ级别的请求所 中断。
在主设备 A的第一个分段突发结束前， MLastl为 SAME, 仲裁器 107进入 仲裁状态， 但主设备 B此时发出的请求 MReq2为 REQ级别， 在本实施例中规 定 REQ级别的请求不能中断一个流突发， 因此， 主设备 A仍将继续进行当前 流突发的第二个分段突发操作。 在主设备 A的第二个分段突发结束前 MLastl 信号为 DIFF， 仲裁器 107进入仲裁状态， 主设备 B此时发出的请求 MReq2为 CREQ级别， 主设备 A的第三个分段突发为 CREQ级别的请求， 由仲裁器 107 对主设备 A和主设备 B的这两个同为 CREQ级别的总线请求做出仲裁。 本示 例中主设备 B的请求得到仲裁器 107的总线授权，因此在主设备 A的第三个分 段突发将被暂时中止， 总线 101先处理主设备 B的总线请求。而主设备 A的第 三个分段突发操作被压入到仲裁器 107的缓冲器 1072中暂存。 在主设备 B的 总线请求已经被处理完后， 总线将回到现场， 若此时无其他新的总线使用请求 需进行仲裁， 则继续进行主设备 A的第三个分段突发操作。 从图中也可得到反 映， MAddl和 MDatal在第三个分段突发都有延迟， 延迟期间即在等待主设备 B的数据传送操作。 仲裁器 107的 AMmim信号在主设备 A的流突发操作中为 1， 表示进行数据传送操作的主设备为主设备 A; 而在主设备 B的总线使用请 求授权后， AMmim信号也成为 2， 表示正在进行数据传送操作的主设备为主设 备8。 在主设备 B的总线请求完成后， AMmim信号又回到 1， 表示总线又返回 到主设备 A的原流突发现场， 继续原流突发的数据传送操作。
图 7是表示执行图 4所示数据传送操作流程的一个数据传送系统的方框图。 该数据传送系统用以经由总线在主设备与从设备之间进行数据传送操作， 而该数据传送操作包含流突发数据传送操作。该数据传送系统包括判断装置 701， 用以判断所述主设备发出的总线控制信号是 CONT信号、 LAST信号、 SAME信号和 DIFF信号中的哪一种信号； 检测装置 702， 用以当所述判断装置 701判断所述总线控制信号是 SAME信号或 DIFF信号时， 检测除当前主设备 以外的其它主设备是否发出新的较高级别的总线请求； 仲裁装置 703， 对当前 主设备的流突发数据传送操作中的下一个分段突发请求与所述检测装置测得 的其它主设备的较高级别的总线请求进行仲裁； 以及数据传送操作装置 704， 根据所述仲裁装置 703的仲裁结果经由所述总线 101在获得授权的主设备与从 设备之间进行所述的数据传送操作。 其中的仲裁装置 703可以采用图 3所示 的仲裁器。
本实施例只是为了进一步更清楚地描述本发明， 而非对本发明的限制。应该可 以理解， 本发明并不限于实施例所做的阐述，任何基于本发明的修改和本发明的等 同物都应涵盖在本发明的权利要求的精神和范围之内。

Claims

权利要求
1. 一种数据传送方法， 包括经由总线在主设备与从设备之间进行数据传送 操作， 所述数据传送操作包含流突发数据传送操作， 所述方法包括如下步骤： a. 对主设备发出的总线使用请求进行仲裁；
b .经仲裁获得授权的主设备进行流突发数据传送操作并同时向总线发出总 线控制信号， 所述流突发包含至少一个分段突发；
c 判断所述总线控制信号是 CONT信号、 LAST信号和中间信号中的哪一 种信号， 其中， CONT信号表示一个流突发中的一个分段突发没有结束， LAST 信号表示一个流突发的结束， 中间信号表示一个流突发中的一个分段突发的结 束， 而该流突发尚未结束；
d. 当判断所述总线控制信号是 CONT信号时， 继续当前流突发数据传送操 作的分段突发的数据传送操作；
e. 当判断所述总线控制信号是中间信号时， 检测是否有其它主设备发出的 新的较高级别的总线请求；
f. 当检测到其它主设备有新的较高级别的总线请求时， 对该请求与当前主 设备的流突发数据传送操作中的下一个分段突发请求进行仲裁；
g. 经仲裁获得授权的主设备优先进行数据传送操作；
. 当判断所述总线控制信号是 LAST信号时， 返回步骤 a的操作。
2. 如权利要求 1所述的方法， 其特征在于， 所述中间信号包括 SAME信 号和 DIFF信号， 其中， SAME信号表示一个流突发中的一个分段突发的结束， 预告下一个分段突发和本分段突发访问同样的从设备且访问请求的等级相同， DIFF表示一个流突发中的一个分段突发的结束，预告下一个分段突发和本分段 突发访问不同的从设备或者访问请求的等级不同。
3. 如权利要求 1或 2所述的方法， 其特征在于， 当步骤 e未检测到其它主 设备发出新的较高级别的总线请求时， 继续当前主设备的流突发数据传送操 作。
4. 如权利要求 1或 2所述的方法， 其特征在于， 当步骤 g获得授权的其它 主设备优先进行数据传送操作时， 暂停当前主设备的流突发数据传送操作中未 完成的操作。
5. 如权利要求 4所述的方法， 其特征在于， 获得授权的其它主设备优先进 行数据传送操作完成后， 继续当前主设备的流突发数据传送操作的下一个分段 突发数据的传送操作。
6. 如权利要求 1或 2所述的方法， 其特征在于还包括对主设备发出的总线 控制信号进行解码的步骤。
7. 一种数据传送系统， 用以经由总线在主设备与从设备之间进行数据传送 操作， 所述数据传送操作包含流突发数据传送操作， 所述系统包括：
判断装置，用以判断所述主设备发出的总线控制信号是 CONT信号、 LAST 信号和中间信号中的哪一种信号， 其中， CONT信号表示一个流突发中的一个 分段突发没有结束， LAST信号表示一个流突发的结束， 中间信号表示一个流 突发中的一个分段突发的结束， 而该流突发尚未结束；
检测装置， 用以当所述判断装置判断所述总线控制信号是中间信号时， 检 测除当前主设备以外的其它主设备是否发出新的较高级别的总线请求；
仲裁装置，对当前主设备的流突发数据传送操作中的下一个分段突发请求 与所述检测装置测得的其它主设备的较高级别的总线请求进行仲裁的仲裁装 置； 以及
数据传送操作装置，根据所述仲裁装置的仲裁结果经由所述总线在获得授 权的主设备与从设备之间进行所述的数据传送操作。
8. 如权利要求 7所述的数据传送系统， 其特征在于， 所述判断装置判断的所 述中间信号包括 SAME信号和 DIFF信号， 其中， SAME信号表示一个流突发 中的一个分段突发的结束， 预告下一个分段突发和本分段突发访问同样的从设 备且访问请求的等级相同， DIFF表示一个流突发中的一个分段突发的结束， 预 告下一个分段突发和本分段突发访问不同的从设备或者访问请求的等级不同。
9. 如权利要求 7或 8所述的数据传送系统， 其特征在于， 所述仲裁装置包括 对主设备发出的总线控制信号进行解码的解码装置。
10. 如权利要求 7或 8所述的数据传送系统， 其特征在于， 所述仲裁装置 包括暂存当前主设备的流突发数据传送操作的缓冲装置。
PCT/CN2004/001003 2004-08-30 2004-08-30 Procede et systeme pour transfert de donnees WO2006024193A1 (fr)

Priority Applications (5)

Application Number Priority Date Filing Date Title
PCT/CN2004/001003 WO2006024193A1 (fr) 2004-08-30 2004-08-30 Procede et systeme pour transfert de donnees
EP04762138A EP1811393B1 (en) 2004-08-30 2004-08-30 Method and system for data transfer
AT04762138T ATE425495T1 (de) 2004-08-30 2004-08-30 Verfahren und system zum datentransfer
US11/661,439 US7543093B2 (en) 2004-08-30 2004-08-30 Method and system for stream burst data transfer
DE602004019990T DE602004019990D1 (de) 2004-08-30 2004-08-30 Verfahren und system zum datentransfer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2004/001003 WO2006024193A1 (fr) 2004-08-30 2004-08-30 Procede et systeme pour transfert de donnees

Publications (1)

Publication Number Publication Date
WO2006024193A1 true WO2006024193A1 (fr) 2006-03-09

Family

ID=35999685

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2004/001003 WO2006024193A1 (fr) 2004-08-30 2004-08-30 Procede et systeme pour transfert de donnees

Country Status (5)

Country Link
US (1) US7543093B2 (zh)
EP (1) EP1811393B1 (zh)
AT (1) ATE425495T1 (zh)
DE (1) DE602004019990D1 (zh)
WO (1) WO2006024193A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114661644A (zh) * 2022-02-17 2022-06-24 之江实验室 辅助3d架构近存计算加速器系统的预存储dma装置

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8407433B2 (en) * 2007-06-25 2013-03-26 Sonics, Inc. Interconnect implementing internal controls
US9087036B1 (en) 2004-08-12 2015-07-21 Sonics, Inc. Methods and apparatuses for time annotated transaction level modeling
US8504992B2 (en) * 2003-10-31 2013-08-06 Sonics, Inc. Method and apparatus for establishing a quality of service model
KR100633773B1 (ko) * 2005-07-01 2006-10-13 삼성전자주식회사 버스 시스템 및 버스 중재 방법
US7478183B2 (en) * 2006-05-03 2009-01-13 Cisco Technology, Inc. Method and system for n dimension arbitration algorithm—scalable to any number of end points
US8868397B2 (en) * 2006-11-20 2014-10-21 Sonics, Inc. Transaction co-validation across abstraction layers
US8108648B2 (en) * 2007-06-25 2012-01-31 Sonics, Inc. Various methods and apparatus for address tiling
US8438320B2 (en) * 2007-06-25 2013-05-07 Sonics, Inc. Various methods and apparatus for address tiling and channel interleaving throughout the integrated system
KR20130071436A (ko) * 2010-05-07 2013-06-28 모사이드 테크놀로지스 인코퍼레이티드 단일 버퍼를 사용하여 복수의 메모리 장치를 동시에 판독하는 방법 및 장치
US8478920B2 (en) * 2010-06-24 2013-07-02 International Business Machines Corporation Controlling data stream interruptions on a shared interface
US8972995B2 (en) 2010-08-06 2015-03-03 Sonics, Inc. Apparatus and methods to concurrently perform per-thread as well as per-tag memory access scheduling within a thread and across two or more threads
US20120089759A1 (en) * 2010-10-08 2012-04-12 Qualcomm Incorporated Arbitrating Stream Transactions Based on Information Related to the Stream Transaction(s)
CN106897281B (zh) 2015-12-17 2020-08-14 阿里巴巴集团控股有限公司 一种日志分片方法和装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0343770A2 (en) * 1988-05-26 1989-11-29 International Business Machines Corporation Multi-bus microcomputer system with bus arbitration
CN1050936A (zh) * 1989-10-27 1991-04-24 国际商业机器公司 带有高速缓冲存储器的中心处理机优先控制
US6081860A (en) * 1997-11-20 2000-06-27 International Business Machines Corporation Address pipelining for data transfers
CN1282924A (zh) * 1999-07-29 2001-02-07 国际商业机器公司 使用可变优先级和合理性的增强总线仲裁器

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62138948A (ja) * 1985-12-13 1987-06-22 Hitachi Ltd デ−タ転送装置
US5448704A (en) * 1994-03-07 1995-09-05 Vlsi Technology, Inc. Method for performing writes of non-contiguous bytes on a PCI bus in a minimum number of write cycles
US6393500B1 (en) * 1999-08-12 2002-05-21 Mips Technologies, Inc. Burst-configurable data bus
US6775727B2 (en) * 2001-06-23 2004-08-10 Freescale Semiconductor, Inc. System and method for controlling bus arbitration during cache memory burst cycles
US6981073B2 (en) * 2001-07-31 2005-12-27 Wis Technologies, Inc. Multiple channel data bus control for video processing
US7337232B2 (en) * 2002-03-28 2008-02-26 Sony Corporation Method and system for providing and controlling sub-burst data transfers
US6981088B2 (en) * 2003-03-26 2005-12-27 Lsi Logic Corporation System and method of transferring data words between master and slave devices
ATE542181T1 (de) * 2004-10-28 2012-02-15 Magima Digital Information Co Ltd Arbitrierer und arbitrierungsverfahren dafür
KR100633773B1 (ko) * 2005-07-01 2006-10-13 삼성전자주식회사 버스 시스템 및 버스 중재 방법

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0343770A2 (en) * 1988-05-26 1989-11-29 International Business Machines Corporation Multi-bus microcomputer system with bus arbitration
CN1050936A (zh) * 1989-10-27 1991-04-24 国际商业机器公司 带有高速缓冲存储器的中心处理机优先控制
US6081860A (en) * 1997-11-20 2000-06-27 International Business Machines Corporation Address pipelining for data transfers
CN1282924A (zh) * 1999-07-29 2001-02-07 国际商业机器公司 使用可变优先级和合理性的增强总线仲裁器

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114661644A (zh) * 2022-02-17 2022-06-24 之江实验室 辅助3d架构近存计算加速器系统的预存储dma装置
CN114661644B (zh) * 2022-02-17 2024-04-09 之江实验室 辅助3d架构近存计算加速器系统的预存储dma装置

Also Published As

Publication number Publication date
DE602004019990D1 (de) 2009-04-23
EP1811393B1 (en) 2009-03-11
US7543093B2 (en) 2009-06-02
EP1811393A4 (en) 2008-01-23
US20070260793A1 (en) 2007-11-08
ATE425495T1 (de) 2009-03-15
EP1811393A1 (en) 2007-07-25

Similar Documents

Publication Publication Date Title
US7096292B2 (en) On-chip inter-subsystem communication
WO2006024193A1 (fr) Procede et systeme pour transfert de donnees
JP2539021B2 (ja) 保留バスに割り込み要求を送る割り込み要求発生ノ―ド
JP2001075918A (ja) 可変優先順位およびフェアネスを使用する、機能強化されたバス・アービタ
CN105068951A (zh) 一种具有非等时传输结构的片上系统总线
KR100644596B1 (ko) 버스 시스템 및 그 버스 중재방법
JPH0679305B2 (ja) 保留バスを用いて割り込みに応じる装置及び方法
US6823410B2 (en) Split transaction bus system
JP2007058716A (ja) データ転送バスシステム
JP2004005677A (ja) 集積回路装置のバスアービター
US6826644B1 (en) Peripheral component interconnect arbiter implementation with dynamic priority scheme
US6546448B1 (en) Method and apparatus for arbitrating access to a PCI bus by a plurality of functions in a multi-function master
US6973520B2 (en) System and method for providing improved bus utilization via target directed completion
WO2006045216A1 (fr) Dispositif et procede d'arbitrage
JP2006215621A (ja) Ｄｍａ制御装置
US7167939B2 (en) Asynchronous system bus adapter for a computer system having a hierarchical bus structure
JPH09153009A (ja) 階層構成バスのアービトレーション方法
JP2008108126A (ja) データ転送制御装置及びそのバスアクセス調停方法
US5815676A (en) Address bus arbiter for pipelined transactions on a split bus
JP3206656B2 (ja) バス上でのプリフェッチ装置およびプリフェッチ方法
JPH09269927A (ja) バスアクセス方法、バス、並びにバス接続システム
JP2003085125A (ja) メモリ制御器及びメモリ制御方法
JPS63175964A (ja) 共有メモリ
TWI244001B (en) An arbiter and the method thereof
JPH11232215A (ja) バスコントローラ、バスマスタ装置及びバス制御システムの制御方法

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BW BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NA NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): GM KE LS MW MZ NA SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LU MC NL PL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 11661439

Country of ref document: US

NENP Non-entry into the national phase

Ref country code: DE

WWE Wipo information: entry into national phase

Ref document number: 428/MUMNP/2007

Country of ref document: IN

WWE Wipo information: entry into national phase

Ref document number: 2004762138

Country of ref document: EP

WWP Wipo information: published in national office

Ref document number: 2004762138

Country of ref document: EP

WWP Wipo information: published in national office

Ref document number: 11661439

Country of ref document: US