WO2006013177A2 - Technique de connexions internes planes pour conduire le courant en cas de defaillance - Google Patents

Technique de connexions internes planes pour conduire le courant en cas de defaillance Download PDF

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Publication number
WO2006013177A2
WO2006013177A2 PCT/EP2005/053644 EP2005053644W WO2006013177A2 WO 2006013177 A2 WO2006013177 A2 WO 2006013177A2 EP 2005053644 W EP2005053644 W EP 2005053644W WO 2006013177 A2 WO2006013177 A2 WO 2006013177A2
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WO
WIPO (PCT)
Prior art keywords
components
electrically
parallel
layer
product according
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PCT/EP2005/053644
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German (de)
English (en)
Other versions
WO2006013177A3 (fr
Inventor
Mark-Matthias Bakran
Norbert Seliger
Original Assignee
Siemens Aktiengesellschaft
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Publication of WO2006013177A2 publication Critical patent/WO2006013177A2/fr
Publication of WO2006013177A3 publication Critical patent/WO2006013177A3/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/2405—Shape
    • H01L2224/24051—Conformal with the semiconductor or solid-state device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01032—Germanium [Ge]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01058—Cerium [Ce]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301—Thyristor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0254—High voltage adaptations; Electrical insulation details; Overvoltage or electrostatic discharge protection ; Arrangements for regulating voltages or for using plural voltages

Definitions

  • thyristors or GTO thyristors are used, which are traditionally used in a pressure-contacted housing.
  • IGBTs Insulated Gate Bipolar Transistors
  • PPI Press Pack IGBTs
  • a plurality of IGBT chips are connected in parallel in a housing and each contacted by a pressure contact.
  • the Druckkon ⁇ clock ensures the right design that can continue to flow in a semiconductor defect by the defective chip current.
  • Si ⁇ lizium melts at a defect and is conductive.
  • the goal is always that the de ⁇ fect power semiconductor can continue to run its rated current. This now flows through the defective point in the silicon, whereby the pressure contact must be able to carry this locally increased current density.
  • WO 03/030247 A2 discloses a planar connection technique for contacting semiconductor components.
  • the object of the invention is to provide a cost-effective connection technique in which current can also be conducted in the event of a fault.
  • a product has a circuit carrier, for example in the form of a DCB ceramic, and a plurality of components arranged on the circuit carrier, which each have device contact surfaces. Furthermore, the product has a layer of electrically insulating material which is arranged on the circuit carrier and the components, wherein the layer of electrically insulating material abuts in contact with the circuit carrier and the sides of the component not arranged on the circuit carrier Area of the components contact surface openings auf ⁇ points. Furthermore, a layer of electrically conductive Materi ⁇ al disposed on the layer of electrically isolie ⁇ rendem material contacting surfaces of the components to the Bauianotory-.
  • the components include a plurality of electrically connected in parallel components.
  • the Bau ⁇ elements of the plurality of electrically connected in parallel components are components that conductive in the event of a fault who ⁇ .
  • the components of the plurality of electrically parallel-connected components thyristors or Transis ⁇ gates, in particular IGBTs.
  • the components preferably include a further plurality of components connected electrically in parallel, which are connected to the plurality of component elements connected electrically in parallel. in a parallel arrangement is electrically connected in parallel and whose components are of a different kind than the components of the plurality of electrically parallel Bauelemen ⁇ th by the components of the further plurality of electrically parallel-connected components, for example, in the event of defects are not conductive.
  • the components of the white elements ⁇ direct plurality of electrically parallel connected Bauele ⁇ are, in particular diodes.
  • the plurality of electrically parallel peeled ⁇ is ten components and / or the further plurality of electrically parallel-connected components on the circuit carrier are arranged spatially in a row.
  • the product preferably has a further parallel arrangement , which is constructed analogously to the parallel arrangement, ie, for example, likewise has a plurality and a further plurality of components connected electrically in parallel, and is connected electrically in series therewith.
  • the further parallel arrangement with the parallel ⁇ arrangement using the planar connection technology connected in series by a further layer of electrically conductive material the device contact surfaces of components of the further parallel arrangement contacted, in elekt ⁇ rischer contact with a guide element, for example in Form of a conductor track, the circuit substrate is on which the construction ⁇ elements of the parallel arrangement are arranged and which contact the components of the parallel arrangement with the circuit carrier facing contact surfaces.
  • the product still has a fixation of the construction ⁇ elements of the plurality of electrically parallel-connected components and optionally of other components, which prevents an explosion of the components and / or an on ⁇ melt of conductors in case of failure.
  • the layer of electrically conducting material advantageously a copper plating with a layer thickness of at least 200 microns.
  • FIG. 2 shows a circuit diagram of the product according to FIG. 1;
  • FIG. 4 shows a circuit diagram of the alternative product according to FIG. 3;
  • FIGS 5 to 7 steps of a process for the production of products.
  • a planar contacting and connection technique for power semiconductors such as the component contact surfaces of components described in WO 03/030247 A2 or, as in the case of power overlay modules, for electrical contacting away from a circuit carrier, is used.
  • the circuit carrier is, for example, a ceramic with conductor tracks arranged thereon.
  • the components contact surfaces are, for example terminals, in particular an emitter contact or a gate contact wheeling diode of an IGBT or the cathode of a free ⁇ .
  • FIG 1 shows a product 10. This has a circuit carrier, not shown, with printed conductors 11, which are designed in particular as DCB. On one of the interconnects 11 of the circuit substrate components 12, 13 are arranged, which have device contact surfaces. A layer not shown in FIG 1 of electrically iso ⁇ lierendem material is on the circuit carrier and the Bau ⁇ elements 12, 13 and has in the region of the Bauele ⁇ elements contact surfaces of the components 12, 13 and the conductor line 11 of the circuit carrier openings. On the layer of electrically insulating material is arranged a layer of elekt ⁇ driven conductive material 14, which contact surfaces the components ⁇ of the devices 12, 13 connected in parallel and contacted with printed conductors 11 of the circuit substrate on which the components 12 are not arranged.
  • the components 12, 13 contain a plurality of electrically parallel-connected components, wherein the components 12 of the plurality of electrically parallel Bauelemen ⁇ th devices that are conductive in the event of a fault.
  • the Components 12 of the plurality of electrically parallel maral ⁇ teten components are in the product 10 IGBTs.
  • the components 12, 13 contain a further plurality of components connected in parallel in electrical terms whose components 13 are electrically connected in parallel with the components 12 of the plurality of components connected in parallel in a parallel arrangement.
  • the Bauele ⁇ elements 13 of the other plurality of electrically parallel ge off devices are of a different type than the Bauemia 12 of the plurality of electrically parallel-connected devices.
  • the components 13 of the further plurality of electrically parallel-connected components of the product 10 are diodes.
  • the components 12 of the plurality of electrically parallel-connected components and the components 13 of the further plurality of components connected electrically in parallel are arranged spatially on the circuit carrier in a row and are contacted by the identical conductor 11.
  • FIG. 2 shows a circuit diagram of the product according to FIG. 1 with two IGBTs and diodes connected in parallel.
  • the plana- re contacting ensures that in case of error, at ⁇ play, when the right IGBT to become low, the current I Nenn ⁇ N via the contact structure in the form of the layer 14 can be guided from electrically conductive material.
  • FIG. 4 shows an example of the series connection of two parallel arrangements 25, 35 of a product 20.
  • the parallel arrangement 25 and the further parallel arrangement 35 of the product 20 are constructed analogously, in particular identically, to the parallel arrangement 15 of the product 10 described in FIG. That is, they each have devices 22, 32, in the form of IGBTs, a plurality of e- lektrisch parallel-connected components, the error case are conductive, and via components 23, 33, in the form of diodes, a further plurality of electrically parallel ge switched components, which is electrically connected in parallel to the plurality of electrically parallel connected components.
  • the components 22, 23; 32, 33 of the Parallelan ⁇ orders 35 are each spatially arranged in a row on a conductor 21 of the circuit substrate of the product 20 ⁇ .
  • a layer 24 of electrically conductive material is constructed in several parts.
  • the parallel arrangement 25 is electrically connected in series with the further parallel arrangement 35 in that a part of the layer 24 of electrically conductive material which contacts the device contact surfaces of components 32, 33 of the further parallel arrangement 35 is in electrical contact with that of FIG Conductor tracks 21 of the circuit substrate is on which the components 22, 23 of the parallel arrangement 25 are arranged and which contacts the components 22, 23 of the parallel arrangement 25 with their device facing the Wegsträ ⁇ device contact surfaces.
  • FIGS. 5 to 7 show a method for producing products of the type described above.
  • a circuit carrier 50 has a DCB ceramic 51, which carries conductor tracks 52 on its bottom side and conductor tracks 53 on its top side in the form of copper metallizations.
  • a construction ⁇ element 54 is arranged on ei ⁇ ner of the interconnects 53 of the circuit substrate 50.
  • a construction ⁇ element 54 is arranged on the component 54 and the shell tung carrier 50 .
  • a layer 55 of electrically isolieren ⁇ the material applied by a film laminated WUR ⁇ de is a layer 55 of electrically isolieren ⁇ the material applied by a film laminated WUR ⁇ de.
  • the layer 55 of electrically insulating material has openings in the region of a device contact surface 56 of the component 54 and in the region of one of the conductor tracks 53 of the substrate 50.
  • a layer 57 of electrically conductive material is sputtered onto the layer 55 of electrically insulating material and the component contact surface 56 and one of the interconnects 53 of the circuit carrier 50 in the region of the openings of the layer 55 of electrically insulating material Structured and developed structured.
  • the layer 57 is made of e lectric conductive material by electrodeposition Kup ⁇ fer / nickel / gold plating (200 microns) and etching back so ver ⁇ strengthens that it can carry the rated current of the device 54 in the case in that the component 54 becomes conductive in the event of a fault.
  • a mechanical fixing can be ⁇ be placed above the current carrying contacts is adapted to the topology of the contacting and performs the following functions:
  • connection technique for semiconductors is used with the purpose of producing a composite of power semiconductor devices, wherein the composite in the event of a fault ei ⁇ nes device, ie the transition into the low-Zu ⁇ , represents a closed electrical contact.
  • a characteristic of the product is that the current is conducted in the event of a fault via an electrical conductor that is part of the chip metallization (in contrast to other solutions such as press-pack with spring contacts and soldered copper temples, etc.).
  • planar conductor guidance results in a very good thermal connection to the chip and, via the insulating layer, to the DCB top side.
  • the track follows the topology.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

L'invention concerne un produit comprenant : un porte-circuit (11, 21, 50, 51, 52) ; plusieurs composants (12, 13, 22, 23, 32, 33, 54) qui sont disposés sur ce porte-circuit (11, 21, 50, 51, 52), et qui comportent respectivement des surfaces de contact de composant (56) ; une couche (55) de matériau électro-isolant (10) qui est disposée sur le porte-circuit (11, 21, 50, 51, 52, 53) et le composant (12, 13, 22, 23, 32, 33, 54), cette couche (55) de matériau électro-isolant étant pourvue d'ouvertures dans la zone des surfaces de contact de composant (56) ; une couche (14, 24, 57) de matériau électroconducteur qui est disposée sur la couche (55) de matériau électro-isolant et qui est en contact avec des composants (12, 13, 22, 23, 54) au niveau des surfaces de contact de composant, lesdits composants (12, 13, 22, 23, 32, 33, 54) comprenant une pluralité de composants montés électriquement en parallèle. Selon l'invention, lesdits composants (12, 22) de la pluralité de composants montés électriquement en parallèle sont des composants qui deviennent conducteurs en cas de défaillance, ce qui permet d'obtenir une technique de connexions internes planes assurant la conduction de courant même en cas de défaillance.
PCT/EP2005/053644 2004-07-30 2005-07-26 Technique de connexions internes planes pour conduire le courant en cas de defaillance WO2006013177A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE200410037078 DE102004037078A1 (de) 2004-07-30 2004-07-30 Planare Verbindungstechnik für Stromführung im Fehlerfall
DE102004037078.8 2004-07-30

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Publication Number Publication Date
WO2006013177A2 true WO2006013177A2 (fr) 2006-02-09
WO2006013177A3 WO2006013177A3 (fr) 2006-07-27

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
RU2747264C2 (ru) * 2017-03-24 2021-05-04 Таль Силовой преобразователь импульсного типа, выполненный с возможностью управления по меньшей мере одной фазой многофазного электрического приемника с по меньшей мере тремя фазами

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10037533C1 (de) * 2000-08-01 2002-01-31 Semikron Elektronik Gmbh Induktivitätsarme Schaltungsanordnung
EP1209742A1 (fr) * 2000-11-22 2002-05-29 ABB Schweiz AG Module semi-conductrice à haut prestation et utilisation de la meme
WO2003030247A2 (fr) * 2001-09-28 2003-04-10 Siemens Aktiengesellschaft Procede d'etablissement de contact pour des surfaces de contact electriques situees sur un substrat et dispositif constitue d'un substrat pourvu de surfaces de contact electriques
DE10244748A1 (de) * 2002-09-25 2003-09-11 Siemens Ag Leistungshalbleitermodul und Verfahren zur Herstellung desselben
DE10255602A1 (de) * 2002-11-28 2004-06-24 eupec Europäische Gesellschaft für Leistungshalbleiter mbH Halbleiterschaltungsanordnung zum Steuern einer hohen Spannung oder eines Stromes großer Stromstärke

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10037533C1 (de) * 2000-08-01 2002-01-31 Semikron Elektronik Gmbh Induktivitätsarme Schaltungsanordnung
EP1209742A1 (fr) * 2000-11-22 2002-05-29 ABB Schweiz AG Module semi-conductrice à haut prestation et utilisation de la meme
WO2003030247A2 (fr) * 2001-09-28 2003-04-10 Siemens Aktiengesellschaft Procede d'etablissement de contact pour des surfaces de contact electriques situees sur un substrat et dispositif constitue d'un substrat pourvu de surfaces de contact electriques
DE10244748A1 (de) * 2002-09-25 2003-09-11 Siemens Ag Leistungshalbleitermodul und Verfahren zur Herstellung desselben
DE10255602A1 (de) * 2002-11-28 2004-06-24 eupec Europäische Gesellschaft für Leistungshalbleiter mbH Halbleiterschaltungsanordnung zum Steuern einer hohen Spannung oder eines Stromes großer Stromstärke

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RU2747264C2 (ru) * 2017-03-24 2021-05-04 Таль Силовой преобразователь импульсного типа, выполненный с возможностью управления по меньшей мере одной фазой многофазного электрического приемника с по меньшей мере тремя фазами

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