WO2006012784A1 - Circuit de polarisation a transistor a effet de champ - Google Patents

Circuit de polarisation a transistor a effet de champ Download PDF

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Publication number
WO2006012784A1
WO2006012784A1 PCT/CN2005/000516 CN2005000516W WO2006012784A1 WO 2006012784 A1 WO2006012784 A1 WO 2006012784A1 CN 2005000516 W CN2005000516 W CN 2005000516W WO 2006012784 A1 WO2006012784 A1 WO 2006012784A1
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WO
WIPO (PCT)
Prior art keywords
fet
voltage
circuit
resistor
bias circuit
Prior art date
Application number
PCT/CN2005/000516
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English (en)
French (fr)
Inventor
Yuejun Yan
Original Assignee
Yuejun Yan
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yuejun Yan filed Critical Yuejun Yan
Priority to US11/568,457 priority Critical patent/US7420420B2/en
Priority to EP05745432A priority patent/EP1777812B1/en
Publication of WO2006012784A1 publication Critical patent/WO2006012784A1/zh

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/04—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only
    • H03F3/16—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only with field-effect devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
    • H03F1/301—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters in MOSFET amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/18—Indexing scheme relating to amplifiers the bias of the gate of a FET being controlled by a control signal

Definitions

  • the invention relates to a field effect tube bias circuit, which aims to provide a high efficiency field effect tube bias circuit, which can overcome the lack of temperature fluctuation of the FET static drain current variation and reduce the temperature at the temperature.
  • the variation of the gain and linear characteristics of the FET during the change, and the static drain current deviation of each FET in the entire wafer can be reduced.
  • the invention overcomes the shortcomings of the quiescent drain current variation of the signal action FET when the temperature changes, and improves the static drain current deviation of each FET in the whole wafer to provide a high efficiency FET bias circuit.
  • the technical solution adopted by the present invention is: providing a field effect tube bias circuit, comprising: a current fluctuation information circuit having a power source; a resistor connected to the signal output end of the current fluctuation information circuit, the other end of the resistor being connected to a reference a voltage source, and a connection point of the resistor and the current fluctuation information circuit as an output terminal for providing voltage variation information; and a voltage dividing circuit connected to at least one voltage source connected to an output terminal for providing voltage variation information; The voltage variation information of the terminal is supplied to the voltage dividing circuit, and a voltage dividing is taken from the voltage dividing circuit as an output terminal of the FET bias circuit for controlling a static drain current of a signal action FET.
  • the FET bias circuit of the present invention can also reduce the gain caused by the static drain current variation when the temperature changes. And the variation range of the linear characteristic; moreover, the electric circuit of the present invention can be integrated on the same chip with the controlled signal action FET, or can be integrated on the same chip without the controlled signal action FET, A stand-alone device is produced and used. V.
  • the circuit of the present invention has a very small circuit area and power consumption, and can be integrated with an operation signal by a control signal.
  • the field effect transistor is integrated in an IC chip, and can also be sealed with a controlled signal action field effect tube. The same tube, low cost, easy to integrate manufacturing.
  • Figure 1 is a circuit diagram of a field effect transistor bias circuit of the present invention.
  • FIG. 2 is a first embodiment of a field effect transistor bias circuit of the present invention.
  • Figure 3 is a temperature characteristic curve of the FET static drain current.
  • Figure 4 is a graph showing the temperature characteristics of the FET static drain current versus the gate voltage. It shows that the quiescent drain current of the signal-action FET decreases with decreasing gate voltage without temperature compensation. .
  • Figure 5 is a static leakage of the signal action FET after implementing the FET bias circuit of the present invention The temperature characteristic curve of the polar current.
  • Figure 6 is a graph showing that the FET has different threshold voltages under different temperature conditions, which shows the characteristic curve of the FET gate voltage versus the quiescent drain current when the FET bias circuit of the present invention is not implemented.
  • Figure 7 is a graph showing that the FETs fabricated at different locations on the entire wafer have different threshold voltages, which show the FET gate voltage vs. quiescent drain current when the FET bias circuit of the present invention is not implemented. Characteristic curve.
  • FIG. 8 is a diagram showing the static drain current deviation distribution of the field effect transistor and the controlled/signal action field effect transistor in each field effect transistor bias circuit in the entire wafer, and after implementing the field effect transistor bias circuit of the present invention, The controlled signal acts on the FET static drain current deviation distribution.
  • Figure 9 is a second embodiment of the field effect transistor bias circuit of the present invention.
  • Figure 10 is a third embodiment of the field effect transistor bias circuit of the present invention.
  • Figure 11 is a modified embodiment of the field effect transistor bias circuit of the present invention.
  • Figure 12 is another modified embodiment of the field effect transistor bias circuit of the present invention. detailed description
  • FIG. 1 is a block diagram of a field effect transistor bias circuit of the present invention.
  • the field effect transistor bias circuit of the present invention includes a voltage fluctuation information circuit composed of a current fluctuation information circuit 1 and a resistor 2, and a voltage dividing circuit 4 coupled to the voltage fluctuation information circuit.
  • the current fluctuation information circuit 1 is constituted by a field effect transistor having a very small power consumption, and is supplied by the power source 18.
  • the resistor 2 is connected to the signal output terminal of the current fluctuation information circuit 1, and the reference voltage source 7 is applied to the other end of the resistor 2.
  • connection point of the current fluctuation information circuit 1 and the resistor 2 serves as the output terminal 3 of the voltage fluctuation information circuit, and the voltage variation information of the output terminal 3 is supplied to the voltage dividing circuit 4 to which at least one voltage source 10 is connected, and the slave voltage is divided.
  • a voltage divider is taken from the voltage circuit 4 as an output terminal 5 of the field effect transistor bias circuit of the present invention for controlling the current of the signal action of the FET.
  • the supply voltage source 10 of the voltage dividing circuit 4 can be selected as a positive power source or a negative power source, the positive and negative of which are determined by the voltage operating state required by the gate of the FET 6; wherein, by calculating the output terminal of the voltage dividing circuit 4 The potential of the voltage difference 5 and the amount of potential fluctuation determine the configuration of the voltage dividing circuit 4.
  • the current fluctuation information circuit 1 includes a field effect transistor 14 and two series-connected voltage dividing resistors 11, 12, the source of the field effect transistor 14 is grounded, and the drain thereof is connected to the reference voltage source 7 via the resistor 2.
  • the gate is connected between the two voltage dividing resistors 11, 12, the two voltage dividing resistors 11 and 12 are grounded, and the other end is connected to the power source 18.
  • the power supply 18 shares a set of power supplies with the voltage source 10, and is applied to the gate of the FET 14 through a voltage dividing resistor 11 and a resistor 12, thereby setting the quiescent drain current of the FET 14.
  • the connection point of the current fluctuation information circuit 1 and the resistor 2 serves as an output terminal 3 for supplying voltage variation information.
  • the output terminal 3 is connected to the voltage dividing circuit 4, and the voltage dividing circuit 4 includes two series resistors 8 and 9, and the resistor 8 is terminated.
  • the electric-J5 source 10 the other end of the resistor 8 is connected to the resistor 9, and the other end of the resistor 9 is connected to the output terminal 3 of the voltage fluctuation information, and an output terminal 5 is connected between the resistors 8 and 9 and the signal is controlled.
  • the FET 6 is connected to the gate to control the quiescent drain current of the signal action FET 6. The drain of the signal action FET 6 is powered by the power source 13.
  • FIG. 3 is a temperature characteristic curve of the FET static drain current. As shown in the figure, when the temperature rises, the quiescent drain current of the signal action FET 6 has an increase in temperature with no temperature compensation.
  • the quiescent drain current of the signal action FET 6 has a characteristic that decreases as the gate voltage decreases with no temperature compensation.
  • the present invention utilizes the characteristic principle illustrated in FIGS. 3 and 4 to suppress fluctuations in the quiescent drain current of the signal action FET 6 when the temperature changes, by the change in voltage applied to the gate of the signal action FET 6.
  • the quiescent drain current of the FET 14 in the current fluctuation information circuit 1 in the present embodiment increases, and the resistance thereof becomes small, and thus the voltage
  • the potential of the fluctuation information output terminal 3 is lowered, and the potential of the output terminal 5 of the voltage dividing circuit 4 is also lowered. Therefore, according to the signal shown in FIG. 4, the quiescent drain current of the transistor 6 decreases as the gate voltage decreases, and the reduced potential is applied to the gate of the signal action FET 6 at this time. It can suppress the increase of the quiescent drain current of the cancellation signal action FET 6 and achieve the purpose of temperature compensation, as follows:
  • the target value of the static leakage current of the signal action FET 6 is set to "100 mA, and the negative voltage applied to the gate of the field effect transistor 14 in the current fluctuation information circuit 1 at this time. ; -0.8V.
  • the voltage of the output terminal 3 which supplies the voltage variation information in the current fluctuation information circuit 1 connected in series with the resistor 2 will be 2V, and is applied to the signal through the voltage dividing circuit 4: ⁇ on the action field effect transistor 6.
  • the voltage is -0.6V, corresponding to the static drain on the FET 6:, the current is 100mA we want.
  • the static leakage current of the FET FET 6 that does not use the FET bias circuit of the present invention will rise to 180 mA, and we want to keep the static leakage current 100 mA. change.
  • the quiescent drain current of the FET 14 also increases with temperature, and the output current of the current fluctuation information circuit 1 also increases. 4, so the voltage drop across the resistor 2 increases, and the reference voltage source 7 voltage is constant, so the voltage drop of the output terminal 3 of the voltage fluctuation information is 1.6V, at this time, the signal is applied to the signal via the voltage dividing circuit 4.
  • the voltage on the gate of the effect transistor 6 is reduced by 0.2V, and the reduced voltage of 0.2V on the gate just pulls the static leakage current of the signal action FET 6 from the lSOmA back to 100mA, thus ensuring the temperature from 25 °C to 85 °C.
  • the static leakage current of the signal action FET 6 is always maintained at about 100 mA.
  • the field effect tube bias circuit does not cause additional loss of the signal action field effect transistor 6, which enables the signal action field effect transistor 6 to operate at a high efficiency while leaking the signal action field effect transistor 6.
  • the pole current acts as a temperature compensation.
  • the signal action field effect transistor 6 embodying the above-described circuit of the present invention can maintain a stable static drain current in a temperature varying environment.
  • the size, required voltage and respective resistance values of the field effect transistor 14 of the present invention can be designed by IC chip test or computer simulation and temperature experiment to make the quiescent drain current of the signal action FET 6 Perform temperature compensation.
  • FIG. 6 shows the curve of the gate voltage versus the quiescent drain current of the signal action FET 6 under different temperature conditions when the field effect transistor bias circuit of the present invention is not implemented, which indicates the signal action field effect transistor. 6 has different threshold voltages Vth under different temperature conditions, and the threshold voltage Vth has a characteristic that decreases as the temperature increases.
  • Figure 7 shows the signal action FET when the field effect transistor bias circuit of the present invention is not implemented.
  • the characteristic of the gate voltage vs. quiescent drain current of (FET) 6 indicates that the signal action FET 6 fabricated at different locations on the entire wafer has different threshold voltages.
  • FIG. 6 is very similar to FIG. 7, so that the principle of the quiescent drain current of the signal-action FET 6 fabricated at different positions on the entire wafer is reduced. 3.
  • the temperature compensation principles of Figure 4 and Figure 5 are the same and will not be described again.
  • FIG. 8 shows the FET 14 and signal action in the whole wafer.
  • the deviation of the quiescent drain current of each FET 6 in the entire chip can be reduced, and the distribution curve c is presented.
  • the two power signal action FETs 6A and 6B are FETs made at different positions of the whole wafer.
  • the static leakage at a certain gate voltage The polar currents are 100mA and 130mA, respectively.
  • the quiescent drain current of the high-power signal action FET 6A is also set to 100 mA
  • the field in the bias circuit in the same chip as the high-power signal action FET 6A is used.
  • the quiescent drain current of the effect transistor 14A is lmA, and the voltage at the output terminal 3 of the voltage variation information is N2005/000516
  • the voltage at output 5 is Vao.
  • the current of the FET MB in the bias circuit of the high-power signal action field effect transistor 6B is larger than the current of the FET 14A, which is 1.3 mA.
  • the output of the voltage fluctuation information in the bias circuit of the high-power signal action field effect transistor 6B is Vbx, and the voltage of the output terminal 5 is Vbo.
  • Vbx ⁇ Vax the voltage Vbc Vao of the output terminal 5 means that the voltage applied to the gate of the high-power signal action FET 6B is higher than that applied to the gate of the high-power signal action FET 6A. The voltage is low.
  • the quiescent drain current of the high-power signal action FET 6B becomes smaller, which is less than 130 mA. Therefore, in addition to the temperature compensation function, the field effect transistor bias circuit of the present invention can also reduce the deviation of the static drain current of each of the high power field effect transistors.
  • the current fluctuation information circuit 1 is constituted by a diode.
  • the diode is grounded at one end, and the other end is connected to the resistor 2.
  • the other end of the resistor 2 is connected to the reference voltage source 7, and the connection point of the resistor 2 and the diode serves as the output terminal 3 for providing voltage variation information.
  • the function of the present invention can be realized by the setting of the voltage dividing circuit 4. At this time, the power supply 18 does not have to be powered, and is in an open state.
  • Figure 10 is a third embodiment of the field effect transistor bias circuit of the present invention, the circuit configuration of which is similar to the embodiment disclosed in Figure 2. This embodiment differs in that the power source 18 is an independent power source.
  • FIG. 11 shows the manner in which the quiescent drain current of the signal action FET 6 is set by performing external fine adjustment on the basis of the circuit in FIG.
  • the portion of the dotted line shown in the figure can be integrated inside the IC, and the resistors 15 and 16 outside the dotted line do not have to be integrated in the IC. Due to the deviation of the IC fabrication process, when the quiescent drain current of the signal action FET 6 deviates from the ideal design value, the fine adjustment can be performed by the adjustment resistors 15, 16 set outside the IC.
  • the internal resistor 17 of the IC is used to increase the isolation to prevent the signal of the FET 6 from interfering with the current fluctuation information circuit 1 when the resistor 9 is small. Please refer to FIG.
  • the circuit provided by the invention can be used in various electronic devices and IC circuits such as electronics and communication, and is especially suitable for high frequency communication circuits.
  • the field effect transistor bias circuit of the present invention has the following advantages:
  • a It can perform high-efficiency temperature compensation on some characteristics of the signal action FET; -; b. It can reduce the static drain current deviation of the signal action FET of each chip in the whole wafer;
  • - e. can control a single positive power signal action FET, or can control a signal action FET with a negative gate power;
  • the static leakage current of the signal action FET can be finely adjusted by the external resistor and voltage applied to the IC.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Logic Circuits (AREA)
  • Amplifiers (AREA)
  • Control Of Electrical Variables (AREA)
  • Semiconductor Integrated Circuits (AREA)

Description

场效应管偏置电路
技术领域
本发明是关于一种场效应管偏置电路， 旨在提供一种高效率的场效 应管偏置电路， 其可克服因温度变动而引发场效应管静态漏极电流变动 的缺失， 减少在温度变化时场效应管的增益及线性特性的变动幅度， 并 可减小整枚晶圆内各个场效应管静态漏极电流偏差。 背景技术
设计含有场效应管的电路时需考虑如下因素： 一、 抑制由周围环境 温度及场效应管自身发热而产生的温度变化所引发的电子器件特性恶化 现象； 二、 减小整枚晶圆内各个场效应管静态漏极电流的偏差。 现有技 术的电路常常靠牺牲场效应管的功率， 通过在漏极或源极上串联一电阻 以获取电流变动信息， 并以此来控制栅极电压， 从而进行补偿。 对于需 要小信号工作的场效应管器件而言， 人们常用信号动作场效应管上采用 自偏压方式， 或在场效应管源极和漏极上加上电阻来稳定静态漏极电流。 对于器件功率消耗较少或对效率要求不高的场效应管来讲， 上述现有技 术的解决方案尚可容忍。 然而， 对于注重效率的大场效应管器件而言， 以上方法则行不通。 因为自偏压方式或在场效应管源极和漏极上加上电 阻来稳定静态漏极电流的时候， 一旦在源极或漏极串联上电阻， 流过电 阻上的电流必然将引起场效应管上电力的损耗。 发明内容
本发明为克服现有的温度变动时信号动作场效应管静态漏极电流变 动的缺点， 改善整枚晶圆内各个场效应管静态漏极电流偏差而提供一种 高效率场效应管偏置电路。 本发明所采用的技术方案是： 提供一种场效应管偏置电路， 其包括 具有电源的电流变动信息电路； 与该电流变动信息电路信号输出端连接 的电阻， 该电阻另一端接于一基准电压源， 且该电阻与电流变动信息电 路的连接点作为提供电压变动信息的输出端； 以及至少接有一电压源的 分压电路， 其连接于提供电压变动信息的输出端； '通过将该输出端的电 压变动信息提供给分压电路， 并从该分压电路中取出一个分压作为该场 效应管偏置电路的输出端， 用以控制一信号动作场效应管的静态漏极电 流。
本发明的有益效果是为： 采用本发明的场效应管偏置电路除可在温 度变化情况下保持静态漏极电流稳定之外， 还可减少在温度变化时静态 漏极电流变动而引发的增益及线性特性的变动幅度； 而且， 本发明的电- 路可与被控制信号动作场效应管制作集成于同一芯片上， 也可不与被控 ^ 制信号动作场效应管集成于同一芯片上， 作为一独立器件制作及使用。. V 另外， 本发明的电路整体的电路面积及功耗极小， 可与被控制信号动作. 场效应管一起集成于一个 IC芯片里， 也可与被控制信号动作场效应管封、 装在同一个管壳内、 成本较低、 易于集成制造。 附图说明
图 1是本发明场效应管偏置电路的电路图。
图 2是本发明场效应管偏置电路的第一实施例。
图 3是场效应管静态漏极电流的温度特性曲线。
图 4是场效应管静态漏极电流对栅极电压的温度特性曲线， 其显示无 温度补偿状态下， 信号动作场效应管的静态漏极电流随栅极电压减小而 减小的特性。 .
图 5是实施本发明场效应管偏置电路后信号动作场效应管的静态漏 极电流的温度特性曲线。
图 6是显示不同温度条件下， 场效应管有不同的临界值电压， 其显示 未实施本发明场效应管偏置电路时场效应管栅极电压对静态漏极电流的 特性曲线。
图 7是显示整枚晶圆上不同位置芯片所制成的场效应管有不同的临 界值电压， 其显示未实施本发明场效应管偏置电路时场效应管栅极电压 对静态漏极电流的特性曲线。
图 8是显示整枚晶圆中， 各场效应管偏置电路中之场效应管与被控制 •信号动作场效应管静态漏极电流偏差分布， 以及实施本发明场效应管偏 置电路后， 被控制信号动作场效应管静态漏极电流偏差分布。
图 9是本发明场效应管偏置电路的第二实施方式。
图 10是本发明场效应管偏置电路的第三实施方式。
图 11是本发明场效应管偏置电路的一种改进的实施例。
图 12是本发明场效应管偏置电路的另一种改进的实施例。 具体实施方式
请参照图 1 , 是本发明场效应管偏置电路的方块图。 本发明的场效应 管偏置电路包括由电流变动信息电路 1与电阻 2构成的电压变动信息电路 以及与该电压变动信息电路结合的分压电路 4。 其中， 该电流变动信息电 路 1是利用功率消耗极小的场效应管构成， 其由电源 18供电。 该电阻 2连 接电流变动信息电路 1的信号输出端， 电阻 2另一端上施加基准电压源 7。 电流变动信息电路 1与电阻 2的连接点作为该电压变动信息电路的输出端 3， 通过将该输出端 3的电压变动信息提供给至少接有一个电压源 10的分 压电路 4， 并从分压电路 4中取出一个分压， 作为本发明场效应管偏置电 路的输出端 5， 用以控制实际信号动作的信号动作场效应管 6的电流。 该 分压电路 4的供给电压源 10可选为一正电源或一负电源， 其正负是由场效 应管 6栅极需要的电压工作状态来决定； 其中， 通过计算分压电路 4的输 出端 5的电位与电位变动量， 来决定分压电路 4的构成。
• 本发明的电路中， 减小整枚晶圆上各个不同位置制成的信号动作场 效应管 6的静态漏极电流偏差与温度补偿所依据的原理相同， 因而下文仅 以温度补偿原理为例， 说明本发明的具体实施例。
请参考图 2，为本发明场效应管偏置电路的第一实施例。本实施例中， 该电流变动信息电路 1包括场效应管 14及两个串联的分压电阻 11， 12， 该 场效应管 14源极接地， 其漏极经电阻 2连接于基准电压源 7， 其栅极连接 于二分压电阻 11，12之间， 该二分压电阻 11， 12—端接地， 另一端连接于 电源 18。 该电源 18与电压源 10共享一组电源， 通过分压电阻 11与电阻 12 加在场效应管 14栅极上， 由此设定场效应管 14的静态漏极电流。 电流变 动信息电路 1与电阻 2的连接点作为提供电压变动信息的输出端 3， 该输出. 端 3接分压电路 4， 该分压电路 4包括二串联电阻 8及 9， 电阻 8—端接电 -J5 源 10， 电阻 8的另一端与电阻 9相连， 电阻 9的另一端与电压变动信息电^ 的输出端 3相连， 在电阻 8和 9之间引出一输出端 5与被控制信号动作场效 应管 6栅极连接， 用来控制信号动作场效应管 6的静态漏极电流。 其中， 信号动作场效应管 6漏极由电源 13供电。
另外， 上述电流变动信息电路 1中采用三极管来代替场效应管 14也可 达成相同的功效。
请参照图 3 ,其为场效应管静态漏极电流的温度特性曲线。如图所示， 当温度升高时， 无温度补偿状态下， 信号动作场效应管 6的静态漏极电流 具有随温度升高而增大的特性。
请参照图 4， 其显示当温度一定时， 无温度补偿状态下， 信号动作场 效应管 6的静态漏极电流具有随栅极电压减小而减小的特性。 本发明利用图 3与图 4所说明的特性原理， 在温度变化时， 通过加在 信号动作场效应管 6栅极上电压的高低变化来抑制信号动作场效应管 6静 态漏极电流的变动。
根据图 3所示的静态漏极电流的温度特性曲线， 当温度升高时， 本实 施例中电流变动信息电路 1中的场效应管 14静态漏极电流增大， 其电阻变 小， 因而电压变动信息输出端 3电位降低， 分压电路 4的输出端 5的电位也 随之降低。 因而， 根据图 4显示的信号动作场棼应管 6的静态漏极电流随 栅极电压减小而减小的特性， 此时降低的电位若施加至信号动作场效应 管 6栅极上则恰可抑制抵消信号动作场效应管 6静态漏极电流的增大， 达 成温度补偿的目的， 具体如下：
在室温 25°C时， 假定要设定信号动作场效应管 6静态漏电流的目标值」- 为 100mA, 此时加到电流变动信息电路 1中的场效应管 14的栅极上的负压； -0.8V。 通过本发明的电路设计， 与电阻 2串联的电流变动信息电路 1中 提供电压变动信息的输出端 3电压将为 2V, 此时通过分压电路 4加到信号: ί 动作场效应管 6上的电压为 -0.6V, 对应信号动作场效应管 6上的静态漏极：., 电流为我们希望的 100mA。
若温度升高时， 假定温度升为 85Ό， 此时未使用本发明场效应管偏 置电路的信号动作场效应管 6的静态漏电流将上升为 180mA， 而我们希望 保持静态漏电流为 100mA不变。 若采用本发明场效应管偏置电路， 参照 图 3及图 4的原理， 随温度增大， 场效应管 14的静态漏极电流也随温度增 大， 电流变动信息电路 1的输出电流也增大 4， 因此在电阻 2上的电压 降增大， 而基准.电压源 7电压是一定的， 因而电压变动信息的输出端 3电 压降为 1.6V, 此时经由分压电路 4加到信号动作场效应管 6栅极上的电压 变为 -0.8V，温度升高到 85°C时引起的信号动作场效应管 6栅极上的电压变 动 Δ V=-0.8V-(-0.6V)=-0.2V, 即.. 当温度升高到 85°C时， 加在信号动作场 效应管 6栅极上的电压降低了 0.2V, 其栅极上降低的 0.2V电压恰好能把信 号动作场效应管 6静态漏电流从 lSOmA拉回到 100mA, 从而保证温度从 25 °C到 85°C变动时， 该信号动作场效应管 6的静态漏电流始终保持在 100mA 左右。
另一方面， 假定当温度降低到 -30°C时， 未使用本发明场效应管偏置 电路的信号动作场效应管 6静态漏电流降为 50mA， 而我们希望信号动作 场效应管 6静态漏电流保持在 100mA不变。 参照前文图 3及图 4的原理， 采 用本发明的偏置电路时： 随温度降低， 电流变动信息电路 1中的场效应管 14静态漏极电流也减少， gP': 电流变动信息电路 1的输出电流也减小， 因 此在电阻 2上的电压降减小， 而基准电压源 7电压是一定的， 于是电压变 动信息的输出端 3电压升为 2.4V， 此时经由分压电路 4加到信号动作场效.. 应管 6栅极上的电压变将为 -0.42V,温度降低到 -30°C时引起的信号动作场 5 效应管 6栅极上的电压变动 A V=-0.42V-(-0.6V)=0.18V， 即： 当温度降低到 -30Ό时， 加在信号动作场效应管 6栅极上电压上升了 0.18V。 栅极上升的 0.18V电压提供至信号动作场效应管 6栅极时恰可能把信号动作场效应管 ^ - 6静态漏电流从 50mA拉回到 100mA,从而保证温度从 25°C至 -30°C变动时， 信号动作场效应管 6静态漏电流始终保持在 100mA附近。
综上所述可知本发^场效应管偏置电路不会导致信号动作场效应管 6的额外损耗， 其使信号动作场效应管 6高效率工作的同时， 可对信号动 作场效应管 6漏极电流起温度补偿的功用。 如图 5所示， 实施本发明上述 电路的信号动作场效应管 6于温度变化的环境下仍可保持稳定的静态漏 极电流。
此外， 可通过 IC芯片试做或计算机模拟以及温度实验设计出本发明 中场效应管 14的尺寸大小、 所需电压及各个电阻值， 使其可对信号动作 场效应管 6的静态漏极电流进行温度补偿。 请参照图 6， 其显示未实施本发明场效应管偏置电路时， 信号动作场 效应管 6在不同温度条件下的栅极电压对静态漏极电流的曲线 ·， 其表明信 号动作场效应管 6在不同温度条件下有着不同的临界值电压 Vth， 且该临 界值电压 Vth具有随着温度升高而减小的特性。
图 7显示未实施本发明场效应管偏置电路时， 信号动作场效应管
(FET) 6的栅极电压对静态漏极电流的特性曲线， 其表明整枚晶圆上不 同位置芯片所制作的信号动作场效应管 6有着不同的临界值电压。
经比较可知图 6与图 7非常相似， 因而， 对减小整枚晶圆上不同位置 所制造的信号动作场效应管 6的静态漏极电流的偏差而言， 其所依据的原 理是与图 3、 图 4及图 5的温度补偿原理相同， 不再赘述。
请参照图 8， 其显示整枚晶圆中各个场效应管 （FET) 14与信号动作 . 场效应管 6静态漏极电流偏差分布， 以及实施本发明场效应管偏置电路 后， 信号动作场效应管 6静态漏极电流的偏差分布。 - - . 参照图 8所示， 对于偏置电路中的场效应管 14而言， 即使在同一温度^: 及一定的栅极电压下，整枚芯片中各个场效应管 14(小功率管)的静态漏极 电流也会出现偏差， 呈现分布曲线 a; 同样， 对信号动作场效应管 6而言， · 即使在同一温度及一定的栅极电压下， 整枚芯片中各个信号动作场效应 管 6的静态漏极电流也会出现偏差， 呈现分布曲线 b。 实施本发明场效应 管偏置电路后可减小整枚芯片中各个场效应管 6静态漏极电流出现的偏 差， 呈现分布曲线 c。例如， 二大功率信号动作场效应管 6A及 6B为整枚晶 圆不同位置所制成的场效应管， 未使用本发明场效应管偏置电路时， 在 一定栅极电压下， 其静态漏极电流分别为 100mA与 130mA。 使用本发明 的偏置电路后， 将大功率信号动作场效应管 6A的静态漏极电流同样设定 为 100mA时， 与大功率信号动作场效应管 6A在同一芯片内的偏置电路中 的场效应管 14A的静态漏极电流为 lmA， 电压变动信息的输出端 3电压为 N2005/000516
Vax, 输出端 5的电压为 Vao。 同样方法制作的电路， 大功率信号动作场效 应管 6B的偏置电路中的场效应管 MB的电流比场效应管 14A的电流大，:为 1.3mA。 大功率信号动作场效应管 6B的偏置电路中的电压变动信息的输 出端 3电压为 Vbx， 输出端 5的电压为 Vbo。 此时， 由于 Vbx<Vax， 因此输 出端 5的电压 Vbc Vao, 意味着加在大功率信号动作场效应管 6B栅极上的 电压要比加在大功率信号动作场效应管 6A栅极上的电压低。 因此， 大功 率信号动作场效应管 6B的静态漏极电流就会变小， 要小于 130mA。 因而， 本发明场效应管偏置电路除温度补偿功能之外， 也可减小各个大功率场 效应管静态漏极电流的偏差。
请参照图 9， 其为本发明场效应管偏置电路的第二实施例， 其电路构 造与图 2揭示的实施例相似。 但是， 其电流变动信息电路 1是采用二极管 · 构成。 该二极管一端接地， 另一端连接电阻 2， 该电阻 2另一端接于基准 电压源 7, 且该电阻 2与该二极管的连接点作为提供电压变动信息之输出 端3。 由于二极管的电流变动特性与场效应管电流变动特性近似， 因此'，― 配合分压电路 4的设定， 也可实现本发明的功能。 此时， 电源 18上不必加 电， 呈开放状态。
图 10为本发明场效应管偏置电路的第三实施例， 其电路构造与图 2揭 示的实施例相似。 此实施例不同之处在于： 电源 18为独立电源。
请参考图 11， 其显示在图 10中的电路基础上， 通过进行外部微调整 来设定信号动作场效应管 6静态漏极电流的方式。 图中所示虚线内的部分 可集成于 IC内部， 虚线外的电阻 15、 电阻 16不必集成在 IC内。 由于 IC制 作工艺的偏差， 当信号动作场效应管 6静态漏极电流与理想设计值有偏差 时， 可通过设定在 IC外部的调整电阻 15,16来进行微调整。 此外， IC内部 的电阻 17是用以增加隔离度， 防止当电阻 9较小时， 信号动作场效应管 6 的信号对电流变动信息电路 1的干扰。 请参考图 12， 其显示偏置电路中电阻 2设置于 IC芯片外部的情况。 IC 内部的电阻除了制造中的偏差外， 其温度 $化时偏差也较大， 而我们希 望电阻 2尽可能是偏差比较小的电阻。 为此将电阻 2设置于 IC外部， 不采 用 IC电阻， 由此电压变动信息的输出端 3电压偏差也会较小， 信号动作场 效应管 6的输出端 5的电压偏差也会较小。
本发明提供的电路可用于电子、 通讯等各种电子器件及 IC电路中， 尤其是适用于高频通信电路。 采用本发明的场效应管偏置电路具有如下 的优点：
a. 可以对信号动作场效应管的部分特性进行高效率的温度补偿; -； b. 可以减小整枚晶圆内各个芯片的信号动作场效应管静态漏极电流 偏差；
c 整个电路面积小， 可与被控制信号动作场效应管一起集成在 个 IC芯片里， 工艺简单、 成本低、 可靠性高； · d. 可以与被控制信号动作场效应管封装在同一支管壳内； ··
- e.可以控制单一正电源信号动作场效应管， 也可控制具有负栅极电 源的信号动作场效应管；
f. 可以通过 IC外部的电阻及施加电压对信号动作场效应管的静态漏 极电流进行微调整。

Claims

权利要求书
1.——种场效应管偏置电路， 其特征在于： 其包括具有电源的电流变 动信息电路； 与该电流变动信息电路信号输出端连接的电阻， 该电阻另 一端接于一基准电压源， 且该电阻与电流变动信息电路的连接点作为提 供电压变动信息的输出端； 以及至少接有一电压源的分压电路， 其连接 于提供电压变动信息的输出端； 通过将该输出端的电压变动信息提供给 分压电路， 并从该分压电路中取出一个分压作为该场效应管偏置电路的 输出端， 用以控制一信号动作场效应管的电流。
2. 根据权利要求 1所述的场效应管偏置电路， 其特征在于：其中该分 压电路的输出端连接该被控制信号动作场效应管的栅极。
3. 根据权利要求 1所述的场效应管偏置电路， 其特征在于： 该分压电 路的输出端与被控制信号动作场效应管的栅极之间接入一增加隔离度的 电阻。
4. ·根据权利要求 1所述的场效应管偏置电路， 其特征在于： 其中该电 流变动信息电路包括场效应管及两个串联的分压电阻， 该场效应管源极 接地， 其漏极经电阻连接于基准电压源， 其栅极连接于两个分压电阻之 间， 该二分压电阻一端接地， 另一端连接于电源； 或者， 该电流变动信 息电路包括三极管及两个串联的分压电阻， 该三极管发射极接地， 其集 电极经电阻连接于基准电压源， 其基极连接于二分压电阻之间， 该二分 压电阻一端接地， 一端连接于电源。
5. 根据权利要求 1所述的场效应管偏置电路， 其特征在于： 该场效应 管偏置电路与被控制的信号动作场效应管是封装在同一支管壳内； 或是 一同集成在同一个集成电路芯片中； 或是制作在不同的晶片上。
6. 根据权利要求 1至 5中任意一项所述的场效应管偏置电路， 其特征 在于： 在该电源与电流变动信息电路之间接入一可调电阻； 在电压源与 分压电路之间接入一可调电阻； 且该可调电阻设置在该偏置电路芯片外 部。
8. 根据权利要求 1所述的场效应管偏置电路， 其特征在于： 供给该分 压电路的电源可为一正电源或一负电源， 其正负是由场效应管栅极需要 的电压工作状态来决定； 其中， 通过计算分压电路输出端的电位与电位 变动量， 来决定分压电路的构成。
9. 根据权利要求 1所述的场效应管偏置电路，其特征在于： 该基准电 压源、 电压源、 信号动作场效应管漏极的供电电源与电源为相互独立的 电源;；或者， 该基准电压源、 电压源、 信号动作场效应管的漏极供电电 源与电源之间相互连接， 接入共同电源。
10. 一种场效应管偏置电路，其特征在于：其包括电流变动信息电路， 该电流变动信息电路为二极管， 该二极管一端接地， 另一端连接一电阻， 该电阻另一端接于一基准电压源， 且该电阻与该二极管的连接点作为提 供电压变动信息的输出端； 以及至少接有一电压源的分压电路， 其连接 于提供电压变动信息的输出端； 通过将该输出端的电压变动信息提供给 分压电路， 并从该分压电路中取出一个分压作为该场效应管偏置电路的 输出端， 用以控制一信号动作场效应管的电流。
PCT/CN2005/000516 2004-08-02 2005-04-18 Circuit de polarisation a transistor a effet de champ WO2006012784A1 (fr)

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Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2541763B1 (en) * 2010-02-25 2018-12-05 Sharp Kabushiki Kaisha Bias circuit, lna, lnb, receiver for communication, transmitter for communication, and sensor system
CN103475312A (zh) * 2013-09-10 2013-12-25 昆山新金福精密电子有限公司 一种信号源电路

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1219024A (zh) * 1997-11-27 1999-06-09 日本电气株式会社 一种可补偿由环境温度变化所引起的失真的半导体电路
US6166591A (en) * 1998-12-11 2000-12-26 E.C.I. Telecom Ltd. FET gate biasing control device for power amplifier
CN1283327A (zh) * 1997-12-22 2001-02-07 艾利森电话股份有限公司 低压晶体管的偏置
US20020009980A1 (en) * 2000-05-12 2002-01-24 Masayuki Katakura Bias circuit and radio communication apparatus using same
CN1346537A (zh) * 1999-04-13 2002-04-24 艾利森电话股份有限公司 用于场效应晶体管的偏置装置
US20020135423A1 (en) 2001-03-21 2002-09-26 Kiichi Yamashita Power amplifier module

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB8810750D0 (en) * 1988-05-06 1988-06-08 Salplex Ltd Mosfet power switch arrangements
CN2054231U (zh) * 1989-06-28 1990-03-07 北京市西城新开通用试验厂 一种大功率数控调压与变流装置
US5757237A (en) * 1996-08-28 1998-05-26 Motorola, Inc. Method for dynamically biasing an amplifier and circuit therefor
DE19742954C1 (de) * 1997-09-29 1999-02-25 Fraunhofer Ges Forschung Temperaturkompensationsschaltung für Feldeffekttransistor-Verstärkerschaltungen
GB2334167B (en) * 1998-02-07 2002-09-11 Motorola Ltd Amplifying circuit and method for determining optimal bias voltages therein
DE19829031A1 (de) * 1998-06-30 2000-01-05 Thomson Brandt Gmbh Kompensation von Bildrohralterungseffekten
US6046642A (en) * 1998-09-08 2000-04-04 Motorola, Inc. Amplifier with active bias compensation and method for adjusting quiescent current
US6201444B1 (en) * 1999-09-01 2001-03-13 Spectrian Corporation Current source bias circuit with hot carrier injection tracking
JP3532834B2 (ja) * 2000-06-27 2004-05-31 富士通カンタムデバイス株式会社 高周波増幅器バイアス回路、高周波電力増幅器および通信装置
US6753734B2 (en) * 2001-06-06 2004-06-22 Anadigics, Inc. Multi-mode amplifier bias circuit
CN100416962C (zh) * 2001-12-31 2008-09-03 中兴通讯股份有限公司 一种过温保护电路
US6614309B1 (en) * 2002-02-21 2003-09-02 Ericsson Inc. Dynamic bias controller for power amplifier circuits
US6891438B2 (en) * 2002-12-12 2005-05-10 Northrop Grumman Corporation Adaptive active bias compensation technique for power amplifiers
US6956437B2 (en) * 2003-12-23 2005-10-18 Agere Systems Inc. Metal-oxide-semiconductor device having integrated bias circuit

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1219024A (zh) * 1997-11-27 1999-06-09 日本电气株式会社 一种可补偿由环境温度变化所引起的失真的半导体电路
CN1283327A (zh) * 1997-12-22 2001-02-07 艾利森电话股份有限公司 低压晶体管的偏置
US6166591A (en) * 1998-12-11 2000-12-26 E.C.I. Telecom Ltd. FET gate biasing control device for power amplifier
CN1346537A (zh) * 1999-04-13 2002-04-24 艾利森电话股份有限公司 用于场效应晶体管的偏置装置
US20020009980A1 (en) * 2000-05-12 2002-01-24 Masayuki Katakura Bias circuit and radio communication apparatus using same
US20020135423A1 (en) 2001-03-21 2002-09-26 Kiichi Yamashita Power amplifier module

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CN1671042A (zh) 2005-09-21
US20070229153A1 (en) 2007-10-04
CN100407572C (zh) 2008-07-30
US7420420B2 (en) 2008-09-02
EP1777812A4 (en) 2007-08-29
EP1777812A1 (en) 2007-04-25
EP1777812B1 (en) 2012-11-21

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