WO2006012376A1 - Reverse link power control in an orthogonal system - Google Patents

Reverse link power control in an orthogonal system Download PDF

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Publication number
WO2006012376A1
WO2006012376A1 PCT/US2005/025803 US2005025803W WO2006012376A1 WO 2006012376 A1 WO2006012376 A1 WO 2006012376A1 US 2005025803 W US2005025803 W US 2005025803W WO 2006012376 A1 WO2006012376 A1 WO 2006012376A1
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WO
WIPO (PCT)
Prior art keywords
rpot
received
packet
over thermal
error
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2005/025803
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English (en)
French (fr)
Inventor
Arak Sutivong
Avneesh Agrawal
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Qualcomm Inc
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Priority to AU2005267163A priority Critical patent/AU2005267163B2/en
Priority to BRPI0513699-7A priority patent/BRPI0513699B1/pt
Priority to MX2007000812A priority patent/MX2007000812A/es
Priority to CN2005800314008A priority patent/CN101023597B/zh
Priority to JP2007522717A priority patent/JP4499786B2/ja
Priority to CA2574561A priority patent/CA2574561C/en
Priority to EP05776325A priority patent/EP1769589A1/en
Publication of WO2006012376A1 publication Critical patent/WO2006012376A1/en
Anticipated expiration legal-status Critical
Priority to IL180829A priority patent/IL180829A0/en
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W52/00—Power management, e.g. Transmission Power Control [TPC] or power classes
    • H04W52/04—Transmission power control [TPC]
    • H04W52/06—TPC algorithms
    • H04W52/14—Separate analysis of uplink or downlink
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W52/00—Power management, e.g. Transmission Power Control [TPC] or power classes
    • H04W52/04—Transmission power control [TPC]
    • H04W52/30—Transmission power control [TPC] using constraints in the total amount of available transmission power
    • H04W52/36—Transmission power control [TPC] using constraints in the total amount of available transmission power with a discrete range or set of values, e.g. step size, ramping or offsets
    • H04W52/367—Power values between minimum and maximum limits, e.g. dynamic range
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W52/00—Power management, e.g. Transmission Power Control [TPC] or power classes
    • H04W52/04—Transmission power control [TPC]
    • H04W52/06—TPC algorithms
    • H04W52/12—Outer and inner loops
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W52/00—Power management, e.g. Transmission Power Control [TPC] or power classes
    • H04W52/04—Transmission power control [TPC]
    • H04W52/06—TPC algorithms
    • H04W52/14—Separate analysis of uplink or downlink
    • H04W52/146—Uplink power control
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W52/00—Power management, e.g. Transmission Power Control [TPC] or power classes
    • H04W52/04—Transmission power control [TPC]
    • H04W52/18—TPC being performed according to specific parameters
    • H04W52/20—TPC being performed according to specific parameters using error rate
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W52/00—Power management, e.g. Transmission Power Control [TPC] or power classes
    • H04W52/04—Transmission power control [TPC]
    • H04W52/18—TPC being performed according to specific parameters
    • H04W52/24—TPC being performed according to specific parameters using SIR [Signal to Interference Ratio] or other wireless path parameters
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W52/00—Power management, e.g. Transmission Power Control [TPC] or power classes
    • H04W52/04—Transmission power control [TPC]
    • H04W52/18—TPC being performed according to specific parameters
    • H04W52/28—TPC being performed according to specific parameters using user profile, e.g. mobile speed, priority or network state, e.g. standby, idle or non-transmission
    • H04W52/286—TPC being performed according to specific parameters using user profile, e.g. mobile speed, priority or network state, e.g. standby, idle or non-transmission during data packet transmission, e.g. high speed packet access [HSPA]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W52/00—Power management, e.g. Transmission Power Control [TPC] or power classes
    • H04W52/04—Transmission power control [TPC]
    • H04W52/30—Transmission power control [TPC] using constraints in the total amount of available transmission power
    • H04W52/36—Transmission power control [TPC] using constraints in the total amount of available transmission power with a discrete range or set of values, e.g. step size, ramping or offsets
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W52/00—Power management, e.g. Transmission Power Control [TPC] or power classes
    • H04W52/04—Transmission power control [TPC]
    • H04W52/38—TPC being performed in particular situations
    • H04W52/48—TPC being performed in particular situations during retransmission after error or non-acknowledgment

Definitions

  • the present invention relates generally to communications, and more specifically to techniques for determining reverse link power control in an orthogonal communication system.
  • FH-OFDMA Frequency-Hopping Orthogonal Frequency Division Multiple Access
  • bandwidth is evenly divided into a number of orthogonal sub- carriers. Each user is given a number of these OFDM sub-carriers.
  • FH-OFDMA users will also be hopping (i.e., the subset of OFDM carriers assigned to each user changes over time) across the whole bandwidth. All users within the same sector or cell are orthogonal to each other and hence cause no interference to each other.
  • FH-OFDMA is an efficient multiplexing technique for high data rate transmission over wireless channels.
  • SNR Signal-to-Noise Ratio
  • H-ARQ H-ARQ
  • a closed-loop power control is often employed to ensure that sufficient SNR (i.e., SNR required to close the communication link) is received at the base station.
  • SNR Signal-to-Noise Ratio
  • the transmit power required for a successful transmission can be decreased if the number of (re)transmissions allowed increases.
  • rate and power adaptation makes the design of a power control loop for a system with retransmissions a nontrivial task.
  • a method of reverse link power control comprises transmitting a packet, determining whether the packet has been received without error, decreasing an effective carrier-to-interference (C/I) setpoint if the packet has been received without error, and increasing the effective C/I setpoint if the packet has not been received without error.
  • C/I carrier-to-interference
  • a method of reverse link power control further comprises determining whether a Received Power Over Thermal (RpOT) is less than a maximum
  • a method of reverse link power control further comprises issuing a down command if the RpOT is not greater than the RpOT m3x .
  • a method of reverse link power control further comprises determining whether an effective carrier-to-interference ratio (C/I) is less than an effective carrier-to-interference ratio for the setpoint (C/I sp ). In an aspect, a method of reverse link power control further comprises determining whether a Received Power
  • RpOT Received Power Over Thermal
  • a method of reverse link power control further comprises issuing a down command if the effective carrier-to-interference ratio (C/I) is not less than the effective carrier-to-interference ratio for the setpoint (C/I sp ) or the Received Power Over
  • a method of reverse link power control further comprises issuing a up command if the effective carrier-to-interference ratio (C/I) is less than the effective carrier-to-interference ratio for the setpoint (C/I sp ) and the Received Power Over
  • the steps of determining whether the packet has been received without error, decreasing an effective carrier-to-interference (C/I) setpoint if the packet has been received without error, and increasing the effective C/I setpoint if the packet has not been received without error comprise an outer loop power control.
  • method of reverse link power control further comprises disabling the outer loop power control if the Received Power Over Thermal (RpOT) is less than or equal to the minimum Received Power Over Thermal (RpOT m j n ) or if the Received Power Over Thermal (RpOT) is greater than or equal to the maximum Received Power Over Thermal RpOT m2x .
  • method of reverse link power control further comprises enabling the outer loop power control if the Received Power Over Thermal (RpOT) is greater than the minimum Received Power Over Thermal (RpOT m i n ) and the Received Power Over Thermal (RpOT) is less than the maximum Received Power Over Thermal RpOT n13x .
  • a wireless communications device comprises means for transmitting a packet, means for determining whether the packet has been received without error, means for decreasing an effective carrier-to-interference (C/I) setpoint if the packet has been received without error, and means for increasing the effective C/I setpoint if the packet has not been received without error.
  • C/I carrier-to-interference
  • a processor is programmed to execute a method of estimating interference in a wireless communication system, the method comprising transmitting a packet, determining whether the packet has been received without error, decreasing an effective carrier-to-interference (C/I) setpoint if the packet has been received without error, and increasing the effective C/I setpoint if the packet has not been received without error.
  • C/I carrier-to-interference
  • a computer readable media embodying a method of reverse link power control comprises transmitting a packet, determining whether the packet has been received without error, decreasing an effective carrier-to-interference (C/I) setpoint if the packet has been received without error, and increasing the effective C/I setpoint if the packet has not been received without error.
  • C/I carrier-to-interference
  • FIG. 1 shows a wireless multiple-access communication system 100 in accordance with an embodiment
  • FIG. 2 shows a flowchart of an outer loop power control in accordance with an embodiment
  • FIG. 3 shows a flowchart of an inner loop power control in accordance with an embodiment
  • FIG. 4 shows a block diagram of a terminal and a base station.
  • the techniques described herein for performance based rank prediction may be used for various communication systems such as a Code Division Multiple Access (CDMA) system, a Wideband CDMA (WCDMA) system, a direct sequence CDMA (DS-CDMA) system, a Time Division Multiple Access (TDMA) system, a Frequency Division Multiple Access (FDMA) system, a High Speed Downlink Packet Access (HSDPA) system, an orthogonal frequency division multiplexing (OFDM)-based system, an Orthogonal Frequency Division Multiple Access (OFDMA) system, a single- input single-output (SISO) system, a multiple-input multiple-output (MIMO) system, and so on.
  • CDMA Code Division Multiple Access
  • WCDMA Wideband CDMA
  • DS-CDMA direct sequence CDMA
  • TDMA Time Division Multiple Access
  • FDMA Frequency Division Multiple Access
  • HSDPA High Speed Downlink Packet Access
  • OFDM orthogonal frequency division multiplexing
  • OFDMA Orthogonal Fre
  • OFDM is a multi-carrier modulation technique that effectively partitions the overall system bandwidth into multiple (NF) orthogonal subbands. These subbands are also referred to as tones, subcarriers, bins, and frequency channels. With OFDM, each subband is associated with a respective subcarrier that may be modulated with data. Up to NF modulation symbols may be transmitted on the NF subbands in each OFDM symbol period. Prior to transmission, these modulation symbols are transformed to the time-domain using an NF-point inverse fast Fourier transform (EFFT) to obtain a "transformed" symbol that contains NF chips.
  • EFFT NF-point inverse fast Fourier transform
  • An OFDMA system utilizes OFDM and can support multiple users simultaneously.
  • data for each user is transmitted using a specific frequency hopping (FH) sequence assigned to the user.
  • the FH sequence indicates the specific subband to use for data transmission in each hop period.
  • Multiple data transmissions for multiple users may be sent simultaneously using different FH sequences.
  • FH sequences are defined to be orthogonal to one another so that only one data transmission uses each subband in each hop period.
  • a power control loop can be broken into two parts: an inner loop and an outer loop.
  • a base station issues an UP/DOWN power control command as dictated by an inner loop to regulate the user's transmit power such that the desired quantity (such as received signal power, signal-to-interference-and-noise ratio (SINR), etc.) set by the power control outer loop is maintained.
  • the outer loop dynamically adjusts this set-point so that the specified quality-of-service (QoS) is met, irrespective of the changing channel conditions.
  • QoS quality-of-service
  • IS-95 and CDMA2000 use a packet error rate (PER) as a QoS metric of choice.
  • PER packet error rate
  • the power control loop regulates the transmit power such that the PER is near the target setpoint (e.g. 1%).
  • target setpoint e.g. 1%
  • a Packet-Error-Rate-based (PER-based) power control algorithm attempts to minimize the transmit power while trying to maintain the target packet error rate. As the maximum number of transmissions allowed increases, the required transmit power decreases (assuming the packet size remains the same).
  • FIG. 1 shows a wireless multiple-access communication system 100 in accordance with an embodiment.
  • System 100 includes a number of base stations 110 that support communication for a number of wireless terminals 120.
  • a base station is a fixed station used for communicating with the terminals and may also be referred to as an access point, a Node B, or some other terminology.
  • Terminals 120 are typically dispersed throughout the system, and each terminal may be fixed or mobile.
  • a terminal may also be referred to as a mobile station, a user equipment (UE), a wireless communication device, or some other terminology.
  • Each terminal may communicate with one or more base stations on the forward and reverse links at any given moment. This depends on whether the terminal is active, whether soft handoff is supported, and whether the terminal is in soft handoff. For simplicity, FIG. 1 only shows transmissions on the reverse link.
  • a system controller 130 couples to base stations 110, provides coordination and control for these base stations, and further controls the routing of data for the terminals served by these base stations.
  • H-ARQ hybrid- ARQ
  • FIG. 1 shows a flowchart 200 of an outer loop power control in accordance with an embodiment.
  • the goal of the outer loop is to set a target effective carrier-to- interference (C/I) for an inner loop to track.
  • An effective C/I is used instead of, for instance, an average C/I.
  • Effective C/I is a better measure of the channel condition than average C/I in an FH-OFDMA system.
  • Effective SNR is (approximately) proportional to the geometric mean of the SNRs averaged over all tones.
  • a packet is considered in error if it has not been successfully decoded after the specified maximum number of transmissions is reached or if its latency exceeds a specified latency limit. Latency includes both queuing delay and transmission delay. [0039] By declaring packets with latency higher than the maximum latency allowed as packet errors, a latency constraint is seamlessly incorporated into the power control loop. The rationale behind this is that in most real-time applications, late packets are simply discarded since as far as a user's perception is concerned, a corrupted packet or a late-arriving packet is more or less equally detrimental. In addition, packets may be dropped at the transmitter to help regulate packet latency further (because it does not make sense to transmit packets whose latency has already exceeded the limit, as they will be discarded by the receiver anyway).
  • the receiver can detect that some packets have been dropped at the transmitter by detecting that packets are received out of sequence. These missing packets (once detected) are treated as packet errors. Missing packets can only be detected once the next packet in the sequence is decoded correctly at the receiver. In essence, corrupted packets, dropped packets and packets with excessive latency are declared as packet errors and the outer loop dynamically adjusts the effective C/I setpoint to maintain the packet error rate at a target value. By choosing the step sizes in adjusting the effective C/I setpoint properly, the target PER can be controlled to a desired value.
  • step 202 a check is made to determine whether the setpoint is to be updated. If not, then the flow of control goes back to step 202 on the next iteration. If the setpoint is to be updated, then the flow of control proceeds to step 204. [0042] In step 204, a check is made to determine whether there is a packet error. If there is no packet error, then the flow of control proceeds to step 206. Otherwise, the flow of control proceeds to step 208.
  • step 206 a check is made to determine whether a packet is missing. If the packet is missing, then the flow of control proceeds to step 208 and the effective C/I setpoint is increased. Otherwise, the flow of control proceeds to step 210 and the effective C/I setpoint is decreased.
  • the base station then issues an UP/DOWN power control command (e.g., +/- 1 dB) using an inner loop, as shown in Figure 3.
  • Figure 3 shows a flowchart 300 of an inner loop power control in accordance with an embodiment.
  • the outer loop can be disabled when data is not present.
  • only inner loop control is enabled when data is not present.
  • the inner loop is updated periodically (e.g., every few hops/slots).
  • the base station measures the received signal power and the effective C/I over the measurement interval.
  • the inner loop attempts to maintain the target effective C/I set by the outer loop, while still satisfying a R P OT constraint (i.e., operating R P OT should be between RpOTmin and R p OTmax).
  • the Received Power Over Thermal (R p OT) is defined as the ratio between the received signal power (P) and thermal noise (N 0 ).
  • the inner loop of this proposed algorithm tries to satisfy both the effective C/I and R P OT targets.
  • Set points (e-C/I sp , R p OT min , RpOT m1x ) are user specific. Different Quality of Service (QoS) users may have different RpOT m j n)max constraints. Updates are also user specific.
  • QoS Quality of Service
  • RpOTmin and RpOT 1113x can be determined according to QoS.
  • R p OT m i n and R p OT max can be set equal to each other.
  • the outer loop update is disabled in accordance with an embodiment. This is to prevent the effective C/I setpoint from being incremented or decremented indefinitely.
  • R P OT does not depend on interference power from other users
  • the power control loop is inherently stable (i.e., no indefinite power race between users).
  • the power control loop may drive the transmit power to a very low level, as it may be all that is needed to satisfy the specified packet error rate requirement. This leads to a lower throughput, as discussed previously.
  • R P OT By enforcing the operating range of R P OT, users can essentially choose to tradeoff between data rate and transmit power (e.g., users can enjoy a higher rate from an early termination by transmitting at higher power).
  • RpOTmin helps protect against unnecessary rate loss
  • R p OTmax helps ensure stable operation.
  • R p OTmin R p OTmax
  • the outer loop is essentially disabled. Effectively, the base station regulates the user's transmit power such that the target RpOT is met.
  • This setting may be used in supporting best-effort traffic, where a user can always benefit from having a higher data rate.
  • step 302 a check is made to determine whether the inner loop is to be updated. If not, then the flow of control goes back to step 302 on the next iteration. If the inner loop is to be updated, then the flow of control proceeds to step 304. [0054] In step 304, a check is made to determine whether R P OT > R p OTmax. If yes, then the flow of control proceeds to step 306 and a DOWN command is issued by the base station. If not, then the flow of control proceeds to step 308. [0055] In step 308, a check is made to determine whether an effective C/I is less than an effective C/I sp or R P OT ⁇ R p OT min .
  • Effective C/I sp is the effective C/I for a setpoint. If yes, then the flow of control proceeds to step 310 and the base station issues an UP command. If no, then the flow of control proceeds to step 306 and the base station issues a DOWN command.
  • a hysteresis function is added to the update functions of the outer and inner loops 200, 300 of figures 2 and 3, respectively.
  • the hysteresis function helps prevent the system from getting into a limit cycle.
  • a packet error automatically results in an UP command to speed up the recovery (assuming, of course, that the R P OT constraint is not violated).
  • the outer loop is disabled while continuing to execute the inner loop. When a data channel comes back, the operation of the outer loop can seamlessly be resumed. Thus, same underlying power control loop is used for both the control and data channels.
  • a transmit (TX) data processor 510 receives and processes (e.g., formats, codes, interleaves, and modulates) reverse link (RL) traffic data and provides modulation symbols for the traffic data.
  • TX data processor 510 also processes control data (e.g., CQI) from a controller 520 and provides modulation symbols for the control data.
  • a modulator (MOD) 512 processes the modulation symbols for traffic and control data and pilot symbols and provides a sequence of complex- valued chips. The processing by TX data processor 510 and modulator 512 is dependent on the system.
  • modulator 512 may perform OFDM modulation if the system utilizes OFDM.
  • a transmitter unit (TMTR) 514 conditions (e.g., converts to analog, amplifies, filters, and frequency upconverts) the sequence of chips and generates a reverse link signal, which is routed through a duplexer (D) 516 and transmitted via an antenna 518.
  • TMTR transmitter unit
  • D duplexer
  • the reverse link signal from terminal 12Ox is received by an antenna 552, routed through a duplexer 554, and provided to a receiver unit (RCVR) 556.
  • Receiver unit 556 conditions (e.g., filters, amplifies, and frequency downconverts) the received signal and further digitizes the conditioned signal to obtain a stream of data samples.
  • a demodulator (DEMOD) 558 processes the data samples to obtain symbol estimates.
  • a receive (RX) data processor 560 then processes (e.g., deinterleaves and decodes) the symbol estimates to obtain decoded data for terminal 12Ox.
  • RX data processor 560 also performs erasure detection and provides to a controller 570 the status of each received codeword used for power control.
  • the processing by demodulator 558 and RX data processor 560 is complementary to the processing performed by modulator 512 and TX data processor 510, respectively.
  • the processing for a forward link transmission may be performed similarly to that described above for the reverse link.
  • the processing for reverse link and forward link transmissions is typically specified by the system.
  • an SNR estimator 574 estimates the received SNR for terminal 12Ox and provides the received SNR to a TPC generator 576.
  • TPC generator 576 also receives the target SNR and generates TPC commands for terminal 12Ox.
  • the TPC commands are processed by a TX data processor 582, further processed by a modulator 584, conditioned by a transmitter unit 586, routed through duplexer 554, and transmitted via antenna 552 to terminal 12Ox.
  • the forward link signal from base station HOx is received by antenna 518, routed through duplexer 516, conditioned and digitized by a receiver unit 540, processed by a demodulator 542, and further processed by an RX data processor 544 to obtain received TPC commands.
  • a TPC processor 524 detects the received TPC commands to obtain TPC decisions, which are used to generate a transmit power adjustment control.
  • Modulator 512 receives the control from TPC processor 524 and adjusts the transmit power for the reverse link transmission. Forward link power control may be achieved in a similar manner.
  • Controllers 520 and 570 direct the operations of various processing units within terminal 12Ox and base station HOx, respectively. Controller 520 and 570 may also perform various functions for erasure detection and power control for the forward link and reverse link. For example, each controller may implement the SNR estimator, TPC generator, and target SNR adjustment unit for its link. Controller 570 and RX data processor 560 may also implement processes 200 and 300 in FIGS. 2 and 3. Memory units 522 and 572 store data and program codes for controllers 520 and 570, respectively.
  • the erasure detection and power control techniques described herein may be implemented by various means. For example, these techniques may be implemented in hardware, software, or a combination thereof.
  • the processing units used to perform erasure detection and/or power control may be implemented within one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), processors, controllers, micro-controllers, microprocessors, other electronic units designed to perform the functions described herein, or a combination thereof.
  • ASICs application specific integrated circuits
  • DSPs digital signal processors
  • DSPDs digital signal processing devices
  • PLDs programmable logic devices
  • FPGAs field programmable gate arrays
  • processors controllers, micro-controllers, microprocessors, other electronic units designed to perform the functions described herein, or a combination thereof.
  • the techniques described herein may be implemented with modules (e.g., procedures, functions, and so on) that perform the functions described herein.
  • the software codes may be stored in a memory unit (e.g., memory unit 572 in FIG. 5) and executed by a processor (e.g., controller 570).
  • the memory unit may be implemented within the processor or external to the processor, in which case it can be communicatively coupled to the processor via various means as is known in the art.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Mobile Radio Communication Systems (AREA)
  • Radio Relay Systems (AREA)
PCT/US2005/025803 2004-07-20 2005-07-19 Reverse link power control in an orthogonal system Ceased WO2006012376A1 (en)

Priority Applications (8)

Application Number Priority Date Filing Date Title
AU2005267163A AU2005267163B2 (en) 2004-07-20 2005-07-19 Reverse link power control in an orthogonal system
BRPI0513699-7A BRPI0513699B1 (pt) 2004-07-20 2005-07-19 Controle de potência de link reverso em um sistema ortogonal
MX2007000812A MX2007000812A (es) 2004-07-20 2005-07-19 Control de potencia de enlace inverso en un sistema ortogonal.
CN2005800314008A CN101023597B (zh) 2004-07-20 2005-07-19 正交系统中的反向链路功率控制
JP2007522717A JP4499786B2 (ja) 2004-07-20 2005-07-19 直交システムにおける逆方向リンクパワー制御
CA2574561A CA2574561C (en) 2004-07-20 2005-07-19 Reverse link power control in an orthogonal system based on effective carrier-to-interference (c/i)
EP05776325A EP1769589A1 (en) 2004-07-20 2005-07-19 Reverse link power control in an orthogonal system
IL180829A IL180829A0 (en) 2004-07-20 2007-01-21 Reverse link power control in an orthogonal system

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US58982304P 2004-07-20 2004-07-20
US60/589,823 2004-07-20
US11/022,348 2004-12-22
US11/022,348 US7594151B2 (en) 2004-06-18 2004-12-22 Reverse link power control in an orthogonal system

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US (2) US7594151B2 (enExample)
EP (2) EP2429246B1 (enExample)
JP (1) JP4499786B2 (enExample)
KR (1) KR100881545B1 (enExample)
CN (1) CN101023597B (enExample)
AU (1) AU2005267163B2 (enExample)
BR (1) BRPI0513699B1 (enExample)
CA (1) CA2574561C (enExample)
IL (1) IL180829A0 (enExample)
MX (1) MX2007000812A (enExample)
RU (1) RU2355110C2 (enExample)
TW (1) TWI322586B (enExample)
WO (1) WO2006012376A1 (enExample)

Cited By (13)

* Cited by examiner, † Cited by third party
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US7536626B2 (en) 2004-06-18 2009-05-19 Qualcomm Incorporated Power control using erasure techniques
JP2009527197A (ja) * 2006-02-17 2009-07-23 アルカテル−ルーセント ユーエスエー インコーポレーテッド リバースリンク電力制御の方法
US7962826B2 (en) 2004-07-20 2011-06-14 Qualcomm Incorporated Reverse link power control in an orthogonal system
US8018945B2 (en) 2004-04-29 2011-09-13 Interdigital Technology Corporation Method and apparatus for forwarding non-consecutive data blocks in enhanced uplink transmissions
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AU2005267163B2 (en) 2009-03-05
CA2574561A1 (en) 2006-02-02
EP1769589A1 (en) 2007-04-04
TW200627829A (en) 2006-08-01
CN101023597A (zh) 2007-08-22
KR100881545B1 (ko) 2009-02-02
RU2007106107A (ru) 2008-08-27
RU2355110C2 (ru) 2009-05-10
US7594151B2 (en) 2009-09-22
US20060002346A1 (en) 2006-01-05
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BRPI0513699A (pt) 2008-05-13
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AU2005267163A1 (en) 2006-02-02
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IL180829A0 (en) 2007-06-03
EP2429246B1 (en) 2017-04-26
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CN101023597B (zh) 2011-11-23
US20090274232A1 (en) 2009-11-05

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