Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
  • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
  • H01L33/26—Materials of the light emitting region
  • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
  • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
  • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
  • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
  • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission

Definitions

• the present invention relates to a Ill-nitride semiconductor light emitting device, and more particularly, to a method for improving electrostatic discharge (ESD) property of a GaN-based nitride light emitting device.
• ESD electrostatic discharge
• Hi-nitride compound semiconductor light emitting device refers to a light emitting device, such as a light emitting diode comprising a compound semiconductor layer made of Al(x)Ga(y)In(l-x-y)N (O ⁇ x ⁇ l, O ⁇ y ⁇ l, 0 ⁇ x+y ⁇ l), and does not exclude the inclusion of either materials made of other group elements, such as SiC, SiN, SiCN, and CN, or a semiconductor layer made of such materials.
• Fig. 1 is a view showing a conventional Hi-nitride semiconductor light emitting device.
• the light emitting device comprises a substrate 100, a buffer layer 200 which is epitaxially grown on the substrate 100, an n-type nitride semiconductor layer 300 which is epitaxially grown on the buffer layer 200, an active layer 400 which is epitaxially grown on the n-type nitride semiconductor layer 300, a p-type nitride semiconductor layer 500 which is epitaxially grown on the active layer, a p-side electrode 600 which is epitaxially grown on the p-type nitride semiconductor layer 500, a p-side bonding pad 700 which is formed on the p-side electrode 600, a n-side electrode 800 which is formed on an n-type nitride semiconductor layer 301 which is exposed by mesa etching of the p-type nitride semiconductor layer 500 and the active layer 400.
• the substrate 100 can use a GaN-based substrate as a homogeneous substrate, and a sapphire substrate, a silicon carbide substrate or a silicon substrate as a heterogeneous substrate, but can use any other substrates on which nitride semiconductor layers can be grown.
• the nitride semiconductor layers epitaxially grown on the substrate 100 are usually grown by means of MOCVD (Metal Organic Chemical Vapor Deposition) method.
• MOCVD Metal Organic Chemical Vapor Deposition
• the buffer layer 200 serves to reduce differences in lattice constant and the coefficient of thermal expansion between the heterogeneous substrate 100 and the nitride semiconductor.
• U.S. Patent No.5, 122,845 discloses a technology in which an A1N buffer layer having a thickness of 100A to 500A is grown on a sapphire substrate at a temperature ranging from 380°C to 800°C.
• U.S. Patent No.5,290,393 discloses a technology in which an Al(x)Ga(l-x)N (0 ⁇ x ⁇ l) buffer layer having a thickness of 10A to 5000A is grown on a sapphire substrate at a temperature ranging from 200°C to 900°C.
• Korean Patent No.10-0448352 discloses a technology in which a SiC buffer layer is grown at a temperature ranging from 600°C to 990°C, and an In(x)Ga(l-x)N (0 ⁇ x ⁇ l) layer is grown on the SiC buffer layer.
• n-type contact layer In the n-type nitride semiconductor layer 300, at least a region (n-type contact layer) in which the n-side electrode 800 is formed is doped with an impurity.
• the n- type contact layer is preferably made of GaN and is doped with Si.
• U.S. Patent No.5,733,796 discloses a technology in which an n-type contact layer is doped with a desired doping concentration by controlling a mixing ratio of Si and other source materials.
• the active layer 400 is a layer for emitting a photon (light) by recombination of electrons and holes, and is mainly made of In(x)Ga(l-x)N (0 ⁇ x ⁇ l).
• the active layer 400 is composed of a single quantum well or multi quantum wells.
• WO02/021121 discloses a technology in which only some of a plurality of quantum wells and barrier layers are doped.
• the p-type nitride semiconductor layer 500 is doped with an impurity such as Mg, and has a p-type conductivity through an activation process.
• U.S. Patent No.5,247,533 discloses a technology in which a p-type nitride semiconductor layer is activated by means of irradiation of electron beam.
• U.S. Patent No.5,306,662 discloses a technology in which a p-type nitride semiconductor layer is activated through annealing at a temperature of 400°C or more.
• Korean Patent No.10-043346 discloses a technology in which NH and a hydrazine-based source material are used together as a nitrogen precursor for growing a p-type nitride semiconductor layer, so that the p-type nitride semiconductor layer has a p-type conductivity without an activation process.
• the p-side electrode 600 serves to allow the current to be supplied to the entire p- type nitride semiconductor layer 500.
• U.S. Patent No.5,563,422 discloses a technology of a light-transmitting electrode, which is formed almost on the entire p-type nitride semiconductor layer, in ohmic contact with the p-type nitride semiconductor layer, and made of Ni and Au.
• U.S. Patent No.6,515,306 discloses a technology of a light- transmitting electrode made of ITO(Indium Tin Oxide), which is formed on the n-type superlattice layer formed on the p-type nitride semiconductor layer.
• the p-side electrode 600 can be formed to have such a thick thickness that the p-side electrode 600 does not transmit light, i.e., the p-side electrode 600 reflects light toward the substrate.
• a light emitting device using this p-side electrode 600 is called a flip chip.
• U.S. Patent No.6,194,743 discloses a technology of an electrode structure including an Ag layer of 20nm or more in thickness, a diffusion barrier layer covering the Ag layer, and a bonding layer made of Au and Al, which covers the diffusion barrier layer.
• P-side bonding pad 700 and n-side electrode 800 are for providing current into the device and for wire-bonding out of the device.
• U.S. Patent No.5,563,422 discloses a technology of an n-side electrode made of Ti and Al.
• U.S. Patent No.5,652,434 discloses a technology of p-side bonding pad directly contacted with p-type nitride semiconductor layer by partially removing the light-transmitting electrode.
• the ⁇ i-nitride semiconductor light emitting device is known to have poor electrostatic properties as compared to other compounds based light emitting devices. This is because the GaN-based light emitting device is formed on a sapphire substrate with a high lattice mismatch.
• Such a high lattice mismatch (16%) between the substrate and the grown thin film causes high crystal defects in the GaN-based thin film.
• the crystal defects increases leakage current of the light emitting device and when external static electricity is introduced into the light emitting device, the active layer of the device is destroyed in a strong field due to the crystal defect.
• the GaN 10 12 2 thin film has typically crystal defects of 10 to 10 /Cm .
• the electrostatic discharge property of the light emitting device is very important in connection with practical application of the ⁇ i-nitride semiconductor light emitting device. Particularly, when the light emitting device is packaged, it is very critical to design the device to endure static electricity generated from equipments and workers, considering improvement of yield of the finally produced device.
• the Ill-nitride semiconductor light emitting device is recently used in coarse environmental conditions such as outdoor signboards and automobile lightings, the electrostatic property is regarded as important parameter.
• the conventional Ill-nitride semiconductor light emitting devices can endure up to several thousands of voltage in the forward direction under human body mode (HBM) condition but hardly endure even several hundreds of volt in the backward direction. This is owing to the crystal defect of the device, as described above, and is related to the electrode design of the device as well.
• the ⁇ i-nitride semiconductor light emitting device normally employs a non- conductive sapphire substrate and the n-side electrode and the p-side electrode in the device structure are formed in the same direction.
• the conventional methods mainly have approached in terms of external aspects of the device.
• the ⁇ i-nitride semiconductor light emitting device is connected to a protection diode (typically, Zener diode) in parallel in a reverse direction to prevent a high voltage ESD from being reversely applied to the Ill-nitride semiconductor light emitting device.
• the Ill-nitride semiconductor light emitting device may be connected to a capacitor in parallel so that a high voltage can flow through the capacitor.
• the addition of such an external ESD protection element is not preferred in terms of cost and yield.
• the fundamental method for improving ESD property is to improve quality of the GaN thin film.
• the device is designed applying such circuit property to the Ill-nitride semiconductor light emitting device so that the propagating rate of instantaneous generated ESD is slowed down, whereby the peak intensity is diminished and the ESD impact applied on the active layer is minimized.
• the property of reverse ESD is 10 times lower than that of normal ESD.
• the reverse ESD voltage is numerically several hundreds of volt while the normal ESD voltage is several thousands of volt. This can be explained by resistance and capacitance model of the device. Capacitance of a semiconductor device is formed due to a depletion region generated in a P-N junction. Generally, the capacitance is represented by the following formula.
• the buffer layer may be preferably a low temperature grown GaN buffer (US PAT No. 5,290,393), or SiC or SiCN buffers (Korean Patent Application Nos. 2003-85334 and 2004-35610, filed by the present inventors).
• the n-type III- nitride semiconductor layer may comprise an intentionally non-doped n-type GaN layer.
• the present invention is essentially characterized by comprising a reverse p-n junction between the active layer and the n-type contact layer and may comprise a III- nitride semiconductor layer or ⁇ i-nitride semiconductor layers between the active layer and the p-n junction diode and/or between the p-n junction diode and n-contact layer, in which the type and formation of the additional Ill-nitride semiconductor layer may be selected by the person in this field.
• the repeatedly grown layers may have different composition and ingredient variation and thickness change in the scope which can be clearly understood by the persons in this field.
• FIG. 1 is a view for explanation of a ⁇ i-nitride semiconductor light emitting device according to the prior art
• Fig. 2 is a view showing the intensity change by the injected pulse according to resistance and capacitance
• Fig. 3 is a graph of experimentally measured capacitance according to voltage of the light emitting diode
• Fig. 4 is a view showing the structure of the light emitting diode with improved electrostatic discharge property according to the present invention.
• FIG. 5 is a schematic view showing the energy band shape, structure and capacitance of the main part of the electrostatic discharge improvement according to Example 1 of the present invention.
• Fig. 6 is a schematic view showing the energy band shape, structure and capacitance of the main part of the electrostatic discharge improvement according to Example 2 of the present invention.
• Fig. 7 is a table showing the measured ESD voltages of the light emitting diode produced according to Example 1 and Example 2 and the light emitting diode according to the prior art. Mode for the Invention
• Fig. 3 is a graph of experimentally measured capacitance according to voltage of the light emitting diode. As described above, when the reverse voltage is increased, the capacitance is reduced.
• the foregoing principle is applied to the GaN light emitting diode to improve reverse ESD.
• a light emitting device to improve reverse ESD it is more important to insert a big capacitance to the device than to increase resistance of the device.
• a buffer layer 11 is formed on a sapphire substrate 10 and an n- type GaN layer 12 is subsequently grown thereon.
• the inserted p-type layer does not have a significant effect on the device.
• the insertion of the p-type layer may cause formation of depletion region between the p-type layer and the n-type layers, providing a big capacitance. Since the p-type layer is thin and the n-type layer is doped, when a reverse voltage is applied, a big capacitance is also formed for the distance of the depletion region is not long. Thus, as such big capacitance is present under the active layer, the peak intensity of static electricity is reduced, whereby the active layer can be protected.
• FIG. 5 and Fig. 6 schematically illustrate the energy band and capacitance formation in the structure inserted according to the present invention.
• a buffer layer 11 was formed on a sapphire substrate 10 and an n-type GaN 12 was formed thereon.
• a p-type In x Ga 1-x N layer 30 was formed to a thickness of 5nm on the n-type GaN layer 12.
• x was 0.05.
• the reason why the InGaN layer was used is because InGaN has a bigger dielectric constant to form a relatively big capacitance, as compared to GaN or AlGaN.
• GaN or AlGaN may be used instead of InGaN.
• x was set to 0.05.
• the p- doping was performed using a Cp Mg source, the growth rate for growing the p-type layer was kept at 0. lnm/s. The doped amount of Mg was believed to be about 10 to 21 10 .
• an n-type GaN layer 31 doped with 1 1x10 silicon was grown to a thickness of 20nm and an active layer 13 and a p-type GaN layer 14 were grown thereon.
• a buffer layer 11 was formed on a sapphire substrate 10 and an n-type GaN 12 was formed thereon.
• n-type GaN layer 12 On the n-type GaN layer 12, a p-type In x Ga 1-x N layer 30 with a thickness of 3nm and an n-type GaN layer 31 with a thickness of 5nm were formed periodically 3 times.
• x was 0.05, as in Example 1.
• the reason why the InGaN layer was used is because InGaN has a bigger dielectric constant to form a relatively big capacitance, as compared to GaN or AlGaN.
• GaN or AlGaN may be used instead of InGaN.
• x was set to 0.05. This is because the reactor temperature should be lowered to increase x, whereby crystal quality of a thin film to be grown may be deteriorated. Therefore, the x value was resulted from negotiation of temperature and capacitance. However, the In content may be freely adjusted.
• the p- doping was performed using a Cp Mg source, the growth rate for growing the p-type 19 layer was kept at 0. lnm/s. The doped amount of Mg was believed to be about 10 to 21
• the n-type GaN layer 31 which had been periodically inserted to improve ESD 18 was doped with silicon at about 1x10 , had a thickness of about 5nm and was grown at a rate of 0. lnm s, like the p-type InGaN layer 30.
• the inserted p-type InGaN layer 30 and n-type GaN layer 30 were 3 times repeated.
• the structure thus-obtained is illustrated in Fig. 6. Samples having this structure were measure for reverse ESD voltage. It was found that the reverse ESD voltage was improved from 200V to 1000-2000V. The numbers were a little lowered than Example 1.

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• 2004
  • 2004-06-10 KR KR1020040042761A patent/KR100448351B1/ko not_active IP Right Cessation
• 2005
  • 2005-06-10 WO PCT/KR2005/001743 patent/WO2005122292A1/en active Application Filing

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