WO2005117285A1 - 歪み補償等化器 - Google Patents
歪み補償等化器 Download PDFInfo
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- WO2005117285A1 WO2005117285A1 PCT/JP2005/006473 JP2005006473W WO2005117285A1 WO 2005117285 A1 WO2005117285 A1 WO 2005117285A1 JP 2005006473 W JP2005006473 W JP 2005006473W WO 2005117285 A1 WO2005117285 A1 WO 2005117285A1
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/25—Arrangements specific to fibre transmission
- H04B10/2507—Arrangements specific to fibre transmission for the reduction or elimination of distortion or dispersion
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03006—Arrangements for removing intersymbol interference
- H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
- H04L25/03019—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception
- H04L25/03057—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception with a recursive structure
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03006—Arrangements for removing intersymbol interference
- H04L2025/03592—Adaptation methods
- H04L2025/03598—Algorithms
- H04L2025/03611—Iterative algorithms
- H04L2025/03617—Time recursive algorithms
- H04L2025/0363—Feature restoration, e.g. constant modulus
Definitions
- the present invention relates to a distortion compensation equalizer that compensates for distortion of a received signal without using a known sequence, and particularly to a distortion compensation equalizer that uses a CMA (Constant Modulus Algorithm). is there.
- CMA Constant Modulus Algorithm
- the received signal waveform has a waveform that is delayed in time by a multipath or an individual wave source. That is, the synthesized signal at the receiving point loses the property of a constant envelope, and distortion occurs. Such distortion can be compensated for by an adaptive equalizer.
- an adaptive equalizer uses an adaptive filter and a tap coefficient estimator.
- An adaptive filter is called a transversal filter or a moving average filter, and is composed of a chain of delay elements. Then, a multiplier with a tap coefficient is arranged at the output of each delay element, and all the outputs of the multipliers are added to obtain the output of the adaptive filter.
- the tap coefficient estimator has an evaluation function of the mean square error between the output of the adaptive filter and the corresponding reference signal, and updates the evaluation function so as to minimize the evaluation function.
- the reference signal is a signal obtained by determining a known signal sequence or a signal after output of the adaptive filter.
- Blind equalization has a tap coefficient estimator that corrects distortion without using a known sequence signal. In this case, it has an evaluation function different from the above-mentioned root mean square error.
- an algorithm for estimating tap coefficients in a conventional blind equalizer for example, there is CMA.
- a conventional blind equalizer is, for example, a frequency divider described in Non-Patent Document 1 below.
- the operation when a modulation (Frequency Modulation: FM) signal is received will be described.
- An FM transmission signal without distortion is a signal with a constant envelope waveform in which the amplitude or power is evenly distributed in positive and negative directions.
- a conventional blind equalizer performs analog-to-digital conversion on an FM signal received by an analog-to-digital (AZD) converter, and inputs the result to a digital filter.
- ABD analog-to-digital
- the digital filter is a transversal filter or a moving average filter, and is composed of a chain of delay elements. Then, a multiplier with a tap coefficient is placed at the output of each delay element, and all the outputs of the multipliers are added, and the addition result becomes an output of the digital filter.
- the output of the digital filter is output to, for example, a CMA tap coefficient estimator and an FM demodulator.
- the CMA tap coefficient estimator receives the output signal of the AZD converter and the output signal of the digital filter, and estimates and updates tap coefficients using the CMA.
- the tap coefficient value output from the CMA tap coefficient estimator is input to the digital filter and used as the tap coefficient of the multiplier.
- the output of the digital filter using the tap coefficients estimated by the CMA tap coefficient estimator has a distortion-compensated waveform.
- the FM demodulation unit receives the output signal of the digital filter and performs FM demodulation on the FM reception signal whose distortion has been compensated, so that a highly accurate FM demodulated signal can be obtained.
- Non-patent document l J.R.Treichler and B.G.Agee: "A New Approach to Multipath Correction of Constant Modulus Signals, IEEE
- PMD polarization mode dispersion
- the present invention has been made in view of the above, and has as its object to obtain a distortion compensation equalizer (blind equalizer) using a CMA, which compensates for distortion of the NRZ signal and the RZ signal. It shall be.
- a distortion compensation equalizer is a distortion compensation equalizer using a CMA.
- Received signal adjusting means (corresponding to a reference value calculation unit 2 and a reference value processing unit 3 in an embodiment described later) for adjusting the amplitude value so as to have a waveform uniformly distributed in positive and negative directions, and the number of taps connected in series Minute delay elements add a specific delay to the input signal in order, multiply the delayed signals output from each delay element by the corresponding tap coefficients, and add all the multiplied signals.
- a digital filter section for outputting the addition result, and a CMA tap coefficient estimating section for performing tap coefficient estimating processing using CMA based on an output signal of the digital filter section and an output signal of the received signal adjusting means. And The processing of the digital filter section and the CMA tap coefficient estimating section is repeatedly executed, thereby equalizing means for compensating for the waveform distortion of the adjusted received signal (corresponding to the digital filter section 4 and the CMA tap coefficient estimating section 5). ).
- the adjustment process is performed such that the amplitude components of the received signal are uniformly distributed in the positive and negative directions, and the equalized process is performed on the adjusted received signal.
- the adjustment process is performed such that the amplitude components of the received signal are evenly distributed in the positive and negative directions, and the equalized process is performed on the adjusted received signal.
- This has the effect of compensating for distortion of a signal or RZ signal, a received signal having the property of a single polarity, and a received signal whose amplitude is not evenly distributed.
- FIG. 1 is a diagram showing a configuration of a distortion compensation equalizer according to a first embodiment of the present invention.
- FIG. 2 is a diagram showing an example of an NRZ signal before and after reference value processing.
- FIG. 3 is a diagram showing a configuration example of a digital filter unit.
- FIG. 4 is a diagram showing a configuration of a distortion compensation equalizer according to a second embodiment of the present invention.
- FIG. 5 is a diagram showing a configuration of a distortion compensation equalizer according to a third embodiment of the present invention.
- FIG. 6 is a diagram showing a configuration of a distortion compensation equalizer according to a fourth embodiment of the present invention.
- FIG. 7 is a diagram showing a configuration of a distortion compensation equalizer according to a fifth embodiment of the present invention.
- FIG. 8 is a diagram showing a configuration of a distortion compensation equalizer according to a sixth embodiment of the present invention.
- FIG. 9 is a diagram showing a configuration of a distortion compensation equalizer according to a seventh embodiment of the present invention.
- FIG. 10 is a diagram showing a configuration of a distortion compensation equalizer according to an eighth embodiment of the present invention.
- FIG. 11 is a diagram illustrating a configuration example of a determination reference value calculation unit.
- FIG. 12 is a diagram showing a configuration of a ninth embodiment of a distortion compensation equalizer according to the present invention.
- FIG. 13 is a diagram showing a configuration of a distortion compensation equalizer according to a tenth embodiment of the present invention.
- FIG. 14 is a diagram illustrating a configuration example of a digital filter unit after determination.
- FIG. 15 is a diagram showing a configuration of a distortion compensation equalizer according to Embodiment 11 of the present invention.
- FIG. 1 is a diagram showing a configuration of a distortion compensation equalizer according to a first embodiment of the present invention.
- This distortion compensation equalizer includes an AZD conversion unit 1, a reference value calculation unit 2, a reference value It includes a processing unit 3, a digital filter unit 4, a CMA tap coefficient estimating unit 5, and a judging unit 6.
- the power for explaining the processing using the NRZ signal is not limited to this, and the same can be applied to the RZ signal.
- FIG. 2A and 2B are diagrams showing the NRZ signal before and after the reference value processing.
- FIG. 2A shows the NRZ signal ⁇ without distortion output by the D conversion unit 1
- FIG. 3 is a diagram showing an example of the configuration of the digital filter section 4.
- the digital filter section 4 includes delay elements (D) 101-1, 101-2,... ⁇ - ( ⁇ - ⁇ ), and the output of each delay element. , 102— (N ⁇ 1) which multiplies the corresponding tap coefficient with the adder 103 which adds the output of each multiplier. Have.
- D delay elements
- 102— (N ⁇ 1) which multiplies the corresponding tap coefficient with the adder 103 which adds the output of each multiplier.
- the AZD converter 1 converts an analog electric signal (analog NRZ signal) into a digital electric signal.
- the AZD converter 1 samples an analog NRZ signal (t), which is a positive input signal, at a transmission data bit rate of 1ZT at a rate of every second, and outputs an NRZ signal ( ⁇ as a reference value calculator) as an output signal.
- t represents time
- T represents a transmission data period
- n represents an integer value.
- the reference value calculation section 2 calculates a reference value a based on the output signal ⁇ of the AZD conversion section 1.
- the reference value ⁇ for example, the average value of over the past several samples is calculated.
- the reference value processing unit 3 adjusts the output signal of the AZD conversion unit 1 based on the reference value a (digital value (amplitude value) corresponding to the voltage of the analog signal). ), For example, as shown in FIG. 2 (b), to generate a waveform in which the amplitude values are uniformly distributed in the positive and negative directions.
- the reference value processing unit 3 subtracts the output signal u ′ force reference value ⁇ of the AZD conversion unit 1 as shown in the following equation (1), and converts the result into a signal u whose amplitude value is uniformly distributed in the positive and negative directions.
- N-1 delay elements corresponding to 101-1 to LOl- (N-1)
- each delay element outputs a signal after the delay is added.
- the amount of delay by each delay element is set to one of the bit periods T, TZ2, and TZL.
- each multiplier corresponding to 102-0-102-(N-1)
- the adder 103 adds up the signals after the multiplication in each multiplier, and outputs the addition result to the CMA tap coefficient estimation unit 5 and the determination unit 6 as a waveform y after distortion compensation.
- the output signal y n of the digital filter unit 4 can be expressed by the following equation (3).
- the CMA tap coefficient estimating unit 5 operates at the bit period ⁇ . Then, based on the output signal u and the output signal y of the reference value processing unit 3, the tap coefficients are updated to h (real number vector notation) power h.
- the subscript m is the sample time in the bit period T, and the bit m + 1
- a constant representing an ideal envelope value of the transmission signal is set in R.
- the above R P may be obtained by calculating the following equation (5) using the transmission signal s having no distortion, and setting the calculation result as a constant.
- ⁇ [ ⁇ ] represents an expected value.
- the CMA tap coefficient estimator 5 updates the tap coefficient h (real number vector notation) so as to minimize the evaluation function Q.
- the CMA tap coefficient estimating unit 5 first sets p and q to 1 or 2, and substitutes the above equation (3) into the above equation (4) to take a gradient.
- V hQ y m y m u m sgn (y m -R) (7)
- V hQ 2y m u m sgn (
- V h Q 4y m u m (
- Non-Patent Document 1 the variable corresponding to u * (complex vector notation) is u (multiple
- sgn is a real variable signum and is defined as in the following equation (11). Also, in equation (4) It is also possible to define as in Eq. (11) using R described above.c
- ⁇ is a parameter for adjusting the update speed of the tap coefficient, and an appropriate value is set.
- the CMA tap coefficient estimating unit 5 applies the above formulas (7), (8), (9), and (10) to the above formula (6) to obtain the evaluation function of the above formula (4).
- the digital filter unit 4 updates h (real vector notation) m + 1
- the determination unit 6 performs a determination process on the waveform whose distortion has been corrected by the above process.
- the adjustment process is performed so that the amplitude components of the received signal are evenly distributed in the positive and negative directions, and the equalization process is performed on the received signal after the adjustment process. did .
- the equalization process is performed on the received signal after the adjustment process. did .
- the force described in the case of compensating for the distortion of the NRZ signal or the RZ signal is not limited to this.
- the property of a single polarity is used.
- the amplitude is evenly distributed in the positive and negative directions, and the distortion of the received signal can be compensated in the same manner.
- FIG. 4 is a diagram showing a configuration of a distortion compensation equalizer according to a second embodiment of the present invention.
- This distortion compensation equalizer includes an AZD conversion unit 1, a reference value calculation unit 2, a reference value It includes a processing unit 3, a digital filter unit 4, a CMA tap coefficient estimating unit 5a, a judging unit 6, a 0 neighboring point detecting unit 11, and a 0 neighboring point avoiding unit 12.
- the same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted. Here, only the processing different from the first embodiment will be described.
- the reference value processing unit 3 outputs the above-described output signal u to the neighboring point detection unit 11 and the digital filter unit 4.
- the 0-neighboring point detecting section 11 sets a specific threshold value ⁇ , and detects the signal when the absolute value of the output signal u of the reference value processing section 3 becomes smaller than ⁇ .
- the 0 vicinity point avoiding unit 12 corrects the detected signal so as to be ⁇ or ⁇ , and outputs the corrected signal to the CMA tap coefficient estimating unit 5a.
- ⁇ or ⁇ is a value whose absolute value is not less than ⁇ .
- Signals that are not detected by the 0-neighbor point detection unit 11 are output from the 0-neighbor point avoidance unit 12 to the CMA tap coefficient estimation unit 5a in a normal state while retaining the current signal.
- the output of the near-zero point avoidance unit 12 is g, and the vector notation is defined by the following equation (14). [0057] [Number 13]
- the CMA tap coefficient estimating unit 5a processes the expressions (6) and (7) to (10) based on the output signal y of the digital filter unit 4 and the corrected signal g in the bit period. Do, mm
- the update processing is performed by replacing the corrected signal with g m (real number vector notation).
- the present embodiment a part where the absolute value of the output signal u of the reference value processing unit is equal to or smaller than a specific threshold is detected, and the detected signal is determined to be equal to or larger than the threshold. It was decided to correct to the value of. As a result, the same effect as in Embodiment 1 described above can be obtained, and even when the near-zero point frequently exists in the received signal subjected to the sample processing in the AZD conversion unit, the tap coefficient can be correctly adjusted. Can be estimated.
- the 0-neighboring-point detecting unit 11 and the 0-neighboring-point avoiding unit 12 are applied to the configuration in FIG. 1 of the first embodiment. Similar effects can be obtained even when applied to the configuration of FIG. 13 of the tenth embodiment or the configuration of FIG. 15 of the eleventh embodiment described later.
- FIG. 5 is a diagram illustrating a configuration of a distortion compensation equalizer according to a third embodiment of the present invention.
- This distortion compensation equalizer includes an AZD conversion unit 1, a reference value calculation unit 2, a reference value It includes a processing unit 3, a digital filter unit 4, a CMA tap coefficient estimating unit 5a, a judging unit 6, a 0 neighboring point detecting unit 11, and a 0 neighboring point avoiding unit 12.
- the same components as those in the above-described first or second embodiment are denoted by the same reference numerals, and description thereof will be omitted. Here, only the processing different from the first or second embodiment will be described.
- the near-zero point avoidance unit 12 outputs the above-mentioned corrected signal to the digital filter unit 4 and the CMA tap coefficient estimation unit 5a.
- the signal not detected by the 0 vicinity point detection unit 11 is output to the digital filter unit 4 and the CMA tap coefficient estimation unit 5a in a normal state while retaining the current signal.
- the digital filter unit 4 calculates the above-described equation (3) based on the output signal from the 0-neighbor point avoiding unit 12 and the tap coefficient output from the CMA tap coefficient estimating unit 5a, and shows the result.
- the signal y is output to the CMA tap coefficient estimation unit 5a and the determination unit 6.
- a portion in which the absolute value of output signal u is equal to or smaller than the specific threshold is detected by the same processing as in Embodiment 2, and the detected signal is detected.
- the value was corrected to a value that is higher than the threshold. Further, the corrected signal is output to the digital filter unit and the CM tap coefficient estimating unit.
- the 0-neighboring-point detecting unit 11 and the 0-neighboring-point avoiding unit 12 are applied to the configuration in FIG. 1 of the first embodiment, but the present invention is not limited to this and will be described later. Similar effects can be obtained even when applied to the configuration of FIG. 13 of the tenth embodiment or the configuration of FIG. 15 of the eleventh embodiment described later.
- FIG. 6 is a diagram illustrating a configuration of a distortion compensation equalizer according to a fourth embodiment of the present invention.
- the distortion compensation equalizer includes an AZD conversion unit 1, a reference value calculation unit 2, a reference value It includes a processing unit 3, a digital filter unit 4, a CMA tap coefficient estimating unit 5a, a judging unit 6, a 0 neighboring point detecting unit l ib, a 0 neighboring point avoiding unit 12, and a timing adjusting unit 21.
- the same components as those of the above-described second or third embodiment are denoted by the same reference numerals, and description thereof will be omitted.
- the processing different from the first, second, or third embodiment will be described.
- the 0-neighboring point detecting unit 1 lb outputs the detection result of the 0-neighboring point to the 0-neighboring point avoiding unit 12 as described above, and further outputs a signal (detection signal) indicating that the 0-neighboring point is detected. ) To the timing adjustment unit 21.
- the 0 vicinity point detection unit l ib frequently outputs the detection signal of the 0 vicinity point. If it is detected, the AZD converter 1 offsets the sample timing of the received signal. As a result, the signal at a point near 0 is not sampled.
- a counter is provided inside the timing adjustment unit 21, and a threshold value j8 is set as a specific counter value. Then, this counter counts up the number of detections when a point near 0 is continuously detected, and resets the counter value to 0 when no near point is detected. As a result, when the counter value exceeds the threshold value j8, the timing adjustment unit 21 outputs to the AZD conversion unit 1 a signal that is offset by the number of samples at the timing. However, the sample period is not changed. Further, the count-up condition and the threshold value j8 may be changed according to the magnitude of the distortion.
- the detection signal at the near zero point is frequently detected, the signal at the near zero point is not sampled.
- the same effect as in Embodiment 1 described above can be obtained, and furthermore, since the near-zero point does not exist in the received signal that has been sampled by the AZD conversion unit, the tap coefficients must be correctly estimated. Can be.
- the timing adjustment unit 21 is applied to the configuration of FIG. 4 of the second embodiment.
- the present invention is not limited to this.
- the configuration of FIG. A similar effect can be obtained even when applied to the configuration of FIG. 13 of the tenth embodiment or the configuration of FIG. 15 of the eleventh embodiment described later.
- FIG. 7 is a diagram showing a configuration of a distortion compensation equalizer according to a fifth embodiment of the present invention.
- This distortion compensation equalizer includes an AZD conversion unit 1, a reference value calculation unit 2, a reference value A processing unit 3, a digital filter unit 4, a CMA tap coefficient estimating unit 5c, a judging unit 6, a 0 neighboring point detecting unit lib, a 0 neighboring point avoiding unit 12, a timing adjusting unit 21c, and an error threshold.
- a value determining unit 31 The same components as those in the above-described first to fourth embodiments are denoted by the same reference numerals, and description thereof is omitted. Here, only the processing different from the first to fourth embodiments will be described.
- CMA tap coefficient estimating section 5c estimates the tap coefficient in the same process as CMA tap coefficient estimator 5a described above, further, the evaluation function Q of the aforementioned equation (4) I y I P - R P The value of m Output to the error threshold value determination unit 31.
- the error threshold judging unit 31 set in advance certain threshold gamma, and compares this threshold value y and the I y I P -R P, the comparison result (the magnitude Signal) to adjust the timing m
- the timing adjustment unit 21c determines the sample timing based on the detection signal output from the near-zero point detection unit l ib and the comparison result (large or small signal) output from the error threshold value determination unit 31. To adjust. As an example, assuming that the signal output from the error threshold value determination unit 31 is ⁇ , if this force is 1 ”, the above I y
- m I P -R P is determined to be greater than the threshold value gamma, if ⁇ force 0 "the I y
- a counter is provided inside the timing adjustment unit 21c, and the threshold value j8 is set as a specific counter value. Then, this counter counts up the number of detections when a point near 0 is continuously detected, and resets the counter value to 0 when no force is detected.
- the timing adjustment unit 21c refers to ⁇ , and if the power is “l”, the signal that offsets the timing by ⁇ samples is subjected to AZD conversion. Output to part 1. However, the sampling period is not changed.
- the timing offset signal is not output if the power S is “0” by referring to ⁇ .
- the count-up condition, the threshold value j8, and the threshold value ⁇ may be changed depending on the magnitude of the distortion!
- the detection signal of the 0-neighboring point output from the 0-neighboring point detection unit and the threshold values ⁇ and I y from which the error threshold value is also output
- FIG. 8 is a diagram showing a configuration of a distortion compensation equalizer according to a sixth embodiment of the present invention.
- This distortion compensation equalizer includes an AZD conversion unit 1, a reference value calculation unit 2d, and a reference value Processing unit 3, digital filter unit 4, CMA tap coefficient estimating unit 5d, determining unit 6, 0 neighboring point detecting unit 1 lb, 0 neighboring point avoiding unit 12, timing adjusting unit 21c, error A threshold determination unit 31, an analog reference value processing unit 41, a DZA conversion unit 42, and an analog filter unit 43 are provided.
- the same components as those in the first to fifth embodiments are denoted by the same reference numerals, and description thereof is omitted. Here, only processing different from the first to fifth embodiments will be described.
- the received analog NRZ signal or analog RZ signal iT (t) is input to the A / D conversion unit 1 as described above, and is also input to the analog reference value processing unit 41 in the present embodiment. Is done.
- the reference value calculation unit 2d outputs the reference value oc calculated by the same processing as the above-described reference value calculation unit 2 to the reference value processing unit 3 and the analog reference value processing unit 41.
- the analog reference value processing unit 41 adjusts the analog NRZ signal or the analog RZ signal (t) based on the reference value calculated by the reference value calculation unit 2d, and generates a waveform in which the amplitude values are uniformly distributed in the positive and negative directions. Generate. As an example, the analog reference value processing unit 41 converts the reference value ⁇ into an analog voltage signal, and performs processing such as applying noise to the received analog NRZ signal or analog RZ signal based on the voltage value. .
- the CMA tap coefficient estimating unit 5d estimates the tap coefficient by the same processing as that of the above-described CMA tap coefficient estimating unit 5c, and furthermore, calculates I y of the evaluation function Q of the above-described equation (4).
- the CMA tap coefficient estimating unit 5d outputs the tap coefficient (digital signal of the sample period T) to the DZA converting unit 42.
- the DZA conversion section 42 converts the digital signal of the sample period T into an analog signal, and outputs the analog signal to the analog filter section 43.
- the sample timing of the DZA converter 42 is, for example, the same as that of the AZD converter 1.
- the analog filter 43 performs the same processing as that of the digital filter 4 described above. It is realized by analog processing which is not the same as total processing.
- the delay element, multiplier, and adder shown in FIG. 3 are all configured by analog elements, and the delay amount of the delay element is set equal to the delay element of the digital filter. Set to TZ2 or TZL.
- the determination unit 6 performs a determination process on the waveform whose distortion has been corrected by the above process.
- the adjustment process is performed so that the amplitude components of the analog reception signal are uniformly distributed in the positive and negative directions, and the equalization process is performed on the analog reception signal after the adjustment process. I decided. This makes it possible to obtain a blind adaptive equalizer using a CMA that compensates for distortion of an analog NRZ signal or an analog RZ signal.
- the timing adjusting section 21c, the error threshold value judging section 31, the analog reference value processing section 41, the DZA conversion section 42 and the analog filter section 43 are the same as those shown in FIG.
- the force applied to the configuration of this embodiment is not limited to this, and the same effect can be obtained even when applied to the configuration of FIG. 5 of the third embodiment.
- FIG. 9 is a diagram showing a configuration of a distortion compensation equalizer according to a seventh embodiment of the present invention.
- This distortion compensation equalizer includes an AZD conversion unit 1, a reference value calculation unit 2d, and a reference value Processing unit 3, digital filter unit 4, CMA tap coefficient estimating unit 5d, determining unit 6, 0 neighboring point detecting unit 1 lb, 0 neighboring point avoiding unit 12, timing adjusting unit 21c, error It comprises a threshold value judging section 31, an analog reference value processing section 41, a DZA conversion section 42, an analog filter section 43, and an analog reference value processing section 51.
- the same components as those in the above-described first to sixth embodiments are denoted by the same reference numerals, and description thereof is omitted. Here, only the processing different from the first to sixth embodiments will be described.
- the received analog NRZ signal or analog RZ signal is input to analog reference value processing section 1.
- the analog reference value processing unit 51 performs analog electric signal processing so that the voltage of the received signal is evenly and positively and negatively distributed to some extent (for example, an analog received signal having a unipolar property is converted to both polarities). Coarsely adjust the waveform and send the adjusted received signal to the AZD converter 1 and analog reference value processor 41. Output.
- analog reference value processing unit 51 performs coarse adjustment in advance so that the voltage of the received signal is evenly and positively and negatively distributed to some extent.
- the average power reference value ⁇ the number of samples for calculating the average value can be reduced, and as a result, the reference value ⁇ can be calculated at high speed. Further, the convergence (estimation) speed of tap coefficient estimation in the CMA can be increased. That is, compared to the above-described sixth embodiment, it is possible to compensate for the distortion of the analog waveform at high speed.
- the timing adjustment unit 21c, the error threshold value determination unit 31, the analog reference value processing unit 41, the DZA conversion unit 42, the analog filter unit 43, and the analog reference value processing unit 51 Although applied to the configuration of FIG. 4 of the second embodiment, the present invention is not limited to this, and similar effects can be obtained even when applied to the configuration of FIG. 5 of the third embodiment.
- FIG. 10 is a diagram showing a configuration of a distortion compensation equalizer according to the eighth embodiment of the present invention.
- This distortion compensation equalizer includes an AZD conversion unit 1, a reference value calculation unit 2, a reference value processing unit.
- a section 3, a digital filter section 4, a CMA tap coefficient estimating section 5e, a judging section 6e, a judging reference value calculating section 61, and a convergence threshold judging section 62 are provided.
- the same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted. Here, only the processing different from the first embodiment will be described.
- the CMA tap coefficient estimating unit 5e estimates tap coefficients by the same processing as that of the CMA tap coefficient estimating unit 5 in the first embodiment, and furthermore, the evaluation function of the above-described equation (4).
- the I y I P -R P of Q outputs with respect to the convergence threshold judging unit 62.
- the digital filter unit 4 converts the output signal y described above into a CMA tap coefficient estimating unit.
- the convergence threshold !, the value determination unit 62 operates at the bit period T, and sets a predetermined threshold ⁇ in advance.
- the criterion value calculation unit 61 operates at the bit period ⁇ , and performs an optimum determination based on statistical values such as signal distribution, variance, and average value of the output signal y of the digital filter unit 4 in a process described later.
- the constant threshold value S is calculated, and the result is output to the judgment unit 6e.
- the criterion value calculation unit 61 determines whether the convergence threshold value
- the constant threshold value S is output to the judgment unit 6e.
- the judging unit 6e operates at the bit period T, and outputs S, which is the output signal of the judgment reference value calculating unit 61.
- n D D is small, it is judged as 0 (or -1) or -R.
- FIG. 11 is a diagram illustrating a configuration example of the determination reference value calculation unit 61, which includes a signal branching unit 201, statistical value calculation units 202 and 203, a threshold value calculation unit 204, and a threshold value setting unit 205.
- the threshold value setting unit 205 refers to S for each CL for a predetermined time
- an operation signal is output to the signal branching unit 201, the statistical value calculating unit 202, the statistical value calculating unit 203, and the threshold value calculating unit 204 so that the operation is performed for a fixed time CL. Then, the output value TH of the calculation result by the threshold value calculation unit 204 described later is set as the determination threshold value S.
- S which is the output value of threshold value setting section 205, is used as a threshold value.
- the output value y of the digital filter unit 4 is branched.
- digital threshold For example, digital threshold
- the signal branching unit 201 outputs y to the statistical value calculation unit 202. Also, the output value y of the digital filter unit 4 is smaller than the threshold value S.
- signal branching section 201 outputs y to statistical value calculating section 203.
- the statistical value calculation unit 202 calculates, for example, an average value MA and a standard deviation value MSD based on y input during the fixed time CL.
- the statistical value calculation unit 203 for example,
- the threshold value calculation unit 204 calculates the following equation (15) based on the average value MA, the standard deviation value MSD, the average value SA, and the standard deviation value SSD calculated by the statistical value calculation units 202 and 203. Is calculated. Then, the calculation result TH of the following equation (15) is output to the threshold value setting unit 205.
- the CMA tap coefficient estimation unit 5e accurately estimates the tap coefficient with reference to the output signal S of the convergence threshold value determination unit 62 at regular time intervals CL, Convergence
- S 1 is continuously output for every CL for a certain period of time.
- determination criterion value calculation section 61 determines the optimum determination threshold. Also, a convergence threshold value judging section 62 is provided, and the optimum threshold value is updated by performing adaptive control on the signal after suppressing the distortion. This allows the determination unit 6e to make a determination with an optimal threshold, thereby suppressing a determination error.
- the CMA tap coefficient estimating unit 5e, the judging unit 6e, the judging reference value calculating unit 61, and the convergence threshold judging unit 62 are the same as those shown in FIG.
- the present invention is not limited to this, and may be applied to the configurations shown in FIG. 4 of the second embodiment, FIG. 5 of the third embodiment, FIG. 6 of the fourth embodiment, and FIG. 7 of the fifth embodiment. Even when applied, the same effect can be obtained.
- FIG. 12 is a diagram showing a configuration of a ninth embodiment of a distortion compensation equalizer according to the present invention.
- This distortion compensation equalizer includes an AZD conversion unit 1, a reference value calculation unit 2d, and a reference value processing unit.
- Unit 3 digital filter unit 4, CMA tap coefficient estimating unit 5d, determining unit 6f, 0 neighboring point detecting unit l ib, 0 neighboring point avoiding unit 12, timing adjusting unit 21c, error threshold value A determination unit 31, an analog reference value processing unit 41, a DZA conversion unit 42, an analog filter unit 43, a determination reference value calculation unit 61, a convergence threshold determination unit 62, a threshold conversion unit 63, It has.
- the same components as those in the above-described sixth or eighth embodiment are denoted by the same reference numerals, and description thereof will be omitted. Here, only the processing different from the sixth and eighth embodiments will be described.
- the threshold value conversion unit 63 the optimum threshold value S calculated in the criterion value calculation unit 61 is calculated.
- the determination unit 6f determines the analog output signal from the analog filter unit 43 by analog processing in the same process as the determination unit 6e described in the eighth embodiment. At this time, the determination unit 6f is configured by an analog element, and the analog voltage threshold V output by the threshold conversion unit 63.
- the method of compensating for the distortion of the analog NRZ signal or the analog RZ signal which is the same as that of the above-described sixth embodiment, A method of calculating the threshold was applied. As a result, it is possible to suppress a determination error in the analog NRZ signal or the analog RZ signal.
- determination reference value calculation section 61 and convergence threshold determination section 62 are applied to the configuration of FIG. 8 of the sixth embodiment, but the present invention is not limited to this, and may be applied to the configuration of FIG. 9 of the seventh embodiment. A similar effect can be obtained.
- FIG. 13 is a diagram showing a configuration of a tenth embodiment of a distortion compensation equalizer according to the present invention.
- This distortion compensation equalizer includes an AZD conversion unit 1, a reference value calculation unit 2, Section 3, digital filter section 4, CMA tap coefficient estimation section 5g, determination section 6g, determination reference value calculation section 61g, convergence threshold value determination section 62g, post-determination digital filter section 71, delay An adjusting unit 72 and a distortion removing unit 73 are provided. Note that the same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted. Here, only the processing different from the first embodiment will be described.
- the output signal y of the digital filter unit 4 is output to the distortion removing unit 73.
- the distortion removal unit 73 performs the processing of the following equation (16) based on the output signal D of the post-judgment digital filter unit 71 described later. Then, it outputs Z, which is the output signal of distortion removal section 73, to determination reference value calculation section 61g, determination section 6g, and CMA tap coefficient estimation section 5g.
- the suffix m represents a signal of a bit cycle time as in the first embodiment.
- the output signal ZZ of the unit 6g is the final output of the distortion compensation equalizer and the delay adjustment m
- the delay adjustment unit 72 uses a delay element to add a delay m to the output signal ZZ of the determination unit 6g.
- the delay amount of the delay element is adjusted so as to be TZ2 including the circuit delay of the determination unit 6g.
- the output signal ZD of the delay adjustment unit 72 is 71 and output to the CMA tap coefficient estimator 5g.
- the convergence threshold! Value judging section 62g operates in the bit period T, sets a predetermined threshold ⁇ in advance, and outputs I Z which is an output value of the CMA tap coefficient estimating section 5g described later.
- m I P averages R P over a period of time CL.
- the criterion calculation unit 61g calculates the criterion based on S, which is the output value of the convergence threshold determination unit 62g.
- the optimal determination threshold value S is output to the determination unit 6g by the method described in (1).
- the post-judgment digital filter section 71 operates in the bit period T, and operates, for example, as shown in FIG.
- FIG. 14 is a diagram illustrating a configuration example of the digital filter unit 71 after determination.
- the digital filter unit 71 after the determination for example, when the number of taps is NN and the tap coefficients output from the CMA tap coefficient estimating unit 5g described later are w (0) to w (NN-1), the input signal NN delay elements for ZD (corresponding to 301-0 to 301- (NN-1)) m
- each delay element Respectively add a delay, and each delay element outputs a signal after the delay is added.
- the delay amount due to each delay element is a bit period T.
- each multiplier corresponds to a tap coefficient (w (0) to w (NN-1)) corresponding to the output signal of each delay element.
- the adder 303 adds the signals obtained by the multiplication by the respective multipliers, and outputs the addition result as a waveform D after distortion compensation to the delay adjustment unit 72.
- the processing of the post-judgment digital filter unit 71 is expressed by a general expression (vector notation: ⁇ ), first, the input sequence ZD of the NN multipliers of the post-judgment digital filter unit 71 and m ⁇ 1
- the CMA tap coefficient estimating unit 5g operates at the bit period T and outputs the output signal u of the reference value processing unit 3, the output signal Z of the distortion removing unit 73, and the output signal ZD of the delay adjusting unit 72. Based on the tap coefficient h (in real vector notation) of the digital filter unit 4 and the digital
- the tap coefficient w (in real vector notation) of the filter unit 71 is obtained.
- y mm in equation (4) is replaced with Z, and as in the first embodiment described above, the tag m is set so that the evaluation function Q is minimized.
- V Q and ⁇ Q are given by h w as in the following equations (20), (21), (22), and (23).
- V h Q ZD m
- V v Q ZD m
- V h Q 2ZD m u m * sgn (jZ m
- V W Q 2ZD m ZDm- sgn (
- V W Q 2ZD m
- V h Q 4ZD m u m * (
- V, V Q 4ZD ra ZD m — (
- ⁇ are parameters for adjusting the update speed of the tap coefficient, and appropriate values are set.
- the digital filter unit 4 receives the newly input signal u Repeat the above process for each (real number vector notation).
- the NRZ signal or the RZ signal is compensated for by using the signal after the determination. This Accordingly, it is possible to compensate for such a large signal distortion that cannot be compensated for in the first embodiment.
- the CMA tap coefficient estimating unit 5g, the judging unit 6g, the post-judging digital filter unit 71, the delay adjusting unit 72, and the distortion removing unit 73 are the same as those in the first embodiment.
- the force applied to the configuration of FIG. 1 The configuration is not limited to the configuration of FIG. 4 of Embodiment 2, FIG. 5 of Embodiment 3, FIG. 6 of Embodiment 4, and FIG. 7 of Embodiment 5. Similar effects can be obtained even when applied.
- FIG. 15 is a diagram showing a configuration of a distortion compensation equalizer according to Embodiment 11 of the present invention.
- This distortion compensation equalizer includes an AZD conversion unit 1, a reference value calculation unit 2, a reference value processing unit.
- Unit 3 digital filter unit 4, CMA tap coefficient estimation unit 5g, determination unit 6g, determination unit 6f, analog reference value processing unit 41, DZA conversion unit 42, analog filter unit 43, analog reference A value processing unit 51, a judgment reference value calculation unit 61g, a convergence threshold value judgment unit 62g, a threshold value conversion unit 63, a post-judgment digital filter unit 71, a delay adjustment unit 72, and a distortion removal unit 73.
- a post-determination analog filter section 81 A post-determination analog filter section 81, a delay adjustment section 82, a distortion removal section 83, and a DZA conversion section 84.
- LO the same components as those in Embodiments 6 to 6: LO are denoted by the same reference numerals, and description thereof is omitted.
- processing different from the sixth to tenth embodiments will be described.
- the CMA tap coefficient estimating unit 5g estimates the tap coefficients of the digital filter unit 4 and the post-judgment digital filter unit 71, as in the tenth embodiment described above. Further, similarly to the above-described seventh embodiment, the tap coefficient of digital filter section 4 is output to DZA conversion section 42. Similarly, the tap coefficient of the digital filter unit 71 after the judgment estimated by the CMA tap coefficient estimation unit 5g is output to the DZA conversion unit 84. After that, the DZA converter 84 converts the signal into an analog voltage signal, and generates a tap coefficient of the analog filter 81 after the determination.
- delay adjustment section 82 executes the same processing as delay adjustment section 72 in the above-described tenth embodiment by analog processing on an output signal of determination section 6f described later.
- an analog element is used as the delay element, and the amount of delay is adjusted to be TZ2 in consideration of the analog circuit delay of the determination unit 6f.
- the post-judgment analog filter unit 81 executes the same processing as the post-judgment digital filter unit 71 in the above-described Embodiment 10 by analog processing on the output signal of the judgment unit 6f.
- the delay element, multiplier, and adder shown in Fig. 14 are all composed of analog elements, and the delay amount of the delay element is equal to the delay element of the digital filter. Set the period to T.
- the distortion removing unit 83 performs the same processing as the distortion removing unit 73 in the above-described tenth embodiment on the basis of the output signal of the post-determination analog filter unit 81 and the output signal of the analog filter unit 43. Execute at The subtraction circuit that realizes the expression (16) is configured by an analog element.
- determination section 6f performs the same processing as in Embodiment 9 described above, and the output value is the final output value of the distortion compensation equalizer, and is output to analog delay adjustment section 82 as well. It is output.
- the distortion compensation method in Embodiment 10 described above is also performed on an analog NRZ signal or an analog RZ signal. Further, similarly to Embodiment 9 described above, it is possible to suppress a determination error in an analog NRZ signal or an analog RZ signal.
- the distortion compensation equalizer according to the present invention is useful as a blind adaptive equalizer that compensates for distortion of a received signal without using a known sequence, and in particular, equalization using CMA. Suitable as a container.
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- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
- Filters That Use Time-Delay Elements (AREA)
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Abstract
Description
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GB0618858A GB2429382A (en) | 2004-05-28 | 2005-04-01 | Distortion compensation equalizer |
US11/587,372 US20070223570A1 (en) | 2004-05-28 | 2005-04-01 | Distortion Compensating Equalizer |
JP2006513820A JPWO2005117285A1 (ja) | 2004-05-28 | 2005-04-01 | 歪み補償等化器 |
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JP (1) | JPWO2005117285A1 (ja) |
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Cited By (5)
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JP2009153200A (ja) * | 2009-03-30 | 2009-07-09 | Fujitsu Ltd | 波形歪み補償装置 |
US7602322B2 (en) | 2007-02-16 | 2009-10-13 | Fujitsu Limited | Analog-to-digital conversion controller, optical receiving device, optical receiving method, and waveform-distortion compensating device |
WO2010128577A1 (ja) * | 2009-05-07 | 2010-11-11 | 日本電気株式会社 | コヒーレント受信機 |
JP2011223563A (ja) * | 2010-04-02 | 2011-11-04 | Fujitsu Ltd | コヒーレント受信装置およびコヒーレント受信方法 |
US9602784B2 (en) | 2009-01-30 | 2017-03-21 | Intersil Americas LLC | Mixed format media transmission systems and methods |
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US8265133B2 (en) * | 2009-09-30 | 2012-09-11 | Silicon Laboratories Inc. | Radio receiver having a multipath equalizer |
EP2487813B1 (en) * | 2011-02-01 | 2013-04-17 | Alcatel Lucent | Polarization de-multiplex for multilevel signals |
US20130230311A1 (en) * | 2012-03-02 | 2013-09-05 | Neng Bai | Systems and methods for compensating for interference in multimode optical fiber |
Family Cites Families (1)
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AU2002213589A1 (en) * | 2000-03-22 | 2001-12-17 | University Of Maryland Baltimore County | System and method for reducing differential mode dispersion effects in multimode optical fiber transmissions |
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2005
- 2005-04-01 GB GB0618858A patent/GB2429382A/en not_active Withdrawn
- 2005-04-01 JP JP2006513820A patent/JPWO2005117285A1/ja not_active Withdrawn
- 2005-04-01 WO PCT/JP2005/006473 patent/WO2005117285A1/ja active Application Filing
- 2005-04-01 US US11/587,372 patent/US20070223570A1/en not_active Abandoned
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Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7602322B2 (en) | 2007-02-16 | 2009-10-13 | Fujitsu Limited | Analog-to-digital conversion controller, optical receiving device, optical receiving method, and waveform-distortion compensating device |
US9602784B2 (en) | 2009-01-30 | 2017-03-21 | Intersil Americas LLC | Mixed format media transmission systems and methods |
JP2009153200A (ja) * | 2009-03-30 | 2009-07-09 | Fujitsu Ltd | 波形歪み補償装置 |
JP4757323B2 (ja) * | 2009-03-30 | 2011-08-24 | 富士通株式会社 | 波形歪み補償装置 |
WO2010128577A1 (ja) * | 2009-05-07 | 2010-11-11 | 日本電気株式会社 | コヒーレント受信機 |
JP5024481B2 (ja) * | 2009-05-07 | 2012-09-12 | 日本電気株式会社 | コヒーレント受信機 |
US8515293B2 (en) | 2009-05-07 | 2013-08-20 | Nec Corporation | Coherent receiver |
JP2011223563A (ja) * | 2010-04-02 | 2011-11-04 | Fujitsu Ltd | コヒーレント受信装置およびコヒーレント受信方法 |
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GB2429382A (en) | 2007-02-21 |
GB0618858D0 (en) | 2006-11-08 |
US20070223570A1 (en) | 2007-09-27 |
JPWO2005117285A1 (ja) | 2008-04-03 |
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