Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
  • H01L29/76—Unipolar devices, e.g. field effect transistors
  • H01L29/772—Field effect transistors
  • H01L29/78—Field effect transistors with field effect produced by an insulated gate
  • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
  • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
  • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
  • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
  • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
  • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/66007—Multistep manufacturing processes
  • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
  • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
  • H01L29/66409—Unipolar field-effect transistors
  • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
  • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
  • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/66007—Multistep manufacturing processes
  • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
  • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
  • H01L29/66409—Unipolar field-effect transistors
  • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
  • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
  • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
  • H01L29/66719—With a step of forming an insulating sidewall spacer
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/66007—Multistep manufacturing processes
  • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
  • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
  • H01L29/66409—Unipolar field-effect transistors
  • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
  • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
  • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
  • H01L29/66727—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the source electrode
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
  • H01L29/76—Unipolar devices, e.g. field effect transistors
  • H01L29/772—Field effect transistors
  • H01L29/78—Field effect transistors with field effect produced by an insulated gate
  • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
  • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/66007—Multistep manufacturing processes
  • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
  • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
  • H01L29/66409—Unipolar field-effect transistors
  • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
  • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/66007—Multistep manufacturing processes
  • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
  • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
  • H01L29/66409—Unipolar field-effect transistors
  • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
  • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers

Definitions

• the present invention relates to a high breakdown voltage semiconductor device. More particularly, the present invention relates to a high breakdown voltage semiconductor device wherein an insulation spacer capable of substitute-perfonning functions of an inter-insulation film, a contact hole and a mask, etc. by a self- alignment and simplifying a general process for manufacturing a device is newly ananged in a part of a gate electrode pattern.
• an insulation spacer capable of substitute-perfonning functions of an inter-insulation film, a contact hole and a mask, etc. by a self- alignment and simplifying a general process for manufacturing a device is newly ananged in a part of a gate electrode pattern.
• the invention relates to a method of manufacturing the high breakdown voltage semiconductor device.
• a semiconductor substrate 1 is separated into a device separating area and an active area by a device separating film 5.
• the semiconductor device 1 comprises, for example, a high concentration impurity layer la and a high breakdown voltage epitaxial layer lb.
• the active area of the semiconductor substrate 1 is sequentially provided with a gate electrode pattern 7, a gate insulating film pattern 6, a channel diffusion layer 2, a source diffusion layer 4, a resistance drop-inducing layer 3, an inter-insulation film 8 and a metal electrode 9, etc.
• the channel diffusion layer 2 consists of, for example, a low concentration of P-type impurities.
• the source diffusion layer 4 consists of a high concentration of N-type impurities.
• the resistance drop-inducing layer 3 consists of a high concentration of P-type impurities.
• At least 5 ⁇ 7 masks are typically required to manufacture the high breakdown voltage semiconductor device having the above-mentioned structure.
• the high breakdown voltage semiconductor device 10 as shown in Fig. 1 it is required five masks, i.e., one mask in a process of forming the gate electrode pattern 7, one mask in a process of separately forming the source diffusion layer 4, one mask in a process of forming the resistance drop-inducing layer 3, one mask in a process of forming a contact hole of the inter-insulation film 8 and one mask in a process of the metal electrode 9. Needless to say, it is required additional time and costs to use each masks.
• the miss-alignment continues to exert a bad influence on the normal formation of the various device patterns as mentioned above. Accordingly, it cannot be avoided that the device to be finally completed has an increased size larger than an originally designed size. The problem of the size increase becomes worse as the photograph etching process is repeated (i.e., as the required number of the masks is increased).
• the object of the present invention is to newly anange an insulation spacer capable of substitute-performing functions of an inter-insulation layer, a contact hole and a mask, etc. by a self-alignment and simplifying a general process for manufacturing a device in a part of a gate electrode pattern.
• the number of masks required for the device manufacture can be naturally reduced. It allows a manufacturer to easily avoid various problems caused due to an increase of the number of masks, for example, an increase of manufacturing cost, an extension of a manufacturing period, an increase of a burden of stored goods (physical distribution), a falling off in cost competitiveness, and an extension of a product development period, etc.
• Another object of the invention is to newly anange an insulation spacer capable of substitute-performing functions of an inter-insulation film, a contact hole and a mask, etc. by a self-alignment, thereby naturally reducing the number of masks required for a device manufacture, minimizing a morphology abnormality of each unit patterns due to a miss-alignment of the mask and effectively reducing a size of the device to be finally completed.
• a high breakdown voltage semiconductor device comprising gate electrode patterns individually spacedly formed in an active area of a semiconductor substrate; a channel diffusion layer selectively occupying a part under the space between the gate electrode patterns; source diffusion layers located in both sides of each gate electrode patterns and spacedly formed in a pair in the channel diffusion layer; a resistance drop-inducing layer electrically contacting to each pair of the source diffusion layers located in the channel diffusion layer and selectively ananged in the channel diffusion layer; insulation spacers selectively covering both side walls of each gate electrode patterns so as to allow a part of the source diffusion layer and a part of the resistance drop- inducing layer to be selectively exposed and protruding from each of the gate electrode patterns upward; and a metal electrode occupying an upper part of the semiconductor substrate so as to allow each insulation spacers to be exposed, electrically contacting to the source diffusion layer and the resistance drop-inducing layer exposed by the insulation spacer, and electrically divided by the insulation spacers.
• a method of manufacturing a high breakdown voltage semiconductor device comprising steps of sequentially depositing a raw material layer of a gate electrode pattern and a sacrificial film on a front surface of a semiconductor substrate having an active area defined, and selectively patterning the raw material layer of the gate electrode pattern and the sacrificial film to form a plurality of gate electrode pattern/sacrificial film pattern deposits individually spaced in the active area; selectively ion-implanting first conductive impurities in the active area to form a channel diffusion layer in a part under the space between the gate electrode pattern/sacrificial film pattern deposits; selectively ion-implanting second conductive impurities in both sides of the gate electrode pattern/sacrificial film pattern deposits to form a pair of source diffusion layers spaced in the channel diffusion layer; forming insulation spacers on both side walls of the gate electrode pattern/sacrificial film pattern deposits so as to allow the channel diffusion layer and the source diffusion layers
• FIG. 1 an exemplary view of a high breakdown voltage semiconductor device according to the prior art
• FIG. 2 is an exemplary view of a high breakdown voltage semiconductor device according to an embodiment of the invention
• FIGS. 3 to 10 are process flow views sequentially illustrating a method of manufacturing a high breakdown voltage semiconductor device according to an embodiment of the invention
• FIG. 11 is an exemplary view of a high breakdown voltage semiconductor device according to another embodiment of the invention
• FIGS. 12 to 16 are process flow views sequentially illustrating a method of manufacturing a high breakdown voltage semiconductor device according to another embodiment of the invention
• FIGS. 17, 25, 30 and 36 are exemplary views of a high breakdown voltage semiconductor device according to still another embodiment of the invention.
• FIGS. 18 to 24, 26 to 29, 31 to 35 and 37 to 42 are process flow views sequentially illustrating a method of manufacturing a high breakdown voltage semiconductor device according to still another embodiment of the invention.
• a semiconductor substrate 21 is separated into a device separating area and an active area.
• the semiconductor substrate 21 comprises, for example, a high concentration impurity layer 21a and a high breakdown voltage epitaxial layer 21b.
• the active area of the semiconductor substrate 21 is sequentially provided with gate electrode patterns 27 individually spacedly formed, gate insulating film patterns 26 for electrically insulating the gate electrode patterns 27 from the semiconductor substrate 21, and channel diffusion layers 22, source diffusion layers 24 and resistance drop-inducing layers 23 under a bottom of the gate insulating film patterns 26, which layers are formed by an ion implantation.
• the channel diffusion layer 22 consists of a low concentration of first conductive impurities, for example P-type impurities.
• the source diffusion layer 24 consists of a high concentration of second conductive impurities, for example N-type impurities.
• the resistance drop-inducing layer 23 consists of a high concentration of first conductive impurities, for example P-type impurities.
• the conductive types of the impurities constituting each of the diffusion layers may be variously changed according to the conditions.
• the chamiel diffusion layer 22 selectively occupies a part under the space between the gate electrode patterns 27.
• the source diffusion layers 24 are positioned at both sides of each gate electrode patterns 27 and spacedly ananged while forming a pair in the channel diffusion layer 22.
• the resistance drop-inducing layer 23 is selectively positioned in the channel diffusion layer 22 while electrically contacting to the source diffusion layers 24 ananged in the each of the channel diffusion layers 22. With the structure, the resistance drop- inducing layer 23 flexibly performs functions of dropping a resistance of a metal electrode 29 electrically contacting to the resistance drop-inducing layer and inducing smooth operating characteristics to be shown when the device performs an off operation.
• insulation spacers 28 which protrude from the gate electrode patterns 27 upward while selectively covering both side walls of each of the gate electrode patterns 27 so that parts of the source diffusion layer 24 and the resistance drop-inducing layer 23 are selectively exposed, are additionally ananged an upper part of the semiconductor substrate 21.
• the insulation spacer 28 is made of an oxide film, for example.
• the insulation spacer 28 is formed through a process not requiring a separate mask, for example, an oxide film deposition process and an anisotropic etching process for the oxide film, etc., a manufacturer can easily avoid an additional defrayment of the mask under the use circumstances of the insulation spacer 28.
• Each of the insulation spacers 28 selectively exposes the upper part of the semiconductor substrate 21 by a self-alignment manner on which the resistance drop- inducing layer 23 is formed.
• the manufacturer can normally form the resistance drop-inducing layer 23 which electrically contacts to each pair of the source diffusion layers 24 ananged in each of the channel diffusion layers 22 and is selectively positioned in the channel diffusion layer 22, without additionally using a separate mask for a selective ion implantation for the resistance drop-inducing layer 23.
• the manufacture can effectively eliminate a necessity of the mask for forming the resistance drop-inducing layer 23.
• the insulation spacer 28 selectively opens the source diffusion layer 24 and the resistance drop-inducing layer 23, except an area for forming the gate electrode pattern 27, by a self-alignment manner, similarly to the existing contact hole.
• the manufacturer can electrically connect the metal electrode 29 to the source diffusion layer 24 and the resistance drop-inducing layer 23 normally, without additionally using a separate mask for forming the contact hole.
• the manufacturer can effectively remove a necessity of the mask for forming the contact hole.
• the insulation spacer 28 is protruded from the gate electrode pattern
• the manufacturer can nonnally form the patterned metal electrode 29 without additionally using a separate mask for forming the metal electrode 29.
• the manufacturer can effectively remove a necessity of the mask for patterning the metal electrode 29.
• the insulation spacer 28 capable of substitute-performing functions of an inter-insulation layer, a contact hole and a mask, etc. by a self-alignment and simplifying a general process for manufacturing a device is newly ananged in a part of a gate electrode pattern.
• a manufacturer can easily avoid various problems caused due to an increase of the number of masks, for example, an increase of manufacturing cost, an extension of a manufacturing period, an increase of a burden of stored goods (physical distribution), a falling off in cost competitiveness, and an extension of a product development period, etc.
• a high concentration impurity layer 21a implanted with a high concentration of P-type impurities or N-type 5 impurities is firstly formed. Then, a high breakdown voltage epitaxial layer 21b is formed to have a thickness of several ⁇ m ⁇ several tens ⁇ m on an upper part of the impurity layer 21a.
• a device separating film 25 is fonned to have a thickness of 5,OO ⁇ A ⁇ 15,OO ⁇ A through a series of deposition 10 processes and patterning processes, so as to define an active area on the semiconductor substrate 21, for example, an upper part of the high breakdown voltage epitaxial layer 21b.
• the device separating film 25 is made of SiO 2 , for example.
• a gate insulating film 26 15 having a thickness of, for example, 500 A ⁇ l,50 ⁇ A is grown on the active area of the semiconductor substrate 21 through a series of thermal oxidation processes.
• a raw material layer 27a of a gate electrode pattern having a thickness of, for example, 4,OO ⁇ A ⁇ 8,OO ⁇ A is formed on the gate insulating film 26 through a series of deposition processes. Then, a sacrificial film
• the sacrificial film 43 a comprises a nitride film 41a having a thickness of, for example, 2,000 A ⁇ 30,000A and an oxide film 42a having a thickness of, for example, 3,000A ⁇ 30,000A.
• the thickness and the material of the sacrificial film 43 a may be variously changed
• the raw material layer 27a of the gate electrode pattern and the sacrificial film 43 a are selectively patterned through a series of photograph etching processes using a photoresist pattern (not shown), thereby forming a plurality of gate electrode pattern/sacrificial film deposits 44 on the gate insulating film 26, which are positioned and individually spaced in the active area. 5
• One mask is required to perform the process of forming the gate electrode pattern/sacrificial film deposits 44.
• a low concentration of impurities for example, a low concentration of P-type impurities 10 are ion-implanted and then driven-in for 30 minutes ⁇ 600 minutes under circumstances of 1,000°C ⁇ 1,250°C, thereby forming a channel diffusion layer 22 in a part under the space between the gate electrode pattern/sacrificial film deposits 44.
• a photoresist pattern (PR) for forming a source diffusion layer 24 on the channel diffusion layer 22 is formed through a series of
• a high concentration of impurities for example, a high concentration of N-type impurities having a dosage of about 4.9E15(atoms/cm ) ⁇ 5.1E15(atoms/cm ) are selectively ion-implanted with 75KeV ⁇ 85KeV on both sides of the gate electrode pattern/sacrificial film deposits 44 exposed by the photoresist pattern (PR), thereby forming the source diffusion layers
• an insulation film for example, an oxide film having a thickness of 2,OO ⁇ A ⁇ 14,OO ⁇ A is deposited on the semiconductor substrate 21
• the insulation spacer 28 preferably maintains its thickness of l,OO ⁇ A ⁇ 12,OO ⁇ A.
• a part of the gate insulating film 26 conesponding to the space between the gate electrode pattern/sacrificial pattern deposits 44 is selectively removed by properly regulating an ending point of the etching prcoess, thereby inducing the source diffusion layer 24 and the channel diffusion layer 22 (it is an area in which a resistance drop-inducing layer will be formed) to be easily exposed to an exterior, simultaneously with the formation of each insulation spacers 28.
• a high concentration of impurities for example, a high concentration of P-type impurities having a dosage of about 9 9
• 4.9E15(atoms/cm ) ⁇ 5.1E15(atoms/cm ) are selectively ion-implanted with 75KeV ⁇ 85KeV in the channel diffusion layer 22 (it is an area in which a resistance drop-inducing layer will be formed) exposed by the insulation spacers 28, thereby forming a resistance drop-inducing layer 23 which electrically contacts to each source diffusion layers 24 and is located in the channel diffusion layer 22.
• the resistance drop-inducing layer 23 flexibly performs functions of dropping a resistance of the metal electrode 29 electrically contacting to the resistance drop-inducing layer and inducing smooth operating characteristics to be shown when the device performs an off operation, as described above.
• the insulation spacers 28 selectively exposing an expected area in a self-alignment manner, in which the resistance drop- inducing layer 23 will be formed, have been already formed on the semiconductor substrate 21.
• a manufacturer can easily avoid a use of a separate mask even when forming the resistance drop-inducing layer 23. Accordingly, it is possible to effectively eliminate various difficulties caused due to a use of the mask.
• the sacrificial film pattern 43 is selectively removed from the gate electrode pattern/sacrificial film pattern deposits 44 through a series of wet-etching process using an etching solution, thereby inducing each of the insulation spacers 28 to be naturally protruded from the gate electrode pattern 27 upward. Continuously, as shown in Fig.
• a metal layer is formed on the semiconductor substrate 21 through a series of deposition processes and then is allowed to slowly reflow through a reflow process until the insulation spacers 28 are exposed, thereby forming metal electrodes 29 on the semiconductor substrate 21 which are electrically divided by the insulation spacers 28 and electrically contacts to the source diffusion layer 24 and the resistance drop-inducing layer 23.
• a series of metal etch-back processes may be further performed as necessary.
• the metal electrode may be formed through a metal flow process of depositing a metal layer and progressing a flow process at the same time.
• the insulation spacers 28, which selectively opens the source diffusion layer 24 and the resistance drop-inducing layer 23 except an area for forming the gate electrode pattern 27 by a self-alignment manner similarly to the existing contact hole, have been already formed on the semiconductor substrate 21.
• a manufacturer can electrically connect the metal electrode 29 to the source diffusion layer 24 and the resistance drop-inducing layer 23 normally, without a separate mask for forming the contact hole. Accordingly, the manufacturer can effectively remove a necessity of the mask for forming the contact hole.
• the insulation spacer 28 is protruded from the gate electrode pattern 27 upward and electrically divides the metal electrodes 29 like as individual pattern structures.
• a manufacturer can normally form the patterned metal electrode 29 without a separate mask for forming the metal electrode 29. 5 Accordingly, the manufacturer can effectively remove a necessity of the mask for patterning the metal electrode 29.
• an alloying process for bonding a metal and a silicon, a process of machining a back surface of the substrate, a back surface metal deposition and alloying processes are further performed, thereby finishing an 10 initial process for manufacturing a device having a completed shape.
• the insulation spacer may comprise, for example, a core spacer 34 and side spacers 31, 32 covering both sides of the core spacer 34.
• each of the insulation spacers 15 33 preferably maintains its thickness of about 6,OO ⁇ A ⁇ 36,OO ⁇ A.
• the insulation spacer 33 when the insulation spacer 33 consists of the core spacer 34 and the side spacers 31, 32 and thus a thickness thereof is increased, the insulation spacer 33 has an improved insulation characteristic as an increase of the thickness thereof. Accordingly, the metal 20 electrodes 29 which are electrically divided by the insulation spacers 33 can maintain a more stable characteristic.
• an insulation film for example, an oxide film having a thickness of about 2,OO ⁇ A ⁇ 14,OO ⁇ A is deposited on the semiconductor substrate comprising the gate electrode pattern/sacrificial film pattern deposits 44 through a series of deposition processes and then anisotropically etched, thereby forming the core spacers 34 on both side walls of each gate electrode pattern/sacrificial film pattern deposits 44.
• the core spacer 34 preferably 5 maintains its thickness of 1 ,OO ⁇ A ⁇ l 2,OO ⁇ A.
• a high concentration of impurities for example, a high concentration of P-type impurities having a dosage of about 9 9 4.9E15(atoms/cm ) ⁇ 5.1E15(atoms/cm ) are selectively ion-implanted with 75KeV ⁇ 85KeV in the channel diffusion layer 22 (it is an area in which a resistance 10 drop-inducing layer will be formed) exposed by the core spacers 34, thereby forming a resistance drop-inducing layer 23 which electrically contacts to each source diffusion layers 24 and is located in the channel diffusion layer 22.
• the core spacers 34 selectively exposing an expected area in a self-alignment manner, in which the resistance drop-inducing layer 15 23 will be formed, have been already formed on the semiconductor substrate 21.
• a manufacturer can easily avoid a use of a separate mask even when forming the resistance drop-inducing layer 23. Accordingly, it is possible to effectively eliminate various difficulties caused due to a use of the mask.
• the sacrificial film pattern 43 is selectively 20 removed from the gate electrode pattern/sacrificial film pattern deposits 44 through a series of wet-etching process using an etching solution, thereby inducing each of the core spacers 28 to be naturally protruded from the gate electrode pattern 27 upward.
• an insulation film for example, an oxide film having a thickness of 2,OO ⁇ A ⁇ 14,OO ⁇ A is further deposited on the semiconductor substrate 21
• each of the side spacers 31,32 preferably maintain its thickness of l,000A ⁇ 12.000A.
• a part of the gate insulating film 26 conesponding to the space between the gate electrode patterns 27 is selectively removed by properly regulating an ending point of the etching process, thereby inducing the source diffusion layer 24 and the resistance drop-inducing layer 23 to be easily exposed to an exterior, simultaneously with the formation of the side spacer 32.
• a metal layer is formed on the semiconductor substrate 21 through a series of deposition processes and then is allowed to slowly reflow through a reflow process until the insulation spacers 33 are exposed, thereby forming metal electrodes 29 on the semiconductor substrate 21 which are electrically divided by the insulation spacers 33 and electrically contacts to the source diffusion layer 24 and the resistance drop- inducing layer 23.
• a series of metal etch-back processes may be also further performed as necessary.
• the metal electrode may be formed through a metal flow process of depositing a metal layer and progressing a flow process at the same time.
• insulation spacers 51 can serve to induce the source diffusion layer 24 to be divided into two areas spaced apart simultaneously with the formation of the insulation spacer, contrary to the above embodiment.
• a manufacturer can naturally spacedly anange the source diffusion layers 24 in the channel diffusion layer 22 without additionally using the photoresist pattern (PR) as shown in Fig. 6. Accordingly, it is possible to normally fonn the completed source diffusion layers 24 without a separate mask for spacedly arranging the source diffusion layers 24.
• a manufacturer can effectively avoid uses of a mask for spacing the source diffusion layer 24 as well as a mask for forming the resistance drop-inducing layer 23, a mask for fonning a contact hole and a mask for patterning the metal electrode 29.
• a low concentration of impurities for example, a low concentration of P-type impurities are ion-implanted and then driven-in for 30 minutes ⁇ 600 minutes under circumstances of 1,000°C ⁇ 1,250°C, thereby forming the channel diffusion layer 22 in a part under the space between the gate electrode pattern/sacrificial film deposits 44. Then, as shown in Fig.
• a high concentration of impurities for example, a high concentration of N-type impurities having a dosage of about 4.9E15(atoms/cm 2 ) ⁇ 5.1E15(atoms/cm 2 ) are selectively ion-implanted with 75KeV ⁇ 85KeV on both sides of the gate electrode pattern sacrificial film deposits 44, thereby forming the source diffusion layer 24 which is located in the channel diffusion layer 22.
• a high concentration of impurities for example, a high concentration of P-type impurities are selectively ion-implanted in the channel diffusion layer 22 (it is an area in which a resistance drop-inducing layer will be formed) with an energy higher than the energy in the case of forming the source diffusion layer 24, thereby forming the resistance drop-inducing layer 23 which electrically contacts to a bottom of the source diffusion layer 24 and is located in the channel diffusion layer 22.
• the formations of the gate electrode pattern/sacrificial film pattern deposits 44, the channel diffusion layer 22, the source diffusion layer 24 and the resistance drop-inducing layer 23, etc.
• an insulation film for example, an oxide film having a thickness of 2,000 A ⁇ l 4,000 A is deposited on the semiconductor substrate comprising the gate electrode pattern/sacrificial film pattern deposits 44 through a series of deposition processes. Then, the oxide film is anisotropically etched, thereby forming insulation spacers 51 on both side walls of each gate electrode pattern/sacrificial pattern deposits 44 as shown in Fig 22. In this case, the insulation spacer 51 preferably maintains its thickness of 1 ,OO ⁇ A ⁇ 12,OO ⁇ A.
• a part of the gate insulating film 26 and a part of the source diffusion layer 24 conesponding to the space between the gate electrode pattern/sacrificial pattern deposits 44 are selectively removed by properly regulating an ending point of the etching process as described above, thereby inducing the source diffusion layer 24 to be divided into two spaced areas and the resistance drop-inducing layer 23 to be easily exposed to an exterior, simultaneously with the formation of each insulation spacers 51.
• the source diffusion layer 24 is divided into two spaced areas simultaneously with the formation of each insulation spacers 51, a manufacturer can normally obtain the source diffusion layer 24 having a completed shape without a separate mask for spacing the source diffusion layer 24.
• the sacrificial film pattern 43 is selectively removed from the gate electrode pattern sacrificial film pattern deposits 44 through a series of wet-etching processes using an etching solution, thereby inducing each of the insulation spacers 51 to be naturally protruded from the gate electrode pattern 27 upward.
• a metal layer is formed on the semiconductor substrate 21 through a series of deposition processes and then is allowed to slowly reflow through a reflow process until the insulation spacers are exposed, thereby fonning a metal electrode 29 on the semiconductor substrate 21 which is electrically divided by the insulation spacers 51 and electrically contacts to the source diffusion layer 24 and the resistance drop-inducing layer 23.
• a series of metal etch-back processes may be also further performed as necessary.
• the metal electrode may be formed through a metal flow process of depositing a metal layer and progressing a flow process at the same time according to the conditions.
• the insulation spacer may comprise, for example, a core spacer 55 and side spacers 52, 53 covering both sides of the core spacer 55.
• the insulation spacer 54 preferably maintains its thickness of 6,OO ⁇ A ⁇ 36,000 A.
• the insulation spacer 54 when the insulation spacer 54 consists of the core spacer 55 and the side spacers 51, 52 and thus a thickness thereof is increased, the insulation spacer 54 can provide an improved insulation characteristic as an increase of the thickness thereof. Accordingly, each of the metal electrodes 29 which are electrically divided by the insulation spacers 54 can maintain a more stable characteristic.
• an insulation film for example, an oxide film having a thickness of about 2,OO ⁇ A ⁇ 14,OO ⁇ A is deposited on the semiconductor substrate 21 comprising the gate electrode pattern/sacrificial film pattern deposits 44 through a series of deposition processes. Then, the oxide film is anisotropically etched, thereby forming core spacers 55 on both side walls of each gate electrode pattern/sacrificial pattern deposits 44. In this case, the core spacer 55 preferably maintains its thickness of 1 ,OO ⁇ A ⁇ l 2,OO ⁇ A.
• the sacrificial film pattern 43 is selectively removed from the gate electrode pattern/sacrificial film pattern deposits 44 through a series of wet-etching process using an etching solution, thereby inducing each of the core spacers 55 to be naturally protruded from the gate electrode pattern 27 upward.
• an insulation film for example, an oxide film having a thickness of about 2,OO ⁇ A ⁇ 14,OO ⁇ A is further deposited on the semiconductor substrate 21 comprising the core spacer 55 through a series of deposition processes.
• the oxide film is anisotropically etched, thereby forming side spacers 52,53 on both side walls of each core spacers 55 as shown in Fig. 28.
• each of the side spacers 52,53 preferably maintains its thickness of 1,000A ⁇ 12,000A.
• a part of the gate insulating film 26 and a part of the source diffusion layer 24 conesponding to the space between the gate electrode patterns 27 are selectively removed by properly regulating an ending point of the etching process, thereby inducing the source diffusion layer 24 to be divided into two spaced areas and the resistance drop-inducing layer 23 to be easily exposed to an exterior, simultaneously with the formation of the side spacer 53.
• a metal layer is formed on the semiconductor substrate 21 through a series of deposition processes and then is allowed to slowly reflow through a reflow process until the insulation spacers 54 are exposed, thereby forming metal electrode 29 on the semiconductor substrate 21, which is electrically divided by the insulation spacers 54 and electrically contacts to the source diffusion layer 24 and the resistance drop-inducing layer 23.
• a series of metal etch-back processes may be also further performed as necessary.
• the metal electrode may be formed through a metal flow process of depositing a metal layer and progressing a flow process at the same time, according to the conditions.
• an alloying process for bonding a metal and a silicon, a process of machining a back surface of the substrate, a back surface metal deposition and alloying processes are further performed, thereby finishing an initial process for manufacturing a device having a completed shape.
• the insulation spacers 28 may be formed, based on a gate electrode pattern 61 only, without depending on the sacrificial film pattern.
• each of the gate electrode patterns 61 is spacedly ananged in the active area of the semiconductor substrate 21 and preferably has an increased thickness of 9,000A ⁇ 38,000A, compared to the above embodiments (and the prior art).
• insulation spacers 28 may be formed, based on the gate electrode pattern 61 only, without depending on the sacrificial film pattern, a manufacturer can eliminate the processes of forming and removing the sacrificial film pattern at ease and obtain an improved process efficiency.
• a plurality of gate electrode patterns having an increased thickness of 9,000A ⁇ 38,000A are individually spacedly formed on the gate insulating film 26 through a series of deposition and patterning processes.
• the channel diffusion layer and the source diffusion layer, etc. are further formed in the active area of the semiconductor substrate 21 through a series of ion implantation and photoresist patterning processes.
• an insulation film for example, an oxide film having a 5 thickness of about 2,000 A ⁇ 14,OO ⁇ A is deposited on the semiconductor substrate 21 comprising the gate electrode pattern 61 through a series of deposition processes. Then, the oxide film is anisotropically etched, thereby forming insulation spacers 28 on both side walls of each of the gate electrode patterns 61 as shown in Fig. 33. In this case, each of the insulation spacers 28 preferably maintains its thickness of 10 1,000A ⁇ 12,000A.
• a part of the gate insulating film 26 conesponding to the space between the gate electrode patterns 61 is selectively removed by properly regulating an ending point of the etching process, thereby inducing the source diffusion layer 24 and the channel diffusion layer 22 (it is an 15 expected area in which a resistance drop-inducing layer will be formed) to be easily exposed to an exterior, simultaneously with the formation of the insulation spacer 28.
• a high concentration of impurities for example, a high concentration of P-type impurities having a dosage of about 9 9 4.9E 15 (atoms/cm ) ⁇ 5.1E15(atoms/cm ) are selectively ion-implanted with 20 75KeV ⁇ 85KeV in the channel diffusion layer 22 (it is an area in which a resistance drop-inducing layer will be formed) exposed by the insulation spacers 28, thereby forming a resistance drop-inducing layer 23 which electrically contacts to each pair of source diffusion layers 24 and is located in the channel diffusion layer 22.
• the metal electrode may be formed hrougha metal flow process of depositing a metal layer and progressing a flow process at the same time.
• each insulation spacer 71 can perform the function of inducing the source diffusion layer 24 to be divided into the two spaced areas, simultaneously with the formation of the insulation spacer itself.
• a manufacturer can effectively eliminate a use of the mask for spacing the source diffusion layers 24 as well as inconveniences caused due to the formation and removal of the sacrificial film pattern.
• a low concentration of impurities for example, a low concentration of P-type impurities are ion-implanted and then driven- in for 30 minutes ⁇ 600 minutes under circumstances of 1,000°C ⁇ 1,250°C, thereby forming a channel diffusion layer 22 in a part under the space between the gate electrode patterns 61.
• a high concentration of impurities for example, a high concentration of N-type impurities having a dosage of about
• a high concentration of impurities for example, a high concentration of P-type impurities are selectively ion-implanted in the channel diffusion layer 22 (it is an area in which a resistance drop-inducing layer will be formed) with an energy higher than the energy in the case of forming the source diffusion layer 24, thereby forming a resistance drop-inducing layer 23 which electrically contacts to a bottom of the source diffusion layer 24 and is located in the channel diffusion layer 22.
• an insulation film for example, an oxide film having a thickness of 2,OO ⁇ A ⁇ 14,OO ⁇ A is deposited on the semiconductor substrate comprising the gate electrode pattern/sacrificial film pattern deposits 44 through a series of deposition processes. Then, the oxide film is anisotropically etched, thereby forming insulation spacers 71 on both side walls of each gate electrode pattern/sacrificial pattern deposits 44, as shown in Fig. 41. In this case, each of the insulation spacer 71 preferably maintains its thickness of l,OO ⁇ A ⁇ 12,OO ⁇ A.
• a part of the gate insulating film 26 and a part of the source diffusion layer 24 conesponding to the space between the gate electrode patterns 61 are selectively removed by properly regulating an ending point of the etching process as described above, thereby inducing the source diffusion layer 24 to be divided into two spaced areas and the resistance drop-inducing layer 23 to be easily exposed to an exterior, simultaneously with the formation of each insulation spacers 71.
• a metal layer is formed on the semiconductor substrate 21 through a series of deposition processes and then is allowed to slowly reflow through a reflow process until the insulation spacers 71 are exposed, thereby forming metal electrodes 29 on the semiconductor substrate 21, which are electrically divided by the insulation spacers 71 and electrically contacts to the source diffusion layer 24 and the resistance drop-inducing layer 23.
• a series of metal etch-back processes may be also further performed as necessary.
• the metal electrode may be formed through a metal flow process of depositing a metal layer and progressing a flow process at the same time.
• the invention may be variously modified according to the conditions.
• the metal electrode may be formed through a contact plug process, for instance, a tungsten plug process.
• the metal electrode may be formed by continuously progressing the tungsten plug process and the metal reflow (flow) process.
• an alloying process for bonding a metal and a silicon, a process of machining a back surface of the substrate, a back surface metal deposition and alloying processes are further performed, thereby finishing an initial process for manufacturing a device having a complete shape.
• an insulation spacer capable of substitute-performing functions of an inter-insulation film, a contact hole and a mask, etc. by a self-alignment and simplifying a general process for manufacturing a device is newly ananged in a part of a gate electrode pattern.
• an insulation spacer capable of substitute-performing functions of an inter-insulation film, a contact hole and a mask, etc. by a self-alignment is newly arranged and thus the number of masks required for a device manufacture is naturally reduced, so that a morphology abnormality of each unit patterns caused due to a miss-alignment of the mask is minimized.
• a size of the device to be finally completed can be effectively reduced.

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