WO2005096634A1 - マルチタスク処理システム、及び、マルチタスク処理方法 - Google Patents
マルチタスク処理システム、及び、マルチタスク処理方法 Download PDFInfo
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- WO2005096634A1 WO2005096634A1 PCT/JP2005/006192 JP2005006192W WO2005096634A1 WO 2005096634 A1 WO2005096634 A1 WO 2005096634A1 JP 2005006192 W JP2005006192 W JP 2005006192W WO 2005096634 A1 WO2005096634 A1 WO 2005096634A1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
- G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/3296—Power saving characterised by the action undertaken by lowering the supply or operating voltage
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Definitions
- the present invention relates to a multi-task processing system and a multi-task processing method for processing a plurality of tasks in a time-division manner, and is particularly suitable for a case where a task of a moving image encoding process and a Z or moving image decoding process is included.
- the present invention relates to a multitask processing system and a multitask processing method.
- Picture Experts Group and H.26X. These perform encoding or decoding of a plurality of temporally consecutive frames constituting a moving image, and reduce redundancy using temporal correlation and spatial correlation of the moving image. In this technique, the amount of information of a moving image is reduced and encoded, and the encoded moving image is decoded again into the original moving image.
- Powerful encoding / decoding technology is applied to information terminal devices such as mobile phones having a built-in personal computer or microcomputer, and is based on a program that describes encoding / decoding means.
- the system functions as a moving image encoding system when transmitting a moving image, and as a moving image decoding system when receiving a moving image.
- the power consumption tends to increase due to the relatively large amount of computation in the moving image encoding or decoding processing, and software that is more versatile than hardware is used.
- reducing power consumption in the encoding and decoding processes has become a major issue.
- Non-Patent Document 1 A conventional means for reducing power consumption is disclosed in, for example, the following Non-Patent Document 1.
- Non-Patent Document 1 Proceedings of IEEE International Symposium on Circuits and System 2001 (May, 2001) pp918—921 "AnLSI for Vdd—Hopping and MPEG4 System Based on the Chip, (H. Kawaguchi, G. Zhang, S .Lee, and T. Sakurai)
- FIG. 13 is a diagram showing a conventional technique for reducing power consumption of a moving image (moving image) encoding processing system shown in Non-Patent Document 1.
- the means for reducing power consumption is the same in a moving picture decoding processing system.
- Non-Patent Document 1 discloses an operating power supply for reducing power consumption when processing moving image coding (especially MPEG) on a processor capable of dynamically changing an operating power supply voltage and an operating frequency. Show how to control voltage and operating frequency! That is, as disclosed in Non-Patent Document 1, as shown in FIG. 14, when performing moving image encoding, the operation of moving image encoding or decoding is performed in frame units depending on the intensity of motion in the moving image. The power consumption is controlled by controlling the operating frequency and operating power supply voltage of the processor, noting that the amount differs.
- the processing time of one frame is restricted by the time Tf due to the regulations of the encoding system (such as MPEG), and the encoding process of one frame is completed within the processing time Tf. That power S is needed.
- Tf seconds
- Tslot TfZN
- TRi Tf Tslot Xi.
- the number of video blocks processed in one time slot Tslot (video coding is processed in block units) is R (ie, RXN is the number of blocks of one frame), and (RX i)
- TaccG + l) be the time spent in block processing (that is, the time actually taken to process a group of blocks to be processed from time slot Tslotl to time slot Tslot).
- Trd The time it takes for the operating power supply voltage and operating frequency to stabilize when the voltage is changed.
- the actual time slot RTsloti indicates the processing time actually required for the processing to be completed in the time slot Tsloti. In FIG. 13, first, processing of the block group assigned to the time slot Tsloti and the time slot Tslot2 is performed.
- Tacc 3 Tacc3 (Tf-TR2), that is, if the allocated block group completes processing in time slots Tslotl and Tslot2, it is assigned to the next time slot Tslot3.
- the minimum operation frequency among the operation frequencies capable of processing a predetermined number of block groups within the control time is selected, so that the overall operation frequency is changed.
- the processor at a constant operating frequency FfC, power consumption can be further reduced as compared with a case where the operating frequency Fl is changed many times within the processing time Tf.
- Non-Patent Document 1 the operating power supply voltage and operating frequency are changed up to N times in one frame, even though the unit of synchronization of the processing time Tf is one frame. And low power consumption was not achieved enough.
- the low power consumption of the moving picture coding or decoding processing in a processor capable of controlling the operating power supply voltage and operating frequency in multiple stages as in the conventional example is achieved by reducing the operating power supply many times during the processing of one frame.
- the control since the unit of the constraint on the processing time is a frame, it is preferable that the control is performed at a minimum constant frequency that allows processing during the processing of one frame. For this reason, the power supply voltage and the operating frequency are changed up to N times during the processing of one frame. In this conventional example, the power consumption has not been sufficiently reduced.
- Patent Document 1 The inventors of the present application have completed the invention of Patent Document 1 below.
- the present invention is intended to reduce power consumption by performing encoding / decoding processing while operating the processor 1 at a constant operating power supply voltage / operating frequency.
- Patent Document 1 Japanese Patent Application No. 2003—48535
- One of the other factors that hinder the low power consumption of the processor is a subthreshold leakage current of a MOS transistor included in the processor.
- the subthreshold leakage current is a small current that flows when the gate voltage of a MOS transistor formed on a semiconductor substrate is equal to or lower than a threshold voltage.
- the power consumption due to the sub-threshold leakage current tends to be dominant as the size of the MOS transistor increases, and using a processor in which the MOS transistor is integrated on a semiconductor substrate, the power consumption of the moving image is reduced. Is one of the factors that hinder low power consumption in a moving picture coding or decoding system that performs decoding.
- This sub-threshold leakage current is larger at a constant operating frequency Ff throughout the processing time Tf ⁇ than when the operating frequency Fl ⁇ of the processor is varied many times within the processing time Tf of one frame.
- the operation reduces the power consumption, and the power consumption of the processor can be reduced.
- the unit of processing time Tf is synchronized with one frame, the operating frequency is changed up to N times in one frame.
- the viewpoint power of the sub-threshold leakage current was also favorable.
- MOS transistors it is known that the subthreshold leakage current can be controlled by controlling the substrate bias voltage in the semiconductor region where the MOS transistor is formed.
- the leakage current flowing in the processor includes a charge / discharge current, a sub-threshold leakage current t>, (jIDL (Gate-Induced Drain Leakage) ⁇ DIBL (Drain-Induced Barrier Lowering), and gate leakage. And other currents, and these currents tend to increase as the size of MOS transistors increases, which is a factor that hinders the reduction in power consumption of processors.
- GIDL Gate-Induced Drain Leakage
- DIBL drain-induced barrier lowering
- the inventors of the present application have completed the invention of Patent Document 2 below.
- the present invention calculates the amount of calculation necessary for encoding or decoding for each frame, and processes the computation at a constant substrate bias voltage-operating frequency or a constant substrate bias voltage 'operating power supply voltage' operating frequency.
- the power consumption is reduced by performing the encoding and decoding processes while operating the computer.
- Patent Document 2 Japanese Patent Application 2003--409641
- an object of the present invention is to provide a multitask processing system and a multitask processing method capable of reducing power consumption, and particularly to reduce power consumption when a task of moving image encoding processing and decoding processing is included.
- An object of the present invention is to propose a multitask processing system and a multitask processing method that can be implemented. Means for solving the problem
- the inventors have confirmed that low power consumption can be achieved by controlling the processor at a constant operating frequency and operating power supply voltage, and have completed the present invention.
- Figure 15 shows an example of the relationship between the substrate bias voltage Vbn and the threshold voltage Vtn of an n-channel MOS transistor, and an example of the relationship between the substrate bias voltage Vbp and the threshold voltage Vtp of a p-channel MOS transistor. To represent.
- the threshold voltage Vtn decreases when the substrate bias voltage Vbn of the n-channel MOS transistor increases, and the threshold voltage Vtp increases when the substrate bias voltage Vbp of the p-channel MOS transistor increases, and the substrate bias voltages Vbn, Vbp
- the threshold voltage Vtn, —Vtp can be controlled.
- the operating frequency of the processor generally increases, and the operating frequency f of the processor 1 changes by controlling the threshold voltage.
- Vtn, —Vtp is 0 [V]
- (2) is when Vtn, — Vtp is 0.1 [V]
- (3) is Vtn, — V
- An example of the relationship between the threshold voltage Vtn, —Vtp and the subthreshold leakage current 1st when tp is 0.2 [V] is shown.
- the threshold voltage Vtn, —Vtp increases, the subthreshold leak current 1st decreases, and the subthreshold leak current 1st can be controlled by controlling the threshold voltage Vtn, —Vtp. Therefore, the subthreshold leak current 1st can be controlled by the substrate bias voltages Vbn and Vbp.
- the operating frequency f suitable for the calculation amount is calculated, and the substrate bias voltages Vbn and Vbp are controlled so that the operating frequency f can be realized and the subthreshold leakage current 1st can be suppressed.
- the sub-threshold leak current 1st can be suppressed by performing the encoding or decoding of one frame while keeping the processor operating at a constant level. For example, when the operating frequency can be set low, the threshold voltage can be raised by lowering the substrate bias voltage, and the subthreshold leakage current can be suppressed. Therefore, the total current can be suppressed, and low power consumption can be realized.
- the inventors control not only the substrate bias voltage but also the operating power supply voltage, so that the sub-threshold leakage current, the charging / discharging current, and other leakage currents are appropriately controlled.
- the present invention has been completed in which the power consumption can be suppressed and the power consumption can be more effectively reduced.
- Icd aXCXfXVDD
- VDD Operating power supply voltage
- Vgs gate-source voltage
- Vt threshold! /, Value voltage (Vtn or-Vtp), S: sub-threshold swing
- the threshold voltage is determined by using the substrate bias voltage.
- Vt VtO + ⁇ ( ⁇ —VBB)
- VtO, ⁇ , ⁇ constant
- VBB substrate bias voltage (Vbn or-Vbp)
- the operating frequency uses the operating power supply voltage and the threshold voltage
- FIG. 16 is a diagram illustrating the relationship between the power consumption P and the operating power supply voltage VDD when the operating frequency f of the processor is fixed. For example, if the operating power supply voltage VDD of processor 1 is reduced, the charging / discharging current led will decrease. It is necessary to increase the substrate bias voltage Vbn and / or Vbp and decrease the value voltage Vt, and accordingly, the subthreshold leakage current 1st increases exponentially.
- the power consumption P there is a minimum value for the power consumption P, and there is a combination of the operating power supply voltage VDD, the substrate bias voltage Vbn, and / or -Vbp that minimizes the power consumption.
- a processor which is a semiconductor device in which MOS transistors are integrated, controls GIDL (Gate-Induced Drain Leakage) besides charge / discharge current and sub-threshold leakage current by controlling substrate bias voltage and operating power supply voltage.
- GIDL Drain-induced barrier lowering
- DIBL drain-induced barrier lowering
- GIDL is a current flowing toward a drain substrate due to a tunneling phenomenon when a high electric field is generated in an overlapping portion between a gate region and a drain region of a MOS transistor.
- DIBL is a current that flows when a drain voltage of a MOS transistor is high, a source barrier is lowered, and a source force is injected into a channel surface by carriers.
- Gate leak is a current flowing from the gate to the channel due to the tunneling phenomenon in the gate oxide film of a MOS transistor.
- DIBL is a function of operating supply voltage only; GIDL, gate leakage, and other currents are functions of operating supply voltage and substrate bias voltage. Taking these leakage currents into account, the power consumption P in the processor is
- Pcd Charge / discharge power
- Pst Power due to sub-threshold leak
- PGIDL Power consumption by GIDL
- PDIBL Power consumption by DIBL
- Pgl Power consumption due to gate leakage
- Pother Other power consumption
- the power consumption P is a function of the operating power supply voltage and the substrate bias voltage.
- the processor can be operated with an operating power supply voltage and a substrate bias voltage that minimize the total power consumption for a predetermined operating frequency, thereby further effectively reducing the power consumption. Strengthening can be achieved.
- the multitask processing system and the multitask processing method of the present invention are applied to a multitask processing system and a multitask processing method that process a plurality of tasks in a time-division manner. Then, the total operation amount H required for the task processing to be completed within the control time T is calculated, and the operating frequency at which the total operation amount H can be processed within the remaining time T-t is determined. And performing task processing while operating the processor with an operating power supply voltage and Z or a substrate bias voltage suitable for the operating frequency.
- the present invention it is possible to calculate the total operation amount H required for the task processing to be completed within the control time T, and process the operating frequency of the processor within the remaining time T1 t Since the operating frequency is set to a low value, task processing can be performed with an operating frequency low enough to process the total amount of computation H, and an operating power supply voltage and Z or a substrate bias voltage suitable for the operating frequency.
- the period during which the processor is constantly operated at the operating frequency or the like may be, for example, until the timing of switching the task processing or until all the tasks are completed.
- a total operation amount required for completing unprocessed task processing at a predetermined timing is calculated, and the total operation amount is defined as the total operation amount H.
- the operation frequency is re-determined.
- the total operation amount required for completing the unprocessed task processing is calculated as the total operation amount H, and the total operation amount H and the remaining Since the relationship between time T and t also determines the operating frequency again, the operating frequency is corrected at each timing, such as when task processing is switched, to increase the possibility that all task processing will be completed within the control time T. it can.
- the multitask processing system and the multitask processing method according to the present invention provide the multitask processing system H is characterized by being the sum of the calculation amount of each task and the calculation amount required for switching task processing.
- the operation amount of each task a predicted operation amount Hp to be described later may be used, or the maximum operation amount Hw may be used.
- the total operation amount H is the sum of the operation amount of each task and the operation amount required for switching the task processing. Therefore, the operating frequency is determined in consideration of the operation amount of the switching process. Is done. Even if time is consumed for task switching, it is possible to increase the possibility that all task processing will be completed within the control time T.
- the multitask processing system and the multitask processing method of the present invention include at least one failure avoiding means Z step for avoiding a failure phenomenon that occurs when the total operation amount H is smaller than the actually required total operation amount. It is characterized by having. If the calculated total operation amount H is smaller than the actually required operation amount, the task processing is not completed within the control time T and a failure phenomenon occurs.However, the present invention provides one or more methods for avoiding the failure phenomenon. The provision of the failure avoidance means Z step prevents the failure phenomenon from occurring.
- the multitask processing system and the multitask processing method of the present invention are characterized in that the failure avoiding means includes a first failure avoiding means Z step for giving a margin to the total computation amount H.
- the failure avoiding means Z step increases the total amount of calculation H by a predetermined value, the possibility that the calculated total amount of calculation H satisfies the actually required amount of calculation increases, and the failure phenomenon Can be increased.
- the first failure avoiding means Z step calculates the value by adjusting the values of m and n in order to multiply the total operation amount H by m and add Z to the total operation amount H or n.
- the calculated total calculation amount H can be set to a value larger than the actually required calculation amount and close to the actually required calculation amount, and the failure phenomenon can be efficiently avoided.
- the multitask processing system and the multitask processing method of the present invention are characterized by comprising a second failure avoiding means Z step for interrupting at a predetermined timing and simplifying the task processing.
- a part of the task processing is replaced with the alternative Since the amount of calculation is reduced by simplifying the task processing, for example, by changing the logic or by omitting a part of the task, the possibility that the failure phenomenon can be avoided can be increased.
- an interrupt is performed at a predetermined timing, and when a task of a moving image encoding process exists among tasks processed within the control time T.
- Blocks include macroblocks.
- the invalid blocking processing can greatly reduce the amount of calculation as compared with the ordinary code processing. Therefore, by using the invalid blocking processing to reduce the amount of calculation in the moving picture coding processing, it is possible to allocate the shortened time to other task processing.
- the task processing is completed by the invalid blocking processing, and a sufficient time is allocated to the other task processing, so that the possibility of avoiding the breakdown phenomenon can be increased.
- the task process is interrupted at a timing that leaves a processing time for invalidating all blocks included in one frame constituting a moving image, and the invalid blocking process is performed.
- the tasks processed within the control time T include a video encoding task and a Z or a video decoding task. It is characterized by being included.
- the moving picture encoding processing and the moving picture decoding processing require a large amount of computation for the processing as compared with other processing, and thus the power consumption required for the processing tends to increase.
- applications to mobile terminals such as mobile phones have been active, and demands for lower power consumption have been increasing.
- a task of a moving image encoding process and a task of Z or a moving image decoding process are combined with other tasks, such as a multimedia processing device built in a mobile phone, for example, Even in a multitask processing system that is divided and processed, power consumption can be effectively reduced.
- the multitask processing system and the multitask processing method of the present invention are characterized in that the task of the moving picture decoding processing is executed with a higher priority than the task of the moving picture coding processing. To do. Since the moving picture decoding processing cannot be switched to another processing such as the invalid blocking processing as in the moving picture coding processing to reduce the amount of calculation, a breakdown phenomenon is likely to occur. According to the present invention, the task of the video decoding process is executed with a higher priority than the task of the video encoding process. Therefore, the task of the video decoding process may be completed within the control time T. Will be higher. The failure phenomenon of the moving picture coding processing may be dealt with by the above-mentioned invalid blocking processing.
- the total operation amount for task processing is calculated, and the operating frequency capable of processing the total operation amount,
- the processor since the task processing is performed with the operating power supply voltage and Z or substrate bias voltage suitable for the operating frequency, the processor operates at a constant operating frequency and operating power supply voltage low enough to handle the total amount of computation H and consumes it.
- the power is reduced, or the sub-threshold leakage current is suppressed by controlling the operating frequency and the substrate bias voltage, or the sub-threshold leakage current and the charging and discharging are controlled by controlling the operating frequency, the substrate bias voltage and the operating power supply voltage. Current and other leakage currents are moderately suppressed, and low power consumption is achieved even in multitask processing. This is particularly effective when a plurality of tasks to be multitasked include a moving image encoding process and a moving image decoding process.
- the multitask processing system 100 is realized by a computer that is an information terminal device such as a mobile phone or a personal computer having a built-in microcomputer, and particularly functions as a part of a multimedia signal processing unit and the like in the computer. This is a system for moving image encoding and Z decoding.
- the multi-task processing system 100 includes a task Al of encoding processing for sequentially encoding a moving image composed of a predetermined number of continuous frames in frame units, and a plurality of tasks A2, ,, An are multitasked in a time-sharing manner.
- FIG. 1 is a schematic block diagram of a multitask processing system 100 of the present invention using dynamic control of a processor in a multitask environment.
- the multitask processing system 100 includes the processor 1.
- the processor 1 includes a task processing unit 11, a task schedule processing unit 12, and a task table memory 13, and the operating frequency, the operation power supply voltage, and the substrate bias voltage can be controlled stepwise by the dynamic processor control unit 2.
- the task processing means 11 and the task schedule processing means 12 are realized by causing the processor 1 to function as each of the means 11 and 12 by a program.
- Processor 1 is composed of a semiconductor element having a triple-well structure as shown in FIG. By making the processor 1 a triple-well structure, the substrate bias voltage Vbn can be applied to the n-channel MOS transistor, the substrate bias voltage Vbp can be applied to the P-channel MOS transistor, and the substrate bias voltage can be controlled. .
- the task processing means 11 has a function of processing a plurality of tasks Al,,, An in a time-division manner, and processes the tasks Al,,, An corresponding to the tasks Al,,, An.
- each task A1 processing means,... Task An processing means is required to complete its own processing within the designated control time T in response to a request from the task schedule processing means 12.
- the processing routine that calculates the predicted value (predicted calculation amount) Hp and the maximum value (maximum calculation amount) Hw of the complex calculation amount and notifies the task schedule processing means 12, and the self-processing routine within the specified control time T It has a function to call and execute a processing routine that calculates a predicted value (predicted number of times of execution) Cp and a maximum value (maximum number of times of execution) Cw and notifies the task schedule processing means 12 of the execution.
- the task table memory 13 is a storage area that holds a task table indicating the status of each task (see FIG. 5).
- the task table contains the tasks Al,,, An, the task numbers A1,,, An, the predicted computation amount Hp, the maximum computation amount Hw, the predicted execution count Cp, the maximum execution count Cw, and the priority P Column is provided.
- the task schedule processing means 12 has a function of scheduling the operation time of the task A1 processing means,,, and the task An processing means.
- the task schedule processing means 12a, the control time transmission means 12b, and the control time The receiving means 12c, the operating frequency instruction receiving means 12d, the number-of-executions receiving means 12e, the calculation amount receiving means 12f, and the processor control signal transmitting means 12g Prepare.
- the control remaining time transmitting means 12a has a function of transmitting a signal si to the task A1 processing means,,, and task An processing means to notify the remaining time that can be spent on the processing of each of the tasks Al,,, An. .
- the control time transmitting means 12b has a function of notifying the task processing means 11 (each task A1 processing means,..., Task An processing means) of the control time T.
- the control time receiving means 12c has a function of receiving the control time signal s3 of each task transmitted from the task A1 processing means, and the task An processing means.
- the operating frequency instruction receiving means 12d has a function of receiving an operating frequency instruction signal s4 transmitted from the task A1 processing means,,, and the task An processing means to directly indicate the operating frequency of the processor 1.
- the number-of-executions receiving means 12e calculates the predicted number of executions Cp and the maximum number of executions as the number of executions of each of the tasks Al,,, An in the control time T of the processor 1 transmitted from the task A1 processing means,, and the task An processing means. A function to receive the number of times Cw is provided.
- the computational amount receiving unit 12f calculates the predicted value (predicted computational amount) Hp of the computational amount of each of the tasks Al,,, An within the control time T of the processor to be transmitted by the task A1 processing unit,, and the task An processing unit power.
- a function to receive the value (maximum computation amount) Hw is provided.
- the processor control signal transmitting means 12g has a function of generating a signal s7 indicating the operating frequency of the processor 1 and transmitting the signal s7 to the dynamic processor control means 2.
- Each of the above means 12a, 12b, 12c, 12d, 12e, 12f, 12g is a function implemented in the task scheduling means 12, and is implemented as a system call or API (application programming interface) of the multitasking operating system. Ultimately be.
- the dynamic processor control means 2 is a circuit that controls the operation of the processor 1.
- An operating frequency table memory 21, operating frequency generating means 22, operating power supply voltage generating means 23, and substrate bias voltage generating means 24 are provided.
- the operating frequency generating means 22 includes a PLL or the like, generates an operating frequency supply signal s8 to the processor 1, and controls the operating frequency of the processor 1.
- the substrate bias voltage generating means 24 generates a substrate bias voltage supply signal slO for the processor 1 and controls the substrate bias voltage of the processor 1.
- the operating power supply voltage generating means 23 has a function of generating an operating power supply voltage supply signal s9 to the processor 1 and controlling the operating power supply voltage of the processor 1.
- the operating power supply voltage generating means 23 and the substrate bias voltage generating means 24 are preferably realized by a DC-DC converter or the like, but may be realized by using other means.
- Operating frequency table memory 21 Holds the operating frequency F at which the processor 1 can operate and the values of the operating power supply voltage Vdd and the substrate bias voltages Vbn and Vbp suitable for the operating frequency F, as shown in FIG.
- the combination of the operating frequency F, the substrate bias voltages Vbn and Vbp, and the operating power supply voltage Vdd is a combination that can realize the operating frequency F with the minimum power consumption.
- the operating power supply voltage Vdd and the substrate bias voltages Vbn, Vbp that minimize the power consumption are obtained from experiments, calculations, etc., based on the relationship between the sub-threshold leakage current, charge / discharge current, and other leakage currents. It is desirable to use a combination of the power supply voltage Vdd and the substrate bias voltages Vbn and Vbp.
- the dynamic processor control means 2 when receiving the operating frequency instruction signal s7 from the processor 1, the dynamic processor control means 2 refers to the operating frequency table memory 21 and controls the operating frequency generating means 22.
- the operating frequency supply signal s8 is set to the specified operating frequency F, and the operating power supply voltage generating means 23 and the substrate bias voltage generating means 24 are controlled to specify the operating power supply voltage supply signal s9 and the substrate bias voltage supply signal slO.
- the signals sl to s6 are described only between the task A1 processing means and the respective means 12a to 12f of the task schedule processing means 12, but are not actually provided. There is also a gap between the means and the task An processing means.
- the multitask processing system 100 includes a task A1 which is a moving picture coding process and a task executed simultaneously with the task A1 processing means (task A2, task A3, ⁇ , task An (n is an integer of 2 or more)). Is registered in the task table of the task table memory 13.
- Tasks A2,,, An executed simultaneously with task A1 include video decoding, audio encoding, audio decoding, baseband signal processing, media demultiplexing, 2D graphics, and 3D graphics Processing, EncriptionZDecription processing, camera video capture processing, facial feature point extraction processing, YUVRGB conversion processing, high-quality filtering processing, etc. available.
- the number and types of tasks called at the same time vary depending on the use of the video coding function of the terminal.
- a terminal when a terminal is used as a video recording device such as a video camera instead of a real-time communication device such as a videophone, the baseband signal processing required for real-time communication of encoded and decoded data is not called, If the audio is not encoded at the same time as the encoding of, the audio encoding process will not be called.
- the task A1 processing means notifies the control time receiving means 12c of the time (frame rate) Frme of one frame of the moving picture coding in the task A1. For example, when the moving image encoding process is performed in 10 (frame Z seconds), the time Frme of one frame is 100 (milliseconds). If the moving picture decoding processing is called in step 1, the task Ai (i is an integer of 2 or more) processing means for performing the task processing of the moving picture decoding processing is performed by the task schedule processing means 12. , The time Frmd of one frame of video decoding is notified. The time Fr me and the time Frmd may or may not be equal.
- the task schedule processing means 12 determines the control time T of the processor 1 when the control time receiving means 12c receives the time Frme or the time Frmd of one frame.
- a method of determining the control time T either the time Frme or the time Frmd is used as the control time T, or an arbitrary time interval is used as the control time T. From the ease of control of the frame memory used for the moving picture coding processing and the moving picture decoding processing, the time Frmd at which it is desirable to adopt the time Frme or Frmd as the control time T is notified. In this case, it is desirable to adopt the time Frme as the control time T.
- the task schedule processing means 12 notifies the control time T of the processor 1 determined in step 3 to the task processing means 11 (task A1 processing means, ..., task An processing means) by the control time transmitting means 12b.
- the task processing unit 11 (the task A1 processing unit,, The task An processing means) predicts the amount of computation (predicted computation) Hp and the maximum value (maximum computation) Hw required for the completion of its task during the control time T.
- the task schedule processing means 12 is notified of the predicted value (predicted execution number) Cp and the maximum value (maximum execution number) Cw of the number of transfers and the priority P of its own task.
- the task schedule processing means 12 calculates, for each of the tasks Al,, and An, the predicted operation amount Hp and the maximum operation amount Hw received by the operation amount receiving means 12f, and the predicted execution number Cp received by the execution number receiving means 12e.
- the maximum number of executions Cw and the priority P are stored in the task table of the task table memory 13.
- the priority P is determined by the same method as in a normal multitask processing system.
- the priority P of the tasks A2,,, An other than the video coding is It is desirable to set priority P higher than task A1. Even if the task A1 of the moving picture coding processing cannot be performed within the control time T, the failure phenomenon can be avoided by simplifying the processing by invalid blocking processing or the like. In particular, it is preferable that the task A1 of the moving image encoding process has a lower priority than the task of the moving image decoding process. In the moving picture decoding processing, a breakdown phenomenon is more likely to occur than in the moving picture coding processing in which a failure can be avoided by invalid block processing or the like.
- Fig. 5 (a) shows an example of the saved contents of the task table after step 5 is executed.
- n represents an integer of 2 or more.
- the prediction calculation amount Hp and the prediction execution number Cp may be equal to the maximum calculation amount Hw and the maximum execution number Cw.
- the predicted calculation amount Hp and the maximum calculation amount Hw, and the number of predicted executions Cp and the maximum number of executions Cw are necessarily equal.
- the maximum calculation amount Hw and the maximum execution number Cw are notified as the prediction calculation amount Hp and the prediction execution number Cw.
- the maximum operation amount Hw and the maximum number of executions Cw are obtained by experimentally calculating the operation amount Hw and the number of executions Cw when the task is executed under the condition that the operation amount and the number of executions are maximized. These values Hw and Cw are built in the task processing means 11, and are called and used as appropriate.
- Predicted calculation amount Hp As the predicted number of executions Cp, the amount of calculation and the number of executions that were actually required to execute the task itself in the previous control time are used, or the average value of the amount of calculation and the number of executions determined experimentally in advance May be built in each task processing means, and its value may be called and used. In the case of a video encoding or decoding task, it is desirable to derive the prediction operation amount Hp using a method described later, but the method of deriving the prediction operation amount Hp is not limited to this. ,.
- the task schedule processing means 12 determines the tasks Al,,, An that should be completed within the control time T based on the predicted operation amount Hp of each task A1,,, An stored in the task table and the predicted execution count. A calculation is performed to predict the total amount of computation H required for processing and the required operating frequency Fp of the processor.
- the formulas 1 and 2 below are the possible formulas for calculating the total amount of computation H and the required operating frequency Fp, respectively.
- Hp (i) is the predicted operation amount of the task processing of the task number i
- Cp (i) is the predicted execution number of the task processing of the task number i
- S is the operation amount required to switch the task in the execution state
- t is the elapsed time from the start time of the control time T
- i is an integer from 1 to n.
- S the average value or the maximum value of the values obtained by experimentally measuring the amount of computation required when switching the task in the execution state is used.
- the total operation amount H may be derived from the following expression 3 using the maximum operation amount Hw and the maximum number of executions Cw, instead of the number 1 using the predicted operation amount Hp and the number of executions Cp.
- Equation 1 When using Equation 1, there is an advantage that the value of the total operation amount H can be prevented from becoming redundant and power consumption can be effectively reduced, and when Equation 3 is used, the total There is the advantage that the generation of the breakdown phenomenon can be suppressed by providing a margin for the calculation amount H. (Step 7) Determination of Operating Frequency F
- the operating frequency of the processor 1 is stepwise variable from the operating frequencies F (1) to F (r).
- the task schedule means 12 uses the required operating frequency Fp determined in step 6 and Equation 4 to determine an appropriate operating frequency F from the operating frequencies F (1) to F (r) at which the processor 1 can operate.
- F may have a plurality of options. It is desirable to select a value closest to Fp above Fp as the operating frequency F, but any value above Fp may be selected.
- the task schedule processing means 12 shifts the processor control program for setting the processor 1 to the operating frequency F to the execution state. That is, the processor control signal transmitting means 12g instructs the operating frequency F to the dynamic processor control means 2 (s7).
- the dynamic processor control means 2 Upon receiving the operating frequency F from the task schedule processing means 12, the dynamic processor control means 2 refers to the operating frequency table in the operating frequency table memory 21 and refers to the operating frequency generating means 22, the operating power supply voltage generating means 23 and the board.
- the bias voltage generating means 24 generates the specified operating frequency F, the operating power supply voltage Vdd and the substrate bias voltages Vbn and Vbp suitable for the operating frequency F (s8, s9, slO), and sets the processor 1 to the specified command. And the operating power supply voltage Vdd and the substrate bias voltages Vbn and Vbp.
- the task schedule processing means 12 shifts the task having the highest priority P among the tasks Al,, and An registered in the task table memory 13 to the execution state.
- the task shifted to the execution state is executed on the processor 1 by the corresponding task processing means 11.
- the task in the execution state can transmit the operating frequency instruction signal s4 to the operating frequency instruction receiving means 12d to directly indicate the operating frequency F of the processor 1.
- the task schedule processing means 12 which has received the operating frequency instruction signal s4 interrupts the task processing (Al,,, An) being executed, and executes the processor control program to change the operating frequency of the processor 1 to the specified value. Move to the execution state. After the operating frequency of the processor is changed, the task schedule processing unit 12 shifts the suspended task processing (Al,,, An) to the execution state again.
- the task in the execution state includes a processing routine for operating frequency correction in consideration of occurrence of an error between the calculated total operation amount H and the actual operation amount.
- This processing routine may be called only once during the execution of the task, or may be called multiple times at an arbitrary time interval (for example, at regular time intervals). By executing the following processing routine, the operating frequency is appropriately modified so that the processing of all tasks Al to An is completed within the control time T.
- the task processing unit in the execution state receives the remaining time Tt of the control time T in which the task schedule processing unit power is also notified using the control remaining time transmission unit 12a.
- the operating frequency Fr is calculated from the total value Ha of the remaining operation time T—t and the predicted operation amount Hp of the task waiting to be registered registered in the task table by the following equation (5).
- the processing of the corresponding task is completed by r% of the processing amount that must be completed in the control time T.
- each of Hp ′, Hw ′, Cp ′, and Cw ′ is calculated using, for example, Equation 6, Equation 7, Equation 8, and Equation 9. (Equation 6)
- Hp, Hp X (100—r)
- Hw ' Hw X (100—r)
- FIG. 10 (a) shows the saved contents of the task table before execution of step 10, and if the number of the task executed in step 9 was A2, an example of the saved contents of the task table after completion of step 10 Are shown in Figs. 5 (b) and 5 (c).
- FIG. 5B shows an example in which the maximum number of executions Cw ′ calculated in step 10 is 1 or more.
- the task A2 processing means 11 recalculates the unprocessed predicted operation amount Hp ', the maximum operation amount Hw', the predicted execution number Cp ', the maximum execution number Cw', and the priority P 'at the end of step 10, and Are replaced with the calculated Hp ', Hw', Cp ', Cw', P '.
- FIG. 5C shows an example in which the maximum number of executions Cw 'is zero. If the maximum number of executions Cw 'is 0, it is considered that the processing of task A2 has been completed, and task A2 is deleted from the task table.
- the processor 1 shifts to the idle state or the standby state and waits until the start time of the next control time T. If there is a task waiting to be executed in the task table, go to branch 2.
- step 11 If the task table has a task of moving image encoding processing (task A1 in the present embodiment), the process proceeds to step 11. If there is no moving image encoding task in the task table, the process proceeds to step 14.
- Step 11 Total calculation amount ⁇ ⁇ Determine required operating frequency Fp Perform the same processing as step 6. Since the task table memory 13 has been rewritten to the unprocessed predicted operation amount H P ', the maximum operation amount Hw', the predicted execution number Cp ', the maximum execution number Cw', and the priority P ', The required total operation amount H is the total operation amount required for processing the unprocessed task at that time. Here, it is preferable that the total operation amount H is derived by Expression 1. This is because, in the case where the moving image encoding process is included, the breakdown phenomenon can be avoided by the invalid blocking process or the like even if the total operation amount H cannot be given a margin according to Equation 3. Even if the task of the video encoding process is a task table, if there is a task that can avoid the failure phenomenon, the process proceeds to step 11.
- step 9 the highest priority task at that time is processed.
- the process of step 14 is performed.
- the task schedule processing means 12 calculates the total operation amount H and the required operating frequency Fp using Equations 1 and 2 or Equations 3 and 2.
- the total amount of calculation H may be calculated by Equation 1, but is preferably calculated by Equation 3. If the task A1 of the moving picture coding process is not included, it is not possible to avoid the breakdown phenomenon due to the invalid blocking process or the like. Therefore, it is desirable that the total computation amount H be given a margin by using Equation 3 to suppress the occurrence of the failure phenomenon. However, when the avoidance of the bankruptcy phenomenon is not taken into account, the calculation may be performed using Equation 1.
- step 9 the highest priority task at that time is shifted to the execution state.
- the control of the processor 1 executed when the task being executed in Steps 8, 13, 16 or 10 directly instructs the operating frequency will be described in detail.
- the control of the processor 1 is executed based on a processor control program.
- a processor control program an example of the operation of the multitask processing system 100 in controlling the processor 1 based on the processor control program will be described.
- the operating frequency instruction is given to dynamic processor control means 2. Outputs signal s7.
- the dynamic processor control means 2 Upon receiving the operating frequency instruction signal s7, the dynamic processor control means 2 controls the operating frequency generating means 22 and outputs the operating frequency F to the processor 1 (s8).
- the dynamic processor control means 2 controls the substrate bias voltage generation means 24 and supplies the processor 1 with the substrate bias voltages Vbn and Vbp corresponding to the operating frequency F stored in the operating frequency table memory 21. (SlO).
- the dynamic processor control means 2 controls the operating power supply voltage generating means 23 to supply the operating power supply voltage Vdd corresponding to the operating frequency F stored in the operating frequency table memory 21 to the processor 1 (s9 ).
- the order of steps 1, 4, 3, and 2 is used to increase the operating frequency, and the order of steps 1, 2, 4, and 3 is set to decrease the operating frequency. It is desirable to perform the operations in steps 2, 3, and 4 at the same time, or may be performed in an arbitrary order and in chronological order.
- the operating frequency and the substrate bias voltage may be controlled simultaneously, the operating frequency may be controlled to control the substrate bias voltage, or the substrate noise voltage may be controlled to control the operating frequency. May be.
- Step 11 (Step 14), Step 12 (Step 15), and Step 13 (Step 16) may be appropriately omitted.
- Step 11 (Step 14), Step 12 (Step 15), and Step 13 (Step 16) are executed.
- Step 11 (Step 14), Step 12 (Step 15), and Step 13 (Step 16) are executed.
- Step 11 (Step 14), Step 12 (Step 15), and Step 13 (Step 16) are executed.
- Step 11 (Step 14), Step 12 (Step 15), and Step 13 (Step 16) By omitting Step 11 (Step 14), Step 12 (Step 15), and Step 13 (Step 16) appropriately, the time that can be spent processing tasks in Step 10 can be increased. It is possible to reduce the probability of failure.
- FIG. 6 is a diagram showing a timing chart when the multitask processing system 100 is operated according to the flowchart of FIG.
- steps 1, 2, and 3 are performed in the initialization period 11.
- steps 4 and 5 are performed in the initialization period 1-2.
- Steps 6, 7, and 8 are executed in the control period 11.
- Steps 9, 10, Branch 1 and Branch 2 are executed during the operation period 1—i (i is an integer from 1 to n).
- Steps 11, 12, and 13 or steps 14, 15, and 16 are executed in the control period l—i (i is an integer of 2 or more and n or less).
- the same processing as that of the first control time T is performed according to the flowchart of FIG. Thereafter, the same processing is performed at the i-th control time (i is an integer of 3 or more).
- the multitask processing system 100 of the present invention includes failure avoidance means.
- failure avoidance means if the total value of the amount of computation required for actual processing is larger than the total amount of computation H of each task registered in the task table, one or more of the tasks registered in the task table A phenomenon in which a task cannot complete processing within the control time T is called a failure phenomenon. If the predicted operation amount Hp or the predicted number of executions Cp of each task for which processing is executed in the multitask processing system 100 of the present invention is not accurate, a failure phenomenon may occur. It is desirable to provide a failure avoiding means in the multitask processing system 100 of the present invention in order to avoid the occurrence of the failure phenomenon.
- the means for avoiding bankruptcy for example, the following means for avoiding bankruptcy 1, 2, 3 can be considered. Note that each of the following bankruptcy avoidance means executes the corresponding bankruptcy avoidance step. [0077] (Failure Avoidance Measures 1)
- the failure avoiding means 1 is provided inside the task schedule processing means 12, and in steps 6 and 11, when calculating the total amount of computation H, which must be realized with the current control time of the processor, The following Equation 10 is used instead of Equation 1.
- Equation 10 m represents a real number of 1 or more, and n represents a real number of 0 or more.
- the failure avoidance means 2 has a function of simplifying task processing. Specifically, the task processing is interrupted at predetermined intervals, and the amount of computation that can be processed in the remaining time (Tt) of the control time T and the amount of computation that must be executed in the remaining time (Tt) are Compare big and small. If the remaining amount of computation is larger than the amount of computation that can be processed, task processing is simplified. As a method of simplification, the normal task processing may be switched to an alternative processing with a small amount of calculation, or a part of the normal task processing may be omitted. As a result, the amount of calculation can be reduced as compared with the normal task processing, and the failure phenomenon can be avoided.
- Tasks that can be simplified include a moving image encoding process, a 3D graphics process, and a high-quality filtering process.
- the amount of computation can be reduced by processing unprocessed macroblocks or blocks as strong IJ-like invalid macroblocks or invalid blocks, and in the case of 3D graphics processing,
- the amount of calculation can be reduced by performing the process of omitting the rendering of the background polygon object, and in the case of the high-quality filtering processing, the amount of calculation can be reduced by performing the process of omitting the unprocessed filtering operation.
- This failure avoiding means 3 is a moving picture coding method. At the time of processing, it has a function of invalidating macroblocks and blocks. According to video coding standards (MPEG2, MPEG4, H.264, etc.), one frame is composed of a plurality of macroblocks or blocks. Moving picture coding is performed on a macroblock or block basis.
- the failure avoidance unit 3 significantly reduces the amount of computation required for encoding by forcibly performing invalid macroblocks and invalid blocks instead of the normal encoding of each macroblock or block. .
- the failure avoiding means 3 uses this property of the moving picture coding process to reduce the amount of calculation of the moving picture coding process, and reduces the processing time of the moving picture coding process which is reduced as a result.
- Each task process is completed within the control time T by assigning it to the task process.
- the video coding processing program forcibly processes unprocessed macroblocks as invalid macroblocks.
- Tr (MBiX Hs + ( ⁇ Hw (i)) + S X ( ⁇ Cw (i))) / Fpl
- T is the control time of the processor
- MBi is the number of unprocessed macroblocks when the video coding processing program enters the execution state
- Hs is one macroblock that is forcibly treated as an invalid macroblock.
- Hw is the value of the maximum operation amount of task number i in the task table
- Cw is the value of the maximum number of executions of task number i in the task table
- S is necessary to switch the task in the execution state.
- Fpl is the operating frequency of the processor
- ⁇ Hw (i) is Hw (2) + Hw (3) H hHw (n)
- ⁇ Cw (i) is ⁇ Cw (l) +
- any one of the frames to be encoded is the current frame (that is, the frame to be encoded next with reference to the time when a certain frame is encoded).
- the mark is still A frame that has not been subjected to the encoding process and will be subjected to the encoding process in the future), and one frame encoded before the current frame (a frame encoded in the past) is the previous frame.
- Ability to explain processing of current frame Similar processing is performed for any frame.
- Task 1 processing means accesses the input frame memory to obtain input image data of the current frame, and calculates a prediction operation amount Hp required for encoding processing of the current frame.
- the distortion value calculated by the sum of absolute differences as the amount of motion between the current frame and the previous frame the value calculated by the sum of absolute differences between adjacent pixels as the activity amount of each frame, the macro The number of block matchings, the number of effective blocks, the number of effective coefficients, the encoding bit rate, the number of generated bits, the amount of computation actually required for encoding the previous frame, and the calculated prediction of the previous frame Hp.
- the value of one element is large!
- the prediction calculation amount Hp is set to be relatively large as compared with the case, and when the value of one element is small, the prediction calculation amount Hp is set to be relatively small as compared with the case where the value is large.
- the prediction calculation amount Hp is relatively small compared to the inter-frame encoding, and when the current frame is an inter-frame encoding, the intra-frame encoding is performed.
- the prediction calculation amount Hp is set to be relatively large as compared with a certain case. That is, since these multiple elements are elements that affect the amount of prediction operation Hp required for the encoding process of the current frame, the task A1 processing means determines the amount of prediction operation Hp according to these elements. By performing calculation so as to increase or decrease (cycle), the predicted operation amount Hp becomes closer to the operation amount when the encoding process is actually performed.
- the input image data of the current frame calculated by using the function G and stored in the input frame memory and the decoded image stored in the local decoded frame memory are stored. Compare the magnitude of the motion of the input image with the locally decoded data of the frame. Prediction (calculation).
- the local decoded data of the previous frame is obtained by encoding the previous frame, which is formed by encoding the previous frame, in the encoding process of the previous frame in which encoding is performed before the current frame.
- prediction (calculation) of the magnitude of the motion for example, a sum of absolute differences is used.
- the following describes how to calculate the sum of absolute differences Z and the amount of prediction operation Hp.
- image data of the previous frame local decoded data decoded by the local decoder after encoding may be used, or the input image data of the input previous frame may be used as it is. ,.
- the input image data of the current frame stored in the input frame memory is stored in X (i, j) (where i is the horizontal coordinate of the image and j is the vertical coordinate) and stored in a local decoding frame memory described later.
- the motion amount between the current frame and the previous frame is the sum of the absolute differences.
- z ⁇ I x (i, j) -YG, j) Compute I for all (or sampled) pixels. Let Z be the value of this sum of absolute differences.
- Z is the sum of absolute differences
- Wa is the activity amount of the current frame
- Wb is the activity amount of the previous frame (past frame)
- W is the average quantization step size of the previous frame (the average value of the quantization step size).
- Qprev M is the number of macroblock matching in the previous frame
- B is the number of effective blocks in the previous frame
- C is the number of effective coefficients in the previous frame
- S is the amount of processing actually required to encode the previous frame
- the current frame is the sum of absolute differences
- Wa is the activity amount of the current frame
- Wb is the activity amount of the previous frame (past frame)
- W is the average quantization step size of the previous frame (the average value of the quantization step size).
- Qprev M is the number of macroblock matching in the previous frame
- B is the number of effective blocks in the previous frame
- C is the number of effective coefficients in the previous frame
- S is the amount of processing actually required to encode the previous frame
- the current frame is the amount of processing actually required
- the bit rate of the coding frame is BR
- the difference between the average value of the quantization step size of the previous frame and the average value of the quantization step size of the immediately preceding frame is A Qprev
- the actual number of bits generated in the previous frame is D
- the required computation amount of the calculated previous frame is assumed to be Hp ′
- the predicted computation amount Hp is calculated using one or more of these elements.
- Hp G (Z, Wa, Wb, Qprev, M, B, C, S, BR, ⁇ Qprev, D, Hp ') Is calculated by
- G is a function derived from one or more elements among Z, Wa, Wb, Qprev, M, B, C, S, BR, ⁇ Qprev, D, and HP ′.
- G is a function derived from one or more elements among Z, Wa, Wb, Qprev, M, B, C, S, BR, ⁇ Qprev, D, and HP ′.
- Hp j + a M + j8 B + y C + ⁇ Z + ⁇ AQprev
- the present invention is not limited to this.
- a type I of whether the current frame is an intra-frame encoding or an inter-frame encoding is used as an element used in the calculation of the prediction operation amount Hp.
- the effective block of the effective block generated in the encoding processing of the current frame is The number and the number of effective coefficients increase (decrease), and the amount of computation required for IDCT processing of the current frame (depending on the number of effective blocks that occur) and the amount of computation required for IQ processing (the number of effective coefficients that occur ), The amount of computation required for VLC processing (depending on the number of effective coefficients to be generated) is large (small). Therefore, the function G is configured to set Hp large (small) when parameters such as Z and Wa are large (small).
- the function G is configured to set Hp large (small) when parameters such as M, B, C, S, Wb, and Hp 'are large (small).
- the function G is such that when the coding bit rate BR of the current frame is large (small), the actual number of generated bits D of the previous frame is large compared to BR so that Hp is set large (small).
- Hp (If it is small, set Hp to be small and large). Furthermore, by taking into account the average quantization step size Qprev of the previous frame and the difference ⁇ Qp rev between the average value of the quantization step size of the previous frame and the average value of the quantization step size of the immediately preceding frame, The value of Hp calculated by the function G can be set to a value close to the amount of calculation required to actually encode the current frame.
- the predicted operation amount Hp of the previous frame is stored in advance in an element memory, which is a storage area for storing elements, and is read and used by the task A1 processing means when calculating the predicted operation amount Hp.
- Average value of the quantization step size of the previous frame is fed back when the coding process of the previous frame is performed.
- H p When calculating the prediction operation amount H p, only one of these elements may be used, or a plurality of elements may be used in combination.
- the task processing means calculates the amount of information (the number of bits) FB generated for one frame of the encoded data (that is, the encoded data 301 of the current frame), and calculates the predicted operation amount Hp.
- the prediction operation amount Hp is
- Hp G (FB, MVa, MVv, B, C, BR, Q, A Q, I, E, P)
- FB is the number of bits of the encoded data of the current frame or the previous frame
- MVa is the average value of the motion vector size of the current frame or the previous frame
- MVv is the size of the motion vector size of the current frame or the previous frame.
- B is the number of effective blocks in the current or previous frame
- C is the number of effective coefficients in the current or previous frame
- BR is the bit rate of the current or previous frame
- Q is the quantization of the current or previous frame
- ⁇ Q is the difference between the average values of the quantization step sizes of the current frame and the previous frame or the average value of the quantization step sizes of the previous frame and the frame immediately before the previous frame
- I is the current frame power picture A certain power A power that is a P picture Type of whether it is a B picture
- E is the operation amount actually required to decode the previous frame
- P is the required operation amount It represents the required amount of calculation for the previous frame calculated by the calculation means.
- the amount of computation required to decode the current frame depends on the number of times the IDCT, IQ, and VLD processes are executed in decoding the current frame.
- the number of executions of the IDCT processing depends on the number of effective blocks included in the current frame
- the number of executions of the IQ processing and the VLD processing depends on the number of effective coefficients included in the current frame. That is, when the number of valid blocks and the number of valid coefficients included in the current frame are large (small), the amount of calculation necessary for the decoding process is large (small). Therefore, the function G is configured to set Hp large (small) when B and C are large (small).
- the function G is configured to set Hp large (small) when MVa or MV V is large (small).
- the function G is configured to set Hp small when the current frame is an I picture.
- the function G is configured to set Hp large (small) when FB or BR is large (small).
- the value of the quantization step size is changed when controlling the bit rate, for example, when Q or ⁇ Q is large (small)
- the Hp is set small (large).
- MVa, MVv, B, C, BR, FB, and Q have close values between the current frame and the previous frame. Therefore, when these parameters are used in the above function G, the values in the current frame or the values in the previous frame may be used.
- the prediction operation amount Hp can be set to a value closer to the operation amount necessary for the actual decoding process by using the value of the current frame.
- the prediction operation amount Hp can be calculated before receiving the input code data of the current frame.
- the decryption processing can be performed simultaneously for the minutes.
- the amount of computation required for decoding the current frame is close to the amount of computation E actually required for decoding the previous frame. Value.
- P ⁇ E is obtained. Therefore, the required computation amount of the current frame is set to a value obtained by increasing or decreasing E or P according to the magnitude of parameters such as FB, MVa, MVv, B, C, BR, Q, and ⁇ Q.
- the task processing unit determines the amount of prediction operation Hp (cycle ) Is calculated so as to increase or decrease, the predicted operation amount Hp calculated by the task processing means becomes a value closer to the operation amount when the decoding process is actually performed.
- the operating frequency F and the case where the operating power supply voltage Vdd and the substrate bias voltages Vbn and Vbp suitable for the operating frequency F are controlled have been described. Only the operating power supply voltage Vdd may be controlled, or only the operating frequency F and the substrate bias voltages Vbn and Vbp may be controlled.
- the substrate bias voltage to be controlled may be only the pMOS substrate bias voltage Vbp! / Or may be only the nMOS substrate bias voltage Vbn.
- the dynamic processor control means 2 stores a table of a combination of the operating frequency and the operating power supply voltage in the operating frequency table memory 21 and operates with the operating frequency generating means 22.
- the power supply voltage generating means 23 may be provided to control only the operating frequency and the operating power supply voltage, or a table of combinations of the operating frequency and the substrate bias voltage may be held as shown in FIG.
- the operating frequency generating means 22 and the substrate bias voltage generating means 24 may be provided to control only the operating frequency and the substrate bias voltage.
- the substrate bias voltage generating means 24 is unnecessary in FIG.
- the processor does not have to be configured by the MOS having the triple-level structure.
- the operating power supply voltage generating means 23 is unnecessary.
- Step 1 Task Al, which is a task of the video encoding process, and another task A2 are registered in the task table, and the saved contents of the task table are as shown in FIG. 8 (a).
- Step 5 Upon receiving the notification of the control time T of the processor 1, the task A1 processing means and the task A2 processing means respectively perform the prediction operation amount Hp, the maximum operation amount Hw, the prediction execution number Cp, the maximum execution number Cw, and the priority.
- the task schedule processing means 12 is notified of the degree P.
- the task schedule processing unit 12 stores the predicted operation amount Hp, the maximum operation amount Hw, the predicted execution number Cp, the maximum execution number Cw, and the priority P received by the operation amount receiving unit 12f and the execution number receiving unit 12e in a task table. To save.
- the contents stored in the task table are as shown in Fig. 8 (b).
- the task schedule processing means 12 calculates the total operation amount H and the required operating frequency Fp by using Equations 1 and 2.
- the total operation amount H and the required operating frequency Fp are as follows.
- Step 7) In the processor 1, the operating frequency F is variable in three stages F (l), F (2), and F (3) (see FIG. 9).
- the task schedule processing means 12 executes the processing of the processor 1 based on Equation 4. Determine the operating frequency F as F (3).
- FIG. 9 is an operating frequency table.
- the operating frequency table holds a combination of the operating frequency F and the appropriate substrate bias voltage Vbn, Vbp, and is a combination that minimizes power consumption.
- the task schedule processing means 12 shifts the processor control program to an execution state.
- the dynamic processor control means 2 refers to the operating frequency table based on the processor control program, and sets the operating frequency of the processor 1 to F (3) and the nMOS substrate bias voltage to the operating frequency F (3). Control the pMOS substrate bias voltage to Vbn (3) to Vbp (3) corresponding to the operating frequency F (3).
- the task schedule processing means 12 shifts the task A2 processing means having the higher priority P to the execution state.
- the task A2 processing means executes the processing of task A2.
- the task A2 processing means calculates the unprocessed predicted operation amount Hp ', the maximum operation amount Hw', the predicted execution number Cp ', the maximum execution number Cw', and the priority P '. Since the maximum number of unprocessed executions Cw 'is 1 or more, the task A2 processing means rewrites the task table to the unprocessed values Hp, Hw', Cp, Cw, P, and P.
- Figure 8 (c) shows the task table after rewriting.
- the task schedule processing means 12 calculates the total operation amount H and the required operating frequency Fp by using Expressions 1 and 2.
- the total operation amount H and the required operating frequency Fp are as follows.
- the task schedule processing means 12 calculates the three-stage operating frequency using Equation 4. From the number (see Fig. 9), determine the operating frequency of processor 1 as F (2). (Step 13) The task schedule processing means 12 shifts the processor control program to the execution state. Based on the processor control program, the dynamic processor control means 2 sets the operating frequency of the processor 1 to F (2), sets the nMOS substrate bias voltage to Vbn (2) corresponding to F (2), and sets the pMOS substrate bias Control the voltage to Vbp (2) corresponding to F (2).
- Step 9) The task schedule processing means 12 shifts the task A1 processing means having a high priority P in FIG. 8C to the execution state.
- Step 10) The task A1 processing means executes the processing of task A1.
- the task A1 processing means calculates the unprocessed predicted operation amount Hp 'and the like, and rewrites each column of the task A1 in the task table as shown in FIG. 8 (d).
- (Branch 1) Task table As shown in Figure 8 (d), there are tasks A1 and A2 waiting to be executed, so the process proceeds to branch 2.
- the task schedule processing means 12 calculates the total operation amount H and the necessary operation amount Fp by using Expressions 1 and 2.
- the total operation amount H and the required operating frequency Fp are as follows.
- the task schedule processing means 12 determines the operating frequency of the processor 1 as F (2) from the three-stage operating frequency (see FIG. 9) by using Equation 4.
- the task schedule processing means 12 shifts the processor control program to the execution state. Based on the processor control program, the dynamic processor control means 2 sets the operating frequency of processor 1 to F (2), the nMOS substrate bias voltage to Vbn (2) corresponding to F (2), and the pMO Control the S substrate bias voltage to Vbp (2) corresponding to F (2).
- Step 9) The task schedule processing means 12 shifts the task A2 processing means having the higher priority P in FIG. 5D to the execution state.
- Step 10) The task A2 processing means executes the task A2.
- Branch 1 As shown in FIG. 8 (e), since there is a task A1 waiting to be executed in the task table, the process proceeds to branch 2.
- (Branch 2) Since there is a task A1 which is a moving picture coding process in the task table, the process proceeds to step 11.
- the task schedule processing means 12 calculates the total calculation amount H and the required frequency Fp by using Equations 1 and 2.
- the total operation amount H and the required operating frequency Fp are as follows.
- the operating frequency of the processor 1 is determined as F (2) from the three stages of operating frequencies F (1) to F (3) prepared in the processor 1.
- the task schedule processing means 12 shifts the processor control program to the execution state. Based on the processor control program, the dynamic processor control means 2 sets the operating frequency of the processor 1 to F (2), sets the nMOS substrate bias voltage to Vbn (2) corresponding to F (2), and sets the pMOS-based Control the plate bias voltage to Vbp (2) corresponding to F (2).
- the task schedule processing means 12 shifts the last remaining task A1 to the execution state.
- the task A1 processing means executes the processing of task A1.
- the control time T is set to 0.1 (seconds), and in the flowchart of FIG. 4, steps 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, branch 1, branch 2, step 11, 12, 13, 9, 10, branch 1, branch 2, step 11, 12, 13, 9, 10, ..., branch 1, branch 2, step 11, 12, 13, 9, 1
- (Branch 1) As shown in FIG. 10 (a), the process proceeds to branch 2 because there are tasks A1 and A2 waiting to be executed in the task table.
- (Branch 2) Proceed to step 11 because task A1 of the moving picture coding process exists.
- the task schedule processing means 12 calculates the total operation amount H and the required operating frequency Fp by using Equations 1 and 2.
- the total operation amount H and the required operating frequency Fp are as follows.
- Step 12 The task schedule processing means 12 determines the operating frequency of the processor 1 to be F (3) from the three-stage operating frequency (see FIG. 9) using Equation 4.
- the task schedule processing means 12 shifts the processor control program to an execution state.
- the dynamic processor control means 2 sets the operating frequency of processor 1 to F (3), the nMOS substrate bias voltage to Vbn (3) corresponding to F (3), and the pMOS substrate bias voltage based on the processor control program. Control to Vbp (3) corresponding to F (3). [0114] (Step 9)
- the task schedule processing means 12 shifts the task Al processing means having the higher priority P to the execution state.
- the task A1 processing means that has shifted to the execution state uses the formulas (11) and (12) to invalidate the contents of the video encoding process by forcing unprocessed macroblocks into invalid macroblocks. Calculate the time Ti for switching to the blocking process.
- the time Ti is calculated as follows using Expressions 12 and 11.
- Tr (30 X 2000 + 2000000 + 1000 X 1) / 200000000
- the task schedule processing means 12 calculates the total operation amount H and the required operating frequency Fp using Equations 3 and 2, which calculate the total operation amount using the maximum operation amount Hw and the maximum number of executions Cw.
- the total operation amount H and the required operating frequency Fp are calculated as follows.
- Step 15 The task schedule processing means 12 determines the operating frequency F as F (3) among the three stages of operating frequencies prepared in the processor 1 (see FIG. 9) by using Expression 4.
- Step 16 The task schedule processing means 12 shifts the processor control program to the execution state. Based on the processor control program 1, the dynamic processor control means 2 sets the operating frequency of the processor 1 to F (3), sets the nMOS substrate bias voltage to Vbn (3) corresponding to F (3), and sets the pMOS substrate bias Control the voltage to Vbp (3) corresponding to F (3).
- Step 9 The task schedule processing means 12 shifts the task A2 to the execution state by the task A2 processing means.
- Step 10 The task A2 processing means executes the task A2. At this time, the amount of computation realized at the operating frequency Fp2 before the end time of the control time T is larger than the maximum amount of computation required for completing the processing of the task A2. The process ends before the time arrives. Modify the task table as shown in Fig. 10 (c) and end the process.
- the present invention can further reduce the power consumption due to the subthreshold leakage current as compared with the related art in which one frame is encoded while changing the operating frequency of the processor a plurality of times.
- the substrate bias voltage and the operating frequency of the processor 1 are made variable in P stages, the required calculation amount of any one frame is Kt, and the time allocated to the processing of that frame is Tt.
- the operating frequency is set to Ft
- the substrate bias voltage when operating the processor 1 at the operating frequency Ft is set to Vb
- the value voltage is set to Vt as appropriate for the substrate bias voltage Vb.
- Case 1 The case where the processing of the required amount of computation Kt ends at time Tt is referred to as Case 1, and as shown in FIG. Ft and set the substrate bias voltage when operating the processor at the operating frequency h * Ft.
- the threshold voltage suitable for the substrate bias voltage Vbl is Vtl
- the operating frequency of the processor is changed to h * FtZ2, and the processor 1 is operated at the operating frequency h * Ft / 2.
- the substrate bias voltage at this time is Vb2
- the threshold voltage is Vt2
- the value voltage is Vt2.
- VDD operating power supply voltage
- Vgs gate-source voltage
- Vt threshold! / ⁇ value voltage
- S sub-threshold swing
- Pstl 10 " 2 : (10 _ 3 + 10" 1 X 2/3)
- the present invention can achieve lower power consumption as compared with the conventional technique in which one frame is encoded while changing the operating power supply voltage and the operating frequency of the processor a plurality of times. For example, when performing a specific operation amount Kt at a specific time Tt, control is performed at the same frequency during the specific time, and the frequency Ft is changed.
- the operating power supply voltage and operating frequency of the processor 1 are variable in P stages, the required amount of operation for any one frame is Kt, and the time allocated to the processing of that frame is Tt.
- the operating frequency is set to Ft
- the operating power supply voltage for operating the processor 1 at the operating frequency Ft is set to V DD
- the processing of the required amount of computation Kt ends at time Tt.
- Case i.e., when the operating frequency is constant
- the initial operating frequency is set as h * Ft, and when the processor operates at the operating frequency h * Ft.
- the operating power supply voltage is set to VDD1
- the operating frequency of the processor is changed to h * FtZ2 when the time T1 has elapsed
- the operating power supply voltage for operating the processor 1 at the operating frequency h * FtZ2 is set to VDD2.
- Pa a XCXFtXVDD 2 XTt
- Pb a XCX (hXFt) XVDD1 2 XT1 + a XCX (hXFt / 2) XVDD2 2 XT2
- Pb VDD 2 XTt: (hX VDD1 2 XT1 + (h / 2) XVDD2 2 XT2).
- h l.5
- Tl lZ3XTt
- Tb 2Z3XTt
- VDD2 0.75
- the operating power supply voltage and operating frequency are determined for each block, so that It is clear that the power consumption can be reduced as compared with the related art in which the operation power supply voltage and the operation frequency are changed many times during the encoding of the frame.
- the multitask processing system and the multitask processing method suitable for the case where the tasks of the video encoding process and the Z or video decoding process are included have been described as examples.
- the task processing system and the multitask processing method can be applied to a case where other tasks are processed in a time-division manner.
- FIG. 1 is a block diagram showing a configuration of a multitask processing system of the present invention.
- FIG. 2 is a diagram showing a configuration of a processor according to the present invention.
- FIG. 3 is a diagram showing contents stored in an operating frequency table memory in a table format.
- FIG. 4 is a flowchart illustrating the operation of the multitask processing system of the present invention.
- FIG. 5 is a diagram showing the contents stored in a task table memory in a table format.
- FIG. 6 is a timing chart when a multitask processing system is operated.
- FIG. 7 is a timing chart illustrating an example of a multitask processing system.
- FIG. 8 is a diagram showing an example of saved contents of a task table in a table format.
- FIG. 9 is a diagram showing an example of stored contents of an operating frequency table in a table format.
- FIG. 10 A diagram showing an example of saved contents of a task table in a table format.
- FIG. 11 is an explanatory diagram explaining that subthreshold leakage current can be reduced by keeping the operating frequency constant.
- FIG. 12 is an explanatory diagram explaining that low power consumption can be achieved by keeping the operating power supply voltage and the operating frequency constant.
- FIG. 13 is a diagram showing a conventional technique for reducing the power consumption of the moving picture coding processing system.
- FIG. 14 is a conceptual diagram showing a state in which the amount of calculation for moving image encoding or decoding is different for each frame.
- FIG. 15 is a diagram showing an example of a relationship between a threshold voltage and a substrate bias voltage in an n-channel MOS transistor and a p-channel MOS transistor.
- FIG. 16 is a diagram showing an example of a relationship between an operating frequency and a threshold voltage in a processor.
- FIG. 17 is a diagram showing an example of a relationship between a sub-threshold leak current, a gate voltage, and a threshold voltage
- FIG. 18 is a diagram showing the relationship between current and operating power supply voltage when the operating frequency of the processor is fixed.
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Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009159478A (ja) * | 2007-12-27 | 2009-07-16 | Toshiba Corp | 動画像処理回路 |
CN101667110A (zh) * | 2008-09-04 | 2010-03-10 | 三星Techwin株式会社 | 图像处理设备 |
CN103123579A (zh) * | 2011-09-08 | 2013-05-29 | 英飞凌科技股份有限公司 | 具有附加微控制器的备用工作 |
CN103201702A (zh) * | 2010-11-09 | 2013-07-10 | 国际商业机器公司 | 通过改变计算工作负载进行的随时间变化的能量源的能量捕捉 |
JP2014096158A (ja) * | 2010-01-11 | 2014-05-22 | Qualcomm Inc | 中央処理ユニットをリアルタイムで監視するシステムおよび方法 |
WO2022244331A1 (ja) * | 2021-05-20 | 2022-11-24 | 日立Astemo株式会社 | 演算装置、認識装置および制御装置 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003324735A (ja) * | 2002-02-26 | 2003-11-14 | Kanazawa Univ Tlo Inc | 動画像符号化又は復号化処理システム及び動画像符号化又は復号化処理プログラム |
-
2005
- 2005-03-30 WO PCT/JP2005/006192 patent/WO2005096634A1/ja active Application Filing
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003324735A (ja) * | 2002-02-26 | 2003-11-14 | Kanazawa Univ Tlo Inc | 動画像符号化又は復号化処理システム及び動画像符号化又は復号化処理プログラム |
Non-Patent Citations (7)
Title |
---|
KAO J.T. ET AL: "A 175-mV Multiply-Accumulate Unit Using an Adaptive Supply Voltage and Body Bias Architecture.", IEEE., vol. 37, no. 11, November 2002 (2002-11-01), pages 1545 - 1554, XP001222652 * |
KAWAGUCHI H. ET AL: "An LSI for Vdd-Hopping and MPEG4 System Based on the Chip.", IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS., May 2001 (2001-05-01), pages 918 - 921, XP010542007 * |
KAWAKAMI K. ET AL: "Dogazo Fugoka Shori ni okeru Denryoku Saishoka no tameno Feedforward-gata Dosa Shuhasu/Den'atsu Kyocho Seogyo Algorithm. (A Low Power Video Compression Algorithm using Dynamic Voltage Control based on Feed Forward Analysis)", THE INSTITUTE OF ELECTRONICS, INFORMATION AND COMMUNICATION ENGINEERS ICD2002-57, August 2002 (2002-08-01), pages 67 - 72, XP002991853 * |
KAWAKAMI K. ET AL: "Feedforward-gata doteki Den'atsu Seigyo ni yoru MPEG4 Tei Shohi denryokuka Algorithm. (A Low Power/High Quality Video Compression Algorithm using Dynamic Voltage based on Feed-Forward Analysis.", THE INSTITUTE OF ELECTRONICS, INFORMATION AND COMMUNICATION ENGINEERS. ICD 2003-30, May 2003 (2003-05-01), pages 25 - 30, XP002991854 * |
LEE S. ET AL: "Run-time Voltage Hopping for Low-power Real-time Systems.", PROC DESIGN AUTOMATION CONFERENCE., June 2000 (2000-06-01), pages 806 - 809, XP002991852 * |
MORITA Y. ET AL: "D-23 Feedforward Seigyo o Mochiita MPEG4 Tei Shohi Denryokuka Algorithm (2)-2 Denkai Dosa Den'atsu/Shuhasu Seigyoteki Yoji no Shohi Denryoku Sakugen Koka no Mitsumori.", INSTITUTE OF ELECTRICAL AND INFORMATION ENGINEERS., 22 September 2003 (2003-09-22), pages 192, XP002991855 * |
NOSE K. ET AL: "VTH-Hopping Scheme to Reduce Subthreshold Leakage for Low-Power Processors.", IEEE JOURNAL OF SOLID STATE CIRCUITS., vol. 37, no. 3, March 2002 (2002-03-01), pages 413 - 419, XP001222672 * |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009159478A (ja) * | 2007-12-27 | 2009-07-16 | Toshiba Corp | 動画像処理回路 |
CN101667110A (zh) * | 2008-09-04 | 2010-03-10 | 三星Techwin株式会社 | 图像处理设备 |
JP2010063102A (ja) * | 2008-09-04 | 2010-03-18 | Samsung Techwin Co Ltd | 映像処理装置 |
US8717373B2 (en) | 2008-09-04 | 2014-05-06 | Samsung Techwin Co., Ltd. | Image processing apparatus |
JP2014096158A (ja) * | 2010-01-11 | 2014-05-22 | Qualcomm Inc | 中央処理ユニットをリアルタイムで監視するシステムおよび方法 |
CN103201702A (zh) * | 2010-11-09 | 2013-07-10 | 国际商业机器公司 | 通过改变计算工作负载进行的随时间变化的能量源的能量捕捉 |
JP2014502389A (ja) * | 2010-11-09 | 2014-01-30 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 計算作業負荷を変更することによる時間変動エネルギー源のエネルギー捕獲 |
CN103201702B (zh) * | 2010-11-09 | 2016-04-20 | 国际商业机器公司 | 对计算工作负载进行管理的方法和系统 |
CN103123579A (zh) * | 2011-09-08 | 2013-05-29 | 英飞凌科技股份有限公司 | 具有附加微控制器的备用工作 |
WO2022244331A1 (ja) * | 2021-05-20 | 2022-11-24 | 日立Astemo株式会社 | 演算装置、認識装置および制御装置 |
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