Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
  • H03F3/04—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only
  • H03F3/08—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only controlled by light
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
  • H03F1/56—Modifications of input or output impedances, not otherwise provided for
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
  • H03F3/45—Differential amplifiers
  • H03F3/45071—Differential amplifiers with semiconductor devices only
  • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
  • H03F3/4508—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using bipolar transistors as the active amplifying circuit
  • H03F3/45085—Long tailed pairs
  • H03F3/45089—Non-folded cascode stages
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
  • H03F3/45—Differential amplifiers
  • H03F3/45071—Differential amplifiers with semiconductor devices only
  • H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
  • H03F3/45484—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with bipolar transistors as the active amplifying circuit
  • H03F3/45488—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with bipolar transistors as the active amplifying circuit by using feedback means
  • H03F3/45515—Measuring at the active amplifying circuit of the differential amplifier
  • H03F3/4552—Controlling the input circuit of the differential amplifier
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
  • H03F3/45—Differential amplifiers
  • H03F3/45071—Differential amplifiers with semiconductor devices only
  • H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
  • H03F3/45484—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with bipolar transistors as the active amplifying circuit
  • H03F3/45596—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with bipolar transistors as the active amplifying circuit by offset reduction
  • H03F3/45618—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with bipolar transistors as the active amplifying circuit by offset reduction by using balancing means
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F2200/00—Indexing scheme relating to amplifiers
  • H03F2200/261—Amplifier which being suitable for instrumentation applications
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F2200/00—Indexing scheme relating to amplifiers
  • H03F2200/453—Controlling being realised by adding a replica circuit or by using one among multiple identical circuits as a replica circuit
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
  • H03F2203/45—Indexing scheme relating to differential amplifiers
  • H03F2203/45538—Indexing scheme relating to differential amplifiers the IC comprising balancing means, e.g. trimming means
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
  • H03F2203/45—Indexing scheme relating to differential amplifiers
  • H03F2203/45541—Indexing scheme relating to differential amplifiers the IC comprising dynamic biasing means, i.e. controlled by the input signal
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
  • H03F2203/45—Indexing scheme relating to differential amplifiers
  • H03F2203/45576—Indexing scheme relating to differential amplifiers the IC comprising input impedance adapting or controlling means

Definitions

• This invention relates to the field of operational amplifiers (op amps) , comparators, instrumentation amplifiers, and the like, and particularly to circuits designed to reduce the input bias currents in such circuits.
• the input stage of a bipolar circuit such as an op amp, comparator, or an instrumentation amplifier has an input bias current I B - i.e., the amount of current which flows into or out of the circuit's input terminals - of zero. This is because the resolution of the input stage increases with a decreasing I B .
• I B input bias current
• the output current I D of a photodiode is to be amplified by an op amp configured as an inverting amplifier, with a feedback resistance R.
• the op amp's output voltage V out will be given by (I D -I B )/R; i.e., the amount of photodiode current converted into an output voltage by the op amp is reduced by the magnitude of the op amp's input bias current .
• the input bias current I B of a bipolar input stage is non-zero because the stage's inputs are the bases of two bipolar transistors, arranged as a differential pair.
• One approach to reducing I B is to use input transistors with very high betas, known as "superbeta" transistors.
• bipolar input transistors Ql and Q2 form a differential input pair.
• the common emitters of Ql and Q2 are connected to a bias current source 10, and their collectors are coupled to respective biasing transistors Q3 and Q4.
• a ⁇ tracking" transistor Q5 is connected in series between Ql and Q3, and another tracking transistor Q6 is connected in series between Q2 and Q4, such that the collector-emitter circuits of Q5 and Q6 conduct the collector currents of Ql and Q2, respectively.
• the present invention comprises a bipolar differential input stage, with the input pair's bases connected to respective input terminals and their emitters connected together at a common emitter node; a first current source connected to the common emitter node provides a first bias current to the input pair, such that the pair transistors conduct respective output currents in response to a differential input signal applied to the input terminals.
• the invention also includes a bipolar tracking transistor, and a second current source which provides a second bias current to the tracking transistor.
• the input stage is arranged such that the collector currents in the input pair and tracking transistor, and the collector-emitter voltages of the input pair and tracking transistor, are substantially equal. This causes the tracking transistor's base current to track the base currents of the input pair.
• the copy circuit provides the tracking transistor base current required to achieve the substantially equal collector current in the tracking transistor, and replicates the base current to provide first and second bias current cancellation currents to the bases of the input pair. Since the tracking transistor base current tracks the base current of the input pair, the bias current cancellation currents will be substantially equal to the input bias currents of the input pair - and as such will reduce the input stages' input bias currents.
• the base current copy circuit is preferably implemented with a lateral PNP transistor, having respective collectors connected to the bases of the tracking transistor and the input transistors, and biased such that it provides currents to the input pair bases which are approximately equal to the tracking transistor's base current. When so arranged, the currents provided to the input pair bases will serve as cancellation currents which substantially reduce the input stages' input bias currents .
• FIG. 1 is a schematic diagram of a known bipolar input stage and input bias current cancellation scheme.
• FIG. 2 is a block/schematic diagram illustrating the basic principles of a bipolar differential input stage which includes an input bias current cancellation circuit per the present invention.
• FIG. 3 is a schematic of a preferred embodiment of the present invention.
• FIG. 4 is a more detailed schematic of a preferred embodiment of per the present invention.
• a bipolar differential input pair comprises first and second transistors Ql and Q2 , having their emitters connected to a common emitter node 20 and their bases connected to respective input terminals IN + and IN- .
• a first current source 22 is connected to common emitter node 20 and provides bias current to Ql and Q2 such that they conduct respective output currents in response to a differential input signal applied to IN+ and IN- .
• the invention includes circuitry for reducing the input bias currents of Ql and Q2. This circuitry includes a tracking transistor Q3 and a base current copy circuit 2 .
• a current source 26 provides bias current to Q3.
• the first and second current sources are arranged such that second current source 26 provides a bias current I, and first current source 22 provides a bias current 2*1. Then, when IN+ and IN- are equal, Ql and Q2 each conduct currents I-I B , where I B is the base current of Ql and Q2. Currents I B are the input bias currents which the present invention is intended to reduce or cancel . Circuitry (not shown) provides current to the collector of tracking transistor Q3 such that Q3 also conducts a current I-I B , where I B is the base current of Q3. The input stage is also arranged to ensure that the collector-emitter voltages of Ql, Q2 and Q3 are substantially equal.
• Q3's base current With Q1-Q3 having equal collector currents and equal collector-emitter voltages (when IN+ * IN-), Q3's base current will be substantially equal to that of Ql and Q2.
• Q3 ' s base current is defined by its collector current and its collector-emitter voltage.
• Base current copy circuit 24 is arranged to provide the base current I trk to tracking transistor Q3 required to make its collector current equal to those in Ql and Q2.
• Copy circuit 24 replicates I tr k and provides the copies as first and second bias current cancellation currents Ic n cii. Ic n ci 2 to the bases of Ql and Q2, respectively, such that Icncii *» Icci 2 * I trk * I B .
• the input stages' input bias currents are substantially reduced.
• Making the collector currents and collector-emitter voltages of Q1-Q3 substantially equal reduces cancellation current inaccuracies that might arise due to the Early effect, and ensures that the base current of Q3 will equal those of Ql and Q2 with a high degree of precision. Under these conditions, when the base current of Q3 is copied to the bases of Ql and Q2, the input pairs' input bias currents can be reduced down to the picoampere level.
• Q1-Q3 are preferably superbeta transistors, which inherently reduce the base current needed for a particular collector current, and thus serve to further reduce the input pairs' input bias currents.
• Q1-Q3 should have matching characteristics - particularly with respect to emitter size, temperature coefficient, and beta. Note that, when the input pair collector currents are unequal, their base currents are also unequal. As the present bias current cancellation scheme provides equal cancellation currents to both input devices, there will therefore be some inaccuracy in the cancellation currents when the input pair collector currents are unequal .
• a preferred embodiment of the present invention is shown in FIG. 3. As before, Ql and Q2 form a bipolar differential input pair, connected to input terminals IN+ and IN-, respectively.
• a current source 32 is connected to node 30 to provide bias current to Ql and Q2.
• the collectors of Ql and Q2 are connected to the emitters of respective cascode transistors Q4 and Q5, with the bases of Q4 and Q5 connected together at a node 34; the collectors of Q4 and Q5 are coupled to a supply voltage VCC (connection to VCC not shown) .
• cascode transistors Q4 and Q5 conduct the collector currents of Ql and Q2, respectively.
• tracking transistor Q3 has its emitter connected to common emitter node 30 such that it is biased by current source 32.
• Q3's collector is connected to the collector-emitter circuit of a cascode transistor Q6 having its base connected to node 32, such that Q6 conducts Q3's collector current.
• Current source 32 is arranged to provide a bias current given by 3*1 to common emitter node 30, and a current source 36 is arranged to provide a current I to the collector of cascode transistor Q6.
• Base current copy circuit 24 is implemented with a lateral PNP transistor Q7, having a first collector connected to the base of tracking transistor Q3, a second collector connected to the base of Ql, and a third collector connected to the base of Q2.
• Q7 must be biased to operate in its linear region - i.e., with its emitter-base junction forward-biased and its base-collector junction reverse-biased - so that the current provided to Q3 via Q7's first collector is replicated on its second and third collectors .
• One way of biasing Q7 as specified above is shown in FIG. 3.
• the base of Q7 is connected to a node 38.
• a PNP transistor Q8 has its collector-emitter circuit connected between node 38 and a circuit common point 40, typically the negative supply (VEE) .
• a current source 42 and a diode- connected NPN transistor Q9 are connected in series between supply voltage VCC and node 38.
• the emitter of Q7 is connected to the collector of Q6.
• This arrangement ensures that the voltages at Q7's base and emitter are such that its emitter-base junction is forward-biased, and that the voltages at Q7's base and collector are such that its collector-base junction is reverse-biased. This remains true even if the input common mode voltage changes, since node 38 varies with input common mode voltage, and the collector of Q6 is a floating, high impedance node.
• the presence of diode-connected Q9 also ensures that node 34 is one base-emitter voltage above the input common mode voltage, to keep the base-collector voltages of Q1-Q3 equal to zero. This protects superbeta devices, which tend to have low base-collector breakdown voltages.
• the arrangement of current sources 32 and 36 cause Ql, Q2, and Q3 to have substantially equal collector currents I. Because the bases of cascode transistors Q4, Q5 and Q6 are all connected together at node 34, the collectors of Q1-Q3 will be at equal voltages - one base-emitter junction voltage below node 34. The emitters of Q1-Q3 are connected together at common emitter node 30. As a result, the collector-emitter voltages of Ql, Q2 and Q3 will be substantially equal.
• collector currents and collector- emitter voltages of Q1-Q3 substantially equal reduces inaccuracies that might arise due to the Early effect, and ensures that the base current of Q3 will equal those of Ql and Q2 with a high degree of precision.
• Lateral PNP transistor Q7 is connected to provide base current (It rk ) to tracking transistor Q3 via its first collector.
• Q7 replicates current I tr k to the bases of Ql and Q2 (as cancellation currents Icncii and I C nci2) "via its second and third collectors, respectively.
• current source 32 is implemented with a NPN transistor Q10 with an emitter resistor Rl; Rl may be implemented with a single resistor or 3 resistors (Rla, Rib, Rlc) , preferably of equal resistance, connected in parallel.
• Current source 36 is preferably implemented with a transistor Qll having its emitter coupled to circuit common point 40 via a resistor R2 ; the bases of Qll and Q10 are connected together and to a common bias voltage V B .
• a diode-connected NP transistor Q12 is connected between the collector of Qll and a current mirror made from a diode-connected PNP transistor Q13 and a PNP transistor Q14.
• current source 32 provides a bias current given by 3*1 and Qll conducts a current I.
• Qll's current I is mirrored by the Q13/Q14 current mirror to the collector of Q6 , thereby ensuring that, when IN+ « IN-, tracking transistor Q3 has a collector current I equal to the collector currents of Ql and Q2.
• Current source 42 is here replaced with a resistor R3 connected between Q9 and a node 50, and Q13 and Q14 are connected to node 50 via respective resistors R4 and R5.
• Node 50 is connected to supply voltage VCC via a PNP transistor Q15.
• Q15 is biased with a bias voltage V B2 such that it acts as a current source which outputs a current 3*1.
• Q15 also serves to decouple the input bias current cancellation circuit from VCC. Because of Q15, the voltage at node 50 can vary with the input common mode voltage. As such, the biasing of the cancellation circuit's devices does not change with a change of the input common mode voltage. If node 50 was connected directly to VCC, the cancellation scheme would be input common mode voltage dependant . When arranged as shown in FIG.
• a voltage loop is formed between the collector of Q10 and the collector of Qll, via the base-emitter junctions of Q8 and Q9, R3, R4, and the base-emitter junctions of Q13 and Q12.
• This loop makes the collector voltages of Q10 and Qll approximately equal, and enables them to vary equally with a varying input common mode voltage. For example, if the input common mode voltage decreases, the voltage loop ensures that the collector-emitter voltages across Q10 and Qll are reduced by equal amounts, as are their collector currents. Therefore, the 3:1 ratio between the collector currents is kept constant for a changing input common mode voltage, which prevents cancellation current errors from being introduced due to the Early effect when the input common mode voltage changes.
• Mirror transistor Q13 preferably includes a resistor R6 connected between its collector and base.
• the present input stage and input bias current cancellation circuit can be employed in numerous applications which use a bipolar differential input stage. Examples of such applications include op amps, comparators, and instrumentation amplifiers. When arranged as described herein (including using superbeta transistors for Q1-Q3) , a significant reduction in input bias current can be achieved; i.e., a typical base current of ⁇ 15 ⁇ A is reduced to ⁇ 0.3 ⁇ A/ ⁇ , where ⁇ is the beta value of the input pair and tracking transistor.
• the input stage's input bias current will be reduced to about lOOpA.
• This improvement is achieved without the need to perform a final resistor trim step.
• Additional input bias current reduction can be achieved with the addition of a trim step that trims the resistance values of resistors R4 and/or R5 in FIG. 4, which adjusts the magnitude of the current through tracking transistor Q3.
• Q3 ' s current can be increased or decreased, depending on whether R4 or R5 is trimmed. While particular embodiments of the invention have been shown and described, numerous variations and alternate embodiments will occur to those skilled in the art. Accordingly, it is intended that the invention be limited only in terms of the appended claims .

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• 2004
  • 2004-02-27 US US10/789,738 patent/US6965267B2/en not_active Expired - Lifetime
  • 2004-12-14 JP JP2007500752A patent/JP4560541B2/ja not_active Expired - Fee Related
  • 2004-12-14 EP EP04813977A patent/EP1719246B1/en not_active Expired - Lifetime
  • 2004-12-14 DE DE602004027956T patent/DE602004027956D1/de not_active Expired - Lifetime
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