WO2005091339A2 - Structure semi-conductrice - Google Patents

Structure semi-conductrice Download PDF

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Publication number
WO2005091339A2
WO2005091339A2 PCT/US2005/008038 US2005008038W WO2005091339A2 WO 2005091339 A2 WO2005091339 A2 WO 2005091339A2 US 2005008038 W US2005008038 W US 2005008038W WO 2005091339 A2 WO2005091339 A2 WO 2005091339A2
Authority
WO
WIPO (PCT)
Prior art keywords
region
semiconductor material
recess
transistor
pillar
Prior art date
Application number
PCT/US2005/008038
Other languages
English (en)
Other versions
WO2005091339A3 (fr
Inventor
Manish Sharma
Original Assignee
Hewlett-Packard Development Company, L.P.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett-Packard Development Company, L.P. filed Critical Hewlett-Packard Development Company, L.P.
Publication of WO2005091339A2 publication Critical patent/WO2005091339A2/fr
Publication of WO2005091339A3 publication Critical patent/WO2005091339A3/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only

Definitions

  • the present invention relates to a semiconductor structure and a method of fabricating a semiconductor structure.
  • the invention relates to a semiconductor structure which has semiconductor features having a high aspect ratio defined as the depth of the feature divided by the width of the feature.
  • Memory devices used for storing data in computer systems typically comprise an array of memory cells. These memory cells are linked by a grid of conductors running in the longitudinal direction and the transverse direction. These memory cells typically have integrated semiconductor elements such as diodes or transistors. For example, magneto-resistive random access memory (MRAM) devices may have a diode integrated into each MRAM cell for the prevention of sneak currents.
  • MRAM magneto-resistive random access memory
  • a dynamic random access memory (DRAM) typically includes an access field-effect transistor (FET) and a storage capacitor. The access FET allows the transfer of data charges to and from the storage capacitor during reading and writing operations.
  • a semiconductor array is typically formed by processes of masking and etching.
  • lithography a mask is created on the semiconductor substrate, whereupon the unmasked regions can be etched away.
  • the minimum feature size that can be created is therefore determined by the lithographic process. The minimum feature size will therefore determine the array dimensions and therefore the data storage capacity of a memory device.
  • a known fabrication method for DRAM involves building up layers of doped semiconductor material to form the p type and n type layers of a transistor and then subsequently forming trenches in the layered structured by etching. Pillars of layers of npn material thereby form transistors in a grid array. During the various masking and etching steps, oxidation of the base of the trenches occurs. In order to protect the side walls of the trenches, silicon nitride is deposited by chemical vapour deposition to be subsequently removed. The purpose of the nitride layers on the side walls of the trenches is to protect the adjacent layers of the transistor pillars during the oxidation process.
  • a method of fabricating a semiconductor structure comprises etching the semiconductor material to form at least one recess having side walls. The side walls of the semiconductor material are then reacted to form an oxide of the semiconductor material. This oxide is selectively removed from the side walls of the at least one recess.
  • FIGS 1 to 4 illustrate in schematic cross-section, the fabrication of transistors in accordance with one embodiment of the present invention
  • Figure 5 is a schematic perspective view of an array of diodes constructed in accordance with an embodiment of the present invention.
  • Figure 6 is a schematic side view of PIN diodes formed in accordance with the present invention.
  • FIG. 7 to 15 illustrate in schematic cross-section, the fabrication of a transistor in accordance with another embodiment of the present invention. Description of Preferred Embodiments
  • Figure 1 illustrates a substrate 100 with layers of p type and n type material 102, 104 and 106 formed on the substrate 100.
  • the substrate 100 may comprise a silicon crystal wafer with the layers of p type and n type material built up by conventional epitaxial methods.
  • the layers of p type and n type material may be constructed of amorphous or polycrystalline silicon.
  • the process may involve the low temperature deposition of the appropriately doped p type and n type of silicon, either in amorphous or polycrystalline phase.
  • PECVD plasma-enhanced chemical vapour deposition
  • Other techniques include pulsed laser deposition (PLD) which involves irradiating the amorphous or polycrystalline silicon following the introduction of dopants. This results in the crystallisation of the silicon and simultaneously in the activation of the dopants via ultra fast melting and solidification.
  • PLD pulsed laser deposition
  • the silicon layers can therefore be deposited on low temperature substrates such as ceramics, dielectrics, glass or polymers. Furthermore, as the process preserves the substrate, the silicon layers can be constructed over underlayers and structures such as silicon integrated circuits. It will therefore be appreciated that through the use of lower temperature deposition of amorphous or polycrystalline silicon, multiple layers of semiconductor devices may be built up one atop the other. If the semiconductor devices in the layers are arranged in arrays then multiple arrays of the semiconductor devices may be built one atop the other. The silicon layers 102, 104 and 106 may be built over a planarized dielectric layer or a quartz layer.
  • Figure 2 illustrates the formation of recesses in the form of trenches 200 through the layers 102, 104 and 106 of semiconductor material. If these trenches 200 are arranged in orthogonal grids then the remaining material of the layers 102, 104 and 106 will form pillars 202 of semiconductor material.
  • the patterning of the deposited silicon material layers may initially form longitudinal and transverse trenches simultaneously. Alternatively, it is possible that parallel lines of longitudinal trenches may be initially formed, followed by the subsequent formation of parallel lines of transversely extending trenches. The latter case is particularly desirable where the etched depth for the longitudinal trenches is required to be different than the etched depth for the transverse trenches. Alternatively, the patterning may simply create parallel lines of trenches creating one or more ridges of semiconductor material.
  • the formation of the trenches may initially involve a lithographic process followed by deep silicon anisotropic etching techniques. This has been achieved at dimensions in the range of 50 nm to 150 nm for the width of the remaining material between the trenches. Widths down to 10 nm may also be achieved.
  • the outside of the silicon pillars 202 is then subject to thermal oxidation to form native oxide regions 302.
  • the side walls of the pillars 202 may be selectively oxidized by initially providing a protective nitride layer on the tops of the pillars 202 and the bases of the trenches 200.
  • the tops of the pillars and the bases of the trenches may be oxidised also.
  • the oxide on the tops of the pillars can be removed in a later planarizing step.
  • thermal oxidation involves using a standard semi-conductor processing furnace at a temperature of approximately 900 to 1100 °.
  • the silicon pillars 202 may be exposed to an oxygen or steam atmosphere.
  • the oxidized regions 302 are then removed from the side walls of the pillars 202 to form even thinner pillars.
  • This enables pillar widths in the range of 10 - 100 nm wide with pillar heights in the range of 200 - 400 nm.
  • This provides high aspect ratios for the resulting transistor pillars 202.
  • the aspect ratios are greater than 10:1.
  • the aspect ratios are in the range of 10:1 to 50:1.
  • Another preferred range is 10:1 to 20:1.
  • a pnp type transistor 400 as shown in Figure 4.
  • Appropriate connections may be made to the regions of the connector in subsequently processing steps.
  • the transistors 400 may be constructed over the top of a conductor line formed within substrate 100.
  • gate connections may be formed within the trenches between the transistors 400. Additional space between the trenches may be filled with isolation materials such as dielectric material.
  • conductor lines may be formed above the transistors 400.
  • the conductor lines may be formed by a copper damascene process. The conductor lines may be arranged orthogonal to each other so as to form a cross-linked array of transistors.
  • transistors 400 may form part of other devices including memory devices, including MRAM, DRAM or any other type of cross-linked memory array.
  • Figures 1 to 4 illustrate the construction of a pnp type transistor. A similar process may be used to form a npn type transistor. Furthermore, diode pillars may also be constructed as per the array of diode pillars 500 illustrated in Figure 5. Likewise, Figure 6 illustrates a formation of a positive-intrinsic-negative diode. This is a photodiode with a large neutrally doped intrinsic region (i) 602 sandwiched between p doped and n doped semiconductor regions 604, 606 on substrate 600. Nevertheless, the principles of construction remain similar to those explained in conjunction with Figures 1 to 4.
  • Figures 7 to 15 illustrate the fabrication of a field effect transistor according to a second preferred embodiment as shown in Figure 15.
  • a substrate in the form of a silicon wafer 700 is doped with p type impurities.
  • n type impurities are introduced into a region 702 spaced from the surface 704 of the substrate 700.
  • the n type region will become the source of the transistor.
  • a region above the n type impurity region 702 will form the channel of the transistor.
  • a further region of n type impurities may also be introduced closer to the surface 704 of the substrate 700 to become the drain of the transistor.
  • the drain region is separately deposited as will be explained in conjunction with Figure 15.
  • the p type substrate 700 may comprise a single crystal substrate.
  • the p type region 700 may comprise amorphous silicon deposited on an insulator (not shown).
  • the silicon material has been patterned to define a pillar 802.
  • the silicon substrate 700 is etched down to the n type region 702 so that the silicon pillar 802 of p type material is disposed on the n type region 702.
  • the patterning is conducted by lithography in conjunction with deep anisotropic etching.
  • the substrate 700 and pillar 802 are subjected to thermal oxidation. This is shown to produce oxide regions 902 on the sides of the pillar 802. In reality, oxides form on all surfaces including the top of the pillar 802. The oxide material on the top of the pillar 802 can be removed in a later planarizing step.
  • the oxide regions 902 are removed by reactive ion etching (RIE). This results in a slimmed down pillar 1000 as shown in Figure 10, thus leading to a greater aspect ratio for the pillar 1000.
  • RIE reactive ion etching
  • the pillar 1000 may be subjected to further thermal oxidization to produce gate oxide regions 1102 on the sides of the pillar 1000.
  • the gate oxide regions 1102 could be formed by leaving some of the oxide regions 902 behind to constitute the gate oxide.
  • the steps shown in Figures 10 and 11 are preferred.
  • a dielectric material 1204 is deposited on the substrate region 700. While this is shown as a separate material, the dielectric region 1204 could simply constitute silicon dioxide formed as a result of the thermal oxidation described in conjunction with Figures 9 and 11.
  • a via is etched into the dielectric region 1204. Metal is deposited to form a suicide contact such as Tungsten suicide or cobolt suicide. This via contact 1302 makes contact with the n type region 702 as shown.
  • conductor lines including a source line 1402 and a gate line 1404 are then formed above the dielectric material 1204. These may be formed of any suitable metal such as platinum or copper. Copper line conductors may be made by a copper damascene process.
  • the space above the conductors is then covered by a second dielectric material 1502.
  • This material is then planarized to the top of pillar 1000 and in so doing, the top oxide layers of the pillar 1000 are removed, n type material may be deposited on top of the pillar 1000 to form the drain 1504 for the transistor.
  • This n type material may be deposited as a layer which is then etched back to a region within the top of the pillar 1000.
  • the second dielectric region 1502 should constitute silicon dioxide.
  • a drain line 1506 may then be formed in contact with the drain 1504 as appropriate. Further dielectric material (not shown) may be added to the top and planarized level where desired.
  • the p type region of the pillar 1000 forms the channel of a vertical MOSFET transistor.
  • the length of the channel is equal to the height of the pillar 1000 which is determined by the extent of the selective vertical etching which takes place in Figure 8.
  • the separate formation of the source 702 and drain 1504 means that the channel length can be made the full length of the extent which can be achieved by the anisotropic etching.
  • long channel lengths can be created which extend vertically and thus do not take up valuable silicon real estate.
  • There are certain operational benefits which can be achieved by a long channel length For example, with a long narrow channel, a smaller bias will be required to reach the pinch-off voltage.
  • a variation in composition can be made along the channel to give rise high frequency effects as will be understood by those skilled in the art.
  • Such high frequency effects may include carrier mobility modulations and concentration variations along the channel.
  • a semiconductor structure which comprises semiconductor material having recesses formed therein.
  • the aspect ratio is defined as the depth of the one or more recesses divided by the width of the semiconductor material between the recesses. This aspect ratio is greater than 10:1.
  • a method of forming a transistor having a source, drain and channel comprising: forming in semiconductor material, a first region of a first conductivity type spaced from the surface of the semiconductor material and a second region of a second conductivity type between the surface of the material and the first region; forming at least one recess in the semiconductor material to form a pillar between the sides of the at least one recess; wherein the first region is disposed below the pillar and defines one of the source and the drain of the transistor and the second region defines the channel of the transistor.

Abstract

L'invention concerne une structure semi-conductrice, produite par gravure d'un matériau semi-conducteur (100), afin de former un ou plusieurs évidements (200) présentant des parois latérales. Le matériau semi-conducteur est ensuite mis à réagir sur les parois latérales, afin de former un oxyde (302) du matériau semi-conducteur. Ledit oxyde peut ensuite être éliminé de manière sélective des parois latérales du(des) évidement(s), ce qui permet d'obtenir une structure semi-conductrice (400) à grand allongement, qui est défini comme correspondant à la profondeur de l'évidement (des évidements), divisée par la largeur du matériau semi-conducteur entre lesdits évidements.
PCT/US2005/008038 2004-03-19 2005-03-14 Structure semi-conductrice WO2005091339A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/805,471 US20050208769A1 (en) 2004-03-19 2004-03-19 Semiconductor structure
US10/805,471 2004-03-19

Publications (2)

Publication Number Publication Date
WO2005091339A2 true WO2005091339A2 (fr) 2005-09-29
WO2005091339A3 WO2005091339A3 (fr) 2005-11-17

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2005/008038 WO2005091339A2 (fr) 2004-03-19 2005-03-14 Structure semi-conductrice

Country Status (3)

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US (1) US20050208769A1 (fr)
TW (1) TW200534355A (fr)
WO (1) WO2005091339A2 (fr)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7667250B2 (en) * 2004-07-16 2010-02-23 Aptina Imaging Corporation Vertical gate device for an image sensor and method of forming the same
KR100574498B1 (ko) * 2004-12-28 2006-04-27 주식회사 하이닉스반도체 반도체 장치의 초기화 회로
US7795673B2 (en) * 2007-07-23 2010-09-14 Macronix International Co., Ltd. Vertical non-volatile memory
KR100948093B1 (ko) * 2007-12-21 2010-03-16 주식회사 하이닉스반도체 반도체 소자 및 그 제조 방법

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0544408A2 (fr) * 1991-10-28 1993-06-02 Xerox Corporation Dispositifs à semi-conducteurs émetteurs de lumière à confinement quantique
US5476802A (en) * 1991-08-26 1995-12-19 Semiconductor Energy Laboratory Co., Ltd. Method for forming an insulated gate field effect transistor
US5739057A (en) * 1995-11-06 1998-04-14 Tiwari; Sandip Method of making self-aligned dual gate MOSFET with an ultranarrow channel
US5990509A (en) * 1997-01-22 1999-11-23 International Business Machines Corporation 2F-square memory cell for gigabit memory applications
US6355532B1 (en) * 1999-10-06 2002-03-12 Lsi Logic Corporation Subtractive oxidation method of fabricating a short-length and vertically-oriented channel, dual-gate, CMOS FET
US20030015755A1 (en) * 2001-06-26 2003-01-23 Peter Hagemeyer Vertical transistor, memory arrangement and method for fabricating a vertical transistor
EP1291907A2 (fr) * 2001-09-07 2003-03-12 Power Integrations, Inc. Méthode de fabrication de dispositifs semi-conducteurs à haute tension
WO2003083919A2 (fr) * 2002-03-28 2003-10-09 Koninklijke Philips Electronics N.V. Procede de production de nanofils et dispositif electronique

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020074585A1 (en) * 1988-05-17 2002-06-20 Advanced Power Technology, Inc., Delaware Corporation Self-aligned power MOSFET with enhanced base region
DE69841171D1 (de) * 1997-08-01 2009-11-05 Canon Kk Reaktionsstellenarray, Verfahren zu seiner Herstellung, Reaktionsverfahren unter seiner Verwendung und quantitatives Bestimmungsverfahren für eine Substanz in einer Probelösung unter seiner Verwendung
US6319813B1 (en) * 1998-07-06 2001-11-20 Micron Technology, Inc. Semiconductor processing methods of forming integrated circuitry and integrated circuitry constructions
TW591756B (en) * 2003-06-05 2004-06-11 Nanya Technology Corp Method of fabricating a memory cell with a single sided buried strap

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5476802A (en) * 1991-08-26 1995-12-19 Semiconductor Energy Laboratory Co., Ltd. Method for forming an insulated gate field effect transistor
EP0544408A2 (fr) * 1991-10-28 1993-06-02 Xerox Corporation Dispositifs à semi-conducteurs émetteurs de lumière à confinement quantique
US5739057A (en) * 1995-11-06 1998-04-14 Tiwari; Sandip Method of making self-aligned dual gate MOSFET with an ultranarrow channel
US5990509A (en) * 1997-01-22 1999-11-23 International Business Machines Corporation 2F-square memory cell for gigabit memory applications
US6355532B1 (en) * 1999-10-06 2002-03-12 Lsi Logic Corporation Subtractive oxidation method of fabricating a short-length and vertically-oriented channel, dual-gate, CMOS FET
US20030015755A1 (en) * 2001-06-26 2003-01-23 Peter Hagemeyer Vertical transistor, memory arrangement and method for fabricating a vertical transistor
EP1291907A2 (fr) * 2001-09-07 2003-03-12 Power Integrations, Inc. Méthode de fabrication de dispositifs semi-conducteurs à haute tension
WO2003083919A2 (fr) * 2002-03-28 2003-10-09 Koninklijke Philips Electronics N.V. Procede de production de nanofils et dispositif electronique

Also Published As

Publication number Publication date
WO2005091339A3 (fr) 2005-11-17
TW200534355A (en) 2005-10-16
US20050208769A1 (en) 2005-09-22

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