WO2005078785A1 - Procede de realisation d’un circuit electronique integre et circuit electronique integre ainsi obtenu - Google Patents
Procede de realisation d’un circuit electronique integre et circuit electronique integre ainsi obtenu Download PDFInfo
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- WO2005078785A1 WO2005078785A1 PCT/FR2005/000318 FR2005000318W WO2005078785A1 WO 2005078785 A1 WO2005078785 A1 WO 2005078785A1 FR 2005000318 W FR2005000318 W FR 2005000318W WO 2005078785 A1 WO2005078785 A1 WO 2005078785A1
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- WO
- WIPO (PCT)
- Prior art keywords
- substrate
- circuit
- temporary
- temporary material
- capacitor
- Prior art date
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- 238000000034 method Methods 0.000 title claims abstract description 40
- 239000000463 material Substances 0.000 claims abstract description 134
- 239000000758 substrate Substances 0.000 claims abstract description 65
- 239000003990 capacitor Substances 0.000 claims abstract description 42
- 239000002250 absorbent Substances 0.000 claims abstract description 24
- 230000002745 absorbent Effects 0.000 claims abstract description 24
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims abstract description 16
- 239000010941 cobalt Substances 0.000 claims abstract description 10
- 229910017052 cobalt Inorganic materials 0.000 claims abstract description 10
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims abstract description 10
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 claims abstract description 7
- 229910052759 nickel Inorganic materials 0.000 claims abstract description 7
- 239000010936 titanium Substances 0.000 claims abstract description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 6
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 6
- 239000010937 tungsten Substances 0.000 claims abstract description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 5
- 239000010931 gold Substances 0.000 claims abstract description 5
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 5
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims abstract description 4
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims abstract description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims abstract description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 4
- 229910052737 gold Inorganic materials 0.000 claims abstract description 4
- 229910052750 molybdenum Inorganic materials 0.000 claims abstract description 4
- 239000011733 molybdenum Substances 0.000 claims abstract description 4
- 229910052709 silver Inorganic materials 0.000 claims abstract description 4
- 239000004332 silver Substances 0.000 claims abstract description 4
- 229910052715 tantalum Inorganic materials 0.000 claims abstract description 4
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims abstract description 4
- 229910052742 iron Inorganic materials 0.000 claims abstract description 3
- 238000010521 absorption reaction Methods 0.000 claims description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 11
- 239000010703 silicon Substances 0.000 claims description 11
- 238000010438 heat treatment Methods 0.000 claims description 10
- 238000001465 metallisation Methods 0.000 claims description 8
- 238000006243 chemical reaction Methods 0.000 claims description 7
- 230000008018 melting Effects 0.000 claims description 5
- 238000002844 melting Methods 0.000 claims description 5
- 239000011651 chromium Substances 0.000 claims description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 3
- 230000004075 alteration Effects 0.000 claims description 3
- 229910052787 antimony Inorganic materials 0.000 claims description 3
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 claims description 3
- 229910052785 arsenic Inorganic materials 0.000 claims description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 3
- 229910052804 chromium Inorganic materials 0.000 claims description 3
- 229910052732 germanium Inorganic materials 0.000 claims description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 239000011574 phosphorus Substances 0.000 claims description 3
- 239000003989 dielectric material Substances 0.000 abstract description 7
- 230000015572 biosynthetic process Effects 0.000 abstract description 6
- 230000002787 reinforcement Effects 0.000 abstract description 6
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052733 gallium Inorganic materials 0.000 abstract description 2
- 229910052738 indium Inorganic materials 0.000 abstract description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 abstract description 2
- 238000004519 manufacturing process Methods 0.000 description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- 229910052782 aluminium Inorganic materials 0.000 description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 7
- 230000015556 catabolic process Effects 0.000 description 7
- 230000008569 process Effects 0.000 description 7
- 239000004065 semiconductor Substances 0.000 description 6
- 150000001875 compounds Chemical class 0.000 description 5
- 238000000151 deposition Methods 0.000 description 5
- 239000000126 substance Substances 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 239000011669 selenium Substances 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- BUGBHKTXTAQXES-UHFFFAOYSA-N Selenium Chemical compound [Se] BUGBHKTXTAQXES-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 239000003153 chemical reaction reagent Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 229910052711 selenium Inorganic materials 0.000 description 2
- 229910052714 tellurium Inorganic materials 0.000 description 2
- PORWMNRCUJJQNO-UHFFFAOYSA-N tellurium atom Chemical compound [Te] PORWMNRCUJJQNO-UHFFFAOYSA-N 0.000 description 2
- 229910019001 CoSi Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000004090 dissolution Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- PEUPIGGLJVUNEU-UHFFFAOYSA-N nickel silicon Chemical compound [Si].[Ni] PEUPIGGLJVUNEU-UHFFFAOYSA-N 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 230000009257 reactivity Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 238000011144 upstream manufacturing Methods 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/764—Air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
Definitions
- the present invention relates to a method for producing an integrated electronic circuit incorporating a substantially empty volume of material. It also relates to an integrated electronic circuit thus produced.
- US Patent 5,296,408 describes a method of forming an empty cavity within an integrated circuit, for producing various electronic components such as a light source, a detector, a transistor or a vacuum tube. According to this process, absorption of aluminum in silicon is caused by heating, so as to create the empty cavity of material, the shape of which can be determined beforehand.
- a disadvantage of the process described in patent 5,296,408 results from the chemical reactivity and the relatively low melting temperature of aluminum.
- An object of the present invention to provide a method of manufacturing a cavity in an integrated electronic circuit which does not have the drawbacks mentioned above.
- the invention proposes a method for producing an integrated electronic circuit, the method comprising the steps consisting in: a) forming, on a substrate of the circuit, part of which is made of absorbent material, a portion of temporary material coming in contact with a face of the part of the substrate made of absorbent material; b) forming a rigid portion in fixed contact with the substrate, on one side of the portion of temporary material opposite to said face of the portion of the substrate made of absorbent material; and c) heating the circuit to create a substantially empty volume of material by absorption of the temporary material in the part of the substrate made of absorbent material, the method being characterized in that the temporary material has a melting temperature above 900 ° C.
- step c) is well controlled.
- a substantially empty volume of material is obtained, the shape and dimensions of which can be precisely controlled.
- a method according to the invention is therefore compatible with technologies for producing integrated circuits corresponding to widths of transistor gates equal to or less than 0.18 micrometer, and in particular equal to 90 or 65 nanometers.
- all the temporary material of the corresponding portion is preferably absorbed in the part of the substrate made of absorbent material. Improved reproducibility of the shape and dimensions of the substantially empty volume of material is thus obtained.
- Step c) of heating the circuit to create the empty volume is particularly simple. It does not require any access to the portion of temporary material, nor any implementation of a solution or a plasma of engraving.
- the absorption of the temporary material in the part of the substrate made of absorbent material, in step c) can result from a chemical reaction between the temporary material and the absorbent material.
- step c) can be carried out at any later time during the process for producing the circuit.
- steps for producing parts of the circuit other than the electronic component which comprises the substantially empty volume of material can be carried out, between steps a) and b) on the one hand and step c) on the other hand .
- steps for making other parts of the circuit involve mechanical stresses on the circuit.
- Step c) is then executed after these steps, so that the circuit does not yet have an empty volume when it is subjected to mechanical stresses. The risk of deterioration or rupture of the circuit during its production is thus reduced, this risk being due to the presence of empty volumes in the circuit.
- the method further comprises, between steps a) and b), forming an intermediate layer, said intermediate layer being situated, at the end of step b), between the portion of temporary material and the rigid portion.
- Such an intermediate layer can have several functions. One of these functions can be the improvement of the formation of the rigid portion. A more regular surface of the rigid portion can thus be obtained, which results in a more homogeneous and more complete absorption of the temporary material in step c).
- Another function of the intermediate layer is to contribute to chemical isolation of the portion of temporary material, so that the temporary material is not altered by atoms from other parts of the circuit.
- the temporary material may include cobalt, nickel, titanium, tantalum, tungsten, molybdenum, silver, gold, iron and / or chromium.
- the absorbent material can include silicon, germanium, phosphorus, arsenic and / or antimony. It can also potentially include selenium and / or tellurium.
- the portion of temporary material is formed in a cavity below the level of a surface of the substrate. The rigid portion can then continuously cover the portion of temporary material in the cavity and the substrate outside the cavity.
- the substantially empty volume of material can have different shapes and be oriented in various ways relative to the substrate. In particular, it may have a large section substantially parallel to a surface of the substrate. According to the preferred embodiment of the invention, the substantially empty volume of material is located between two plates of a capacitor belonging to the circuit.
- the rigid portion comprises a first of the reinforcements of the capacitor.
- the part of the substrate made of absorbent material, after the absorption of the temporary material in step c), may comprise one second of the reinforcements of the capacitor.
- the material of this second reinforcement is therefore directly formed during step c), without the additional step of depositing a new material on the circuit.
- the process for producing the capacitor is therefore simplified, which contributes to a reduction in the price of the electronic circuit.
- at least one of the two plates of the capacitor may have a main surface substantially parallel to the surface of the substrate.
- the invention also relates to an integrated electronic circuit produced using a method as described above.
- the substantially empty volume of material can be placed within a layer of metallization level of the circuit.
- FIG. 1 to 5 illustrate different steps of a first mode implementing a method for producing an integrated electronic circuit according to the invention
- - Figures 6 to 8 illustrate different stages of a second embodiment of a method for producing an integrated electronic circuit according to the invention.
- the invention is now described in detail in the context of the production of an integrated electronic circuit which comprises a capacitor of the Metal-lsolant-Metal type (or MIM capacitor).
- a MIM capacitor usually comprises two metallic plates and a portion of a dielectric material placed between the two plates. By using a method according to the invention, at least part of this portion of dielectric material can be replaced by a substantially empty volume of material.
- a first embodiment is described according to which the capacitor is produced below the level of the upper surface of the semiconductor substrate of an integrated electronic circuit.
- the semiconductor material of the substrate constitutes the absorbent material.
- a substrate 100 of semiconductor material has a substantially planar upper surface S.
- a cavity C is formed in the substrate 100, below the level of the surface S.
- the depth of the cavity C in the direction N can be, for example, equal to
- the respective thicknesses of the layers 1 and 2 are chosen so that the layers 1 and 2 each form a conformal coating of the vertical walls of the cavity C.
- the thickness of the layer 3 is chosen so as to fill cavity C. The configuration of the circuit shown in FIG. 2 is thus obtained.
- the layer 1 is in contact with the substrate 100 at the bottom F of the cavity C, as well as at the vertical walls of the cavity C. Thicknesses of the layers 1, 2 and 3 can be, respectively, 20 nanometers, 5 nanometers and 1 micrometer approximately.
- the upper surface of the circuit is then polished, so as to be lowered to below the level of the surface S outside of the cavity C. Portions of layers 1-3 then remain only inside the cavity C (FIG. 3).
- the material of layer 1 is chosen for its property allowing it to be absorbed subsequently in the substrate 100, through the bottom F of the cavity C. For this reason the material of layer 1 is said to be temporary material.
- the material of layer 1 can include, for example, cobalt (Co), nickel (Ni), titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), gallium (Ga), indium (In), silver (Ag), gold (Au) iron (Fe) and or chromium (Cr).
- the semiconductor material of the substrate 100 in which the material of the layer 1 is intended to be absorbed subsequently, can comprise silicon (Si), germanium (Ge), phosphorus (P), arsenic (As), antimony (Sb), selenium (Se) and / or tellurium (Te).
- the material of the substrate 100 is based on silicon and the temporary material of the layer 1 is based on cobalt.
- the deposition of layers 1 to 3 can be easily carried out at the upstream part (or “front end” in English) of a production line of the integrated circuit, using one of the known methods for the deposition of cobalt.
- the remaining portion of layer 3 is intended to constitute a first frame, or upper frame, of the capacitor.
- the material of layer 3 can be a metal which has a high electrical conductivity, such as, for example, tungsten (W).
- the material of layer 3 can also be based on silicon, suitably doped to have sufficient electrical conductivity.
- Layer 2 has an attachment function for layer 3 on the circuit. The material of layer 2 is advantageously chosen so as to promote progressive growth of layer 3, with a uniform thickness.
- the material of layer 2 can be, in particular, titanium nitride (TiN) or tantalum nitride (TaN).
- the circuit is then covered with a layer 4 of a rigid material coming into contact with the substrate 100 and with the first frame 3 (FIG. 4).
- the rigid material of layer 4 can be silica (Si0 2 ) or silicon nitride (S1 3 N 4 ) for example.
- Layer 4 extends continuously above cavity C and above substrate 100 outside cavity C.
- Layer 4 can be deposited by one of the methods known to those skilled in the art, such as, in particular, a chemical vapor deposition, or CVD (for “Chemical Vapor Deposition” in English).
- the intermediate layer 2 also has a chemical insulation function of the portion 1 with respect to reagents used for the formation of layer 4. This isolation is also effective with respect to chemical compounds used for the formation of other parts of the circuit.
- Different conventional steps for producing the circuit can then be carried out. These steps may relate, in particular, to the production of components of the circuit distinct from the capacitor which includes the armature 3, or the production of metallization levels above the level of the surface S.
- electrical connections can be arranged in layers of these metallization levels, according to the Damascene process, or its Dual-Damascene variant.
- the layer 4 can belong to a first level of metallization of the circuit.
- Such stages of making the circuit may include heating the circuit.
- the temperature to which the circuit is heated to increase the density of a portion of material is of the order of 400-500 ° C.
- the temporary material of the portion 1 can be chosen as a function of its melting temperature. In particular, it is chosen so that its melting temperature is higher than the maximum temperature reached by the circuit during these steps.
- the circuit is then heated to a temperature sufficient to cause the absorption of the temporary material of the portion 1 in the material of the substrate 100 present near the bottom F and the vertical walls of the cavity C.
- This absorption may result from a reaction chemical between the temporary material and the material of the substrate 100, or result from a dissolution of the material of the portion 1 in the material of the substrate 100.
- the respective materials of the portion 1 and of the substrate 100 are chosen so that the absorption of the temporary material does not cause the material of the substrate 100 to expand around the cavity C.
- the heating of the circuit to cause the absorption of the temporary material of the portion 1 in the material of the substrate 100 can be performed locally, that is to say only in a limited portion of the circuit.
- This limited portion of the circuit which is heated comprises the portion 1 and the part of the substrate 100 made of absorbent material and located near the bottom F and the vertical walls of the cavity C.
- Such local heating can be carried out, in known manner, using a laser sent over said limited portion of the circuit.
- the part of the cavity C initially occupied by the portion 1 is thus emptied: an empty volume V of material is created between the face formed by the bottom F of the cavity C and the intermediate layer 2.
- the layer 4 and the upper reinforcement 3, covered by the intermediate layer 2 form a rigid portion maintained in position and in fixed contact relative to the substrate 100. This rigid portion is suspended above the face F, parallel to the latter.
- the material of layer 4 is chosen to have sufficient rigidity and solidity to withstand the possible stresses caused by the creation of the empty volume V.
- the silica (Si0 2 ) or the silicon nitride (Si 3 N) are adapted to serve as material of the layer 4.
- the absorption results from the siliciding reaction of the cobalt, which is perfectly known and enhanced during the production of an integrated circuit.
- the heating temperature of the circuit necessary to cause the siliciding reaction is then approximately 800 ° C.
- Line modules for producing already existing integrated circuits can be used for the step of creating the empty volume V.
- heating the circuit to create the empty volume V can be used to simultaneously cause siliciding reactions in d other parts of the circuit, in particular at the level of electrical contacts in order to reduce, in a known manner, electrical contact resistances.
- the material of the substrate 100 and the temporary material of the portion 1 are chosen so that, after the absorption of the temporary material in the material of the substrate, the resulting material near the bottom F and the vertical walls of the cavity C is an electrically conductive compound. This is particularly the case when cobalt silicide
- the volume V fulfills the function of the dielectric material located between the plates of the capacitor obtained. It may optionally contain a certain amount of gaseous compounds, in particular vaporized compounds originating from the substrate 100, layers 2 or 4, or originating by diffusion from other parts of the circuit. It is in this sense that we say that the volume
- the configuration of the capacitor obtained is as follows: the volume V substantially empty of material has a large section substantially parallel to the surface S of the substrate 100, and the frames 3 and 5 each have a main surface substantially parallel to the surface S. The thickness of the volume V in the direction N is then substantially equal to the initial thickness of the layer 1, namely approximately 20 nanometers.
- a peripheral electrical insulation belt can be provided around the part 5 of the substrate 100 which constitutes the lower armature of the capacitor.
- such an insulation belt is formed in the substrate 100 at the start of the process for producing the capacitor.
- the capacitor can be arranged within a layer of a metallization level above the upper surface of the semiconductor substrate of an integrated electronic circuit.
- This second mode of implementation will now be described with reference to FIGS. 6 to 8.
- a substrate 101 of semiconductor material is covered with a layer 102 of an electrical insulating material.
- the layer 102 can be, for example, silica (SiO 2 ).
- An insert 103 for example made of silicon, is arranged within the layer 102, in a limited portion of the latter.
- the thickness of the insert 103, in the direction N can be, for example, equal to 0.6 micrometers.
- the assembly constituted by the substrate 101, the layer 102 and the insert 103 fulfills a function identical to that of the substrate 100 used in the first embodiment of the invention above.
- S corresponds to the upper surface of the layer 102, which continues continuously on the insert 103. Steps identical to those corresponding to FIGS. 1-4 are carried out, so as to produce the capacitor within the insert 103
- a cavity C is formed in a central part of the insert 103.
- the cavity C has a depth, in the direction N, less than the thickness of the insert 103, for example 0.5 micrometer.
- a residual thickness of approximately 0.1 micrometer is present between the bottom of the cavity C and the layer 102.
- Portions 1, 2 and 3, for example of nickel (Ni), of titanium nitride (TiN) and tungsten (W), as well as a layer 4 of silica (S1O 2 ) are formed in the same way as described above.
- the configuration of the circuit shown in Figure 7 is then obtained.
- the material of the insert 103 constitutes the absorbent material.
- the face F corresponds to the bottom of the cavity C, which constitutes the interface between the insert 103 and the portion 1.
- the layer 4 forms, with the layer 102, a first level of metallization, denoted M1, above the substrate 101
- a barrier layer not shown and which may be made of silicon nitride (Si3N-, can be placed between layers 102 and 4, in order to allow the creation of connections in the metallization level M1 using the dual process.
- - Damascene The circuit is then heated to approximately 500 ° C. so as to cause the absorption of the nickel material of the portion 1 in the silicon material of the insert 103.
- the material of the insert 103 is the absorbent material.
- the empty volume V is thus created between the layer 2 and the insert 103.
- the material of the insert 103 near the volume V is transformed into nickel silicide (NiSi).
- the armatures 3 and 5 are separated by the empty volume V.
- the method of the invention can be implemented in multiple ways during the production of a MIM capacitor, keeping an empty volume which replaces a dielectric material placed between the armatures of the capacitor.
- the intermediate layer 2 can be omitted.
- the capacitor may also have a configuration different from that of the described embodiments. In particular, configurations can be envisaged, according to which the empty volume V has a large section substantially perpendicular to the surface S of the substrate. In this case, the reinforcements of the capacitor may have main surfaces also oriented perpendicular to the surface S.
- a capacitor produced using the method of the invention has a particularly high breakdown voltage.
- the value of the breakdown voltage of a capacitor depends on the quality of the portion of dielectric material.
- this portion has intrinsic defects when it is formed by usual techniques for depositing materials used for the production of integrated circuits. These intrinsic faults are at the origin of the breakdown of such capacitors.
- the replacement of at least part of the portion of dielectric material of a MIM capacitor by a substantially empty volume obtained using a method according to the invention results in a high value of the breakdown voltage of the capacitor.
- the MIM capacitor can then be used for particular functions which require a high breakdown voltage value, such as, for example, a decoupling function between several electrical power sources connected to a circuit.
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006552664A JP2007522665A (ja) | 2004-02-13 | 2005-02-10 | 電子集積回路の製造方法及びそれによって得られる電子集積回路 |
EP05717608A EP1714313A1 (fr) | 2004-02-13 | 2005-02-10 | Procede de realisation d'un circuit electronique integre et circuit electronique integre ainsi obtenu |
US10/589,275 US7829449B2 (en) | 2004-02-13 | 2005-02-10 | Process for fabricating an electronic integrated circuit and electronic integrated circuit thus obtained |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0401482A FR2866471A1 (fr) | 2004-02-13 | 2004-02-13 | Procede de realisation d'un circuit electronique integre et circuit electronique integre ainsi obtenu |
FR0401482 | 2004-02-13 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2005078785A1 true WO2005078785A1 (fr) | 2005-08-25 |
Family
ID=34803366
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/FR2005/000318 WO2005078785A1 (fr) | 2004-02-13 | 2005-02-10 | Procede de realisation d’un circuit electronique integre et circuit electronique integre ainsi obtenu |
Country Status (6)
Country | Link |
---|---|
US (1) | US7829449B2 (fr) |
EP (1) | EP1714313A1 (fr) |
JP (1) | JP2007522665A (fr) |
CN (1) | CN100483649C (fr) |
FR (1) | FR2866471A1 (fr) |
WO (1) | WO2005078785A1 (fr) |
Families Citing this family (4)
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US9196568B2 (en) * | 2013-10-01 | 2015-11-24 | Infineon Technologies Ag | Arrangement and method for manufacturing the same |
US20150221523A1 (en) | 2013-10-01 | 2015-08-06 | Infineon Technologies Ag | Arrangement and method for manufacturing the same |
KR102235612B1 (ko) | 2015-01-29 | 2021-04-02 | 삼성전자주식회사 | 일-함수 금속을 갖는 반도체 소자 및 그 형성 방법 |
CN108461629A (zh) * | 2018-03-02 | 2018-08-28 | 福建省福芯电子科技有限公司 | 硅基射频电容及其制备方法 |
Citations (6)
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US5666000A (en) | 1994-10-31 | 1997-09-09 | International Business Machines Corporation | Microcavity capacitive device |
EP1191557A2 (fr) | 2000-09-12 | 2002-03-27 | Robert Bosch Gmbh | Condensateur ajustable intégré |
EP1209738A2 (fr) | 2000-11-27 | 2002-05-29 | Chartered Semiconductor Manufacturing, Inc. | Méthode de fabrication d'une structure d'isolation à tranchées peu profondes avec cavité |
US20020068430A1 (en) | 1998-09-02 | 2002-06-06 | Eldridge Jerome Michael | Methods of forming void regions, dielectric regions and capacitor constructions |
WO2003103029A1 (fr) | 2002-06-03 | 2003-12-11 | Telefonaktiebolaget L.M. Ericsson | Dispositif condensateur forme sur un substrat, circuit integre comprenant un tel dispositif et procede de production d'un dispositif condensateur |
US20030234423A1 (en) | 2002-06-25 | 2003-12-25 | International Rectifier Corporation | Trench fill process |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH05218410A (ja) * | 1992-01-31 | 1993-08-27 | Toshiba Corp | 半導体装置およびその製造方法 |
US5296408A (en) * | 1992-12-24 | 1994-03-22 | International Business Machines Corporation | Fabrication method for vacuum microelectronic devices |
US6147000A (en) * | 1998-08-11 | 2000-11-14 | Advanced Micro Devices, Inc. | Method for forming low dielectric passivation of copper interconnects |
JP3549425B2 (ja) * | 1999-02-24 | 2004-08-04 | シャープ株式会社 | 半導体装置及びその製造方法 |
-
2004
- 2004-02-13 FR FR0401482A patent/FR2866471A1/fr not_active Withdrawn
-
2005
- 2005-02-10 US US10/589,275 patent/US7829449B2/en not_active Expired - Fee Related
- 2005-02-10 JP JP2006552664A patent/JP2007522665A/ja active Pending
- 2005-02-10 EP EP05717608A patent/EP1714313A1/fr not_active Withdrawn
- 2005-02-10 CN CNB2005800042821A patent/CN100483649C/zh not_active Expired - Fee Related
- 2005-02-10 WO PCT/FR2005/000318 patent/WO2005078785A1/fr not_active Application Discontinuation
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
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US5666000A (en) | 1994-10-31 | 1997-09-09 | International Business Machines Corporation | Microcavity capacitive device |
US20020068430A1 (en) | 1998-09-02 | 2002-06-06 | Eldridge Jerome Michael | Methods of forming void regions, dielectric regions and capacitor constructions |
EP1191557A2 (fr) | 2000-09-12 | 2002-03-27 | Robert Bosch Gmbh | Condensateur ajustable intégré |
EP1209738A2 (fr) | 2000-11-27 | 2002-05-29 | Chartered Semiconductor Manufacturing, Inc. | Méthode de fabrication d'une structure d'isolation à tranchées peu profondes avec cavité |
WO2003103029A1 (fr) | 2002-06-03 | 2003-12-11 | Telefonaktiebolaget L.M. Ericsson | Dispositif condensateur forme sur un substrat, circuit integre comprenant un tel dispositif et procede de production d'un dispositif condensateur |
US20030234423A1 (en) | 2002-06-25 | 2003-12-25 | International Rectifier Corporation | Trench fill process |
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Title |
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DE SUGIYAMA ET AL.: "Micro-Diaphragm Pressure Sensor", INTERNATIONAL ELECTRON DEVICES MEETING, LOS ANGELES, 7 December 1986 (1986-12-07), pages 184 - 187 |
SUGIYAMA S ET AL: "MICRO-DIAPHRAGM PRESSURE SENSOR", INTERNATIONAL ELECTRON DEVICES MEETING. LOS ANGELES, DEC. 7 - 10, 1986, NEW YORK, IEEE, US, 7 December 1986 (1986-12-07), pages 184 - 187, XP002039418 * |
Also Published As
Publication number | Publication date |
---|---|
CN1954417A (zh) | 2007-04-25 |
US20070170538A1 (en) | 2007-07-26 |
FR2866471A1 (fr) | 2005-08-19 |
EP1714313A1 (fr) | 2006-10-25 |
US7829449B2 (en) | 2010-11-09 |
CN100483649C (zh) | 2009-04-29 |
JP2007522665A (ja) | 2007-08-09 |
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