WO2005059651A3 - Procede de reparation d'erreurs de motifs realises dans des couches minces - Google Patents

Procede de reparation d'erreurs de motifs realises dans des couches minces Download PDF

Info

Publication number
WO2005059651A3
WO2005059651A3 PCT/FR2004/050698 FR2004050698W WO2005059651A3 WO 2005059651 A3 WO2005059651 A3 WO 2005059651A3 FR 2004050698 W FR2004050698 W FR 2004050698W WO 2005059651 A3 WO2005059651 A3 WO 2005059651A3
Authority
WO
WIPO (PCT)
Prior art keywords
thin layers
repairing errors
patterns embodied
relates
errors
Prior art date
Application number
PCT/FR2004/050698
Other languages
English (en)
Other versions
WO2005059651A2 (fr
Inventor
Laurent Pain
Original Assignee
Commissariat Energie Atomique
Laurent Pain
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat Energie Atomique, Laurent Pain filed Critical Commissariat Energie Atomique
Priority to US10/582,791 priority Critical patent/US7767104B2/en
Priority to JP2006544520A priority patent/JP4733050B2/ja
Priority to EP04816552.6A priority patent/EP1695145B1/fr
Publication of WO2005059651A2 publication Critical patent/WO2005059651A2/fr
Publication of WO2005059651A3 publication Critical patent/WO2005059651A3/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/22—Masks or mask blanks for imaging by radiation of 100nm or shorter wavelength, e.g. X-ray masks, extreme ultraviolet [EUV] masks; Preparation thereof
    • G03F1/24—Reflection masks; Preparation thereof
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/68—Preparation processes not covered by groups G03F1/20 - G03F1/50
    • G03F1/72—Repair or correction of mask defects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Nanotechnology (AREA)
  • Chemical & Material Sciences (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)
  • Electron Beam Exposure (AREA)

Abstract

L'invention se rapporte au domaine des procédés de fabrication en couche minces par exemple de circuits intégrés électroniques ou de MEMS. Elle concerne un procédé de correction permettant de réparer des erreurs de dessin réalisées par exemple par photolithographie dans une couche mince et ce, sans avoir nécessairement à utiliser un nouveau masque ou sans avoir à corriger un masque erroné. L'invention comprend également un dispositif de lithographie permettant de mettre en oeuvre certaines des étapes d'un tel procédé.
PCT/FR2004/050698 2003-12-16 2004-12-15 Procede de reparation d'erreurs de motifs realises dans des couches minces WO2005059651A2 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US10/582,791 US7767104B2 (en) 2003-12-16 2004-12-15 Method for repairing errors of patterns embodied in thin layers
JP2006544520A JP4733050B2 (ja) 2003-12-16 2004-12-15 薄膜に形成されたパターンの誤りの修正方法
EP04816552.6A EP1695145B1 (fr) 2003-12-16 2004-12-15 Procédé de réparation d' erreurs de motifs réalisés dans des couches minces

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0351067 2003-12-16
FR0351067A FR2863772B1 (fr) 2003-12-16 2003-12-16 Procede de reparation d'erreurs de motifs realises dans des couches minces

Publications (2)

Publication Number Publication Date
WO2005059651A2 WO2005059651A2 (fr) 2005-06-30
WO2005059651A3 true WO2005059651A3 (fr) 2006-04-20

Family

ID=34610750

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/FR2004/050698 WO2005059651A2 (fr) 2003-12-16 2004-12-15 Procede de reparation d'erreurs de motifs realises dans des couches minces

Country Status (5)

Country Link
US (1) US7767104B2 (fr)
EP (1) EP1695145B1 (fr)
JP (1) JP4733050B2 (fr)
FR (1) FR2863772B1 (fr)
WO (1) WO2005059651A2 (fr)

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60142518A (ja) * 1983-12-28 1985-07-27 Seiko Epson Corp ハ−ドマスクのピンホ−ル修正方法
US5945238A (en) * 1998-02-06 1999-08-31 Clear Logic, Inc. Method of making a reusable photolithography mask
US5953577A (en) * 1998-09-29 1999-09-14 Clear Logic, Inc. Customization of integrated circuits
US5985518A (en) * 1997-03-24 1999-11-16 Clear Logic, Inc. Method of customizing integrated circuits using standard masks and targeting energy beams
US20020122995A1 (en) * 2001-03-02 2002-09-05 Mancini David P. Lithographic template and method of formation and use
US20030027053A1 (en) * 2001-07-31 2003-02-06 Pei-Yang Yan Damascene extreme ultraviolet lithography ( EUVL) photomask and method of making
US20030039923A1 (en) * 2001-08-27 2003-02-27 Pawitter Mangat Method of forming a pattern on a semiconductor wafer using an attenuated phase shifting reflective mask
US6596465B1 (en) * 1999-10-08 2003-07-22 Motorola, Inc. Method of manufacturing a semiconductor component

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BE793605A (fr) * 1972-01-03 1973-05-02 Rca Corp Appareil et procede pour corriger un masque photographique defectueux
US4639301B2 (en) 1985-04-24 1999-05-04 Micrion Corp Focused ion beam processing
EP0203215B1 (fr) 1985-05-29 1990-02-21 Ibm Deutschland Gmbh Procédé pour la correction des masques par transmission
JPH0611827A (ja) * 1992-03-31 1994-01-21 Matsushita Electron Corp ホトマスクおよびその修正方法
JP3312703B2 (ja) * 1993-04-15 2002-08-12 大日本印刷株式会社 位相シフトフォトマスクの修正方法
JPH07134397A (ja) * 1993-11-09 1995-05-23 Fujitsu Ltd 位相シフトマスクの修正方法と位相シフトマスク用基板
JPH10274839A (ja) * 1997-03-31 1998-10-13 Fujitsu Ltd 修正用マスク及びハーフトーン位相シフトマスクの修正方法
JP3650055B2 (ja) * 2001-10-12 2005-05-18 Ｈｏｙａ株式会社 ハーフトーン型位相シフトマスクの修正方法
US6777137B2 (en) * 2002-07-10 2004-08-17 International Business Machines Corporation EUVL mask structure and method of formation
US7504182B2 (en) * 2002-09-18 2009-03-17 Fei Company Photolithography mask repair
US7005215B2 (en) * 2002-10-28 2006-02-28 Synopsys, Inc. Mask repair using multiple exposures
US20050109278A1 (en) * 2003-11-26 2005-05-26 Ted Liang Method to locally protect extreme ultraviolet multilayer blanks used for lithography

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60142518A (ja) * 1983-12-28 1985-07-27 Seiko Epson Corp ハ−ドマスクのピンホ−ル修正方法
US5985518A (en) * 1997-03-24 1999-11-16 Clear Logic, Inc. Method of customizing integrated circuits using standard masks and targeting energy beams
US5945238A (en) * 1998-02-06 1999-08-31 Clear Logic, Inc. Method of making a reusable photolithography mask
US5953577A (en) * 1998-09-29 1999-09-14 Clear Logic, Inc. Customization of integrated circuits
US6596465B1 (en) * 1999-10-08 2003-07-22 Motorola, Inc. Method of manufacturing a semiconductor component
US20020122995A1 (en) * 2001-03-02 2002-09-05 Mancini David P. Lithographic template and method of formation and use
US20030027053A1 (en) * 2001-07-31 2003-02-06 Pei-Yang Yan Damascene extreme ultraviolet lithography ( EUVL) photomask and method of making
US20030039923A1 (en) * 2001-08-27 2003-02-27 Pawitter Mangat Method of forming a pattern on a semiconductor wafer using an attenuated phase shifting reflective mask

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 0093, no. 05 (E - 363) 3 December 1985 (1985-12-03) *

Also Published As

Publication number Publication date
JP4733050B2 (ja) 2011-07-27
US7767104B2 (en) 2010-08-03
EP1695145A2 (fr) 2006-08-30
JP2007514205A (ja) 2007-05-31
FR2863772B1 (fr) 2006-05-26
FR2863772A1 (fr) 2005-06-17
EP1695145B1 (fr) 2017-08-23
WO2005059651A2 (fr) 2005-06-30
US20070190241A1 (en) 2007-08-16

Similar Documents

Publication Publication Date Title
TW200702899A (en) Method for manufacturing gray scale mask and gray scale mask
WO2008149988A1 (fr) Procédé d'impression
DE602005011196D1 (de) Rohling für Halbton-Phasenschiebermaske, Halbton-Phasenschiebermaske, sowie Verfahren zum Übertragen eines Musters
TWI346347B (en) Method of patterning a positive tone resist layer overlaying a lithographic substrate
TW200636865A (en) Method for etching a molybdenum layer suitable for photomask fabrication
WO2008022178A3 (fr) Procédé de séparation d'effets optiques et de réserve dans des modèles de procédé
TW200834245A (en) Method for manufacturing semiconductor device with four-layered laminate
WO2002008835A3 (fr) Procedes d'alignement de superpositions a haute resolution et systemes de lithographie de surimpression
ATE448507T1 (de) Verfahren zur herstellung eines stempel für mikro/nano imprint-lithographie
TWI265381B (en) Method for coating a substrate for EUV lithography and substrate with photoresist layer
TW200708888A (en) Substrate, lithographic multiple exposure method, machine readable medium
SG109607A1 (en) Method and apparatus for performing model based placement of phase-balanced scattering bars for sub-wavelength optical lithography
WO2005017623A3 (fr) Procede de realisation de motifs a flancs inclines par photolithographie
DE602004018087D1 (de) Phasenschiebermaske, Rohling sowie Verfahren zum Übertragen eines Musters
EP1863071A4 (fr) Procede et masque de mesure de la forme d'une zone partielle d exposition
WO2009078380A1 (fr) Procédé pour fabriquer une réserve durcie à l'aide d'un stratifié de résine photosensible négative, stratifié de résine photosensible négative et utilisation du stratifié de résine photosensible négative
WO2009035087A1 (fr) Composition pour former un motif fin contenant du silicium et procédé de formation de motif fin mettant en œuvre une telle composition
DE602005007776D1 (de) Druckreferenzvorlage zur mehrschicht- oder mehrstruktur-registration und verfahren dafür
WO2007041602A8 (fr) Verification de lithographie moyen de bande de protection
WO2007109103A3 (fr) Procédé et système permettant d'optimiser l'alignement dans un ensemble d'outils d'exposition
WO2008146946A3 (fr) Procédé d'exposition, appareil d'exposition, et procédé pour produire un dispositif
TW200731336A (en) Manufacturing method of microstructure and microelectromechanical system
TW200622482A (en) Method for detecting failure of database patterns of photo mask
WO2006011977A3 (fr) Procede de fabrication d'un masque a echelle de gris pour la production d'un doe a echelle de gris a l'aide d'une couche absorbante
WO2003029897A3 (fr) Fabrication de masque photolithographique

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BW BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NA NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): BW GH GM KE LS MW MZ NA SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LT LU MC NL PL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
REEP Request for entry into the european phase

Ref document number: 2004816552

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 2004816552

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 10582791

Country of ref document: US

Ref document number: 2007190241

Country of ref document: US

WWE Wipo information: entry into national phase

Ref document number: 2006544520

Country of ref document: JP

NENP Non-entry into the national phase

Ref country code: DE

WWW Wipo information: withdrawn in national office

Ref document number: DE

WWP Wipo information: published in national office

Ref document number: 2004816552

Country of ref document: EP

WWP Wipo information: published in national office

Ref document number: 10582791

Country of ref document: US