WO2005051058A1 - Circuit board and method for manufacturing same - Google Patents

Circuit board and method for manufacturing same Download PDF

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Publication number
WO2005051058A1
WO2005051058A1 PCT/JP2004/017069 JP2004017069W WO2005051058A1 WO 2005051058 A1 WO2005051058 A1 WO 2005051058A1 JP 2004017069 W JP2004017069 W JP 2004017069W WO 2005051058 A1 WO2005051058 A1 WO 2005051058A1
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WO
WIPO (PCT)
Prior art keywords
film
thin film
circuit board
substrate
forming
Prior art date
Application number
PCT/JP2004/017069
Other languages
French (fr)
Japanese (ja)
Inventor
Takashi Ueno
Takashi Mochizuki
Original Assignee
Dept Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dept Corporation filed Critical Dept Corporation
Publication of WO2005051058A1 publication Critical patent/WO2005051058A1/en

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/388—Improvement of the adhesion between the insulating substrate and the metal by the use of a metallic or inorganic thin film adhesion layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor

Definitions

  • the present invention relates to a circuit board and a method for manufacturing the same, and more particularly, to a circuit board and a method for manufacturing the same, which can ensure sufficient adhesion between the substrate and the Cu film, a circuit board capable of suppressing generation of etching residues, and a method for manufacturing the same About the method.
  • FIGS. 9A and 9B are cross-sectional views illustrating a conventional method for manufacturing a circuit board.
  • a base film 102 having a strength such as Cr and Ni is formed on a polyimide substrate 101.
  • a Cu plating film 103 is formed on the base film 102 by an electrolytic plating method.
  • the base film 102 acts as an adhesion layer between the Cu plating film and the polyimide substrate, and Cu in the Cu plating film is transferred to the polyimide substrate. It also acts as a barrier layer that suppresses diffusion.
  • a photoresist film (not shown) is applied on the Cu plating film 103, and is exposed and developed, so that the Cu plating film 103 is exposed.
  • a resist pattern (not shown) is formed.
  • the Cu plating film 103 and the base film 102 are wet-etched using the resist pattern as a mask, whereby wiring patterns 104a to 104d composed of the Cu plating film and the base film are formed on the polyimide substrate 101.
  • a base film 102 made of Cr, Ni or the like acting as an adhesion layer is disposed between the Cu plating film 103 and the polyimide substrate 101. As the miniaturization progresses, it is not possible to ensure sufficient adhesion with the underlayer.
  • FIGS. 10A and 10B are cross-sectional views showing another conventional method for manufacturing a circuit board.
  • the other conventional circuit board manufacturing method solves the problem that the plating growth rate in the conventional circuit board manufacturing method shown in FIG. 9 is low.
  • a base film 102 having a strength such as Cr and Ni is formed on a polyimide substrate 101.
  • a Cu film 105 is formed on the base film 102 by sputtering.
  • a Cu plating film 103 is formed on the Cu film 105 by an electrolytic plating method.
  • a photoresist film (not shown) is applied on the Cu plating film 103, and is exposed and developed, so that the Cu plating film 103 A resist pattern (not shown) is formed.
  • the resist pattern as a mask, the Cu plating film 103, the Cu film 105, and the base film 102 are etched to form a wiring pattern 106a-106d composed of a Cu plating film, a Cu film, and a base film on the polyimide substrate 101. Is formed.
  • the conventional and other conventional circuit boards have the following problems: insufficient adhesion due to the underlying film 102 having a strength such as Cr and Ni; and the generation of etching residues.
  • the present invention has been made in view of the above circumstances, and an object of the present invention is to provide a circuit board capable of sufficiently securing the adhesion between a substrate and a Cu film, and a method for manufacturing the same.
  • Another object of the present invention is to provide a circuit board and a circuit board capable of suppressing generation of an etching residue. It is to provide a manufacturing method of.
  • a circuit board according to the present invention comprises:
  • a circuit board comprising:
  • the thin film is made of an alloy containing Cu as a main component, and a group force of Ti, Mo, Ni, A1, and Ag forces. It is characterized by consisting of
  • the above circuit board when a Cu film is formed on this thin film having good adhesion between the thin film and the substrate by electroplating, electroless plating, vacuum evaporation or electron beam evaporation, The thin film has good adhesion to the Cu film. Therefore, by using a circuit board in which a thin film is formed on a substrate, it is possible to sufficiently secure the adhesion between the substrate and the Cu film.
  • a circuit board according to the present invention includes:
  • a circuit board comprising:
  • the thin film contains at least one element selected from the group consisting of Ti, Mo, Ni, A1, and Ag forces in an amount of 0.5-5. ( ⁇ % In total, and has an alloying force consisting of Cu in the balance. You.
  • the thickness of the thin film is 5 nm or more and 1 ⁇ m or less.
  • the circuit board according to the present invention may further include a Cu film formed on the thin film and having a thickness of 300 ⁇ m or more and 30 m or less. Since the adhesion between the thin film and the Cu film is good, the adhesion between the substrate and the Cu film can be sufficiently ensured.
  • a circuit board according to the present invention includes:
  • a thin film formed by sputtering on the substrate is a thin film formed by sputtering on the substrate.
  • the thin film is mainly composed of Cu, and has a group strength of Ti, Mo, Ni, A1, and Ag forces. It is an alloy containing at least one element in a total of 0.5—5 ( ⁇ %, and the film thickness is 5 nm or more and 1 m or less,
  • the thin film and the Cu film are characterized by reducing or reducing propagation loss accompanying a skin effect.
  • a thin film having good adhesion between the thin film and the substrate has good adhesion with the Cu film. Therefore, sufficient adhesion between the substrate and the Cu film can be ensured.
  • a dense Cu film composed of fine particles can be formed by a vacuum evaporation method or an electron beam evaporation method.
  • This Cu film has an excellent skin effect because it has excellent surface flatness.
  • the skin effect means that high-frequency current is concentrated on the conductor surface. From this, the path of the current flowing through the wiring pattern having the uneven surface when viewed microscopically is relatively long and the resistance value increases. Therefore, the path of the current flowing through the wiring pattern having excellent surface flatness does not become longer and the resistance value does not increase as compared with the case where there is unevenness. Therefore, a Cu film having excellent flatness is advantageous in skin effect.
  • a circuit board according to the present invention includes:
  • a circuit board comprising:
  • the wiring pattern has a thin film and a Cu film formed on the thin film
  • the thin film is made of an alloy containing Cu as a main component, and a group force of Ti, Mo, Ni, A1, and Ag forces. And a film thickness of 5 nm or more and 1 ⁇ m or less.
  • a circuit board according to the present invention includes:
  • a first wiring pattern formed on the substrate is a first wiring pattern formed on the substrate.
  • a circuit board comprising:
  • the first wiring pattern has a first thin film, and a first Cu film formed on the first thin film,
  • the second wiring pattern includes a second thin film and a second Cu formed on the second thin film. And a membrane,
  • the first thin film is made of an alloy containing Cu as a main component and a group force of Ti, Mo, Ni, A1, and Ag forces.
  • the film thickness is S5 nm or more and 1 ⁇ m or less,
  • the second thin film is an alloy powder containing Cu as a main component and a group force of Ti, Mo, Ni, A1, and Ag forces. And the film thickness is not less than nm and not more than 1 ⁇ m.
  • a circuit board according to the present invention includes:
  • a first thin film formed on the surface of the substrate is formed
  • a circuit board comprising:
  • the first thin film is made of an alloy containing Cu as a main component and a group force of Ti, Mo, Ni, A1, and Ag forces.
  • the film thickness is S5 nm or more and 1 ⁇ m or less,
  • the second thin film is an alloy powder containing Cu as a main component and a group force of Ti, Mo, Ni, A1, and Ag forces. And the film thickness is not less than nm and not more than 1 ⁇ m.
  • the thin film may be a base for promoting adhesion between the substrate and the Cu film.
  • the board may be provided with a through hole.
  • the substrate may be made of a polymer material, a resin material, or a ceramic material.
  • the polymer material may be one selected from the group consisting of polyimide, liquid crystal polymer, Teflon (registered trademark) and epoxy resin. .
  • a method for manufacturing a circuit board according to the present invention is a method for manufacturing a circuit board, comprising a step of forming a thin film on a substrate by sputtering.
  • the thin film is made of an alloy containing Cu as a main component, and a group force of Ti, Mo, Ni, A1, and Ag forces. It is characterized by consisting of
  • a method for manufacturing a circuit board according to the present invention is a method for manufacturing a circuit board, comprising a step of forming a thin film on a substrate by sputtering.
  • the thin film contains at least one element selected from the group consisting of Ti, Mo, Ni, A1, and Ag forces in an amount of 0.5-5. ( ⁇ % In total, and has an alloying force consisting of Cu in the balance. You.
  • the film thickness is preferably 5 nm or more and 1 ⁇ m or less.
  • a Cu film having a thickness of 300 nm or more and 30 m or less is formed on the thin film by an electroplating method or an electroless plating method.
  • the method may further include a step.
  • a film thickness of 300 nm or more and 30 ⁇ m or less is formed on the thin film by a vacuum evaporation method or an electron beam evaporation method.
  • the method may further include a step of forming a Cu film.
  • the method for manufacturing a circuit board according to the present invention includes the steps of: forming a thin film on the substrate by sputtering;
  • a method for manufacturing a circuit board comprising:
  • the thin film is made of an alloy containing Cu as a main component, and a group force of Ti, Mo, Ni, A1, and Ag forces. And a film thickness of 5 nm or more and 1 ⁇ m or less.
  • the Cu film and the thin film which are pure Cu, can be etched with the same etchant, and the thin film has no difference in chemical reaction with pure Cu. Therefore, one ethin Etching can etch the Cu film and the thin film, and does not cause the problem of etching residue.
  • the method for manufacturing a circuit board according to the present invention includes the steps of: forming a thin film on the substrate by sputtering;
  • a method for manufacturing a circuit board comprising:
  • the thin film is made of an alloy containing Cu as a main component, and a group force of Ti, Mo, Ni, A1, and Ag forces. And a film thickness of 5 nm or more and 1 ⁇ m or less.
  • a method for manufacturing a circuit board comprising:
  • the first thin film is mainly composed of Cu, and has a group force of Ti, Mo, Ni, A1, and Ag force. Alloy containing 0.5 to 5.0 wt% in total of at least one element selected from the group consisting of S5 nm and 1 ⁇ m,
  • the second thin film is an alloy powder containing Cu as a main component and a group force of Ti, Mo, Ni, A1, and Ag forces. And the film thickness is not less than nm and not more than 1 ⁇ m.
  • the method for manufacturing a circuit board according to the present invention includes the steps of: forming a first thin film on a substrate by sputtering;
  • the film thickness is 300 nm or more on the second thin film by a vacuum evaporation method or an electron beam evaporation method.
  • a method for manufacturing a circuit board comprising:
  • the first thin film is made of an alloy containing Cu as a main component and a group force of Ti, Mo, Ni, A1, and Ag forces.
  • the film thickness is S5 nm or more and 1 ⁇ m or less,
  • the second thin film is an alloy powder containing Cu as a main component and a group force of Ti, Mo, Ni, A1, and Ag forces. And a film thickness of 5 nm or more and 1 ⁇ m or less.
  • a circuit board and a method for manufacturing the same can be provided. Further, according to another aspect of the present invention, it is possible to provide a circuit board capable of suppressing generation of an etching residue and a method for manufacturing the same.
  • FIGS. 1A to 1E and FIGS. 2A and 2B are cross-sectional views showing a method for manufacturing a circuit board according to Embodiment 1 of the present invention and mounting electronic components on the circuit board. is there.
  • a Cu alloy thin film 2 having a thickness of 5 nm or more and 1 ⁇ m or less is formed on a substrate 1 by sputtering.
  • the Cu alloy thin film 2 contains Cu as a main component and a group strength of Ti, Mo, Ni, A1, and Ag.The total content of at least one selected element is 0.5 to 5.0% by weight (wt%). Alloy strength.
  • a more preferable Cu alloy thin film 2 contains at least one element selected from group forces consisting of Ti, Mo, Ni, A1, and Ag in a total amount of 0.5 to 5.0 wt%, with the balance being Cu. Alloy strength.
  • the substrate 1 is formed of a strong polymer material or resin material such as polyimide, liquid crystal polymer, Teflon (registered trademark) or epoxy resin.
  • the reason why the above-mentioned materials are used for the Cu alloy thin film 2 is as follows. It is easy to manufacture alloy materials, it is composed of chemically stable materials, and it does not use expensive metals, so the cost advantage of the materials is high. The composition is such that it can easily form a fine and dense film.When performing wet etching, use the same etchant as pure Cu (e.g. The reason is that etching can be performed at the same rate, and there is no problem such as residues that have no difference in chemical reaction from pure Cu during wet etching.
  • a Cu plating film 3 having a film thickness of S300 nm or more and 30 ⁇ m or less is formed on the Cu alloy thin film 2 by an electroplating method or an electroless plating method. Placing the Cu alloy thin film 2 under the Cu plating film 3 can increase the plating growth rate,
  • the put can be improved.
  • the Cu plating film 3 has a different composition from the pure Cu alloy thin film 2 which is pure Cu (but contains unavoidable impurities), but is homogeneous in that Cx is the main component. The sex is very good. Further, the adhesion between the Cu alloy thin film 2 and the substrate 1 made of a polymer material or a resin material is much better than that of a conventional underlayer such as Cr or Ni. Therefore, in the present embodiment, a base film for ensuring adhesion is not required unlike a conventional circuit board.
  • a resist pattern 4 is formed on the Cu plating film 3 by applying a photoresist film on the Cu plating film 3, exposing and developing. It is formed.
  • the Cu plating film 3 and the Cu alloy thin film 2 are etched with an etching solution such as Shii-Dai II Iron, Dani-Dai I, etc. Wet-etching.
  • an etching solution such as Shii-Dai II Iron, Dani-Dai I, etc. Wet-etching.
  • wiring patterns 5a to 5d composed of the Cu plating film 3 and the Cu alloy thin film 2 are formed on the substrate 1.
  • the Cu plating film 3 made of pure Cu and the Cu alloy thin film 2 having the above-mentioned composition can be etched with an etchant such as ferric chloride, chlorinated chloride, and the like, and have almost the same etching rate.
  • the Cu alloy thin film does not cause a problem such as a residue having no difference in chemical reaction from pure Cu.
  • a Ni—Au film 6 is formed on the wiring patterns 5a to 5d, and an Au plating film 7 is formed.
  • the Ni plating film 6 functions as a barrier layer and an adhesion layer.
  • an electronic component such as a semiconductor chip 8 to be mounted on a circuit board is prepared.
  • Au bumps 9 as external terminals are formed on the active surface of the semiconductor chip 8.
  • the semiconductor chip 8 is aligned on the circuit board, the Au bump 9 is arranged on the wiring pattern, and the wiring pattern on the board and the semiconductor chip are thermocompression bonded. With this, wiring no. The turns and the Au bumps are joined, and the semiconductor chip is mounted on the circuit board.
  • the Cu alloy thin film 2 as a plating seed layer when forming the Cu plating film 3
  • a highly reliable thin circuit having a fine wiring pattern is provided.
  • a substrate can be realized.
  • the adhesion to the film 3 is also very good.
  • the Cu alloy thin film 2 does not easily diffuse Cu into the substrate 1.
  • the plating growth rate can be increased, and the throughput can be improved.
  • the Cu plating film 3, which is pure Cu, and the Cu alloy thin film 2 having the above-mentioned composition can be etched with the same etching solution, and the etching rates are almost the same. There is no. Therefore, the Cu plating film 3 and the Cu alloy thin film 2 can be etched by one wet etching, and there is no problem such as an etching residue. Therefore, the throughput in the etching step can be improved.
  • the semiconductor chip 8 is mounted on the circuit board by joining the wiring pattern having the Au plating film formed on the surface thereof and the Au bump 9.
  • the component mounting method is not limited to this, and it is also possible to mount the component on the circuit board using other mounting methods.
  • the semiconductor chip 8 can be mounted on a circuit board by directly bonding the Au bump 9 to a wiring pattern on which no Au plating film is formed (that is, a wiring pattern composed of the Cu plating film 3 and the Cu alloy thin film 2). It is possible.
  • FIGS. 3A to 3E are cross-sectional views showing a method of manufacturing a circuit board according to Embodiment 2 of the present invention, and the same parts as those in FIG.
  • a Cu alloy thin film 2 having a thickness of 5 nm or more and 1 ⁇ m or less is formed on a substrate 1 by sputtering.
  • the Cu alloy thin film 2 has the same alloy strength as in the first embodiment, and the substrate 1 has the same material strength as in the first embodiment.
  • a photoresist pattern is formed on the Cu alloy thin film 2 by applying a photoresist film on the Cu alloy thin film 2, exposing and developing. Is done.
  • This resist pattern 4 is a pattern in which only the portion where the Cu plating film is formed is opened.
  • the film was formed by electrolytic plating using the resist pattern 4 as a mask.
  • a Cu plating film 3 having a thickness of 300 nm or more and 30 ⁇ m or less is formed. Since this Cu plating film 3 is formed using the resist pattern as a mask and has a wiring pattern, it has a wiring pattern when plating growth is completed. Further, the plating growth speed can be increased by disposing the Cu alloy thin film 2 under the Cu plating film 3 as in the first embodiment. Also, the adhesion between the Cu alloy thin film 2 and the substrate 1 is good, as in the first embodiment, in which the adhesion between the Cu alloy thin film 2 and the Cu plating film 3 is good.
  • the resist pattern 4 is removed.
  • an etchant for etching the Cu alloy thin film 2 may be an etchant such as ferric chloride or cupric chloride. This etchant is used to etch both the Cu plating film and the Cu alloy thin film.
  • the S, Cu alloy thin film is very thin compared to the Cu plating film, and can be etched without any problem. However, it is more preferable to use an etchant having a sufficient etching selectivity between the Cu plating film and the Cu alloy thin film so that the Cu plating film is not etched when etching the Cu alloy thin film.
  • the adhesion between the Cu alloy thin film 2 and the substrate 1 is very good, and the adhesion between the Cu alloy thin film 2 and the Cu-gold film 3 is also very good.
  • the Cu alloy thin film 2 the Cu contained therein is difficult to diffuse into the substrate 1.
  • the growth rate of the Cu plating film 3 can be increased, and the throughput can be improved.
  • FIGS. 4A and 4B are cross-sectional views illustrating a method for manufacturing a circuit board according to Embodiment 3 of the present invention.
  • This circuit board has wiring patterns formed on both sides of the board 1.
  • the following Cu alloy thin film 2 is formed by sputtering.
  • the Cu alloy thin film 2 has the same alloy strength as in the first embodiment, and the substrate 1 has the same material strength as in the first embodiment.
  • the film thickness is 300 nm or more and 30 ⁇ m or less by electroplating or electroless plating on the Cu alloy thin film 2 on the front side and the back side of the substrate 1.
  • a Cu plating film 3 is formed.
  • the plating growth speed can be increased by disposing the Cu alloy thin film 2 under the Cu plating film 3.
  • the good adhesion between the Cu alloy thin film 2 and the Cu plating film 3 and the good adhesion between the Cu alloy thin film 2 and the substrate 1 is also the same as in the first embodiment.
  • the Cu plating film 3 and the Cu alloy thin film 2 are wet-etched in the same manner as in the first embodiment, so that the Cu plating films 3 and Cu A wiring pattern made of the alloy thin film 2 is formed (not shown).
  • FIGS. 5A to 5C are cross-sectional views illustrating a method for manufacturing a circuit board according to Embodiment 4 of the present invention.
  • a through hole la is formed in the board 1 and a wiring pattern is formed on both sides of the board 1.
  • a substrate 1 having a through hole la which is a through hole is prepared.
  • a Cu alloy thin film 2 having a thickness of 5 nm or more and 1 ⁇ m or less is formed on the front surface, the back surface, and in the through hole la of the substrate 1 by sputtering.
  • the Cu alloy thin film 2 has the same alloy force as in the first embodiment, and the substrate 1 is made of the same material as in the first embodiment.
  • the film thickness is formed on the Cu alloy thin film 2 on the front side, the back side, and in the through hole la of the substrate 1 by the electroplating method or the electroless plating method.
  • the plating growth rate can be increased by disposing the Cu alloy thin film 2 under the Cu plating film 3.
  • the good adhesion between the Cu alloy thin film 2 and the Cu plating film 3 and the good adhesion between the Cu alloy thin film 2 and the substrate 1 is also the same as in the first embodiment.
  • the Cu plating film 3 and the Cu alloy thin film 2 are wet-etched in the same manner as in Embodiment 1, so that the Cu plating films 3 and Cu A wiring pattern made of the alloy thin film 2 is formed (not shown).
  • FIGS. 6 (A) and 6 (B) are cross-sectional views illustrating a method for manufacturing a circuit board according to Embodiment 5 of the present invention.
  • This circuit board has a multilayer wiring structure.
  • a Cu alloy thin film 2 having a thickness of 5 nm or more and 1 ⁇ m or less is formed on a substrate 1 by sputtering, and electrolytic plating is performed on the Cu alloy thin film 2.
  • a Cu plating film 3 having a film thickness of 300 nm or more and 30 / zm or less is formed by a method or an electroless plating method.
  • a wiring pattern (not shown) composed of the Cu plating film 3 and the Cu alloy thin film 2 is formed on the substrate 1.
  • the steps so far are the same as in the first embodiment.
  • a wiring pattern composed of the Cu plating film 3 and the Cu alloy thin film 2 may be formed on the substrate 1 by the same method as in the second embodiment.
  • a polyimide polyimide varnish is applied on the wiring pattern and the substrate 1 and subjected to a heat treatment, whereby a polyimide film 10 is formed on the wiring pattern and the substrate 1.
  • the polyimide film 10 is etched to form a through hole 10a located on the wiring pattern in the polyimide film 10. If the polyimide film has photosensitivity, a through hole can be formed by exposing and developing the polyimide film.
  • a Cu alloy thin film 11 having a thickness of 5 nm or more and 1 ⁇ m or less is formed by sputtering on the bottom surface, the inner side surface, and the polyimide film 10 of the through hole 10a.
  • a Cu plating film 12 having a thickness of 300 nm or more and 30 / zm or less is formed on the Cu alloy thin film 11 by electroplating or electroless plating.
  • a wiring pattern (not shown) made of the Cu plating film 12 and the Cu alloy thin film 11 is formed on the substrate 1 by butting the Cu plating film 12 and the Cu alloy thin film 11.
  • the wiring pattern on the polyimide film 10 is connected to the wiring pattern on the substrate 1 via a through hole 10a. Note that, in the same manner as in Embodiment 2, the polyimide film 10 A wiring pattern consisting of the Cu plating film 12 and the Cu alloy thin film 11 may be formed on the top.
  • a circuit board having a multilayer wiring structure is formed by the above method.
  • the circuit board shown in FIG. 6B has a multilayer wiring structure in which two wiring layers are formed on the substrate, three or more wiring layers can be formed on the substrate. is there.
  • a multi-layer wiring structure of three or more layers can be formed by repeating the process of forming the second wiring layer shown in FIG. 6B for the third and subsequent layers.
  • the Cu alloy thin film 11 is formed in the through hole 10a by sputtering, the Cu alloy thin film 11 can be formed with a small thickness and good coverage even in the fine through hole 10a. it can. In other words, this is particularly effective when the wiring pattern is miniaturized and the through hole is miniaturized.
  • the film thickness controllability is very good.
  • the adhesiveness between the polyimide film 10 and the Cu alloy thin film 11 is very good, and the adhesiveness necessary for practical use can be sufficiently secured.
  • FIGS. 1 and 2 show a method for manufacturing a circuit board according to the first embodiment.
  • the Cu plating film 3 is formed by vacuum evaporation or electron beam evaporation.
  • Embodiment 6 is an embodiment changed to a deposited film.
  • a Cu alloy thin film 2 having a thickness of 5 nm or more and 1 ⁇ m or less is formed on a substrate 1 by sputtering.
  • the Cu alloy thin film 2 has the same alloy strength as in the first embodiment, and the substrate 1 is made of the same material as in the first embodiment.
  • the reason for using the above-described materials for the Cu alloy thin film 2 is the same as in the first embodiment. It is as follows.
  • a Cu evaporated film 3 having a thickness of 300 nm or more and 30 m or less is formed on the Cu alloy thin film 2 by a vacuum evaporation method or an electron beam evaporation method. Since the deposited Cu film 3 is pure Cu (but contains unavoidable impurities), it has a different composition from the Cu alloy thin film 2 but is homogeneous in that it contains Cu as a main component. Good for Also, the adhesion between the Cu alloy thin film 2 and the substrate 1 is very good.
  • a photoresist pattern is formed on the Cu vapor deposition film 3 by applying a photoresist film on the Cu vapor deposition film 3, exposing and developing. Is done.
  • the Cu vapor deposition film 3 and the Cu alloy thin film 2 are wetted with an etching solution such as ferric chloride, copper salt II, or the like. Touching.
  • an etching solution such as ferric chloride, copper salt II, or the like. Touching.
  • wiring patterns 5a to 5d composed of the Cu vapor deposition film 3 and the Cu alloy thin film 2 are formed on the substrate 1.
  • the Cu vapor deposition film 3 which is pure Cu and the Cu alloy thin film 2 having the above-described composition can be etched with an etching solution such as ferric chloride, cupric chloride, and the like, and have substantially the same etching rate. Further, the Cu alloy thin film has no difference in chemical reaction from pure Cu, and does not cause a problem such as residue.
  • an Au plating film 7 is formed on the wiring patterns 5a to 5d.
  • step (1) the semiconductor chip 8 is aligned on the circuit board, the Au bump 9 is arranged on the wiring pattern, and the wiring pattern on the board and the semiconductor chip are thermocompressed. As a result, the wiring pattern is bonded to the Au bump, and the semiconductor chip is mounted on the circuit board.
  • the adhesion between the Cu alloy thin film 2 and the substrate 1 is very good, and the adhesion between the Cu alloy thin film 2 and the deposited Cu film 3 is also very good.
  • the Cu alloy thin film 2 is one in which Cu contained therein is difficult to diffuse into the substrate 1.
  • the Cu vapor deposition film 3 and the Cu alloy thin film 2 can be etched by one wet etching, and there is no problem such as an etching residue. Therefore, the throughput in the etching step can be improved.
  • the following advantages are obtained by using the Cu vapor deposition film 3.
  • the crystal grain size of Cu in the pure Cu deposited film 3 formed by the vacuum evaporation method or the electron beam evaporation method is smaller than that of the Cu plating film formed by the electroplating method or the electroless plating method. Therefore, a dense film having a high particle density can be obtained.
  • the formation of the Cu alloy thin film 2 by sputtering and the formation of the Cu vapor deposition film 3 by vapor deposition can be continuously performed by one apparatus. In this way, continuous film formation with one device can realize a very cost-effective process with extremely high productivity.
  • the Cu vapor deposited film 3 formed by the vapor deposition method has a finer and more dense grain size than the Cu plated films formed by various plating methods. For this reason, when the Cu vapor-deposited film 3 is wet-etched, it is possible to obtain fine and fine wiring patterns 5a-5d whose surface and cross-section are extremely flat as compared with the case of Cu-plated films formed by various plating methods. In particular, in the case of a wiring pattern having a line or space of 20 / zm or less in width, the reliability of the wiring pattern itself such as migration or disconnection is superior.
  • the skin effect means that the high-frequency current is concentrated on the conductor surface, and in particular, the high-frequency current flows only on the conductor surface with a thickness of about 1 ⁇ m. From this, the noise of the current flowing through the wiring pattern having an uneven surface when viewed microscopically is relatively long and the resistance value increases. Therefore, the path of the current flowing through the wiring pattern having excellent surface flatness does not become longer and the resistance value does not increase as compared with the case where there are concave and convex portions. Therefore, the Cu vapor deposition film 3 having excellent flatness is advantageous in the skin effect.
  • FIG. 4 shows a method for manufacturing a circuit board according to the third embodiment.
  • the Cu plating film 3 is changed to a Cu vapor deposition film formed by a vacuum vapor deposition method or an electron beam vapor deposition method. This is the seventh embodiment.
  • a Cu alloy thin film 2 having a thickness of 5 nm or more and 1 ⁇ m or less is formed on the front surface and the back surface of the substrate 1 by sputtering.
  • the Cu alloy thin film 2 has the same alloy strength as in the first embodiment, and the substrate 1 has the same material strength as in the first embodiment.
  • the film thickness is 300 nm or more and 30 ⁇ m or less on the Cu alloy thin film 2 on the front side and the back side of the substrate 1 by vacuum evaporation or electron beam evaporation.
  • a Cu vapor deposition film 3 is formed. Good adhesion between the Cu alloy thin film 2 and the deposited Cu film 3 Good adhesion between the Cu alloy thin film 2 and the substrate 1 is the same as in the sixth embodiment.
  • the Cu vapor deposition film 3 and the Cu alloy thin film 2 are wet-etched by the same method as in the sixth embodiment, so that the Cu vapor deposition film 3 and Cu A wiring pattern made of the alloy thin film 2 is formed (not shown).
  • FIG. 5 shows a method of manufacturing a circuit board according to the fourth embodiment.
  • the Cu plating film 3 is changed to a Cu deposition film formed by a vacuum deposition method or an electron beam deposition method. This is the eighth embodiment.
  • a substrate 1 having a through hole la as a through hole is prepared.
  • a Cu alloy thin film 2 having a thickness of 5 nm or more and 1 ⁇ m or less is formed on the front surface, the back surface, and in the through hole la of the substrate 1 by sputtering.
  • the Cu alloy thin film 2 has the same alloy force as in the first embodiment, and the substrate 1 is made of the same material as in the first embodiment.
  • the film thickness is formed on the Cu alloy thin film 2 on the front side, the back side, and the through hole la of the substrate 1 by a vacuum evaporation method or an electron beam evaporation method.
  • the Cu vapor deposition film 3 and the Cu alloy thin film 2 are wet-etched in the same manner as in Embodiment 6, so that the Cu vapor deposition film 3 and the Cu vapor deposition film 3 and Cu A wiring pattern made of the alloy thin film 2 is formed (not shown).
  • FIG. 6 shows a method of manufacturing a circuit board according to the fifth embodiment.
  • Cu plating films 3 and 12 are formed on a Cu vapor deposition film formed by a vacuum vapor deposition method or an electron beam vapor deposition method.
  • the modified embodiment is the ninth embodiment.
  • a Cu alloy thin film 2 having a thickness of 5 nm to 1 ⁇ m is formed on a substrate 1 by sputtering, and is vacuum-deposited on the Cu alloy thin film 2.
  • a Cu vapor deposition film 3 having a thickness of 300 nm or more and 30 m or less is formed by a method or an electron beam vapor deposition method.
  • a wiring pattern (not shown) composed of the Cu deposited film 3 and the Cu alloy thin film 2 is formed on the substrate 1. The steps so far are the same as in the sixth embodiment.
  • a polyimide film 10 is formed on the wiring pattern and the substrate 1 by the same method as in the fifth embodiment, and a through hole 10a located on the wiring pattern is formed in the polyimide film 10.
  • a Cu alloy thin film 11 having a thickness of 5 nm or more and 1 ⁇ m or less is formed by sputtering on the bottom surface, the inner side surface of the through hole 10a, and the polyimide film 10;
  • a Cu evaporated film 12 having a thickness of 300 nm or more and 30 m or less is formed by a vacuum evaporation method or an electron beam evaporation method.
  • the Cu deposited film 12 and the Cu alloy thin film 11 are not-turned, so that the Cu deposited film 12 and the Cu alloy thin film 11 are formed on the substrate 1.
  • Wiring pattern (not shown) is formed. These steps use the same method as in the sixth embodiment.
  • the wiring pattern on the polyimide film 10 is connected to the wiring pattern on the substrate 1 via through holes 10a.
  • a circuit board having a multilayer wiring structure is formed by the above method.
  • the circuit board shown in FIG. 6B has a multilayer wiring structure in which two wiring layers are formed on the substrate, three or more wiring layers can be formed on the substrate. is there.
  • a multi-layer wiring structure of three or more layers can be formed by repeating the process of forming the second wiring layer shown in FIG. 6B for the third and subsequent layers.
  • the Cu alloy thin film 11 is formed in the through hole 10a by sputtering, the Cu alloy thin film 11 can be formed with a small thickness and good coverage even in the fine through hole 10a. it can. In other words, this is particularly effective when the wiring pattern is miniaturized and the through hole is miniaturized.
  • the film thickness controllability is very good.
  • the adhesiveness between the polyimide film 10 and the Cu alloy thin film 11 is very good, and the adhesiveness necessary for practical use can be sufficiently secured.
  • the semiconductor chip 8 of the first embodiment can be mounted on the circuit board having wiring patterns on both surfaces according to the third and seventh embodiments by using the same method as that of the first embodiment.
  • the semiconductor chip 8 of the first embodiment can be mounted on the circuit board having the through holes la according to the fourth and eighth embodiments by using the same method as that of the first embodiment.
  • the semiconductor chip 8 of the first embodiment can be mounted on the circuit board having the multilayer wiring structure according to the fifth and ninth embodiments using the same method as that of the first embodiment. is there.
  • the multilayer wiring structure according to the fifth and ninth embodiments on the circuit board according to the third and seventh embodiments.
  • the multilayer wiring structure may be either double-sided or single-sided.
  • the multilayer wiring structure according to the fifth and ninth embodiments on the circuit board according to the fourth and eighth embodiments.
  • the multilayer wiring structure may be either double-sided or single-sided.
  • the multilayer wiring structure is provided on one side of the substrate 1, but it is also possible to provide the multilayer wiring structure on both sides of the substrate 1.
  • the substrate 1 formed of a polymer material or a resin material such as polyimide, liquid crystal polymer, Teflon (registered trademark) or epoxy resin is used.
  • the material of the substrate is not limited to those described above, and the material of the substrate can be variously changed to carry out the invention.
  • Al O or a composite oxide containing Al O as a main raw material
  • Ceramics such as A1N, SiO, etc., paper-based phenol (fat copper-clad laminate, paper-based epoxy)
  • Fat-clad laminates synthetic fiber cloth-based epoxy-clad copper-clad laminates, glass cloth ⁇ Paper composite base epoxy-fat-copper-clad laminates, glass cloth ⁇ Glass nonwoven composite base epoxy-fat-copper-clad laminates , Glass cloth-based epoxy resin-clad laminate, glass-based polyimide resin-clad laminate, glass substrate BT resin-clad laminate, glass-based fluorine resin-clad laminate, glass base It is also possible to use a substrate such as a heat-hardened PPO / copper-clad laminate.
  • the bond strength of this metal laminate / resin base material under normal conditions and the bond strength of the metal layer and the resin base material after being exposed to an environment of 121 ° C and 100% RH for 96 hours are determined according to JIS and C-6481. Evaluated by a 90 degree peel test method at 50 m. [0117] In the evaluation of the examples, the test base materials prepared are as shown in Table 1.
  • the composition of the undercoat film in Table 1 is as follows.
  • Example 14 shows an alloy containing 0.5 to 5% by weight of Ti and the balance being Cu.
  • Examples 5 to 8 contain 0.5 to 5% by weight of Mo.
  • Example 9-12 contains 0.5 to 5% by weight of Ni, and the remainder is an alloy composed of Cu
  • Example 13-16 contains an alloy of 0.5 to 5% by weight of A1.
  • the balance is an alloy composed of Cu
  • Examples 17-20 are alloys containing 0.5 to 5% by weight of Ag and the balance composed of Cu.
  • test substrates as comparative examples shown in Table 2 were prepared. [0119] [Table 2]
  • Table 3 shows the results of the evaluation.
  • Comparative Example 6 4.8.1 .3
  • at least one or more metals are contained at 0.5 to 5% by weight of Cu, Ti, Mo, Ni, Al, and Ag as main components.
  • Circuit boards made by forming an underlayer on the upper layer of various resin base materials using an alloy material by a sputtering method and then forming pure Cu by an evaporation method have high adhesion, and Since there is little change with time after PCT, it is stable regardless of the environment, and it is confirmed that high reliability as a circuit board can be obtained.
  • the normal state of adhesion and the results after PCT sufficiently ensure industrial utility, but metal Cr binds to oxygen during etching.
  • Hexavalent chromium is generated, and this hexavalent chromium is extremely toxic in the environment. It is specified especially in the PRTR regulations and the RoHS regulations. However, the use is being abolished. This is the same for NiCr which has been conventionally used industrially in the prior art of the present invention, and it can be confirmed that the present invention has many environmental advantages in addition to technical advantages.
  • the vacuum evaporation method is a technique in which a metal or nonmetal is heated and evaporated in a vacuum, and is coated on a metal, glass, or plastic surface to form a thin film.
  • a metal or nonmetal is heated and evaporated in a vacuum, and is coated on a metal, glass, or plastic surface to form a thin film.
  • the molten state of the material occurs during the process of heating and evaporating metal, so the material is put into a crucible and melted and evaporated, and the evaporated atoms and molecules are attached to the substrate above and coated. are doing.
  • Forming a circuit board by this method has been a standard in the past, but the conventional technology has not been able to establish a material technology, so it has not been put to practical use. I could't stand. Therefore, by using the underlayer of the present invention, it will be practically used for the first time in industry, and it is a fact that the superiority of the present invention can be confirmed.
  • the effect of forming the pure Cu layer by the vapor deposition method is that, compared to the conventional plating method or the method of laminating copper foil, the circuit is formed by forming a fine layer with fine particles. This improves the reliability of the wiring / electrode to be used.
  • this metal laminate was alternately combined with a comb-shaped electrode wiring pattern having a width of 20 ⁇ m so that the electrode wirings did not contact each other, as shown in FIG.
  • the line widths of A to F and a to f are all 20 ⁇ m.
  • a to F and a to f are all equally spaced 40 ⁇ m.
  • All uppercase and lowercase lines such as A, a, B, and b are equally spaced 20 z m.
  • metal standard electrode potential of copper Cu 2 + at + 0.337V (how represents indicating a difference with respect to the potential of the standard hydrogen electrode "Standard Hydrogen Elect rode”.), Cu + in + 0.520V (vs .SHE) in aqueous solution.
  • copper ions are eluted even at around 1 VDC below the theoretical voltage at which water is electrolyzed, but the higher the voltage, the greater the amount of copper ions eluted.
  • the composition of the sputter layer of the test substrate in Table 4 is an alloy containing 0.5 to 5% by weight of Mo and the balance being Cu.
  • FIG. 8 is a schematic diagram illustrating the mechanism of ion migration.
  • a DC bias voltage is applied to the ⁇ electrode! /, In the case of! /,
  • the part which should be an insulating layer originally has the property of electrolyte due to moisture and ionic residue.
  • the electrode metal is eluted anodicly in the region of ionization due to the relationship between the potential specific to the electrode metal and the pH (pH).
  • pH pH
  • Many are distinguished by the case where this is reduced by precipitation during the growth process or reduced by force sword.
  • the place of occurrence is found on the surface of the insulating layer, at the interface of the insulating layer, between layers, etc., and this extends and leads to a short circuit between the electrodes.
  • FIG. 1 (A) to (E) are cross-sectional views illustrating a method of manufacturing a circuit board according to Embodiment 1 of the present invention and mounting electronic components on the circuit board.
  • FIG. 2 (A) and (B) show a method of manufacturing a circuit board according to Embodiment 1 of the present invention and mounting electronic components on the circuit board.
  • FIG. 6 is a cross-sectional view showing the next step. .
  • FIG. 3 (A) to (E) are sectional views showing a method of manufacturing a circuit board according to Embodiment 2 of the present invention.
  • FIGS. 4A and 4B are cross-sectional views illustrating a method of manufacturing a circuit board according to Embodiment 3 of the present invention.
  • FIG. 5 (A) -1 (C) are cross-sectional views illustrating a method for manufacturing a circuit board according to Embodiment 4 of the present invention.
  • FIGS. 6A and 6B are cross-sectional views illustrating a method of manufacturing a circuit board according to Embodiment 5 of the present invention.
  • FIG. 7 is a schematic diagram illustrating an experiment method of migration resistance.
  • FIG. 8 is a schematic diagram illustrating a mechanism of ion migration.
  • FIGS. 9A and 9B are cross-sectional views illustrating a conventional method for manufacturing a circuit board.
  • (A) and (B) are cross-sectional views illustrating another conventional circuit board manufacturing method.

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Abstract

[PROBLEMS] Disclosed is a circuit board wherein adhesion between a substrate and a Cu film can be sufficiently secured. Also disclosed is a method for manufacturing such a circuit board. [MEANS FOR SOLVING PROBLEMS] A circuit board comprising a substrate (1), a Cu alloy thin film (2) formed on the substrate (1), and a Cu plating film (3) with a thickness of not less than 300 nm and not more than 30 μm which is formed on the Cu alloy thin film (2) is characterized in that the Cu alloy thin film (2) is composed of an alloy mainly containing Cu and further containing at least one element selected from the group consisting of Ti, Mo, Ni, Al and Ag in a total amount of 0.5-5.0 wt% and has a thickness of not less than 5 nm and not more than 1 μm. With such a constitution, adhesion between the substrate and the Cu film can be sufficiently secured.

Description

明 細 書  Specification
回路基板及びその製造方法  Circuit board and method of manufacturing the same
技術分野  Technical field
[0001] 本発明は、回路基板及びその製造方法に係わり、特に、基板と Cu膜との密着性を 十分に確保できる回路基板及びその製造方法、エッチング残渣の発生を抑制できる 回路基板及びその製造方法に関する。  The present invention relates to a circuit board and a method for manufacturing the same, and more particularly, to a circuit board and a method for manufacturing the same, which can ensure sufficient adhesion between the substrate and the Cu film, a circuit board capable of suppressing generation of etching residues, and a method for manufacturing the same About the method.
背景技術  Background art
[0002] 図 9 (A) , (B)は、従来の回路基板の製造方法を示す断面図である。  FIGS. 9A and 9B are cross-sectional views illustrating a conventional method for manufacturing a circuit board.
まず、図 9 (A)に示すように、ポリイミド基板 101の上に Cr、 Ni等力もなる下地膜 10 2を形成する。次いで、この下地膜 102の上に電界鍍金法により Cu鍍金膜 103を形 成する。 Cu鍍金膜 103とポリイミド基板 101との間に下地膜 102を配置することにより 、下地膜 102が Cu鍍金膜とポリイミド基板との密着層として作用すると共に、 Cu鍍金 膜中の Cuがポリイミド基板に拡散するのを抑制するバリア層としても作用する。  First, as shown in FIG. 9A, a base film 102 having a strength such as Cr and Ni is formed on a polyimide substrate 101. Next, a Cu plating film 103 is formed on the base film 102 by an electrolytic plating method. By disposing the base film 102 between the Cu plating film 103 and the polyimide substrate 101, the base film 102 acts as an adhesion layer between the Cu plating film and the polyimide substrate, and Cu in the Cu plating film is transferred to the polyimide substrate. It also acts as a barrier layer that suppresses diffusion.
[0003] 次に、図 9 (B)に示すように、 Cu鍍金膜 103の上にフォトレジスト膜（図示せず)を塗 布し、露光及び現像することにより、 Cu鍍金膜 103の上にはレジストパターン（図示 せず）が形成される。次いで、このレジストパターンをマスクとして Cu鍍金膜 103及び 下地膜 102をウエットエッチングすることにより、ポリイミド基板 101の上には Cu鍍金 膜及び下地膜からなる配線パターン 104a— 104dが形成される。  [0003] Next, as shown in FIG. 9 (B), a photoresist film (not shown) is applied on the Cu plating film 103, and is exposed and developed, so that the Cu plating film 103 is exposed. A resist pattern (not shown) is formed. Next, the Cu plating film 103 and the base film 102 are wet-etched using the resist pattern as a mask, whereby wiring patterns 104a to 104d composed of the Cu plating film and the base film are formed on the polyimide substrate 101.
[0004] ところで、上記従来の回路基板では、密着層として作用する Cr、 Ni等からなる下地 膜 102を Cu鍍金膜 103とポリイミド基板 101との間に配置している力 配線パターン 104a— 104dの微細化が進むに従い、前記下地膜では密着性を十分に確保するこ とができない。  By the way, in the above-mentioned conventional circuit board, a base film 102 made of Cr, Ni or the like acting as an adhesion layer is disposed between the Cu plating film 103 and the polyimide substrate 101. As the miniaturization progresses, it is not possible to ensure sufficient adhesion with the underlayer.
[0005] また、下地膜 102の抵抗値が比較的に高いため、 Cu鍍金膜の成長速度が低いと いう問題がある。  [0005] Furthermore, since the resistance value of the underlying film 102 is relatively high, there is a problem that the growth rate of the Cu plating film is low.
[0006] また、 Cu鍍金膜 103と下地膜 102をウエットエッチングしてパターユングする際、 C u鍍金膜と下地膜では材質が異なるためエッチング性が異なる。従って、 Cu鍍金膜と 下地膜を同一条件で 1回のエッチングによりパターユングを行うとエッチング残渣が 残ってしまい、それによつて配線間のショート、マイグレーション等の問題が発生する ことがある。これに対し、エッチング残渣が残らないようにするため、 Cu鍍金膜と下地 膜を別々の条件で 2回のエッチングによりパターユングを行うことも可能である力 こ の場合はエッチング工程の時間が長くなりスループットが低くなるという問題が生じる [0006] Further, when the Cu plating film 103 and the underlying film 102 are wet-etched and puttering, the Cu plating film and the underlying film have different etching properties due to different materials. Therefore, if the patterning is performed by etching once for the Cu plating film and the underlying film under the same conditions, etching residues are generated. This may cause problems such as short-circuiting between wirings, migration, and the like. On the other hand, in order to prevent the etching residue from remaining, it is also possible to perform pattern junging by etching the Cu plating film and the base film twice under different conditions. The problem of low throughput
[0007] 図 10 (A) , (B)は、他の従来の回路基板の製造方法を示す断面図である。この他 の従来の回路基板の製造方法は、図 9に示す従来の回路基板の製造方法における 鍍金の成長速度が低 ヽと、う問題を解決するものである。 FIGS. 10A and 10B are cross-sectional views showing another conventional method for manufacturing a circuit board. The other conventional circuit board manufacturing method solves the problem that the plating growth rate in the conventional circuit board manufacturing method shown in FIG. 9 is low.
[0008] まず、図 10 (A)に示すように、ポリイミド基板 101の上に Cr、 Ni等力もなる下地膜 1 02を形成する。次いで、この下地膜 102の上にスパッタリングにより Cu膜 105を形成 する。次いで、この Cu膜 105の上に電界鍍金法により Cu鍍金膜 103を形成する。  First, as shown in FIG. 10A, a base film 102 having a strength such as Cr and Ni is formed on a polyimide substrate 101. Next, a Cu film 105 is formed on the base film 102 by sputtering. Next, a Cu plating film 103 is formed on the Cu film 105 by an electrolytic plating method.
[0009] 次に、図 10 (B)に示すように、 Cu鍍金膜 103の上にフォトレジスト膜（図示せず）を 塗布し、露光及び現像することにより、 Cu鍍金膜 103の上にはレジストパターン（図 示せず）が形成される。次いで、このレジストパターンをマスクとして Cu鍍金膜 103、 Cu膜 105及び下地膜 102をエッチングすることにより、ポリイミド基板 101の上には C u鍍金膜、 Cu膜及び下地膜からなる配線パターン 106a— 106dが形成される。  Next, as shown in FIG. 10B, a photoresist film (not shown) is applied on the Cu plating film 103, and is exposed and developed, so that the Cu plating film 103 A resist pattern (not shown) is formed. Next, by using the resist pattern as a mask, the Cu plating film 103, the Cu film 105, and the base film 102 are etched to form a wiring pattern 106a-106d composed of a Cu plating film, a Cu film, and a base film on the polyimide substrate 101. Is formed.
[0010] 上記他の従来の回路基板では、 Cu鍍金膜 103の下に Cu膜 105を形成しているた め、図 9の従来の回路基板より Cu鍍金膜 103の成長速度を速くすることができる。し 力しながら、図 9の回路基板に比べて膜の数が多くなるため、工程数が増えてスルー プットが低くなる。その上、下地膜による密着性とエッチング残渣については図 9の回 路基板と同様の問題がある。  [0010] In the other conventional circuit board described above, since the Cu film 105 is formed under the Cu plating film 103, the growth rate of the Cu plating film 103 can be made faster than that of the conventional circuit board in FIG. it can. However, since the number of films is larger than that of the circuit board in Fig. 9, the number of processes is increased and the throughput is reduced. In addition, there are problems similar to those of the circuit substrate shown in FIG.
発明の開示  Disclosure of the invention
発明が解決しょうとする課題  Problems to be solved by the invention
[0011] 前述した通り、従来及び他の従来の回路基板では、 Cr、 Ni等力もなる下地膜 102 による密着性が不十分であること、エッチング残渣が生じることと 、つた問題がある。 [0011] As described above, the conventional and other conventional circuit boards have the following problems: insufficient adhesion due to the underlying film 102 having a strength such as Cr and Ni; and the generation of etching residues.
[0012] 本発明は上記のような事情を考慮してなされたものであり、その目的は、基板と Cu 膜との密着性を十分に確保できる回路基板及びその製造方法を提供することにあるThe present invention has been made in view of the above circumstances, and an object of the present invention is to provide a circuit board capable of sufficiently securing the adhesion between a substrate and a Cu film, and a method for manufacturing the same.
。また、本発明の他の目的は、エッチング残渣の発生を抑制できる回路基板及びそ の製造方法を提供することにある。 . Another object of the present invention is to provide a circuit board and a circuit board capable of suppressing generation of an etching residue. It is to provide a manufacturing method of.
課題を解決するための手段  Means for solving the problem
[0013] 上記課題を解決するため、本発明に係る回路基板は、基板と、  [0013] In order to solve the above problems, a circuit board according to the present invention comprises:
前記基板上に形成された薄膜と、  A thin film formed on the substrate,
を具備する回路基板であって、  A circuit board comprising:
前記薄膜は、 Cuを主成分とし、 Ti、 Mo、 Ni、 A1及び Ag力 なる群力 選ばれた少 なくとも 1種類の元素を合計で 0.5— 5.(^％含有してなる合金カゝらなることを特徴と する。  The thin film is made of an alloy containing Cu as a main component, and a group force of Ti, Mo, Ni, A1, and Ag forces. It is characterized by consisting of
[0014] 上記回路基板によれば、薄膜と基板との密着性が良ぐこの薄膜上に電界鍍金法 、無電界鍍金法、真空蒸着法又は電子ビーム蒸着法により Cu膜を形成する場合、 前記薄膜は前記 Cu膜との密着性も良い。従って、基板上に薄膜を形成した回路基 板を用いることにより、基板と Cu膜との密着性を十分に確保することが可能となる。  According to the above circuit board, when a Cu film is formed on this thin film having good adhesion between the thin film and the substrate by electroplating, electroless plating, vacuum evaporation or electron beam evaporation, The thin film has good adhesion to the Cu film. Therefore, by using a circuit board in which a thin film is formed on a substrate, it is possible to sufficiently secure the adhesion between the substrate and the Cu film.
[0015] 本発明に係る回路基板は、基板と、 [0015] A circuit board according to the present invention includes:
前記基板上に形成された薄膜と、  A thin film formed on the substrate,
を具備する回路基板であって、  A circuit board comprising:
前記薄膜は、 Ti、 Mo、 Ni、 A1及び Ag力 なる群力 選ばれた少なくとも 1種類の 元素を合計で 0.5— 5.(^％含有し、残部が Cuからなる合金力もなることを特徴とす る。  The thin film contains at least one element selected from the group consisting of Ti, Mo, Ni, A1, and Ag forces in an amount of 0.5-5. (^% In total, and has an alloying force consisting of Cu in the balance. You.
[0016] また、本発明に係る回路基板においては、前記薄膜の膜厚が 5nm以上 1 μ m以下 であることが好ましい。  Further, in the circuit board according to the present invention, it is preferable that the thickness of the thin film is 5 nm or more and 1 μm or less.
また、本発明に係る回路基板においては、前記薄膜上に形成された膜厚が 300η m以上 30 m以下の Cu膜をさらに具備することも可能である。薄膜と Cu膜との密着 性が良いため、基板と Cu膜との密着性を十分に確保できる。  The circuit board according to the present invention may further include a Cu film formed on the thin film and having a thickness of 300 ηm or more and 30 m or less. Since the adhesion between the thin film and the Cu film is good, the adhesion between the substrate and the Cu film can be sufficiently ensured.
[0017] 本発明に係る回路基板は、基板と、 [0017] A circuit board according to the present invention includes:
前記基板上にスパッタリングにより形成された薄膜と、  A thin film formed by sputtering on the substrate,
前記薄膜上に真空蒸着法又は電子ビーム蒸着法により形成された Cu膜と、 を具備する回路基板であって、  A Cu film formed on the thin film by a vacuum evaporation method or an electron beam evaporation method, a circuit board comprising:
前記薄膜は、 Cuを主成分とし、 Ti、 Mo、 Ni、 A1及び Ag力 なる群力 選ばれた少 なくとも 1種類の元素を合計で 0.5— 5.(^％含有してなる合金カゝらなり、膜厚が 5nm 以上 1 m以下であり、 The thin film is mainly composed of Cu, and has a group strength of Ti, Mo, Ni, A1, and Ag forces. It is an alloy containing at least one element in a total of 0.5—5 (^%, and the film thickness is 5 nm or more and 1 m or less,
前記薄膜及び前記 Cu膜は、表皮効果に伴う伝播損失を低減又は削減するもので あることを特徴とする。  The thin film and the Cu film are characterized by reducing or reducing propagation loss accompanying a skin effect.
[0018] 上記回路基板によれば、薄膜と基板との密着性が良ぐ薄膜は Cu膜との密着性も 良い。従って、基板と Cu膜との密着性を十分に確保することができる。また、真空蒸 着法又は電子ビーム蒸着法にて微細な粒子からなる緻密な Cu膜を形成することが できる。この Cu膜は表面の平坦性に優れた膜になるために表皮効果にお!、て有利 である。表皮効果とは、高周波電流が導体表面に集中することである。このことから、 ミクロ的に見て凹凸のある表面を有する配線パターンを流れる電流のパスは相対的 に長く抵抗値が増える。このため、表面の平坦性に優れた配線パターンを流れる電 流のパスは凹凸のある場合に比べて長くならず抵抗値が増えることもない。従って、 平坦性に優れた Cu膜では表皮効果において有利となる。  According to the circuit board, a thin film having good adhesion between the thin film and the substrate has good adhesion with the Cu film. Therefore, sufficient adhesion between the substrate and the Cu film can be ensured. Further, a dense Cu film composed of fine particles can be formed by a vacuum evaporation method or an electron beam evaporation method. This Cu film has an excellent skin effect because it has excellent surface flatness. The skin effect means that high-frequency current is concentrated on the conductor surface. From this, the path of the current flowing through the wiring pattern having the uneven surface when viewed microscopically is relatively long and the resistance value increases. Therefore, the path of the current flowing through the wiring pattern having excellent surface flatness does not become longer and the resistance value does not increase as compared with the case where there is unevenness. Therefore, a Cu film having excellent flatness is advantageous in skin effect.
[0019] 本発明に係る回路基板は、基板と、  [0019] A circuit board according to the present invention includes:
前記基板上に形成された配線パターンと、  A wiring pattern formed on the substrate,
を具備する回路基板であって、  A circuit board comprising:
前記配線パターンは、薄膜と、該薄膜上に形成された Cu膜とを有し、  The wiring pattern has a thin film and a Cu film formed on the thin film,
前記薄膜は、 Cuを主成分とし、 Ti、 Mo、 Ni、 A1及び Ag力 なる群力 選ばれた少 なくとも 1種類の元素を合計で 0.5— 5.(^％含有してなる合金カゝらなり、膜厚が 5nm 以上 1 μ m以下であることを特徴とする。  The thin film is made of an alloy containing Cu as a main component, and a group force of Ti, Mo, Ni, A1, and Ag forces. And a film thickness of 5 nm or more and 1 μm or less.
[0020] 本発明に係る回路基板は、基板と、 [0020] A circuit board according to the present invention includes:
前記基板上に形成された第 1の配線パターンと、  A first wiring pattern formed on the substrate,
前記第 1の配線パターン及び前記基板の上に形成された絶縁膜と、  An insulating film formed on the first wiring pattern and the substrate,
前記絶縁膜上に形成された第 2の配線パターンと、  A second wiring pattern formed on the insulating film,
を具備する回路基板であって、  A circuit board comprising:
前記第 1の配線パターンは、第 1の薄膜と、該第 1の薄膜上に形成された第 1の Cu 膜とを有し、  The first wiring pattern has a first thin film, and a first Cu film formed on the first thin film,
前記第 2の配線パターンは、第 2の薄膜と、該第 2の薄膜上に形成された第 2の Cu 膜とを有し、 The second wiring pattern includes a second thin film and a second Cu formed on the second thin film. And a membrane,
前記第 1の薄膜は、 Cuを主成分とし、 Ti、 Mo、 Ni、 A1及び Ag力 なる群力 選ば れた少なくとも 1種類の元素を合計で 0.5— 5.0wt%含有してなる合金カゝらなり、膜厚 力 S5nm以上 1 μ m以下であり、  The first thin film is made of an alloy containing Cu as a main component and a group force of Ti, Mo, Ni, A1, and Ag forces. The film thickness is S5 nm or more and 1 μm or less,
前記第 2の薄膜は、 Cuを主成分とし、 Ti、 Mo、 Ni、 A1及び Ag力 なる群力 選ば れた少なくとも 1種類の元素を合計で 0.5— 5.0wt%含有してなる合金カゝらなり、膜厚 力 nm以上 1 μ m以下であることを特徴とする。  The second thin film is an alloy powder containing Cu as a main component and a group force of Ti, Mo, Ni, A1, and Ag forces. And the film thickness is not less than nm and not more than 1 μm.
[0021] 本発明に係る回路基板は、基板と、 [0021] A circuit board according to the present invention includes:
前記基板の表面上に形成された第 1の薄膜と、  A first thin film formed on the surface of the substrate,
前記基板の裏面上に形成された第 2の薄膜と、  A second thin film formed on the back surface of the substrate,
を具備する回路基板であって、  A circuit board comprising:
前記第 1の薄膜は、 Cuを主成分とし、 Ti、 Mo、 Ni、 A1及び Ag力 なる群力 選ば れた少なくとも 1種類の元素を合計で 0.5— 5.0wt%含有してなる合金カゝらなり、膜厚 力 S5nm以上 1 μ m以下であり、  The first thin film is made of an alloy containing Cu as a main component and a group force of Ti, Mo, Ni, A1, and Ag forces. The film thickness is S5 nm or more and 1 μm or less,
前記第 2の薄膜は、 Cuを主成分とし、 Ti、 Mo、 Ni、 A1及び Ag力 なる群力 選ば れた少なくとも 1種類の元素を合計で 0.5— 5.0wt%含有してなる合金カゝらなり、膜厚 力 nm以上 1 μ m以下であることを特徴とする。  The second thin film is an alloy powder containing Cu as a main component and a group force of Ti, Mo, Ni, A1, and Ag forces. And the film thickness is not less than nm and not more than 1 μm.
[0022] また、本発明に係る回路基板において、前記薄膜は、前記基板と前記 Cu膜との密 着性を助長するための下地であることも可能である。 Further, in the circuit board according to the present invention, the thin film may be a base for promoting adhesion between the substrate and the Cu film.
[0023] また、本発明に係る回路基板にお 、て、前記基板にはスルーホールが設けられて いることも可能である。 Further, in the circuit board according to the present invention, the board may be provided with a through hole.
[0024] また、本発明に係る回路基板にお ヽて、前記基板は高分子材料、榭脂材料又はセ ラミック材料からなることも可會である。  [0024] Further, in the circuit board according to the present invention, the substrate may be made of a polymer material, a resin material, or a ceramic material.
[0025] また、本発明に係る回路基板においては、前記高分子材料がポリイミド、液晶ポリマ 一、テフロン (登録商標)及びエポキシ榭脂からなる群力も選ばれた一つであることも 可能である。 In the circuit board according to the present invention, the polymer material may be one selected from the group consisting of polyimide, liquid crystal polymer, Teflon (registered trademark) and epoxy resin. .
[0026] 本発明に係る回路基板の製造方法は、基板上にスパッタリングにより薄膜を形成す る工程を具備する回路基板の製造方法であって、 前記薄膜は、 Cuを主成分とし、 Ti、 Mo、 Ni、 A1及び Ag力 なる群力 選ばれた少 なくとも 1種類の元素を合計で 0.5— 5.(^％含有してなる合金カゝらなることを特徴と する。 [0026] A method for manufacturing a circuit board according to the present invention is a method for manufacturing a circuit board, comprising a step of forming a thin film on a substrate by sputtering. The thin film is made of an alloy containing Cu as a main component, and a group force of Ti, Mo, Ni, A1, and Ag forces. It is characterized by consisting of
[0027] 本発明に係る回路基板の製造方法は、基板上にスパッタリングにより薄膜を形成す る工程を具備する回路基板の製造方法であって、  [0027] A method for manufacturing a circuit board according to the present invention is a method for manufacturing a circuit board, comprising a step of forming a thin film on a substrate by sputtering.
前記薄膜は、 Ti、 Mo、 Ni、 A1及び Ag力 なる群力 選ばれた少なくとも 1種類の 元素を合計で 0.5— 5.(^％含有し、残部が Cuからなる合金力もなることを特徴とす る。  The thin film contains at least one element selected from the group consisting of Ti, Mo, Ni, A1, and Ag forces in an amount of 0.5-5. (^% In total, and has an alloying force consisting of Cu in the balance. You.
[0028] また、本発明に係る回路基板の製造方法は、膜厚が 5nm以上 1 μ m以下であるこ とが好ましい。  In the method for manufacturing a circuit board according to the present invention, the film thickness is preferably 5 nm or more and 1 μm or less.
また、本発明に係る回路基板の製造方法においては、前記薄膜を形成する工程の 後に、前記薄膜上に電界鍍金法又は無電界鍍金法により膜厚が 300nm以上 30 m以下の Cu膜を形成する工程をさらに具備することも可能である。  In the method of manufacturing a circuit board according to the present invention, after the step of forming the thin film, a Cu film having a thickness of 300 nm or more and 30 m or less is formed on the thin film by an electroplating method or an electroless plating method. The method may further include a step.
[0029] また、本発明に係る回路基板の製造方法においては、前記薄膜を形成する工程の 後に、前記薄膜上に真空蒸着法又は電子ビーム蒸着法により膜厚が 300nm以上 3 0 μ m以下の Cu膜を形成する工程をさらに具備することも可能である。  Further, in the method for manufacturing a circuit board according to the present invention, after the step of forming the thin film, a film thickness of 300 nm or more and 30 μm or less is formed on the thin film by a vacuum evaporation method or an electron beam evaporation method. The method may further include a step of forming a Cu film.
[0030] 本発明に係る回路基板の製造方法は、基板上にスパッタリングにより薄膜を形成す る工程と、  [0030] The method for manufacturing a circuit board according to the present invention includes the steps of: forming a thin film on the substrate by sputtering;
前記薄膜上に電界鍍金法又は無電界鍍金法により膜厚が 300nm以上 30 μ m以 下の Cu膜を形成する工程と、  Forming a Cu film having a thickness of 300 nm or more and 30 μm or less on the thin film by electroplating or electroless plating,
前記 Cu膜及び前記薄膜をエッチング加工することにより、前記基板上に前記 Cu膜 及び前記薄膜からなる配線パターンを形成する工程と、  Forming a wiring pattern composed of the Cu film and the thin film on the substrate by etching the Cu film and the thin film;
を具備する回路基板の製造方法であって、  A method for manufacturing a circuit board comprising:
前記薄膜は、 Cuを主成分とし、 Ti、 Mo、 Ni、 A1及び Ag力 なる群力 選ばれた少 なくとも 1種類の元素を合計で 0.5— 5.(^％含有してなる合金カゝらなり、膜厚が 5nm 以上 1 μ m以下であることを特徴とする。  The thin film is made of an alloy containing Cu as a main component, and a group force of Ti, Mo, Ni, A1, and Ag forces. And a film thickness of 5 nm or more and 1 μm or less.
[0031] 上記回路基板の製造方法によれば、純 Cuである Cu膜と薄膜は、同じエッチング液 でエッチングでき、薄膜は純 Cuと化学反応上の差異が無い。従って、 1回のエツチン グにより Cu膜と薄膜をエッチングすることが可能であり、エッチング残渣の問題も生じ ない。 According to the method for manufacturing a circuit board, the Cu film and the thin film, which are pure Cu, can be etched with the same etchant, and the thin film has no difference in chemical reaction with pure Cu. Therefore, one ethin Etching can etch the Cu film and the thin film, and does not cause the problem of etching residue.
[0032] 本発明に係る回路基板の製造方法は、基板上にスパッタリングにより薄膜を形成す る工程と、  [0032] The method for manufacturing a circuit board according to the present invention includes the steps of: forming a thin film on the substrate by sputtering;
前記薄膜上に真空蒸着法又は電子ビーム蒸着法により膜厚が 300nm以上 30 m以下の Cu膜を形成する工程と、  Forming a Cu film having a thickness of 300 nm or more and 30 m or less on the thin film by vacuum evaporation or electron beam evaporation;
前記 Cu膜及び前記薄膜をエッチング加工することにより、前記基板上に前記 Cu膜 及び前記薄膜からなる配線パターンを形成する工程と、  Forming a wiring pattern composed of the Cu film and the thin film on the substrate by etching the Cu film and the thin film;
を具備する回路基板の製造方法であって、  A method for manufacturing a circuit board comprising:
前記薄膜は、 Cuを主成分とし、 Ti、 Mo、 Ni、 A1及び Ag力 なる群力 選ばれた少 なくとも 1種類の元素を合計で 0.5— 5.(^％含有してなる合金カゝらなり、膜厚が 5nm 以上 1 μ m以下であることを特徴とする。  The thin film is made of an alloy containing Cu as a main component, and a group force of Ti, Mo, Ni, A1, and Ag forces. And a film thickness of 5 nm or more and 1 μm or less.
[0033] 本発明に係る回路基板の製造方法は、基板上にスパッタリングにより第 1の薄膜を 形成する工程と、 [0033] In the method for manufacturing a circuit board according to the present invention, a step of forming a first thin film on the substrate by sputtering;
前記第 1の薄膜上に電界鍍金法又は無電界鍍金法により膜厚が 300nm以上 30 μ m以下の第 1の Cu膜を形成する工程と、  Forming a first Cu film having a thickness of 300 nm or more and 30 μm or less on the first thin film by electroplating or electroless plating,
前記第 1の Cu膜及び前記第 1の薄膜をエッチング加工することにより、前記基板上 に前記第 1の Cu膜及び前記第 1の薄膜からなる第 1の配線パターンを形成する工程 と、  Forming a first wiring pattern composed of the first Cu film and the first thin film on the substrate by etching the first Cu film and the first thin film;
前記第 1の配線パターン及び前記基板の上に絶縁膜を形成する工程と、 前記絶縁膜上にスパッタリングにより第 2の薄膜を形成する工程と、  Forming an insulating film on the first wiring pattern and the substrate; forming a second thin film on the insulating film by sputtering;
前記第 2の薄膜上に電界鍍金法又は無電界鍍金法により膜厚が 300nm以上 30 μ m以下の第 2の Cu膜を形成する工程と、  Forming a second Cu film having a thickness of 300 nm or more and 30 μm or less on the second thin film by electroplating or electroless plating,
前記第 2の Cu膜及び前記第 2の薄膜をエッチング加工することにより、前記絶縁膜 上に前記第 2の Cu膜及び前記第 2の薄膜からなる第 2の配線パターンを形成するェ 程と、  Forming a second wiring pattern composed of the second Cu film and the second thin film on the insulating film by etching the second Cu film and the second thin film;
を具備する回路基板の製造方法であって、  A method for manufacturing a circuit board comprising:
前記第 1の薄膜は、 Cuを主成分とし、 Ti、 Mo、 Ni、 A1及び Ag力 なる群力 選ば れた少なくとも 1種類の元素を合計で 0.5— 5.0wt%含有してなる合金カゝらなり、膜厚 力 S5nm以上 1 μ m以下であり、 The first thin film is mainly composed of Cu, and has a group force of Ti, Mo, Ni, A1, and Ag force. Alloy containing 0.5 to 5.0 wt% in total of at least one element selected from the group consisting of S5 nm and 1 μm,
前記第 2の薄膜は、 Cuを主成分とし、 Ti、 Mo、 Ni、 A1及び Ag力 なる群力 選ば れた少なくとも 1種類の元素を合計で 0.5— 5.0wt%含有してなる合金カゝらなり、膜厚 力 nm以上 1 μ m以下であることを特徴とする。  The second thin film is an alloy powder containing Cu as a main component and a group force of Ti, Mo, Ni, A1, and Ag forces. And the film thickness is not less than nm and not more than 1 μm.
[0034] 本発明に係る回路基板の製造方法は、基板上にスパッタリングにより第 1の薄膜を 形成する工程と、 [0034] The method for manufacturing a circuit board according to the present invention includes the steps of: forming a first thin film on a substrate by sputtering;
前記第 1の薄膜上に真空蒸着法又は電子ビーム蒸着法により膜厚が 300nm以上 30 μ m以下の第 1の Cu膜を形成する工程と、  Forming a first Cu film having a thickness of 300 nm or more and 30 μm or less on the first thin film by a vacuum evaporation method or an electron beam evaporation method;
前記第 1の Cu膜及び前記第 1の薄膜をエッチング加工することにより、前記基板上 に前記第 1の Cu膜及び前記第 1の薄膜からなる第 1の配線パターンを形成する工程 と、  Forming a first wiring pattern composed of the first Cu film and the first thin film on the substrate by etching the first Cu film and the first thin film;
前記第 1の配線パターン及び前記基板の上に絶縁膜を形成する工程と、 前記絶縁膜上にスパッタリングにより第 2の薄膜を形成する工程と、  Forming an insulating film on the first wiring pattern and the substrate; forming a second thin film on the insulating film by sputtering;
前記第 2の薄膜上に真空蒸着法又は電子ビーム蒸着法により膜厚が 300nm以上 The film thickness is 300 nm or more on the second thin film by a vacuum evaporation method or an electron beam evaporation method.
30 μ m以下の第 2の Cu膜を形成する工程と、 Forming a second Cu film of 30 μm or less;
前記第 2の Cu膜及び前記第 2の薄膜をエッチング加工することにより、前記絶縁膜 上に前記第 2の Cu膜及び前記第 2の薄膜からなる第 2の配線パターンを形成するェ 程と、  Forming a second wiring pattern composed of the second Cu film and the second thin film on the insulating film by etching the second Cu film and the second thin film;
を具備する回路基板の製造方法であって、  A method for manufacturing a circuit board comprising:
前記第 1の薄膜は、 Cuを主成分とし、 Ti、 Mo、 Ni、 A1及び Ag力 なる群力 選ば れた少なくとも 1種類の元素を合計で 0.5— 5.0wt%含有してなる合金カゝらなり、膜厚 力 S5nm以上 1 μ m以下であり、  The first thin film is made of an alloy containing Cu as a main component and a group force of Ti, Mo, Ni, A1, and Ag forces. The film thickness is S5 nm or more and 1 μm or less,
前記第 2の薄膜は、 Cuを主成分とし、 Ti、 Mo、 Ni、 A1及び Ag力 なる群力 選ばれ た少なくとも 1種類の元素を合計で 0.5— 5.0wt%含有してなる合金カゝらなり、膜厚が 5 nm以上 1 μ m以下であることを特徴とする。  The second thin film is an alloy powder containing Cu as a main component and a group force of Ti, Mo, Ni, A1, and Ag forces. And a film thickness of 5 nm or more and 1 μm or less.
発明の効果  The invention's effect
[0035] 以上説明したように本発明によれば、基板と Cu膜との密着性を十分に確保できる 回路基板及びその製造方法を提供することができる。また、他の本発明によれば、ェ ツチング残渣の発生を抑制できる回路基板及びその製造方法を提供することができ る。 As described above, according to the present invention, it is possible to sufficiently secure the adhesion between the substrate and the Cu film. A circuit board and a method for manufacturing the same can be provided. Further, according to another aspect of the present invention, it is possible to provide a circuit board capable of suppressing generation of an etching residue and a method for manufacturing the same.
発明を実施するための形態  BEST MODE FOR CARRYING OUT THE INVENTION
[0036] 以下、図面を参照して本発明の実施の形態について説明する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(実施の形態 1) '  (Embodiment 1) ''
図 1 (A)〜(E)及び図 2 (Λ) , (β)は、本発明の実施の形態 1による回路基板を製 造し、回路基板上に電子部品 実装する方法を示す断面図である。  FIGS. 1A to 1E and FIGS. 2A and 2B are cross-sectional views showing a method for manufacturing a circuit board according to Embodiment 1 of the present invention and mounting electronic components on the circuit board. is there.
[0037] まず、図 1 (Α)に示すように、基板 1の上に膜厚が 5nm以上 1 μ m以下の Cu合金薄 膜 2をスパッタリングにより形成する。 Cu合金薄膜 2は、 Cuを主成分とし、 Ti、 Mo、 N i、 A1及び Agからなる群力 選ばれた少なくとも 1種類の元素を合計で 0.5〜5.0重量 % (wt%)含有してなる合金力 なるものである。また、より好ましい Cu合金薄膜 2とし ては、 Ti、 Mo、 Ni、 A1及び Agからなる群力も選ばれた少なくとも 1種類の元素を合 計で 0.5〜5.0wt%含有し、残部が Cuからなる合金力 なるものである。また、さらに 好ましい Cu合金薄膜としては、 Moを l.l〜1.2wt%含有し、残部が Cuからなる合金 力 なるものである。また、基板 1は、ポリイミド、液晶ポリマー、テフロン (登録商標)又 はエポキシ樹脂等力 なる高分子材料或いは樹脂材料によって形成されたものであ る。 First, as shown in FIG. 1 (Α), a Cu alloy thin film 2 having a thickness of 5 nm or more and 1 μm or less is formed on a substrate 1 by sputtering. The Cu alloy thin film 2 contains Cu as a main component and a group strength of Ti, Mo, Ni, A1, and Ag.The total content of at least one selected element is 0.5 to 5.0% by weight (wt%). Alloy strength. In addition, a more preferable Cu alloy thin film 2 contains at least one element selected from group forces consisting of Ti, Mo, Ni, A1, and Ag in a total amount of 0.5 to 5.0 wt%, with the balance being Cu. Alloy strength. Further, as a more preferable Cu alloy thin film, an alloy containing Mo in an amount of 1.1 to 1.2 wt% and the balance being Cu is used. Further, the substrate 1 is formed of a strong polymer material or resin material such as polyimide, liquid crystal polymer, Teflon (registered trademark) or epoxy resin.
[0038] 前記 Cu合金薄膜 2に上述したような材料を用いる理由は次の通りである。合金材 料を容易に製作することができること、化学的に安定な材料で構成されること、高価 な金属を使用しなレ、ので材料のコスト的優位性が高レ、こと、材料的に粒径が微細で 緻密な膜形成を容易に行うことができる組成であること、ウエットエッチングを行う際に 、純 Cuと同じエッチング液 (例えば塩ィ匕第 II鉄、塩ィヒ第 II銅)で同じレートでエツチン グを行うことが可能であること、ウエットエッチングの際に純 Cuと化学反応上の差異が 無ぐ残渣等の問題が生じないこと、による。  [0038] The reason why the above-mentioned materials are used for the Cu alloy thin film 2 is as follows. It is easy to manufacture alloy materials, it is composed of chemically stable materials, and it does not use expensive metals, so the cost advantage of the materials is high. The composition is such that it can easily form a fine and dense film.When performing wet etching, use the same etchant as pure Cu (e.g. The reason is that etching can be performed at the same rate, and there is no problem such as residues that have no difference in chemical reaction from pure Cu during wet etching.
[0039] この後、図 1 (B)に示すように、 Cu合金薄膜 2の上に電界鍍金法又は無電界鍍金 法により膜厚力 S300nm以上 30 μ m以下の Cu鍍金膜 3を形成する。 Cu鍍金膜 3の 下に Cu合金薄膜 2を配置することにより鍍金成長速度を速くすることができ、スルー  Thereafter, as shown in FIG. 1 (B), a Cu plating film 3 having a film thickness of S300 nm or more and 30 μm or less is formed on the Cu alloy thin film 2 by an electroplating method or an electroless plating method. Placing the Cu alloy thin film 2 under the Cu plating film 3 can increase the plating growth rate,
差替え用紙 (規則 26) プットを向上させることが可能となる。また、 Cu鍍金膜 3は純 Cu (但し、不可避的不純 物は含有する）である力 Cu合金薄膜 2とは組成が異なるけれど C xを主成分とする 点で同質であるから、これらの密着性は非常に良レ、。また、 Cu合金薄膜 2と高分子 材料又は樹脂材料力らなる基板 1との密着性は、従来の Cr又は Ni等の下地膜に比 ベて非常に良い。従って、本実施の形態では、従来の回路基板のように密着性を確 保するための下地膜を必要としなレ、。 Replacement forms (Rule 26) The put can be improved. The Cu plating film 3 has a different composition from the pure Cu alloy thin film 2 which is pure Cu (but contains unavoidable impurities), but is homogeneous in that Cx is the main component. The sex is very good. Further, the adhesion between the Cu alloy thin film 2 and the substrate 1 made of a polymer material or a resin material is much better than that of a conventional underlayer such as Cr or Ni. Therefore, in the present embodiment, a base film for ensuring adhesion is not required unlike a conventional circuit board.
[0040] 次に、図 1 (C)に示すように、 Cu鍍金膜 3の上にフォトレジスト膜を塗布し、露光及 び現像することにより、 Cu鍍金膜 3の上にはレジストパターン 4が形成される。  Next, as shown in FIG. 1 (C), a resist pattern 4 is formed on the Cu plating film 3 by applying a photoresist film on the Cu plating film 3, exposing and developing. It is formed.
[0041] この後、図 1 (D)に示すように、レジストパターン 4をマスクとして Cu鍍金膜 3及ぴ Cu 合金薄膜 2を塩ィ匕第 II鉄、 ¾ィ匕第 I幽等のエッチング液によってウエットエッチングす る。次いで、レジストパターン 4を除去することにより、図 1 (E)に示すように、基板 1の 上には Cu鍍金膜 3及び Cu合金薄膜 2からなる配線パターン 5a〜5dが形成される。 純 Cuである Cu鍍金膜 3と前述した組成の Cu合金薄膜 2は、塩化第 II鉄、塩化第 II鲖 等のエッチング液でエッチングできる上、エッチングレートもほぼ同じである。さらに C u合金薄膜は純 Cuと化学反応上の差異が無ぐ残渣等の問題も生じない。  Thereafter, as shown in FIG. 1 (D), using the resist pattern 4 as a mask, the Cu plating film 3 and the Cu alloy thin film 2 are etched with an etching solution such as Shii-Dai II Iron, Dani-Dai I, etc. Wet-etching. Next, by removing the resist pattern 4, as shown in FIG. 1 (E), wiring patterns 5a to 5d composed of the Cu plating film 3 and the Cu alloy thin film 2 are formed on the substrate 1. The Cu plating film 3 made of pure Cu and the Cu alloy thin film 2 having the above-mentioned composition can be etched with an etchant such as ferric chloride, chlorinated chloride, and the like, and have almost the same etching rate. Furthermore, the Cu alloy thin film does not cause a problem such as a residue having no difference in chemical reaction from pure Cu.
[0042] 次に、図 2 (A)に示すように、配線パターン 5a〜5dの上に Ni鈹金膜 6を形成し、 Au 鍍金膜 7を形成する。 Ni鍍金膜 6はバリア層及ぴ密着層として機能する。  Next, as shown in FIG. 2A, a Ni—Au film 6 is formed on the wiring patterns 5a to 5d, and an Au plating film 7 is formed. The Ni plating film 6 functions as a barrier layer and an adhesion layer.
この後、図 2 (B)に示すように、回路基板に実装する半導体チップ 8のような電子部 品を準備する。半導体チップ 8の能動面には外部端子としての Auバンプ 9が形成さ れている。  Thereafter, as shown in FIG. 2B, an electronic component such as a semiconductor chip 8 to be mounted on a circuit board is prepared. Au bumps 9 as external terminals are formed on the active surface of the semiconductor chip 8.
[0043] 次いで、回路基板上に半導体チップ 8を位置合わせし、配線パターン上に Auバン プ 9を配置し、基板上の配線パターンと半導体チップを熱圧着する。これにより、配線 ノ、。ターンと Auバンプが接合され、回路基板に半導体チップが実装される。  Next, the semiconductor chip 8 is aligned on the circuit board, the Au bump 9 is arranged on the wiring pattern, and the wiring pattern on the board and the semiconductor chip are thermocompression bonded. With this, wiring no. The turns and the Au bumps are joined, and the semiconductor chip is mounted on the circuit board.
[0044] 上記実施の形態 1によれば、 Cu鍍金膜 3を形成する際の鍍金シード層として Cu合 金薄膜 2を用いることにより、微細な配線パターンを有し、信頼性の高い薄型の回路 基板を実現することが可能となる。  According to the first embodiment, by using the Cu alloy thin film 2 as a plating seed layer when forming the Cu plating film 3, a highly reliable thin circuit having a fine wiring pattern is provided. A substrate can be realized.
[0045] また、本実施の形態では、前述したように Cxi合金薄膜 2と高分子材料又は榭脂材 料力 なる基板 1との密着性力 S4〜6N/cmと非常に良ぐ Cu合金薄膜 2と Cu鍍金  Further, in the present embodiment, as described above, the adhesion strength between the Cxi alloy thin film 2 and the substrate 1 made of a polymer material or a resin material S4 to 6 N / cm, which is a very good Cu alloy thin film 2 and Cu plating
差替え用紙 （規則 26) 膜 3との密着性も非常に良い。また、 Cu合金薄膜 2はその中の Cuが基板 1に拡散し にくいことが確認されている。また、 Cu鍍金膜 3の下に Cu合金薄膜 2を配置すること により鍍金成長速度を速くすることができ、スループットを向上させることが可能となる 。また、純 Cuである Cu鍍金膜 3と前述した組成の Cu合金薄膜 2は、同じエッチング 液でエッチングできる上、エッチングレートもほぼ同じであり、さらに Cu合金薄膜は純 Cuと化学反応上の差異が無い。従って、 1回のウエットエッチングにより Cu鍍金膜 3 と Cu合金薄膜 2をエッチングすることが可能であり、エッチング残渣等の問題も生じ ない。よって、エッチング工程におけるスループットを向上させることができる。 Replacement form (Rule 26) The adhesion to the film 3 is also very good. In addition, it has been confirmed that the Cu alloy thin film 2 does not easily diffuse Cu into the substrate 1. Further, by arranging the Cu alloy thin film 2 below the Cu plating film 3, the plating growth rate can be increased, and the throughput can be improved. In addition, the Cu plating film 3, which is pure Cu, and the Cu alloy thin film 2 having the above-mentioned composition can be etched with the same etching solution, and the etching rates are almost the same. There is no. Therefore, the Cu plating film 3 and the Cu alloy thin film 2 can be etched by one wet etching, and there is no problem such as an etching residue. Therefore, the throughput in the etching step can be improved.
[0046] 尚、上記実施の形態 1では、表面に Au鍍金膜を形成した配線パターンと Auバンプ 9とを接合することにより半導体チップ 8を回路基板に実装しているが、半導体チップ などの電子部品の実装方法はこれに限定されるものではなぐ他の実装方法を用い て回路基板に実装することも可能である。例えば、 Au鍍金膜を形成しない配線バタ ーン (即ち Cu鍍金膜 3及び Cu合金薄膜 2からなる配線パターン）に Auバンプ 9を直 接接合することにより半導体チップ 8を回路基板に実装することも可能である。また、 配線パターンと電子部品の外部端子とを導電性ペーストを用いて接合することにより 電子部品を回路基板に実装することも可能であり、また、配線パターンと電子部品の 外部端子との接合部分を接着剤で固定することにより電子部品を回路基板に実装す ることち可會である。  In the first embodiment, the semiconductor chip 8 is mounted on the circuit board by joining the wiring pattern having the Au plating film formed on the surface thereof and the Au bump 9. The component mounting method is not limited to this, and it is also possible to mount the component on the circuit board using other mounting methods. For example, the semiconductor chip 8 can be mounted on a circuit board by directly bonding the Au bump 9 to a wiring pattern on which no Au plating film is formed (that is, a wiring pattern composed of the Cu plating film 3 and the Cu alloy thin film 2). It is possible. In addition, it is possible to mount the electronic component on the circuit board by joining the wiring pattern and the external terminal of the electronic component using a conductive paste, and it is also possible to connect the wiring pattern to the external terminal of the electronic component. It is possible to mount electronic components on a circuit board by fixing them with an adhesive.
[0047] (実施の形態 2)  (Embodiment 2)
図 3 (A)一 (E)は、本発明の実施の形態 2による回路基板を製造する方法を示す 断面図であり、図 1と同一部分には同一符号を付す。  FIGS. 3A to 3E are cross-sectional views showing a method of manufacturing a circuit board according to Embodiment 2 of the present invention, and the same parts as those in FIG.
[0048] まず、図 3 (A)に示すように、基板 1の上に膜厚が 5nm以上 1 μ m以下の Cu合金薄 膜 2をスパッタリングにより形成する。 Cu合金薄膜 2は実施の形態 1と同様の合金力も なり、基板 1は実施の形態 1と同様の材料力もなる。  First, as shown in FIG. 3A, a Cu alloy thin film 2 having a thickness of 5 nm or more and 1 μm or less is formed on a substrate 1 by sputtering. The Cu alloy thin film 2 has the same alloy strength as in the first embodiment, and the substrate 1 has the same material strength as in the first embodiment.
[0049] この後、図 3 (B)に示すように、 Cu合金薄膜 2の上にフォトレジスト膜を塗布し、露光 及び現像することにより、 Cu合金薄膜 2の上にはレジストパターン 4が形成される。こ のレジストパターン 4は Cu鍍金膜を形成する部分のみが開口したパターンである。  After that, as shown in FIG. 3 (B), a photoresist pattern is formed on the Cu alloy thin film 2 by applying a photoresist film on the Cu alloy thin film 2, exposing and developing. Is done. This resist pattern 4 is a pattern in which only the portion where the Cu plating film is formed is opened.
[0050] 次に、図 3 (C)に示すように、レジストパターン 4をマスクとして電界鍍金法により膜 厚が 300nm以上 30 μ m以下の Cu鍍金膜 3を形成する。この Cu鍍金膜 3は、レジス トパターンをマスクとして形成してレヽるため、鍍金成長が終了した時点で配線パター ンを有している。また、 Cu鍍金膜 3の下に Cu合金薄膜 2を配置することにより鍍金成 長速度を速くできることは実施の形態 1と同様である。また、 Cu合金薄膜 2と Cu鍍金 膜 3との密着性が良ぐ Cu合金薄膜 2と基板 1との密着性が良いのも実施の形態 1と 同様である。 Next, as shown in FIG. 3 (C), the film was formed by electrolytic plating using the resist pattern 4 as a mask. A Cu plating film 3 having a thickness of 300 nm or more and 30 μm or less is formed. Since this Cu plating film 3 is formed using the resist pattern as a mask and has a wiring pattern, it has a wiring pattern when plating growth is completed. Further, the plating growth speed can be increased by disposing the Cu alloy thin film 2 under the Cu plating film 3 as in the first embodiment. Also, the adhesion between the Cu alloy thin film 2 and the substrate 1 is good, as in the first embodiment, in which the adhesion between the Cu alloy thin film 2 and the Cu plating film 3 is good.
[0051] この後、図 3 (D)に示すように、レジストパターン 4を除去する。  Thereafter, as shown in FIG. 3D, the resist pattern 4 is removed.
次に、図 3 (E)に示すように、 Cu鍍金膜 3をマスクとして Cu合金薄膜 2をエッチング により除去する。これにより、基板 1の上には Cu鍍金膜 3及び Cu合金薄膜 2からなる 配線パタ ンが形成される。尚、 Cu合金薄膜 2をエッチングする際のエッチング液は 塩化第 II鉄、塩化第 II銅などのエッチング液を用いても良い。このエッチング液は Cu 鍍金膜と Cu合金薄膜の両方がエッチングされるものである力 S、 Cu合金薄膜は Cu鍍 金膜に比べて非常に薄いので、問題無くエッチングすることができる。しかし、 Cu合 金薄膜をエッチングする際に Cu鍍金膜がエッチングされないような Cu鍍金膜と Cu 合金薄膜との間に十分なエッチング選択比を有するエッチング液を用いることがより 好ましい。  Next, as shown in FIG. 3E, the Cu alloy thin film 2 is removed by etching using the Cu plating film 3 as a mask. Thus, a wiring pattern composed of the Cu plating film 3 and the Cu alloy thin film 2 is formed on the substrate 1. Note that an etchant for etching the Cu alloy thin film 2 may be an etchant such as ferric chloride or cupric chloride. This etchant is used to etch both the Cu plating film and the Cu alloy thin film. The S, Cu alloy thin film is very thin compared to the Cu plating film, and can be etched without any problem. However, it is more preferable to use an etchant having a sufficient etching selectivity between the Cu plating film and the Cu alloy thin film so that the Cu plating film is not etched when etching the Cu alloy thin film.
[0052] この後の工程は、図 2 (A)， (B)に示す工程と同様である。  The subsequent steps are the same as the steps shown in FIGS. 2 (A) and 2 (B).
[0053] 上記実施の形態 2においても実施の形態 1と同様の効果を得ることができる。  [0053] In the second embodiment as well, the same effects as in the first embodiment can be obtained.
すなわち、微細な配線パターンを有し、信頼性の高い薄型の回路基板を実現する ことが可能となる。また、 Cu合金薄膜 2と基板 1との密着性が非常に良く、 Cu合金薄 膜 2と Cu鈹金膜 3との密着性も非常に良い。また、 Cu合金薄膜 2はその中の Cuが基 板 1に拡散しにくいものである。また、 Cu鍍金膜 3の成長速度を速くする iとができ、 スループットを向上させることが可能となる。また、エッチング残馇等の問題も生じな い。  That is, a highly reliable thin circuit board having a fine wiring pattern can be realized. Further, the adhesion between the Cu alloy thin film 2 and the substrate 1 is very good, and the adhesion between the Cu alloy thin film 2 and the Cu-gold film 3 is also very good. In the Cu alloy thin film 2, the Cu contained therein is difficult to diffuse into the substrate 1. In addition, the growth rate of the Cu plating film 3 can be increased, and the throughput can be improved. In addition, there is no problem such as an etching residue.
[0054] (実施の形態 3)  (Embodiment 3)
図 4 (A)， (B)は、本発明の実施の形態 3による回路基板の製造方法を示す断面図 である。この回路基板は基板 1の両面に配線パターンを形成するものである。  4A and 4B are cross-sectional views illustrating a method for manufacturing a circuit board according to Embodiment 3 of the present invention. This circuit board has wiring patterns formed on both sides of the board 1.
[0055] まず、図 4 (A)に示すように、基板 1の表面上及び裏面上に膜厚が 5nm以上 1 μ m First, as shown in FIG. 4 (A), a film thickness of 5 nm or more and 1 μm
差替え用紙 （規則 26) 以下の Cu合金薄膜 2をスパッタリングにより形成する。 Cu合金薄膜 2は実施の形態 1 と同様の合金力もなり、基板 1は実施の形態 1と同様の材料力もなる。 Replacement form (Rule 26) The following Cu alloy thin film 2 is formed by sputtering. The Cu alloy thin film 2 has the same alloy strength as in the first embodiment, and the substrate 1 has the same material strength as in the first embodiment.
[0056] この後、図 4 (B)に示すように、基板 1の表面側及び裏面側において Cu合金薄膜 2 の上に電界鍍金法又は無電界鍍金法により膜厚が 300nm以上 30 μ m以下の Cu 鍍金膜 3を形成する。 Cu鍍金膜 3の下に Cu合金薄膜 2を配置することにより鍍金成 長速度を速くできることは実施の形態 1と同様である。また、 Cu合金薄膜 2と Cu鍍金 膜 3との密着性が良ぐ Cu合金薄膜 2と基板 1との密着性が良いことも実施の形態 1と 同様である。 Thereafter, as shown in FIG. 4 (B), the film thickness is 300 nm or more and 30 μm or less by electroplating or electroless plating on the Cu alloy thin film 2 on the front side and the back side of the substrate 1. A Cu plating film 3 is formed. As in the first embodiment, the plating growth speed can be increased by disposing the Cu alloy thin film 2 under the Cu plating film 3. Further, the good adhesion between the Cu alloy thin film 2 and the Cu plating film 3 and the good adhesion between the Cu alloy thin film 2 and the substrate 1 is also the same as in the first embodiment.
[0057] 次に、実施の形態 1と同様の方法により、 Cu鍍金膜 3及び Cu合金薄膜 2をウエット エッチングすることにより、基板 1の表面上及び裏面上それぞれには Cu鍍金膜 3及 び Cu合金薄膜 2からなる配線パターンが形成される（図示せず)。  Next, the Cu plating film 3 and the Cu alloy thin film 2 are wet-etched in the same manner as in the first embodiment, so that the Cu plating films 3 and Cu A wiring pattern made of the alloy thin film 2 is formed (not shown).
[0058] 上記実施の形態 3においても実施の形態 1と同様の効果を得ることができる。  [0058] In the third embodiment, the same effect as in the first embodiment can be obtained.
[0059] (実施の形態 4)  (Embodiment 4)
図 5 (A)一 (C)は、本発明の実施の形態 4による回路基板の製造方法を示す断面 図である。この回路基板は、基板 1にスルーホール laを形成すると共に、基板 1の両 面に配線パターンを形成するものである。  FIGS. 5A to 5C are cross-sectional views illustrating a method for manufacturing a circuit board according to Embodiment 4 of the present invention. In this circuit board, a through hole la is formed in the board 1 and a wiring pattern is formed on both sides of the board 1.
[0060] まず、図 5 (A)に示すように、貫通孔であるスルーホール laを有する基板 1を準備 する。  First, as shown in FIG. 5A, a substrate 1 having a through hole la which is a through hole is prepared.
[0061] 次いで、図 5 (B)に示すように、基板 1の表面上、裏面上及びスルーホール la内に 膜厚が 5nm以上 1 μ m以下の Cu合金薄膜 2をスパッタリングにより形成する。 Cu合 金薄膜 2は実施の形態 1と同様の合金力もなり、基板 1は実施の形態 1と同様の材料 からなる。  Next, as shown in FIG. 5 (B), a Cu alloy thin film 2 having a thickness of 5 nm or more and 1 μm or less is formed on the front surface, the back surface, and in the through hole la of the substrate 1 by sputtering. The Cu alloy thin film 2 has the same alloy force as in the first embodiment, and the substrate 1 is made of the same material as in the first embodiment.
[0062] この後、図 5 (C)に示すように、基板 1の表面側、裏面側及びスルーホール la内に おいて Cu合金薄膜 2の上に電界鍍金法又は無電界鍍金法により膜厚が 300nm以 上 30 μ m以下の Cu鍍金膜 3を形成する。 Cu鍍金膜 3の下に Cu合金薄膜 2を配置 することにより鍍金成長速度を速くできることは実施の形態 1と同様である。また、 Cu 合金薄膜 2と Cu鍍金膜 3との密着性が良ぐ Cu合金薄膜 2と基板 1との密着性が良 いことも実施の形態 1と同様である。 [0063] 次に、実施の形態 1と同様の方法により、 Cu鍍金膜 3及び Cu合金薄膜 2をウエット エッチングすることにより、基板 1の表面上及び裏面上それぞれには Cu鍍金膜 3及 び Cu合金薄膜 2からなる配線パターンが形成される（図示せず)。 Thereafter, as shown in FIG. 5 (C), the film thickness is formed on the Cu alloy thin film 2 on the front side, the back side, and in the through hole la of the substrate 1 by the electroplating method or the electroless plating method. Forms a Cu plating film 3 having a thickness of 300 nm or more and 30 μm or less. As in the first embodiment, the plating growth rate can be increased by disposing the Cu alloy thin film 2 under the Cu plating film 3. Moreover, the good adhesion between the Cu alloy thin film 2 and the Cu plating film 3 and the good adhesion between the Cu alloy thin film 2 and the substrate 1 is also the same as in the first embodiment. Next, the Cu plating film 3 and the Cu alloy thin film 2 are wet-etched in the same manner as in Embodiment 1, so that the Cu plating films 3 and Cu A wiring pattern made of the alloy thin film 2 is formed (not shown).
[0064] 上記実施の形態 4においても実施の形態 1と同様の効果を得ることができる。  [0064] In the fourth embodiment, the same effect as in the first embodiment can be obtained.
[0065] (実施の形態 5)  (Embodiment 5)
図 6 (A) , (B)は、本発明の実施の形態 5による回路基板の製造方法を示す断面図 である。この回路基板は多層配線構造を有するものである。  6 (A) and 6 (B) are cross-sectional views illustrating a method for manufacturing a circuit board according to Embodiment 5 of the present invention. This circuit board has a multilayer wiring structure.
[0066] まず、図 6 (A)に示すように、基板 1の上に膜厚が 5nm以上 1 μ m以下の Cu合金薄 膜 2をスパッタリングにより形成し、 Cu合金薄膜 2の上に電界鍍金法又は無電界鍍金 法により膜厚が 300nm以上 30 /z m以下の Cu鍍金膜 3を形成する。次いで、 Cu鍍 金膜 3及び Cu合金薄膜 2をパターユングすることにより、基板 1の上には Cu鍍金膜 3 及び Cu合金薄膜 2からなる配線パターン（図示せず)が形成される。ここまでの工程 は実施の形態 1と同様である。尚、実施の形態 2と同様の方法により、基板 1の上に C u鍍金膜 3及び Cu合金薄膜 2からなる配線パターンを形成しても良い。  First, as shown in FIG. 6 (A), a Cu alloy thin film 2 having a thickness of 5 nm or more and 1 μm or less is formed on a substrate 1 by sputtering, and electrolytic plating is performed on the Cu alloy thin film 2. A Cu plating film 3 having a film thickness of 300 nm or more and 30 / zm or less is formed by a method or an electroless plating method. Next, by patterning the Cu plating film 3 and the Cu alloy thin film 2, a wiring pattern (not shown) composed of the Cu plating film 3 and the Cu alloy thin film 2 is formed on the substrate 1. The steps so far are the same as in the first embodiment. Note that a wiring pattern composed of the Cu plating film 3 and the Cu alloy thin film 2 may be formed on the substrate 1 by the same method as in the second embodiment.
[0067] この後、配線パターン及び基板 1の上に熱可塑性のポリイミドワニスを塗布し、熱処 理することにより、配線パターン及び基板 1の上にはポリイミド膜 10が形成される。次 いで、このポリイミド膜 10をエッチングカ卩ェすることにより、該ポリイミド膜 10には配線 パターン上に位置するスルーホール 10aが形成される。尚、ポリイミド膜が感光性を 有するものであれば、ポリイミド膜を露光し現像することにより、スルーホールを形成 することができる。  Thereafter, a polyimide polyimide varnish is applied on the wiring pattern and the substrate 1 and subjected to a heat treatment, whereby a polyimide film 10 is formed on the wiring pattern and the substrate 1. Next, the polyimide film 10 is etched to form a through hole 10a located on the wiring pattern in the polyimide film 10. If the polyimide film has photosensitivity, a through hole can be formed by exposing and developing the polyimide film.
[0068] 次に、図 6 (B)に示すように、スルーホール 10aの底面、内側面及びポリイミド膜 10 上に膜厚が 5nm以上 1 μ m以下の Cu合金薄膜 11をスパッタリングにより形成し、 Cu 合金薄膜 11の上に電界鍍金法又は無電界鍍金法により膜厚が 300nm以上 30 /z m 以下の Cu鍍金膜 12を形成する。次いで、 Cu鍍金膜 12及び Cu合金薄膜 11をバタ 一-ングすることにより、基板 1の上には Cu鍍金膜 12及び Cu合金薄膜 11からなる 配線パターン（図示せず)が形成される。これらの工程は実施の形態 1と同様の方法 を用いる。ポリイミド膜 10上の配線パターンは基板 1上の配線パターンとスルーホー ル 10aを介して接続される。尚、実施の形態 2と同様の方法により、ポリイミド膜 10の 上に Cu鍍金膜 12及び Cu合金薄膜 11からなる配線パターンを形成しても良!、。 Next, as shown in FIG. 6B, a Cu alloy thin film 11 having a thickness of 5 nm or more and 1 μm or less is formed by sputtering on the bottom surface, the inner side surface, and the polyimide film 10 of the through hole 10a. A Cu plating film 12 having a thickness of 300 nm or more and 30 / zm or less is formed on the Cu alloy thin film 11 by electroplating or electroless plating. Next, a wiring pattern (not shown) made of the Cu plating film 12 and the Cu alloy thin film 11 is formed on the substrate 1 by butting the Cu plating film 12 and the Cu alloy thin film 11. These steps use the same method as in the first embodiment. The wiring pattern on the polyimide film 10 is connected to the wiring pattern on the substrate 1 via a through hole 10a. Note that, in the same manner as in Embodiment 2, the polyimide film 10 A wiring pattern consisting of the Cu plating film 12 and the Cu alloy thin film 11 may be formed on the top.
[0069] 上記の方法により多層配線構造を有する回路基板が形成される。尚、図 6 (B)に示 す回路基板では基板上に 2層の配線層が形成された多層配線構造となっているが、 3層以上の配線層を基板上に形成することも可能である。この場合は、図 6 (B)に示 す 2層目の配線層を形成する工程を 3層目以降も繰り返すことにより、 3層以上の多 層配線構造を形成することができる。  A circuit board having a multilayer wiring structure is formed by the above method. Although the circuit board shown in FIG. 6B has a multilayer wiring structure in which two wiring layers are formed on the substrate, three or more wiring layers can be formed on the substrate. is there. In this case, a multi-layer wiring structure of three or more layers can be formed by repeating the process of forming the second wiring layer shown in FIG. 6B for the third and subsequent layers.
[0070] 上記実施の形態 5においても実施の形態 1と同様の効果を得ることができる。  [0070] Also in the fifth embodiment, the same effect as in the first embodiment can be obtained.
[0071] また、スルーホール 10a内に Cu合金薄膜 11をスパッタリングにより形成しているた め、微細なスルーホール 10aであっても膜厚を薄く且つカバレージ良く Cu合金薄膜 11を成膜することができる。つまり、配線パターンが微細化されてスルーホールの微 細化が進んだ場合に特に有効なものとなる。  [0071] Further, since the Cu alloy thin film 11 is formed in the through hole 10a by sputtering, the Cu alloy thin film 11 can be formed with a small thickness and good coverage even in the fine through hole 10a. it can. In other words, this is particularly effective when the wiring pattern is miniaturized and the through hole is miniaturized.
[0072] また、 Cu合金薄膜 11をスパッタリングにより成膜すると膜厚制御性が非常に良い。  When the Cu alloy thin film 11 is formed by sputtering, the film thickness controllability is very good.
また、ポリイミド膜 10と Cu合金薄膜 11との密着性が非常に良ぐ実用上必要な密 着性を十分に確保することができる。  In addition, the adhesiveness between the polyimide film 10 and the Cu alloy thin film 11 is very good, and the adhesiveness necessary for practical use can be sufficiently secured.
[0073] (実施の形態 6)  (Embodiment 6)
本発明の実施の形態 6による回路基板の製造方法について図 1及び図 2を参照し つつ説明する。図 1及び図 2は実施の形態 1による回路基板の製造方法を示すもの であるが、実施の形態 1にお!ヽて Cu鍍金膜 3を真空蒸着法又は電子ビーム蒸着法 により成膜した Cu蒸着膜に変更したものが実施の形態 6である。  A method of manufacturing a circuit board according to Embodiment 6 of the present invention will be described with reference to FIGS. FIGS. 1 and 2 show a method for manufacturing a circuit board according to the first embodiment. In the first embodiment, the Cu plating film 3 is formed by vacuum evaporation or electron beam evaporation. Embodiment 6 is an embodiment changed to a deposited film.
[0074] まず、図 1 (A)に示すように、基板 1の上に膜厚が 5nm以上 1 μ m以下の Cu合金薄 膜 2をスパッタリングにより形成する。 Cu合金薄膜 2は実施の形態 1と同様の合金力も なり、基板 1は実施の形態 1と同様の材料カゝらなる。また、前記 Cu合金薄膜 2に上述 したような材料を用いる理由は実施の形態 1と同様である。次の通りである。  First, as shown in FIG. 1A, a Cu alloy thin film 2 having a thickness of 5 nm or more and 1 μm or less is formed on a substrate 1 by sputtering. The Cu alloy thin film 2 has the same alloy strength as in the first embodiment, and the substrate 1 is made of the same material as in the first embodiment. The reason for using the above-described materials for the Cu alloy thin film 2 is the same as in the first embodiment. It is as follows.
[0075] この後、図 1 (B)に示すように、 Cu合金薄膜 2の上に真空蒸着法又は電子ビーム蒸 着法により膜厚が 300nm以上 30 m以下の Cu蒸着膜 3を形成する。 Cu蒸着膜 3 は純 Cu (但し、不可避的不純物は含有する）であるから Cu合金薄膜 2とは組成が異 なるけれど Cuを主成分とする点で同質であるから、これらの密着性は非常に良い。ま た、 Cu合金薄膜 2と基板 1との密着性は非常に良い。 [0076] 次に、図 1 (C)に示すように、 Cu蒸着膜 3の上にフォトレジスト膜を塗布し、露光し 現像することにより、 Cu蒸着膜 3の上にはレジストパターン 4が形成される。 Thereafter, as shown in FIG. 1 (B), a Cu evaporated film 3 having a thickness of 300 nm or more and 30 m or less is formed on the Cu alloy thin film 2 by a vacuum evaporation method or an electron beam evaporation method. Since the deposited Cu film 3 is pure Cu (but contains unavoidable impurities), it has a different composition from the Cu alloy thin film 2 but is homogeneous in that it contains Cu as a main component. Good for Also, the adhesion between the Cu alloy thin film 2 and the substrate 1 is very good. Next, as shown in FIG. 1 (C), a photoresist pattern is formed on the Cu vapor deposition film 3 by applying a photoresist film on the Cu vapor deposition film 3, exposing and developing. Is done.
[0077] この後、図 1 (D)に示すように、レジストパターン 4をマスクとして Cu蒸着膜 3及び Cu 合金薄膜 2を塩化第 II鉄、塩ィヒ第 II銅等のエッチング液によってウエットヱツチングす る。次いで、レジストパターン 4を除去することにより、図 1 (E)に示すように、基板 1の 上には Cu蒸着膜 3及ぴ Cu合金薄膜 2からなる配線パターン 5a〜5dが形成される。 純 Cuである Cu蒸着膜 3と前述した組成の Cu合金薄膜 2は、塩化第 II鉄、塩化第 II銅 等のエッチング液でエッチングできる上、エッチングレートもほぼ同じである。さらに C u合金薄膜は純 Cuと化学反応上の差異が無く、残渣等の問題も生じない。  Thereafter, as shown in FIG. 1 (D), using the resist pattern 4 as a mask, the Cu vapor deposition film 3 and the Cu alloy thin film 2 are wetted with an etching solution such as ferric chloride, copper salt II, or the like. Touching. Next, by removing the resist pattern 4, as shown in FIG. 1E, wiring patterns 5a to 5d composed of the Cu vapor deposition film 3 and the Cu alloy thin film 2 are formed on the substrate 1. The Cu vapor deposition film 3 which is pure Cu and the Cu alloy thin film 2 having the above-described composition can be etched with an etching solution such as ferric chloride, cupric chloride, and the like, and have substantially the same etching rate. Further, the Cu alloy thin film has no difference in chemical reaction from pure Cu, and does not cause a problem such as residue.
[0078] 次に、図 2 (A)に示すように、配線パターン 5a〜5dの上に Au鍍金膜 7を形成する。  Next, as shown in FIG. 2A, an Au plating film 7 is formed on the wiring patterns 5a to 5d.
[0079] この後、図 2 (&)に示すように、回路基板に実装する半導体チップ 8のような電子部 品を準備する。半導体チップ 8の能動面には外部端子としての Auバンプ 9が形成さ れている。  Thereafter, as shown in FIG. 2 (&), electronic components such as the semiconductor chip 8 to be mounted on the circuit board are prepared. Au bumps 9 as external terminals are formed on the active surface of the semiconductor chip 8.
[0080] 次！/ヽで、回路基板上に半導体チップ 8を位置合わせし、配線パターン上に Auバン プ 9を配置し、基板上の配線パターンと半導体チップを熱圧着する。これにより、配線 パターンと Auバンプが接合され、回路基板に半導体チップが実装される。  [0080] Next! In step (1), the semiconductor chip 8 is aligned on the circuit board, the Au bump 9 is arranged on the wiring pattern, and the wiring pattern on the board and the semiconductor chip are thermocompressed. As a result, the wiring pattern is bonded to the Au bump, and the semiconductor chip is mounted on the circuit board.
[0081] 上記実施の形態 6によれば、 Cu合金薄膜 2と基板 1との密着性が非常に良ぐ Cu 合金薄膜 2と Cu蒸着膜 3との密着性も非常に良い。また、 Cu合金薄膜 2はその中の Cuが基板 1に拡散しにくいものである。また、 1回のウエットエッチングにより Cu蒸着 膜 3と Cu合金薄膜 2をエッチングすることが可能であり、エッチング残渣等の問題も 生じない。従って、エッチング工程におけるスループットを向上させることができる。  According to the sixth embodiment, the adhesion between the Cu alloy thin film 2 and the substrate 1 is very good, and the adhesion between the Cu alloy thin film 2 and the deposited Cu film 3 is also very good. Further, the Cu alloy thin film 2 is one in which Cu contained therein is difficult to diffuse into the substrate 1. Further, the Cu vapor deposition film 3 and the Cu alloy thin film 2 can be etched by one wet etching, and there is no problem such as an etching residue. Therefore, the throughput in the etching step can be improved.
[0082] また、本実施の形態では、 Cu蒸着膜 3を用いることにより次のような利点がある。真 空蒸着法や電子ビーム蒸着法により形成された純 Cu力 なる Cu蒸着膜 3内の Cuの 結晶粒径は、電界鍍金法や無電界鍍金法による Cu鍍金膜と比して微細である。この ため、粒子密度の高い緻密な膜を得ることができる。  In the present embodiment, the following advantages are obtained by using the Cu vapor deposition film 3. The crystal grain size of Cu in the pure Cu deposited film 3 formed by the vacuum evaporation method or the electron beam evaporation method is smaller than that of the Cu plating film formed by the electroplating method or the electroless plating method. Therefore, a dense film having a high particle density can be obtained.
[0083] また、真空蒸着法又は電子ビーム蒸着法では各種鍍金法と比して薬品や各種溶 液、水などを利用するウエットプロセスを使用しないで済む。このため、非常に環境に 優し！/、プロセスで製造することが可能となる。  [0083] Further, in the vacuum evaporation method or the electron beam evaporation method, a wet process using chemicals, various solutions, water, or the like can be omitted as compared with various plating methods. For this reason it is very environmentally friendly! /, It can be manufactured by the process.
差替え用紙 （規則 ) [0084] また、 Cu合金薄膜 2の成膜プロセスと Cu蒸着膜 3の成膜プロセスとの間にお 、て、 実施の形態 1のようにドライプロセスからウエットプロセスに切り替えを行わないのでス ループットを向上させることができる。 Replacement form (rules) [0084] Since the switching from the dry process to the wet process as in Embodiment 1 is not performed between the film forming process of the Cu alloy thin film 2 and the film forming process of the Cu vapor-deposited film 3, the throughput is high. Can be improved.
[0085] また、スパッタリングによる Cu合金薄膜 2の形成と蒸着法による Cu蒸着膜 3の形成 とを一つの装置によって連続して行うことも可能である。このように一つの装置で連続 して成膜すれば生産性が極めて高ぐ低コストなプロセスを実現することが可能となる  [0085] Further, the formation of the Cu alloy thin film 2 by sputtering and the formation of the Cu vapor deposition film 3 by vapor deposition can be continuously performed by one apparatus. In this way, continuous film formation with one device can realize a very cost-effective process with extremely high productivity.
[0086] また、蒸着法により形成した Cu蒸着膜 3は、各種鍍金法で形成した Cu鍍金膜に比 ベて結晶粒径が微細で緻密なものとなっている。このため、 Cu蒸着膜 3をウエットェ ツチングした際、各種鍍金法で形成した Cu鍍金膜の場合に比べて表面及び断面が 極めて平坦で精細な状態の配線パターン 5a— 5dを得ることができる。特に、 20 /z m 幅以下のラインやスペースを得る配線パターンにお 、ては、マイグレーションや断線 等の配線パターン自体の信頼性に対して優位性が高 、。 [0086] Further, the Cu vapor deposited film 3 formed by the vapor deposition method has a finer and more dense grain size than the Cu plated films formed by various plating methods. For this reason, when the Cu vapor-deposited film 3 is wet-etched, it is possible to obtain fine and fine wiring patterns 5a-5d whose surface and cross-section are extremely flat as compared with the case of Cu-plated films formed by various plating methods. In particular, in the case of a wiring pattern having a line or space of 20 / zm or less in width, the reliability of the wiring pattern itself such as migration or disconnection is superior.
[0087] また、真空蒸着法又は電子ビーム蒸着法にて微細な粒子からなる緻密な Cu蒸着 膜 3を形成すると各種鍍金法と比して表面の平坦性に優れた膜になるために表皮効 果において有利である。  [0087] Further, when a dense Cu vapor-deposited film 3 composed of fine particles is formed by a vacuum vapor deposition method or an electron beam vapor deposition method, a film having excellent surface flatness is obtained as compared with various plating methods. The result is advantageous.
表皮効果とは、高周波電流が導体表面に集中すること、特に導体表面の 1 μ m程 度の厚みの部分にしか高周波電流が流れないことである。このことから、ミクロ的に見 て凹凸のある表面を有する配線パターンを流れる電流のノ スは相対的に長く抵抗値 が増える。このため、表面の平坦性に優れた配線パターンを流れる電流のパスは凹 凸のある場合に比べて長くならず抵抗値が増えることもない。従って、平坦性に優れ た Cu蒸着膜 3では表皮効果において有利となる。  The skin effect means that the high-frequency current is concentrated on the conductor surface, and in particular, the high-frequency current flows only on the conductor surface with a thickness of about 1 μm. From this, the noise of the current flowing through the wiring pattern having an uneven surface when viewed microscopically is relatively long and the resistance value increases. Therefore, the path of the current flowing through the wiring pattern having excellent surface flatness does not become longer and the resistance value does not increase as compared with the case where there are concave and convex portions. Therefore, the Cu vapor deposition film 3 having excellent flatness is advantageous in the skin effect.
[0088] 交流のように時間的に変化する電流では、これによつて発生する誘導磁界も時間 的に変化し、電流の変化を妨げる向きに起電力が発生する。導体中心部の電流ほど 磁束鎖交数が大きく逆起電力も大きいため電流密度は小さくなり、導体の周辺部を 流れるようになる。電流が導体周辺部に集まる度合いを表皮深さという。ここで、周波 数が 5GHzである場合の Cuの表皮深さは 0. 93 /z mである。このため、このような周 波数帯で使用する回路基板であれば、理論的には 0. 93 /z m X 2の厚さの配線バタ ーンを用いることが可能である。 [0088] With a current that changes over time, such as an alternating current, the induced magnetic field generated by the change also changes over time, and an electromotive force is generated in a direction that prevents the change in the current. As the current in the center of the conductor increases, the number of flux linkages and the back electromotive force also increase, so the current density decreases, and the current flows in the periphery of the conductor. The degree to which the current gathers around the conductor is called the skin depth. Here, when the frequency is 5 GHz, the skin depth of Cu is 0.93 / zm. Therefore, if a circuit board is used in such a frequency band, a wiring bump having a thickness of 0.93 / zm X 2 is theoretically possible. Can be used.
[0089] (実施の形態 7)  (Embodiment 7)
本発明の実施の形態 7による回路基板の製造方法について図 4を参照しつつ説明 する。図 4は実施の形態 3による回路基板の製造方法を示すものであるが、実施の形 態 3において Cu鍍金膜 3を真空蒸着法又は電子ビーム蒸着法により成膜した Cu蒸 着膜に変更したものが実施の形態 7である。  A method of manufacturing a circuit board according to Embodiment 7 of the present invention will be described with reference to FIG. FIG. 4 shows a method for manufacturing a circuit board according to the third embodiment.In the third embodiment, the Cu plating film 3 is changed to a Cu vapor deposition film formed by a vacuum vapor deposition method or an electron beam vapor deposition method. This is the seventh embodiment.
[0090] まず、図 4 (A)に示すように、基板 1の表面上及び裏面上に膜厚が 5nm以上 1 μ m 以下の Cu合金薄膜 2をスパッタリングにより形成する。 Cu合金薄膜 2は実施の形態 1 と同様の合金力もなり、基板 1は実施の形態 1と同様の材料力もなる。  First, as shown in FIG. 4A, a Cu alloy thin film 2 having a thickness of 5 nm or more and 1 μm or less is formed on the front surface and the back surface of the substrate 1 by sputtering. The Cu alloy thin film 2 has the same alloy strength as in the first embodiment, and the substrate 1 has the same material strength as in the first embodiment.
[0091] この後、図 4 (B)に示すように、基板 1の表面側及び裏面側において Cu合金薄膜 2 の上に真空蒸着法又は電子ビーム蒸着法により膜厚が 300nm以上 30 μ m以下の Cu蒸着膜 3を形成する。 Cu合金薄膜 2と Cu蒸着膜 3との密着性が良ぐ Cu合金薄 膜 2と基板 1との密着性が良いことは実施の形態 6と同様である。  [0091] Thereafter, as shown in FIG. 4 (B), the film thickness is 300 nm or more and 30 μm or less on the Cu alloy thin film 2 on the front side and the back side of the substrate 1 by vacuum evaporation or electron beam evaporation. A Cu vapor deposition film 3 is formed. Good adhesion between the Cu alloy thin film 2 and the deposited Cu film 3 Good adhesion between the Cu alloy thin film 2 and the substrate 1 is the same as in the sixth embodiment.
[0092] 次に、実施の形態 6と同様の方法により、 Cu蒸着膜 3及び Cu合金薄膜 2をウエット エッチングすることにより、基板 1の表面上及び裏面上それぞれには Cu蒸着膜 3及 び Cu合金薄膜 2からなる配線パターンが形成される（図示せず)。  [0092] Next, the Cu vapor deposition film 3 and the Cu alloy thin film 2 are wet-etched by the same method as in the sixth embodiment, so that the Cu vapor deposition film 3 and Cu A wiring pattern made of the alloy thin film 2 is formed (not shown).
[0093] 上記実施の形態 7においても実施の形態 6と同様の効果を得ることができる。  [0093] The same effects as in the sixth embodiment can be obtained in the seventh embodiment.
[0094] (実施の形態 8)  (Embodiment 8)
本発明の実施の形態 8による回路基板の製造方法について図 5を参照しつつ説明 する。図 5は実施の形態 4による回路基板の製造方法を示すものであるが、実施の形 態 4において Cu鍍金膜 3を真空蒸着法又は電子ビーム蒸着法により成膜した Cu蒸 着膜に変更したものが実施の形態 8である。  A method of manufacturing a circuit board according to Embodiment 8 of the present invention will be described with reference to FIG. FIG. 5 shows a method of manufacturing a circuit board according to the fourth embodiment.In the fourth embodiment, the Cu plating film 3 is changed to a Cu deposition film formed by a vacuum deposition method or an electron beam deposition method. This is the eighth embodiment.
[0095] まず、図 5 (A)に示すように、貫通孔であるスルーホール laを有する基板 1を準備 する。  First, as shown in FIG. 5A, a substrate 1 having a through hole la as a through hole is prepared.
[0096] 次いで、図 5 (B)〖こ示すように、基板 1の表面上、裏面上及びスルーホール la内に 膜厚が 5nm以上 1 μ m以下の Cu合金薄膜 2をスパッタリングにより形成する。 Cu合 金薄膜 2は実施の形態 1と同様の合金力もなり、基板 1は実施の形態 1と同様の材料 からなる。 [0097] この後、図 5 (C)に示すように、基板 1の表面側、裏面側及びスルーホール la内に おいて Cu合金薄膜 2の上に真空蒸着法又は電子ビーム蒸着法により膜厚が 300η m以上 30 m以下の Cu蒸着膜 3を形成する。 Cu合金薄膜 2と Cu蒸着膜 3との密着 性が良ぐ Cu合金薄膜 2と基板 1との密着性が良いことは実施の形態 6と同様である Next, as shown in FIG. 5B, a Cu alloy thin film 2 having a thickness of 5 nm or more and 1 μm or less is formed on the front surface, the back surface, and in the through hole la of the substrate 1 by sputtering. The Cu alloy thin film 2 has the same alloy force as in the first embodiment, and the substrate 1 is made of the same material as in the first embodiment. Thereafter, as shown in FIG. 5 (C), the film thickness is formed on the Cu alloy thin film 2 on the front side, the back side, and the through hole la of the substrate 1 by a vacuum evaporation method or an electron beam evaporation method. Forms a Cu vapor deposition film 3 having a thickness of 300 η m or more and 30 m or less. Good adhesion between Cu alloy thin film 2 and vapor deposited film 3 Good adhesion between Cu alloy thin film 2 and substrate 1 is the same as in Embodiment 6.
[0098] 次に、実施の形態 6と同様の方法により、 Cu蒸着膜 3及び Cu合金薄膜 2をウエット エッチングすることにより、基板 1の表面上及び裏面上それぞれには Cu蒸着膜 3及 び Cu合金薄膜 2からなる配線パターンが形成される（図示せず)。 [0098] Next, the Cu vapor deposition film 3 and the Cu alloy thin film 2 are wet-etched in the same manner as in Embodiment 6, so that the Cu vapor deposition film 3 and the Cu vapor deposition film 3 and Cu A wiring pattern made of the alloy thin film 2 is formed (not shown).
[0099] 上記実施の形態 8においても実施の形態 6と同様の効果を得ることができる。  [0099] The same effects as in the sixth embodiment can be obtained in the eighth embodiment.
[0100] (実施の形態 9)  [0100] (Embodiment 9)
本発明の実施の形態 9による回路基板の製造方法について図 6を参照しつつ説明 する。図 6は実施の形態 5による回路基板の製造方法を示すものであるが、実施の形 態 5において Cu鍍金膜 3, 12を真空蒸着法又は電子ビーム蒸着法により成膜した C u蒸着膜に変更したものが実施の形態 9である。  A method for manufacturing a circuit board according to Embodiment 9 of the present invention will be described with reference to FIG. FIG. 6 shows a method of manufacturing a circuit board according to the fifth embodiment. In the fifth embodiment, Cu plating films 3 and 12 are formed on a Cu vapor deposition film formed by a vacuum vapor deposition method or an electron beam vapor deposition method. The modified embodiment is the ninth embodiment.
[0101] まず、図 6 (A)に示すように、基板 1の上に膜厚が 5nm以上 1 μ m以下の Cu合金薄 膜 2をスパッタリングにより形成し、 Cu合金薄膜 2の上に真空蒸着法又は電子ビーム 蒸着法により膜厚が 300nm以上 30 m以下の Cu蒸着膜 3を形成する。次いで、 C u蒸着膜 3及び Cu合金薄膜 2をパターユングすることにより、基板 1の上には Cu蒸着 膜 3及び Cu合金薄膜 2からなる配線パターン（図示せず)が形成される。ここまでの 工程は実施の形態 6と同様である。  [0101] First, as shown in FIG. 6 (A), a Cu alloy thin film 2 having a thickness of 5 nm to 1 μm is formed on a substrate 1 by sputtering, and is vacuum-deposited on the Cu alloy thin film 2. A Cu vapor deposition film 3 having a thickness of 300 nm or more and 30 m or less is formed by a method or an electron beam vapor deposition method. Next, by patterning the Cu deposited film 3 and the Cu alloy thin film 2, a wiring pattern (not shown) composed of the Cu deposited film 3 and the Cu alloy thin film 2 is formed on the substrate 1. The steps so far are the same as in the sixth embodiment.
[0102] この後、実施の形態 5と同様の方法により、配線パターン及び基板 1の上にポリイミ ド膜 10を形成し、このポリイミド膜 10に配線パターン上に位置するスルーホール 10a を形成す。  After that, a polyimide film 10 is formed on the wiring pattern and the substrate 1 by the same method as in the fifth embodiment, and a through hole 10a located on the wiring pattern is formed in the polyimide film 10.
[0103] 次に、図 6 (B)に示すように、スルーホール 10aの底面、内側面及びポリイミド膜 10 上に膜厚が 5nm以上 1 μ m以下の Cu合金薄膜 11をスパッタリングにより形成し、 Cu 合金薄膜 11の上に真空蒸着法又は電子ビーム蒸着法により膜厚が 300nm以上 30 m以下の Cu蒸着膜 12を形成する。次いで、 Cu蒸着膜 12及び Cu合金薄膜 11を ノターニングすることにより、基板 1の上には Cu蒸着膜 12及び Cu合金薄膜 11から なる配線パターン（図示せず)が形成される。これらの工程は実施の形態 6と同様の 方法を用いる。ポリイミド膜 10上の配線パターンは基板 1上の配線パターンとスルー ホール 10aを介して接続される。 Next, as shown in FIG. 6 (B), a Cu alloy thin film 11 having a thickness of 5 nm or more and 1 μm or less is formed by sputtering on the bottom surface, the inner side surface of the through hole 10a, and the polyimide film 10; On the Cu alloy thin film 11, a Cu evaporated film 12 having a thickness of 300 nm or more and 30 m or less is formed by a vacuum evaporation method or an electron beam evaporation method. Next, the Cu deposited film 12 and the Cu alloy thin film 11 are not-turned, so that the Cu deposited film 12 and the Cu alloy thin film 11 are formed on the substrate 1. Wiring pattern (not shown) is formed. These steps use the same method as in the sixth embodiment. The wiring pattern on the polyimide film 10 is connected to the wiring pattern on the substrate 1 via through holes 10a.
[0104] 上記の方法により多層配線構造を有する回路基板が形成される。尚、図 6 (B)に示 す回路基板では基板上に 2層の配線層が形成された多層配線構造となっているが、 3層以上の配線層を基板上に形成することも可能である。この場合は、図 6 (B)に示 す 2層目の配線層を形成する工程を 3層目以降も繰り返すことにより、 3層以上の多 層配線構造を形成することができる。  [0104] A circuit board having a multilayer wiring structure is formed by the above method. Although the circuit board shown in FIG. 6B has a multilayer wiring structure in which two wiring layers are formed on the substrate, three or more wiring layers can be formed on the substrate. is there. In this case, a multi-layer wiring structure of three or more layers can be formed by repeating the process of forming the second wiring layer shown in FIG. 6B for the third and subsequent layers.
[0105] 上記実施の形態 9においても実施の形態 6と同様の効果を得ることができる。  [0105] The same effects as in the sixth embodiment can be obtained in the ninth embodiment.
[0106] また、スルーホール 10a内に Cu合金薄膜 11をスパッタリングにより形成しているた め、微細なスルーホール 10aであっても膜厚を薄く且つカバレージ良く Cu合金薄膜 11を成膜することができる。つまり、配線パターンが微細化されてスルーホールの微 細化が進んだ場合に特に有効なものとなる。  [0106] Further, since the Cu alloy thin film 11 is formed in the through hole 10a by sputtering, the Cu alloy thin film 11 can be formed with a small thickness and good coverage even in the fine through hole 10a. it can. In other words, this is particularly effective when the wiring pattern is miniaturized and the through hole is miniaturized.
[0107] また、 Cu合金薄膜 11をスパッタリングにより成膜すると膜厚制御性が非常に良い。  Further, when the Cu alloy thin film 11 is formed by sputtering, the film thickness controllability is very good.
また、ポリイミド膜 10と Cu合金薄膜 11との密着性が非常に良ぐ実用上必要な密 着性を十分に確保することができる。  In addition, the adhesiveness between the polyimide film 10 and the Cu alloy thin film 11 is very good, and the adhesiveness necessary for practical use can be sufficiently secured.
[0108] 尚、本発明は上述した実施の形態に限定されるものではなぐ本発明の主旨を逸 脱しない範囲内で種々変更して実施することが可能である。例えば、実施の形態 1乃 至 9において自明の範囲内で、実施の形態を互いに組み合わせて実施することも可 能である。  [0108] The present invention is not limited to the above-described embodiment, and can be implemented with various modifications without departing from the spirit of the present invention. For example, the first to ninth embodiments can be combined with each other within the obvious range.
[0109] また、実施の形態 3及び 7による両面に配線パターンを有する回路基板に、実施の 形態 1における半導体チップ 8を実施の形態 1と同様の方法を用いて実装することも 可能である。  Further, the semiconductor chip 8 of the first embodiment can be mounted on the circuit board having wiring patterns on both surfaces according to the third and seventh embodiments by using the same method as that of the first embodiment.
[0110] また、実施の形態 4及び 8によるスルーホール laを有する回路基板に、実施の形態 1における半導体チップ 8を実施の形態 1と同様の方法を用いて実装することも可能 である。  The semiconductor chip 8 of the first embodiment can be mounted on the circuit board having the through holes la according to the fourth and eighth embodiments by using the same method as that of the first embodiment.
[0111] また、実施の形態 5及び 9による多層配線構造を有する回路基板に、実施の形態 1 における半導体チップ 8を実施の形態 1と同様の方法を用いて実装することも可能で ある。 Further, the semiconductor chip 8 of the first embodiment can be mounted on the circuit board having the multilayer wiring structure according to the fifth and ninth embodiments using the same method as that of the first embodiment. is there.
[0112] また、実施の形態 3及び 7による回路基板に実施の形態 5及び 9による多層配線構 造を設けることも可能である。この場合、多層配線構造は両面でも片面でも良い。  Further, it is also possible to provide the multilayer wiring structure according to the fifth and ninth embodiments on the circuit board according to the third and seventh embodiments. In this case, the multilayer wiring structure may be either double-sided or single-sided.
[0113] また、実施の形態 4及び 8による回路基板に実施の形態 5及び 9による多層配線構 造を設けることも可能である。この場合、多層配線構造は両面でも片面でも良い。  [0113] Further, it is also possible to provide the multilayer wiring structure according to the fifth and ninth embodiments on the circuit board according to the fourth and eighth embodiments. In this case, the multilayer wiring structure may be either double-sided or single-sided.
[0114] また、実施の形態 5及び 9では、基板 1の片面に多層配線構造を設けているが、基 板 1の両面に多層配線構造を設けることも可能である。  Further, in the fifth and ninth embodiments, the multilayer wiring structure is provided on one side of the substrate 1, but it is also possible to provide the multilayer wiring structure on both sides of the substrate 1.
[0115] また、上記実施の形態では、ポリイミド、液晶ポリマー、テフロン (登録商標）又はェ ポキシ榭脂等カゝらなる高分子材料或いは榭脂材料によって形成された基板 1を用い ているが、基板の材質はこれらに限定されるものではなぐ基板の材質を種々変更し て実施することも可能である。例えば、 Al O又は Al Oを主原料とした複合酸化物、  [0115] In the above embodiment, the substrate 1 formed of a polymer material or a resin material such as polyimide, liquid crystal polymer, Teflon (registered trademark) or epoxy resin is used. The material of the substrate is not limited to those described above, and the material of the substrate can be variously changed to carry out the invention. For example, Al O or a composite oxide containing Al O as a main raw material,
2 3 2 3  2 3 2 3
A1N、 SiOなどのセラミック、紙基材フエノール榭脂銅張積層板、紙基材エポキシ榭  Ceramics such as A1N, SiO, etc., paper-based phenol (fat copper-clad laminate, paper-based epoxy)
2  2
脂銅張積層板、合成繊維布基材エポキシ榭脂銅張積層板、ガラス布 ·紙複合基材ェ ポキシ榭脂銅張積層板、ガラス布 ·ガラス不織布複合基材エポキシ榭脂銅張積層板 、ガラス布基材エポキシ榭脂銅張積層板、ガラス基材ポリイミド榭脂銅張積層板、ガ ラス基材 BT榭脂銅張積層板、ガラス基材ふつ素榭脂銅張積層板、ガラス基材熱硬 化型 PPO榭脂銅張積層板などの基板を用いることも可能である。  Fat-clad laminates, synthetic fiber cloth-based epoxy-clad copper-clad laminates, glass cloth · Paper composite base epoxy-fat-copper-clad laminates, glass cloth · Glass nonwoven composite base epoxy-fat-copper-clad laminates , Glass cloth-based epoxy resin-clad laminate, glass-based polyimide resin-clad laminate, glass substrate BT resin-clad laminate, glass-based fluorine resin-clad laminate, glass base It is also possible to use a substrate such as a heat-hardened PPO / copper-clad laminate.
実施例  Example
[0116] 以下、実施例について説明する。  Hereinafter, examples will be described.
市販のポリイミド、液晶ポリマー、テフロン (登録商標）、エポキシ榭脂からなる基板 上に、 DCマグネトロンスパッタ装置（昭和真空製、 TSP)を用いて、スパッタ膜槽内を 1 X 10— 5トールに排気した後、電圧 1.0キロボルトにて厚み lOOnmの下地層をスパッタ 蒸着し、更にその下地層上に、排気条件が同じ槽内で、電子線加熱方式の真空蒸 着装置（日本真空社製、 EBH—6)を用いて、電圧 2.0キロボルトにて厚み 2— 10 m の銅をそれぞれ蒸着し、金属積層体/樹脂基材を作製した。この金属積層体/樹脂 基材の常態での接着強度と、 121°C100%RHの環境に 96時間曝露した後の金属層と 榭脂基材の接着強度を JIS、 C-6481に従って銅パターン幅 50 mで 90度ピール試験 法にて評価した。 [0117] 実施例の評価に当たり、作成した試験基材は表 1の通りである。表 1における下地 膜の組成は、実施例 1一 4が Tiを 0.5— 5重量％含有し、残部が Cuからなる合金であ り、実施例 5— 8が Moを 0.5— 5重量％含有し、残部が Cuからなる合金であり、実施 例 9一 12が Niを 0.5— 5重量％含有し、残部が Cuからなる合金であり、実施例 13— 1 6が A1を 0.5— 5重量％含有し、残部が Cuからなる合金であり、実施例 17— 20が Ag を 0.5— 5重量％含有し、残部が Cuからなる合金である。 Exhaust commercially available polyimide, liquid crystal polymer, Teflon (registered trademark), on a substrate made of an epoxy榭脂, DC magnetron sputtering apparatus (Showa vacuum Ltd., TSP) using a sputtering film bath to 1 X 10- 5 torr After that, an underlayer with a thickness of 100 nm was sputter-deposited at a voltage of 1.0 kV, and an electron beam heating type vacuum evaporation device (EBH, manufactured by Nippon Vacuum Co., Ltd., EBH- Using 6), copper having a thickness of 2 to 10 m was vapor-deposited at a voltage of 2.0 kV to prepare a metal laminate / resin base material. The bond strength of this metal laminate / resin base material under normal conditions and the bond strength of the metal layer and the resin base material after being exposed to an environment of 121 ° C and 100% RH for 96 hours are determined according to JIS and C-6481. Evaluated by a 90 degree peel test method at 50 m. [0117] In the evaluation of the examples, the test base materials prepared are as shown in Table 1. The composition of the undercoat film in Table 1 is as follows. Example 14 shows an alloy containing 0.5 to 5% by weight of Ti and the balance being Cu. Examples 5 to 8 contain 0.5 to 5% by weight of Mo. Example 9-12 contains 0.5 to 5% by weight of Ni, and the remainder is an alloy composed of Cu, and Example 13-16 contains an alloy of 0.5 to 5% by weight of A1. The balance is an alloy composed of Cu, and Examples 17-20 are alloys containing 0.5 to 5% by weight of Ag and the balance composed of Cu.
[0118] [表 1]  [0118] [Table 1]
Figure imgf000024_0001
Figure imgf000024_0001
[0119] また、表 1に記載する実施例の効果を確認する為に、表 2に記載する比較例となる 試験基材を作成した。 [0120] [表 2] [0119] Further, in order to confirm the effects of the examples shown in Table 1, test substrates as comparative examples shown in Table 2 were prepared. [0120] [Table 2]
Figure imgf000025_0001
Figure imgf000025_0001
[0121] 上記の表 1及び表 2の通りの実施例および比較例の金属積層体/樹脂基材の常態 での接着強度と、 121°C100%RHの環境に 96時間曝露した後の金属層と榭脂基材の 接着強度を JIS、 C- 6481に従って銅パターン幅 50 mで 90度ピール試験法にて評価 した。 [0121] The adhesive strength of the metal laminate / resin base material in Examples and Comparative Examples in Tables 1 and 2 in the normal state and the metal layer after being exposed to an environment of 121 ° C and 100% RH for 96 hours. The adhesive strength between the resin and the resin substrate was evaluated by a 90-degree peel test method with a copper pattern width of 50 m according to JIS and C-6481.
評価の結果は表 3通りである。  Table 3 shows the results of the evaluation.
[0122] [表 3] [0122] [Table 3]
試験基材 常態（N/cm) PCT後（N/cm) Test substrate Normal condition (N / cm) After PCT (N / cm)
実施例 1 8. 9 7. 4  Example 1 8.9 7.4
実施例 2 8. 6 7. 7  Example 2 8.6.7.7
実施例 3 8. 8 7. 5  Example 3 8.8 7.5
実施例 4 8. 3 7. 4  Example 4 8.3 7.4
実施例 5 8. 4 6. 7  Example 5 8. 4.6.7
実施例 6 7. 3 6. 9  Example 6 7.3.6.9
実施例 7 8. 1 6. 6  Example 7 8.1.6.6
実施例 8 8. 6 6. 8  Example 8 8.6.6.8
実施例 9 8. 9 7. 1  Example 9 8.97.1.
実施例 1 0 8. 2 7. 3  Example 1 0 8. 2 7.3
実施例 1 1 8. 5 7. 1  Example 1 1 8.5 7-1
実施例 1 2 8. 6 6. Θ  Example 1 2 8. 6. 6.
実施例 1 3 8. 8 7. 8  Example 1 3 8. 8 7. 8
実施例 1 4 8. 3 7. 3  Example 1 4 8.3 7.3
実施例 1 5 8. 7 7. 4  Example 1 5 8. 7 7.4
実施例 1 6 8. 4 7. 6  Example 1 6 8.4 7.6
実施例 1 7 8. 4 5. 5  Example 1 7 8.4 5.5
実施例 1 8 8. 2 5. 3  Example 1 8 8.2 5.3
実施例 1 9 8. 4 5. 3  Example 1 9 8.4 5.3
実施例 20 8. 9 5. 6  Example 20 8.9 5.6
比較例 1 7. 5 3. 3  Comparative Example 1 7.5 3.3
比較例 2 8. 4 2. 2  Comparative Example 2 8.4.2.2.
比較例 3 8. 1 5. 8  Comparative Example 3 8. 1 5.8
比較例 4 7. 9 5. 4  Comparative Example 4 7. 9 5. 4
比較例 5 6. 5 2. 1  Comparative Example 5 6.5.2.1
比較例 6 4. 8 1 . 3 上記の表 3の通り、 Cuを主成分として Ti, Mo, Ni, Al, Agの内より少なくとも 1種類以 上の金属が 0.5— 5重量％で含有される合金材料を用いて各種榭脂基材の上層にス パッタリング法にて下地を形成し、その後に蒸着法にて純 Cuを形成してなる回路基 板はいずれも高密着性であり、かつ PCT後での経時変化が少ない為に環境に左右 されな ヽで安定で、回路基板として高信頼性を得られることが確認される。 [0124] 上記の表 3にある、比較例 3, 4も密着性の常態および PCT後の結果は充分に産業 上の有用性を確保して 、るが、金属 Crはエッチング中に酸素と結合して六価クロムを 生成し、この六価クロムは環境上極めて毒性が高ぐ PRTR規制や RoHS規制でも特 に指定される為に、特性は得られてもこうした環境上の問題が生じる為に、使用撤廃 の方向に進んでいる。これは従来、本発明の従来技術で産業上、使用されている NiCrについても同様であり、技術的な優位性以外にも本発明は環境上の優位性も多 く含むことは確認できる。 Comparative Example 6 4.8.1 .3 As shown in Table 3 above, at least one or more metals are contained at 0.5 to 5% by weight of Cu, Ti, Mo, Ni, Al, and Ag as main components. Circuit boards made by forming an underlayer on the upper layer of various resin base materials using an alloy material by a sputtering method and then forming pure Cu by an evaporation method have high adhesion, and Since there is little change with time after PCT, it is stable regardless of the environment, and it is confirmed that high reliability as a circuit board can be obtained. [0124] In Comparative Examples 3 and 4 in Table 3 above, the normal state of adhesion and the results after PCT sufficiently ensure industrial utility, but metal Cr binds to oxygen during etching. Hexavalent chromium is generated, and this hexavalent chromium is extremely toxic in the environment. It is specified especially in the PRTR regulations and the RoHS regulations. However, the use is being abolished. This is the same for NiCr which has been conventionally used industrially in the prior art of the present invention, and it can be confirmed that the present invention has many environmental advantages in addition to technical advantages.
[0125] 即ち、本発明の構造にて得られた回路基板を用いてフレキシブルプリント配線板を 製造すると、耐環境性、特には高温高湿環境下に暴露された後での接着強度が優 れる為に、高温高湿の厳しい環境下でも機能を損なうことなく作動する電気機器回路 として好適な金属積層体/樹脂基板及びフレキシブルプリント配線板を提供すること ができると!ヽぅ有利性が与えられる。  [0125] That is, when a flexible printed wiring board is manufactured using the circuit board obtained by the structure of the present invention, the environment resistance, particularly the adhesive strength after being exposed to a high-temperature and high-humidity environment, is excellent. Therefore, if it is possible to provide a metal laminate / resin substrate and a flexible printed wiring board suitable as an electric device circuit that can operate without impairing the function even in a harsh environment of high temperature and high humidity, the advantage is given. .
[0126] 更に、真空蒸着法とは金属や非金属を真空中で加熱蒸発させ、金属やガラス、プ ラスチック表面上にコーティングして薄膜を作製する技術で、レンズの反射防止、光 学フィルターから電子デバイスなどの分野で広く用いられている。現在の真空蒸着法 は金属等を加熱蒸発させる過程で材料の溶融状態が発生することから、材料を坩堝 内に入れて溶融'蒸発させ上方の基板に蒸発した原子、分子を付着させてコーティ ングしている。この方法で回路基板を形成することは従来も標準的であつたが、従来 の技術においては材料技術の確立が実現できずに居た為に、実用化はされず、実 用化及び実現の目処も立っていな力つた。この為、本発明の下地層を用いることで、 産業上でははじめて実用化されることとなり、本発明の優位性が確認できる事実であ る。  [0126] Furthermore, the vacuum evaporation method is a technique in which a metal or nonmetal is heated and evaporated in a vacuum, and is coated on a metal, glass, or plastic surface to form a thin film. Widely used in fields such as electronic devices. In the current vacuum deposition method, the molten state of the material occurs during the process of heating and evaporating metal, so the material is put into a crucible and melted and evaporated, and the evaporated atoms and molecules are attached to the substrate above and coated. are doing. Forming a circuit board by this method has been a standard in the past, but the conventional technology has not been able to establish a material technology, so it has not been put to practical use. I couldn't stand. Therefore, by using the underlayer of the present invention, it will be practically used for the first time in industry, and it is a fact that the superiority of the present invention can be confirmed.
[0127] 次に、純 Cu層を蒸着法で形成する効果としては、従来のメツキ法や銅箔を貼り合わ せる方法と比して、微粒子で緻密な層を形成することで、回路を構成する配線'電極 としての信頼性の向上が上げられる。  [0127] Next, the effect of forming the pure Cu layer by the vapor deposition method is that, compared to the conventional plating method or the method of laminating copper foil, the circuit is formed by forming a fine layer with fine particles. This improves the reliability of the wiring / electrode to be used.
[0128] (実験）  [0128] (Experiment)
この回路パターン自体の信頼性評価として、耐マイグレーション性を実験した。 まず、前記の密着性評価と同様に、市販のポリイミド、液晶ポリマー、テフロン (登録 商標） 、 エポキシ樹脂からなる基板上に、 D Cマグネトロンスパッタ装置 （昭和真空製 、 T S P ) を用いて、 スパッタ膜槽内を 1 x 10 トールに排気した後、 電圧 1.0キロポ ルトにて厚み 100n mの下地層をスパッタ蒸着し、 更にその下地層上に、 排気条件が同 じ槽内で、 電子線加熱方式の真空蒸着装置 （日本真空社製、 E B H- 6 ) を用いて、 電 圧 2.0キロポルトにて厚み 2~1 0 /z mの銅をそれぞれ蒸着し、 金属積層体/樹脂基材を作 製した。 As an evaluation of the reliability of the circuit pattern itself, migration resistance was tested. First, in the same manner as in the adhesion evaluation described above, commercially available polyimide, liquid crystal polymer, Teflon (registered (Trademark) and epoxy resin on a substrate using a DC magnetron sputtering device (manufactured by Showa Vacuum, TSP) to evacuate the sputtered film tank to 1 x 10 Torr and then apply a voltage of 1.0 kPa and a thickness of 100 nm. An underlayer was sputter-deposited, and a voltage of 2.0 kPa was applied on the underlayer using an electron beam heating vacuum evaporation apparatus (EBH-6, manufactured by Nihon Vacuum) in the same evacuation chamber. Then, copper having a thickness of 2 to 10 / zm was vapor-deposited, respectively, to produce a metal laminate / resin base material.
[0129] この金属積層体をウエットエッチング法により図 7に示すように 20 μ ΓΠ幅のくし型の 電極配線パターンを電極配線同士が接しないように交互に組み合わせた。 A〜F , a〜 f の線幅は全て 2 0 μ mである。 A〜F， a〜 f は全て等間隔 4 0 μ mである。 A， a ， B , b等の大文字線と小文字線も全て等間隔 2 0 z mである。  As shown in FIG. 7, this metal laminate was alternately combined with a comb-shaped electrode wiring pattern having a width of 20 μm so that the electrode wirings did not contact each other, as shown in FIG. The line widths of A to F and a to f are all 20 μm. A to F and a to f are all equally spaced 40 μm. All uppercase and lowercase lines such as A, a, B, and b are equally spaced 20 z m.
[0130] その後、 この電極間に 1 // Lのイオン交換水を滴下し、 銅イオン溶出量を、 イオン濃 度を変色度に置き換え、 カラースケールと比較して、 ある程度の量的判定を加味した定 性分析に使用される半定量イオン試験紙を用いて測定した。  [0130] After that, 1 // L of ion-exchanged water was dropped between the electrodes, the copper ion elution amount was replaced with the ion concentration by the degree of color change, and compared with the color scale, taking into account some quantitative judgment It was measured using the semi-quantitative ion test paper used for the qualitative analysis.
[0131] 金属銅の標準電極電位は、 Cu2 +で +0.337V (標準水素電極『Standard Hydrogen Elect rode』 の電位に対する電位差であることを示す表わし方。 ） 、 Cu+で + 0.520V (vs.SHE ) において水溶液中で溶解する。 このため、 水が電気分解する理論電圧以下の 1VDC 付近でも銅イオンは溶出するが、 電圧が高いほど、 銅イオン溶出量が增加する。 [0131] metal standard electrode potential of copper, Cu 2 + at + 0.337V (how represents indicating a difference with respect to the potential of the standard hydrogen electrode "Standard Hydrogen Elect rode".), Cu + in + 0.520V (vs .SHE) in aqueous solution. For this reason, copper ions are eluted even at around 1 VDC below the theoretical voltage at which water is electrolyzed, but the higher the voltage, the greater the amount of copper ions eluted.
[0132] この溶出した金属イオンが拡散、 還元することによりイオンマイグレーションが発生 し、 回路基板内の配線電極の信頼性が損なわれる課題がある。 そこで、 蒸着法で形成し た配線電極を有す回路基板の信頼性を評価して従来のメツキ法との差異を確認する。 評 価の手段としては、 印加電圧および pH を変化させ、 金属イオンの拡散、 還元過程を考 察した。  [0132] There is a problem that the ion migration occurs due to the diffusion and reduction of the eluted metal ions, and the reliability of the wiring electrodes in the circuit board is impaired. Therefore, the reliability of the circuit board having the wiring electrodes formed by the vapor deposition method is evaluated to confirm the difference from the conventional plating method. As a means of evaluation, the applied voltage and pH were varied, and the diffusion and reduction processes of metal ions were considered.
[0133] この際、 イオンマイグレーション耐性の評価基準としては、 IPC (=The institute for Jnterconnecting and Packaging Electronic Circuits) に規格される 『TM― 650 - 2.6.3 プリント配線板の加湿時の絶縁抵抗試験』 のクラス 2と同様に 50°C， 85〜93%RHで引 加電圧量としては 10VDGで 7 日間放置した後での配線電極の破壊もしくは劣化の有無 を確認するものとした。  [0133] At this time, as a standard for evaluating the ion migration resistance, "TM-650-2.6.3 Insulation resistance test during humidification of printed wiring board" specified in IPC (= The institute for Jnterconnecting and Packaging Electronic Circuits) Similar to Class 2 of the above, the applied voltage was applied at 50 ° C and 85 to 93% RH for 10 days at 10 VDG for 7 days.
[0134] 上記のィオンマイグレーション耐性の評価結果として、 表 4の通りに鍍金法や下地層 の材質に関連して、 最上層に Cuを蒸着法で形成した配線電極を有する回路基板  [0134] As a result of the evaluation of the ion migration resistance, as shown in Table 4, a circuit board having a wiring electrode in which Cu is formed on the uppermost layer by a vapor deposition method in relation to the plating method and the material of the underlayer.
羞眷ぇ用弒 （規則 26) は、 Cu層が微粒子で緻密であることより、配線および電極としての信頼性が高いこと が確認できた。尚、表 4における試験基材のスパッタ層の組成は、 Moを 0.5〜5重量 %含有し、残部が Cuからなる合金である。 For Families (Rule 26) It was confirmed that the Cu layer had high reliability as wiring and electrodes because the Cu layer was fine and dense. The composition of the sputter layer of the test substrate in Table 4 is an alloy containing 0.5 to 5% by weight of Mo and the balance being Cu.
[表 4]  [Table 4]
Figure imgf000029_0001
Figure imgf000029_0001
[0136] 図 8は、イオンマイグレーションのメカニズムを説明する模式図である。 FIG. 8 is a schematic diagram illustrating the mechanism of ion migration.
図 8に示すように、两電極に直流のバイアス電圧が印加されて！/、る場合にお!/、て、 本来、絶縁層であるべき箇所が、水分やイオン性残渣などによって、電解質の性質 を持つようになる。この時、電極金属特有の電位と pH (ペーハー）の関係で、イオン化 する領域において、電極金属がアノード力 溶出するようになる。多くはこれ力 その 成長過程で還元析出するか、力ソードで還元析出する場合に区別される。発生場所 は絶縁層表面、絶縁層界面、層間中などに見られ、これが伸びて電極間の短絡に至 る。  As shown in Fig. 8, a DC bias voltage is applied to the 两 electrode! /, In the case of! /, The part which should be an insulating layer originally has the property of electrolyte due to moisture and ionic residue. At this time, the electrode metal is eluted anodicly in the region of ionization due to the relationship between the potential specific to the electrode metal and the pH (pH). Many are distinguished by the case where this is reduced by precipitation during the growth process or reduced by force sword. The place of occurrence is found on the surface of the insulating layer, at the interface of the insulating layer, between layers, etc., and this extends and leads to a short circuit between the electrodes.
図面の簡単な説明  Brief Description of Drawings
[0137] [図 1] (A)〜(E)は、本発明の実施の形態 1による回路基板を製造し、回路基板上に 電子部品を実装する方法を示す断面図である。  [FIG. 1] (A) to (E) are cross-sectional views illustrating a method of manufacturing a circuit board according to Embodiment 1 of the present invention and mounting electronic components on the circuit board.
[図 2] (A) , (B)は、本宪明の実施の形態 1による回路基板を製造し、回路基板上に ' 電子部品を実装する方法を示すものであり、図 1 (E)の次の工程を示す断面図であ る。 .  [FIG. 2] (A) and (B) show a method of manufacturing a circuit board according to Embodiment 1 of the present invention and mounting electronic components on the circuit board. FIG. 6 is a cross-sectional view showing the next step. .
[図 3] (A)〜 (E)は、本努明の実施の形態 2による回路基板を製造する方法を示す断  [FIG. 3] (A) to (E) are sectional views showing a method of manufacturing a circuit board according to Embodiment 2 of the present invention.
差替え用紙 （規則 26) 面図である。 Replacement form (Rule 26) FIG.
[図 4] (A) , (B)は、本発明の実施の形態 3による回路基板の製造方法を示す断面図 である。  FIGS. 4A and 4B are cross-sectional views illustrating a method of manufacturing a circuit board according to Embodiment 3 of the present invention.
[図 5] (A)一 (C)は、本発明の実施の形態 4による回路基板の製造方法を示す断面 図である。  5 (A) -1 (C) are cross-sectional views illustrating a method for manufacturing a circuit board according to Embodiment 4 of the present invention.
[図 6] (A) , (B)は、本発明の実施の形態 5による回路基板の製造方法を示す断面図 である。  FIGS. 6A and 6B are cross-sectional views illustrating a method of manufacturing a circuit board according to Embodiment 5 of the present invention.
[図 7]耐マイグレーション性の実験方法を説明する模式図である。  FIG. 7 is a schematic diagram illustrating an experiment method of migration resistance.
[図 8]イオンマイグレーションのメカニズムを説明する模式図である。  FIG. 8 is a schematic diagram illustrating a mechanism of ion migration.
[図 9] (A) , (B)は、従来の回路基板の製造方法を示す断面図である。  FIGS. 9A and 9B are cross-sectional views illustrating a conventional method for manufacturing a circuit board.
[図 10] (A) , (B)は、他の従来の回路基板の製造方法を示す断面図である。  10] (A) and (B) are cross-sectional views illustrating another conventional circuit board manufacturing method.
符号の説明 Explanation of symbols
1…基板  1 ... substrate
la…スノレーホ一ノレ  la ... Snorejo
2〜Cu合金薄膜  2-Cu alloy thin film
3· · 'Cu鍍金膜又は Cu蒸着膜  3 'Cu plating film or Cu evaporation film
4· ··レジストパターン  4 Resist pattern
5a-一 5d…配線パタ  5a-one 5d… wiring pattern
6· · •Ni鍍金膜  6Ni-plated film
7· · •Au鍍金膜  7 Au plating film
8· · -半導体チップ  8 · · -Semiconductor chip
9· · •Auノンプ  9 Au Aump
10· · 'ポリイミド膜  10 · · 'Polyimide film
10a- · ·スノレーホ一ノレ  10a-
11· · •Cu合金薄膜  11CuCu thin film
12· · 'Cu鍍金膜又は Cu蒸着膜  12'Cu plating film or Cu evaporation film
101· ··基板 101
102…下地膜 103· "Cu鍍金膜 102 ... underlying film 103 · "Cu plating film
104a— 104d, 106a— 106d…配線パタ 105· ··Οι膜  104a— 104d, 106a— 106d… Wiring pattern 105

Claims

請求の範囲 The scope of the claims
[1] 基板と、  [1] a substrate,
前記基板上に形成された薄膜と、  A thin film formed on the substrate,
を具備する回路基板であって、  A circuit board comprising:
前記薄膜は、 Cuを主成分とし、 Ti、 Mo、 Ni、 A1及び Ag力 なる群力 選ばれた少 なくとも 1種類の元素を合計で 0.5— 5.(^％含有してなる合金カゝらなることを特徴と する回路基板。  The thin film is made of an alloy containing Cu as a main component, and a group force of Ti, Mo, Ni, A1, and Ag forces. A circuit board characterized by comprising:
[2] 基板と、 [2] a substrate,
前記基板上に形成された薄膜と、  A thin film formed on the substrate,
を具備する回路基板であって、  A circuit board comprising:
前記薄膜は、 Ti、 Mo、 Ni、 A1及び Ag力 なる群力 選ばれた少なくとも 1種類の 元素を合計で 0.5— 5.(^％含有し、残部が Cuからなる合金力もなることを特徴とす る回路基板。  The thin film contains at least one element selected from the group consisting of Ti, Mo, Ni, A1, and Ag forces in an amount of 0.5-5. (^% In total, and has an alloying force consisting of Cu in the balance. Circuit board.
[3] 前記薄膜の膜厚が 5nm以上 1 μ m以下であることを特徴とする請求項 1又は 2に記 載の回路基板。  3. The circuit board according to claim 1, wherein the thin film has a thickness of 5 nm or more and 1 μm or less.
[4] 前記薄膜上に形成された膜厚が 300nm以上 30 μ m以下の Cu膜をさらに具備する ことを特徴とする請求項 1乃至 3のいずれか一項に記載の回路基板。  [4] The circuit board according to any one of claims 1 to 3, further comprising a Cu film formed on the thin film and having a thickness of 300 nm or more and 30 μm or less.
[5] 基板と、  [5] a substrate,
前記基板上にスパッタリングにより形成された薄膜と、  A thin film formed by sputtering on the substrate,
前記薄膜上に真空蒸着法又は電子ビーム蒸着法により形成された Cu膜と、 を具備する回路基板であって、  A Cu film formed on the thin film by a vacuum evaporation method or an electron beam evaporation method, a circuit board comprising:
前記薄膜は、 Cuを主成分とし、 Ti、 Mo、 Ni、 A1及び Ag力 なる群力 選ばれた少 なくとも 1種類の元素を合計で 0.5— 5.(^％含有してなる合金カゝらなり、膜厚が 5nm 以上 1 m以下であり、  The thin film is made of an alloy containing Cu as a main component, and a group force of Ti, Mo, Ni, A1, and Ag forces. And the film thickness is 5 nm or more and 1 m or less,
前記薄膜及び前記 Cu膜は、表皮効果に伴う伝播損失を低減又は削減するもので あることを特徴とする回路基板。  The circuit board, wherein the thin film and the Cu film reduce or reduce propagation loss due to a skin effect.
[6] 基板と、 [6] a substrate,
前記基板上に形成された配線パターンと、 を具備する回路基板であって、 A wiring pattern formed on the substrate, A circuit board comprising:
前記配線パターンは、薄膜と、該薄膜上に形成された Cu膜とを有し、  The wiring pattern has a thin film and a Cu film formed on the thin film,
前記薄膜は、 Cuを主成分とし、 Ti、 Mo、 Ni、 A1及び Ag力 なる群力 選ばれた少 なくとも 1種類の元素を合計で 0.5— 5.(^％含有してなる合金カゝらなり、膜厚が 5nm 以上 1 μ m以下であることを特徴とする回路基板。  The thin film is made of an alloy containing Cu as a main component, and a group force of Ti, Mo, Ni, A1, and Ag forces. A circuit board comprising a film thickness of 5 nm or more and 1 μm or less.
[7] 基板と、 [7] a substrate,
前記基板上に形成された第 1の配線パターンと、  A first wiring pattern formed on the substrate,
前記第 1の配線パターン及び前記基板の上に形成された絶縁膜と、  An insulating film formed on the first wiring pattern and the substrate,
前記絶縁膜上に形成された第 2の配線パターンと、  A second wiring pattern formed on the insulating film,
を具備する回路基板であって、  A circuit board comprising:
前記第 1の配線パターンは、第 1の薄膜と、該第 1の薄膜上に形成された第 1の Cu 膜とを有し、  The first wiring pattern has a first thin film, and a first Cu film formed on the first thin film,
前記第 2の配線パターンは、第 2の薄膜と、該第 2の薄膜上に形成された第 2の Cu 膜とを有し、  The second wiring pattern has a second thin film and a second Cu film formed on the second thin film,
前記第 1の薄膜は、 Cuを主成分とし、 Ti、 Mo、 Ni、 A1及び Ag力 なる群力 選ば れた少なくとも 1種類の元素を合計で 0.5— 5.0wt%含有してなる合金カゝらなり、膜厚 力 S5nm以上 1 μ m以下であり、  The first thin film is made of an alloy containing Cu as a main component and a group force of Ti, Mo, Ni, A1, and Ag forces. The film thickness is S5 nm or more and 1 μm or less,
前記第 2の薄膜は、 Cuを主成分とし、 Ti、 Mo、 Ni、 A1及び Ag力 なる群力 選ば れた少なくとも 1種類の元素を合計で 0.5— 5.0wt%含有してなる合金カゝらなり、膜厚 力 nm以上 1 μ m以下であることを特徴とする回路基板。  The second thin film is an alloy powder containing Cu as a main component and a group force of Ti, Mo, Ni, A1, and Ag forces. A circuit board having a film thickness of not less than nm and not more than 1 μm.
[8] 基板と、 [8] a substrate,
前記基板の表面上に形成された第 1の薄膜と、  A first thin film formed on the surface of the substrate,
前記基板の裏面上に形成された第 2の薄膜と、  A second thin film formed on the back surface of the substrate,
を具備する回路基板であって、  A circuit board comprising:
前記第 1の薄膜は、 Cuを主成分とし、 Ti、 Mo、 Ni、 A1及び Ag力 なる群力 選ば れた少なくとも 1種類の元素を合計で 0.5— 5.0wt%含有してなる合金カゝらなり、膜厚 力 S5nm以上 1 μ m以下であり、  The first thin film is made of an alloy containing Cu as a main component and a group force of Ti, Mo, Ni, A1, and Ag forces. The film thickness is S5 nm or more and 1 μm or less,
前記第 2の薄膜は、 Cuを主成分とし、 Ti、 Mo、 Ni、 A1及び Ag力 なる群力 選ば れた少なくとも 1種類の元素を合計で 0.5— 5.0wt%含有してなる合金カゝらなり、膜厚 力 nm以上 1 μ m以下であることを特徴とする回路基板。 The second thin film contains Cu as a main component and has a group force of Ti, Mo, Ni, A1, and Ag force. A circuit board, comprising an alloy containing at least one element selected from the group consisting of 0.5 to 5.0 wt% in total and having a film thickness of not less than nm and not more than 1 μm.
[9] 前記薄膜は、前記基板と前記 Cu膜との密着性を助長するための下地であることを特 徴とする請求項 1乃至 6のいずれか一項に記載の回路基板。 9. The circuit board according to claim 1, wherein the thin film is a base for promoting adhesion between the substrate and the Cu film.
[10] 前記基板にはスルーホールが設けられていることを特徴とする請求項 1乃至 9のいず れか一項に記載の回路基板。 [10] The circuit board according to any one of claims 1 to 9, wherein the board is provided with a through hole.
[11] 前記基板は高分子材料、榭脂材料又はセラミック材料カゝらなることを特徴とする請求 項 1乃至 10のいずれか一項に記載の回路基板。 [11] The circuit board according to any one of claims 1 to 10, wherein the substrate is made of a polymer material, a resin material, or a ceramic material.
[12] 前記高分子材料がポリイミド、液晶ポリマー、テフロン (登録商標)及びエポキシ榭脂 力 なる群力 選ばれた一つであることを特徴とする請求項 11に記載の回路基板。 12. The circuit board according to claim 11, wherein the polymer material is one selected from the group consisting of polyimide, liquid crystal polymer, Teflon (registered trademark), and epoxy resin.
[13] 基板上にスパッタリングにより薄膜を形成する工程を具備する回路基板の製造方法 であって、 [13] A method for manufacturing a circuit board, comprising a step of forming a thin film on a substrate by sputtering,
前記薄膜は、 Cuを主成分とし、 Ti、 Mo、 Ni、 A1及び Ag力 なる群力 選ばれた少 なくとも 1種類の元素を合計で 0.5— 5.(^％含有してなる合金カゝらなることを特徴と する回路基板の製造方法。  The thin film is made of an alloy containing Cu as a main component, and a group force of Ti, Mo, Ni, A1, and Ag forces. A method for manufacturing a circuit board, comprising:
[14] 基板上にスパッタリングにより薄膜を形成する工程を具備する回路基板の製造方法 であって、 [14] A method for manufacturing a circuit board, comprising a step of forming a thin film on a substrate by sputtering,
前記薄膜は、 Ti、 Mo、 Ni、 A1及び Ag力 なる群力 選ばれた少なくとも 1種類の 元素を合計で 0.5— 5.(^％含有し、残部が Cuからなる合金力もなることを特徴とす る回路基板の製造方法。  The thin film contains at least one element selected from the group consisting of Ti, Mo, Ni, A1, and Ag forces in an amount of 0.5-5. (^% In total, and has an alloying force consisting of Cu in the balance. Circuit board manufacturing method.
[15] 前記薄膜の膜厚が 5nm以上 1 μ m以下であることを特徴とする請求項 13又は 14に 記載の回路基板の製造方法。  15. The method according to claim 13, wherein the thin film has a thickness of 5 nm or more and 1 μm or less.
[16] 前記薄膜を形成する工程の後に、前記薄膜上に電界鍍金法又は無電界鍍金法によ り膜厚が 300nm以上 30 m以下の Cu膜を形成する工程をさらに具備することを特 徴とする請求項 13乃至 15のいずれか一項に記載の回路基板の製造方法。  [16] The method further comprises, after the step of forming the thin film, a step of forming a Cu film having a thickness of 300 nm or more and 30 m or less on the thin film by electroplating or electroless plating. The method for manufacturing a circuit board according to any one of claims 13 to 15, wherein
[17] 前記薄膜を形成する工程の後に、前記薄膜上に真空蒸着法又は電子ビーム蒸着法 により膜厚が 300nm以上 30 μ m以下の Cu膜を形成する工程をさらに具備すること を特徴とする請求項 13乃至 15のいずれか一項に記載の回路基板の製造方法。 [17] After the step of forming the thin film, the method further comprises a step of forming a Cu film having a thickness of 300 nm to 30 μm on the thin film by a vacuum evaporation method or an electron beam evaporation method. A method for manufacturing the circuit board according to claim 13.
[18] 基板上にスパッタリングにより薄膜を形成する工程と、 [18] a step of forming a thin film on the substrate by sputtering,
前記薄膜上に電界鍍金法又は無電界鍍金法により膜厚が 300nm以上 30 μ m以 下の Cu膜を形成する工程と、  Forming a Cu film having a thickness of 300 nm or more and 30 μm or less on the thin film by electroplating or electroless plating,
前記 Cu膜及び前記薄膜をエッチング加工することにより、前記基板上に前記 Cu膜 及び前記薄膜からなる配線パターンを形成する工程と、  Forming a wiring pattern composed of the Cu film and the thin film on the substrate by etching the Cu film and the thin film;
を具備する回路基板の製造方法であって、  A method for manufacturing a circuit board comprising:
前記薄膜は、 Cuを主成分とし、 Ti、 Mo、 Ni、 A1及び Ag力 なる群力 選ばれた少 なくとも 1種類の元素を合計で 0.5— 5.(^％含有してなる合金カゝらなり、膜厚が 5nm 以上 1 μ m以下であることを特徴とする回路基板の製造方法。  The thin film is made of an alloy containing Cu as a main component, and a group force of Ti, Mo, Ni, A1, and Ag forces. And a film thickness of 5 nm or more and 1 μm or less.
[19] 基板上にスパッタリングにより薄膜を形成する工程と、 [19] forming a thin film on the substrate by sputtering,
前記薄膜上に真空蒸着法又は電子ビーム蒸着法により膜厚が 300nm以上 30 m以下の Cu膜を形成する工程と、  Forming a Cu film having a thickness of 300 nm or more and 30 m or less on the thin film by vacuum evaporation or electron beam evaporation;
前記 Cu膜及び前記薄膜をエッチング加工することにより、前記基板上に前記 Cu膜 及び前記薄膜からなる配線パターンを形成する工程と、  Forming a wiring pattern composed of the Cu film and the thin film on the substrate by etching the Cu film and the thin film;
を具備する回路基板の製造方法であって、  A method for manufacturing a circuit board comprising:
前記薄膜は、 Cuを主成分とし、 Ti、 Mo、 Ni、 A1及び Ag力 なる群力 選ばれた少 なくとも 1種類の元素を合計で 0.5— 5.(^％含有してなる合金カゝらなり、膜厚が 5nm 以上 1 μ m以下であることを特徴とする回路基板の製造方法。  The thin film is made of an alloy containing Cu as a main component, and a group force of Ti, Mo, Ni, A1, and Ag forces. And a film thickness of 5 nm or more and 1 μm or less.
[20] 基板上にスパッタリングにより第 1の薄膜を形成する工程と、 [20] forming a first thin film on the substrate by sputtering;
前記第 1の薄膜上に電界鍍金法又は無電界鍍金法により膜厚が 300nm以上 30 μ m以下の第 1の Cu膜を形成する工程と、  Forming a first Cu film having a thickness of 300 nm or more and 30 μm or less on the first thin film by electroplating or electroless plating,
前記第 1の Cu膜及び前記第 1の薄膜をエッチング加工することにより、前記基板上 に前記第 1の Cu膜及び前記第 1の薄膜からなる第 1の配線パターンを形成する工程 と、  Forming a first wiring pattern composed of the first Cu film and the first thin film on the substrate by etching the first Cu film and the first thin film;
前記第 1の配線パターン及び前記基板の上に絶縁膜を形成する工程と、 前記絶縁膜上にスパッタリングにより第 2の薄膜を形成する工程と、  Forming an insulating film on the first wiring pattern and the substrate; forming a second thin film on the insulating film by sputtering;
前記第 2の薄膜上に電界鍍金法又は無電界鍍金法により膜厚が 300nm以上 30 μ m以下の第 2の Cu膜を形成する工程と、 前記第 2の Cu膜及び前記第 2の薄膜をエッチング加工することにより、前記絶縁膜 上に前記第 2の Cu膜及び前記第 2の薄膜からなる第 2の配線パターンを形成するェ 程と、 Forming a second Cu film having a thickness of 300 nm or more and 30 μm or less on the second thin film by electroplating or electroless plating, Forming a second wiring pattern composed of the second Cu film and the second thin film on the insulating film by etching the second Cu film and the second thin film;
を具備する回路基板の製造方法であって、  A method for manufacturing a circuit board comprising:
前記第 1の薄膜は、 Cuを主成分とし、 Ti、 Mo、 Ni、 A1及び Ag力 なる群力 選ば れた少なくとも 1種類の元素を合計で 0.5— 5.0wt%含有してなる合金カゝらなり、膜厚 が 5nm以上 1 μ m以下であり、  The first thin film is made of an alloy containing Cu as a main component and a group force of Ti, Mo, Ni, A1, and Ag forces. And the film thickness is 5 nm or more and 1 μm or less,
前記第 2の薄膜は、 Cuを主成分とし、 Ti、 Mo、 Ni、 A1及び Ag力 なる群力 選ば れた少なくとも 1種類の元素を合計で 0.5— 5.0wt%含有してなる合金カゝらなり、膜厚 が 5nm以上 1 μ m以下であることを特徴とする回路基板の製造方法。  The second thin film is an alloy powder containing Cu as a main component and a group force of Ti, Mo, Ni, A1, and Ag forces. And a film thickness of 5 nm or more and 1 μm or less.
基板上にスパッタリングにより第 1の薄膜を形成する工程と、 Forming a first thin film on the substrate by sputtering,
前記第 1の薄膜上に真空蒸着法又は電子ビーム蒸着法により膜厚が 300nm以上 30 μ m以下の第 1の Cu膜を形成する工程と、  Forming a first Cu film having a thickness of 300 nm or more and 30 μm or less on the first thin film by a vacuum evaporation method or an electron beam evaporation method;
前記第 1の Cu膜及び前記第 1の薄膜をエッチング加工することにより、前記基板上 に前記第 1の Cu膜及び前記第 1の薄膜からなる第 1の配線パターンを形成する工程 と、 Forming a first wiring pattern composed of the first Cu film and the first thin film on the substrate by etching the first Cu film and the first thin film;
前記第 1の配線パターン及び前記基板の上に絶縁膜を形成する工程と、 前記絶縁膜上にスパッタリングにより第 2の薄膜を形成する工程と、  Forming an insulating film on the first wiring pattern and the substrate; forming a second thin film on the insulating film by sputtering;
前記第 2の薄膜上に真空蒸着法又は電子ビーム蒸着法により膜厚が 300nm以上 The film thickness is 300 nm or more on the second thin film by a vacuum evaporation method or an electron beam evaporation method.
30 μ m以下の第 2の Cu膜を形成する工程と、 Forming a second Cu film of 30 μm or less;
前記第 2の Cu膜及び前記第 2の薄膜をエッチング加工することにより、前記絶縁膜 上に前記第 2の Cu膜及び前記第 2の薄膜からなる第 2の配線パターンを形成するェ 程と、  Forming a second wiring pattern composed of the second Cu film and the second thin film on the insulating film by etching the second Cu film and the second thin film;
を具備する回路基板の製造方法であって、  A method for manufacturing a circuit board comprising:
前記第 1の薄膜は、 Cuを主成分とし、 Ti、 Mo、 Ni、 A1及び Ag力 なる群力 選ば れた少なくとも 1種類の元素を合計で 0.5— 5.0wt%含有してなる合金カゝらなり、膜厚 が 5nm以上 1 μ m以下であり、  The first thin film is made of an alloy containing Cu as a main component and a group force of Ti, Mo, Ni, A1, and Ag forces. And the film thickness is 5 nm or more and 1 μm or less,
前記第 2の薄膜は、 Cuを主成分とし、 Ti、 Mo、 Ni、 A1及び Ag力 なる群力 選ば れた少なくとも 1種類の元素を合計で 0.5— 5.0wt%含有してなる合金カゝらなり、膜厚 が 5nm以上 1 μ m以下であることを特徴とする回路基板の製造方法。 The second thin film contains Cu as a main component and has a group force of Ti, Mo, Ni, A1, and Ag force. A method of manufacturing a circuit board, comprising: an alloy containing at least one element selected from the group consisting of 0.5 to 5.0 wt% in total and having a film thickness of 5 nm or more and 1 μm or less.
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