WO2005041295A3 - Halbleitermodul mit gehäusedurchkontakten - Google Patents

Halbleitermodul mit gehäusedurchkontakten Download PDF

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Publication number
WO2005041295A3
WO2005041295A3 PCT/DE2004/002201 DE2004002201W WO2005041295A3 WO 2005041295 A3 WO2005041295 A3 WO 2005041295A3 DE 2004002201 W DE2004002201 W DE 2004002201W WO 2005041295 A3 WO2005041295 A3 WO 2005041295A3
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WO
WIPO (PCT)
Prior art keywords
housing
semiconductor module
contacts
contacts extending
module provided
Prior art date
Application number
PCT/DE2004/002201
Other languages
English (en)
French (fr)
Other versions
WO2005041295A2 (de
Inventor
Jochen Dangelmaier
Original Assignee
Infineon Technologies Ag
Jochen Dangelmaier
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag, Jochen Dangelmaier filed Critical Infineon Technologies Ag
Publication of WO2005041295A2 publication Critical patent/WO2005041295A2/de
Publication of WO2005041295A3 publication Critical patent/WO2005041295A3/de
Priority to US11/405,015 priority Critical patent/US7505276B2/en

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    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/055—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads having a passage through the base
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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

Die Erfindung betrifft ein Halbleitermodul (10) mit einem Gehäuse (52) einer Kunststoffmasse (43) und Gehäusedurchkontakten (44) von einer Gehäuseunterseite (45) zu einer Gehäuseoberseite (46). Dazu ist das Gehäuse (52) aus mindestens zwei Kunststoffschichten (9) und (19) aufgebaut, wobei die erste Kunststoffschicht (9) Außenkontakte (48) und Schichtdurchgangskontakte (50) aufweist. Eine Umverdrahtungsstruktur (4) trägt die zweite Kunststoffschicht (19), die Halbleiterchips (3) und (5) in einer Kunststoffmasse (43) umgibt, wobei in den Randbereichen des Halbleitermoduls (10) die Gehäusedurchkontakte (44) angeordnet sind.
PCT/DE2004/002201 2003-10-15 2004-10-01 Halbleitermodul mit gehäusedurchkontakten WO2005041295A2 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US11/405,015 US7505276B2 (en) 2003-10-15 2006-04-17 Semiconductor module provided with contacts extending through the package

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10348620A DE10348620A1 (de) 2003-10-15 2003-10-15 Halbleitermodul mit Gehäusedurchkontakten
DE10348620.8 2003-10-15

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US11/405,015 Continuation US7505276B2 (en) 2003-10-15 2006-04-17 Semiconductor module provided with contacts extending through the package

Publications (2)

Publication Number Publication Date
WO2005041295A2 WO2005041295A2 (de) 2005-05-06
WO2005041295A3 true WO2005041295A3 (de) 2005-06-16

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Family Applications (1)

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PCT/DE2004/002201 WO2005041295A2 (de) 2003-10-15 2004-10-01 Halbleitermodul mit gehäusedurchkontakten

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US (1) US7505276B2 (de)
DE (1) DE10348620A1 (de)
WO (1) WO2005041295A2 (de)

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4745697B2 (ja) * 2005-03-29 2011-08-10 富士通セミコンダクター株式会社 複数の配線層を有する半導体回路の端子層設定方法、端子層設定プログラム、配線端子延長処理プログラム、および、その端子層を設定に用いられる端子延長用コンポーネント
US7919844B2 (en) * 2005-05-26 2011-04-05 Aprolase Development Co., Llc Tier structure with tier frame having a feedthrough structure
US7768113B2 (en) 2005-05-26 2010-08-03 Volkan Ozguz Stackable tier structure comprising prefabricated high density feedthrough
JP4498991B2 (ja) 2005-07-15 2010-07-07 新光電気工業株式会社 半導体装置及び電子装置
JP4541253B2 (ja) * 2005-08-23 2010-09-08 新光電気工業株式会社 半導体パッケージ及びその製造方法
US8072059B2 (en) * 2006-04-19 2011-12-06 Stats Chippac, Ltd. Semiconductor device and method of forming UBM fixed relative to interconnect structure for alignment of semiconductor die
US8159828B2 (en) * 2007-02-23 2012-04-17 Alpha & Omega Semiconductor, Inc. Low profile flip chip power module and method of making
FR2917236B1 (fr) 2007-06-07 2009-10-23 Commissariat Energie Atomique Procede de realisation de via dans un substrat reconstitue.
US7933128B2 (en) * 2007-10-10 2011-04-26 Epson Toyocom Corporation Electronic device, electronic module, and methods for manufacturing the same
FR2932004B1 (fr) 2008-06-03 2011-08-05 Commissariat Energie Atomique Dispositif electronique empile et procede de realisation d'un tel dispositif electronique
US7964448B2 (en) 2008-09-18 2011-06-21 Infineon Technologies Ag Electronic device and method of manufacturing same
US7666709B1 (en) 2008-12-10 2010-02-23 Stats Chippac, Ltd. Semiconductor device and method of placing semiconductor die on a temporary carrier using fiducial patterns
US7935570B2 (en) * 2008-12-10 2011-05-03 Stats Chippac, Ltd. Semiconductor device and method of embedding integrated passive devices into the package electrically interconnected using conductive pillars
JP2010165940A (ja) * 2009-01-16 2010-07-29 Shinko Electric Ind Co Ltd 半導体素子の樹脂封止方法
US8097489B2 (en) 2009-03-23 2012-01-17 Stats Chippac, Ltd. Semiconductor device and method of mounting pre-fabricated shielding frame over semiconductor die
JP2011159081A (ja) * 2010-01-29 2011-08-18 Toshiba Corp 電子機器
US8581394B2 (en) * 2010-06-21 2013-11-12 Samsung Electro-Mechanics Co., Ltd Semiconductor package module and electric circuit assembly with the same
JP5645592B2 (ja) * 2010-10-21 2014-12-24 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
DE102011113255B4 (de) * 2011-09-13 2021-03-04 Infineon Technologies Ag Chipmodule und Verfahren zur Herstellung eines Chipmoduls
TWI474444B (zh) * 2011-12-28 2015-02-21 Princo Corp 超薄多層基板之封裝方法
TWI433621B (zh) * 2011-12-28 2014-04-01 Princo Corp 超薄多層基板之封裝方法
TWI440412B (zh) * 2011-12-28 2014-06-01 Princo Corp 超薄多層基板之封裝方法
US8901730B2 (en) 2012-05-03 2014-12-02 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for package on package devices
TWI555166B (zh) * 2013-06-18 2016-10-21 矽品精密工業股份有限公司 層疊式封裝件及其製法
US10319674B2 (en) * 2014-10-29 2019-06-11 Infineon Technologies Americas Corp. Packaged assembly for high density power applications
US9773764B2 (en) * 2015-12-22 2017-09-26 Intel Corporation Solid state device miniaturization
DE102016124270A1 (de) * 2016-12-13 2018-06-14 Infineon Technologies Ag Halbleiter-package und verfahren zum fertigen eines halbleiter-package
US10784220B2 (en) 2017-03-30 2020-09-22 Taiwan Semiconductor Manufacturing Co., Ltd. Plurality of semiconductor devices encapsulated by a molding material attached to a redistribution layer
DE102017212739A1 (de) * 2017-07-25 2019-01-31 Siemens Aktiengesellschaft Halbleiterbauteil sowie Verfahren zu dessen Herstellung
CN107579058A (zh) * 2017-09-02 2018-01-12 中国电子科技集团公司第五十八研究所 一种多类型芯片叠层封装结构及其制作方法
CN112582350A (zh) * 2019-09-29 2021-03-30 江苏长电科技股份有限公司 腔体式封装结构及封装方法

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5128831A (en) * 1991-10-31 1992-07-07 Micron Technology, Inc. High-density electronic package comprising stacked sub-modules which are electrically interconnected by solder-filled vias
US5838061A (en) * 1996-03-11 1998-11-17 Lg Semicon Co., Ltd. Semiconductor package including a semiconductor chip adhesively bonded thereto
US6294830B1 (en) * 1996-04-18 2001-09-25 Tessera, Inc. Microelectronic assembly with conductive terminals having an exposed surface through a dielectric layer
EP1137066A2 (de) * 2000-03-24 2001-09-26 Shinko Electric Industries Co. Ltd. Halbleiter und seine Herstellung
US20010048152A1 (en) * 1998-06-30 2001-12-06 Moden Walter L. Stackable ceramic fbga for high thermal applications
US6384472B1 (en) * 2000-03-24 2002-05-07 Siliconware Precision Industries Co., Ltd Leadless image sensor package structure and method for making the same
US20020066952A1 (en) * 2000-12-04 2002-06-06 Fujitsu Limited Semiconductor device having an interconnecting post formed on an interposer within a sealing resin

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2579937B2 (ja) * 1987-04-15 1997-02-12 株式会社東芝 電子回路装置およびその製造方法
US5422435A (en) 1992-05-22 1995-06-06 National Semiconductor Corporation Stacked multi-chip modules and method of manufacturing
US5454160A (en) * 1993-12-03 1995-10-03 Ncr Corporation Apparatus and method for stacking integrated circuit devices
TW373308B (en) * 1995-02-24 1999-11-01 Agere Systems Inc Thin packaging of multi-chip modules with enhanced thermal/power management
EP0774888B1 (de) * 1995-11-16 2003-03-19 Matsushita Electric Industrial Co., Ltd Gedruckte Leiterplatte und ihre Anordnung
US6117705A (en) * 1997-04-18 2000-09-12 Amkor Technology, Inc. Method of making integrated circuit package having adhesive bead supporting planar lid above planar substrate
DE19744297A1 (de) * 1997-10-07 1999-04-15 Fraunhofer Ges Forschung Gehäustes Bauelement und Verfahren zu dessen Herstellung
JP3109477B2 (ja) * 1998-05-26 2000-11-13 日本電気株式会社 マルチチップモジュール
EP1154474A4 (de) 1999-08-23 2008-07-16 Rohm Co Ltd Halbleiter-bauteil und verfahren zur herstellung hierfür
US6384473B1 (en) * 2000-05-16 2002-05-07 Sandia Corporation Microelectronic device package with an integral window
US6564454B1 (en) * 2000-12-28 2003-05-20 Amkor Technology, Inc. Method of making and stacking a semiconductor package
US6744135B2 (en) * 2001-05-22 2004-06-01 Hitachi, Ltd. Electronic apparatus
US6936917B2 (en) * 2001-09-26 2005-08-30 Molex Incorporated Power delivery connector for integrated circuits utilizing integrated capacitors
KR100430001B1 (ko) * 2001-12-18 2004-05-03 엘지전자 주식회사 다층기판의 제조방법, 그 다층기판의 패드 형성방법 및 그다층기판을 이용한 반도체 패키지의 제조방법
US6906403B2 (en) * 2002-06-04 2005-06-14 Micron Technology, Inc. Sealed electronic device packages with transparent coverings
SG137651A1 (en) * 2003-03-14 2007-12-28 Micron Technology Inc Microelectronic devices and methods for packaging microelectronic devices

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5128831A (en) * 1991-10-31 1992-07-07 Micron Technology, Inc. High-density electronic package comprising stacked sub-modules which are electrically interconnected by solder-filled vias
US5838061A (en) * 1996-03-11 1998-11-17 Lg Semicon Co., Ltd. Semiconductor package including a semiconductor chip adhesively bonded thereto
US6294830B1 (en) * 1996-04-18 2001-09-25 Tessera, Inc. Microelectronic assembly with conductive terminals having an exposed surface through a dielectric layer
US20010048152A1 (en) * 1998-06-30 2001-12-06 Moden Walter L. Stackable ceramic fbga for high thermal applications
EP1137066A2 (de) * 2000-03-24 2001-09-26 Shinko Electric Industries Co. Ltd. Halbleiter und seine Herstellung
US6384472B1 (en) * 2000-03-24 2002-05-07 Siliconware Precision Industries Co., Ltd Leadless image sensor package structure and method for making the same
US20020066952A1 (en) * 2000-12-04 2002-06-06 Fujitsu Limited Semiconductor device having an interconnecting post formed on an interposer within a sealing resin

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