Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
  • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
  • H10F39/10—Integrated devices
  • H10F39/107—Integrated devices having multiple elements covered by H10F30/00 in a repetitive configuration, e.g. radiation detectors comprising photodiode arrays
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
  • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
  • H10F39/10—Integrated devices
  • H10F39/12—Image sensors
  • H10F39/199—Back-illuminated image sensors

Definitions

• the present invention relates to semiconductor photodiodes, and in particular, to the structures of high performance, back-illuminated photodiode arrays and the methods of fabricating such structures .
• Figure la is a simplified cross section of an exemplary prior art front illuminated photodiode array
• Figure lb is a simplified cross section of an exemplary prior art back illuminated photodiode array.
• the substrate 1 may be either n-type or p-type material, with opposite conductivity type diffused regions 2 therein. This creates a p-on-n or n-on-p structure, respectively.
• the anode metal pads 3 for the p- on-n structure (the cathode contacts for the n-on-p structure) are always on the device front surface.
• the opposite polarity electrode is usually deposited (plated, sputtered, or evaporated) on the chip back side in the case of the front illuminated structure (see metal layer 4, Figure la) , or is made on the device front surface (see metal pads 4, Figure lb) using metallized through vias 6,7 in the case of the back illuminated structure.
• the blanket-type implantation 5 of the back surface of the die of the same conductivity type as the substrate improves both the charge collection efficiency and DC/AC electrical performance of the devices .
• these structures are usually fabricated using relatively thick wafers (>50 ⁇ ) and the resistivity of the material has to be high enough (>1000 Ohm-cm) to deplete the entire volume at zero bias, which is required for many applications; 2) Second, the application of a high resistivity material usually diminishes the photodiode performance with respect to the leakage current and shunt resistance;
• Figures la and lb are schematic cross sections of typical, conventional prior art structures for the front illuminated photodiode arrays and back illuminated photodiode arrays, respectively.
• Figure 2 is a schematic cross section of an ultra thin, back illuminating photodiode array in accordance with the present invention.
• Figure 3 is a schematic cross section of a sample structure of the present invention having- a 30 ⁇ m thick, n- type Silicon wafer.
• Figure 4a through 4c illustrate sequential steps of a method for fabricating electrodes of a thin wafer photodiode array structure in accordance with the present invention.
• Figure 5 illustrates an exemplary layout of cathode and anode pads across the front surface of the wafer.
• Figure 6 is a cross section taken through one of the metal contacts of Figure 5.
• Another object is to provide a method of fabricating Si devices on ultra thin wafers, which method can be suitable for fabrication of flip-chip, multi-element, 2-dimensional arrays of silicon photodiodes .
• Figure 2 is a simplified cross-sectional view of a semiconductor ultra-thin chip photodiode array in accordance with a preferred embodiment of the present invention.
• the structure is built using either n-type or p-type bulk silicon 1.
• the anode in the case of p-on-n structure or the cathode in the case of n-on-p structure will be referred to as "the first electrode”
• the cathode in the case of p-on-n structure and the anode in the case of n-on-p structure will be referred to as "the second electrode.
• the material resistivity, thickness of the wafer/die, dopants concentrations and doses, and diffusion conditions are preferably chosen to satisfy the following requirements: a) The active area (the first electrode) diffusion 2 extends sufficiently close to the back surface of the finished die that the rest of the volume between the diffusion edge and the blanket implant in the die back surface and part of the blanket implant, the ' space indicated as "d” in the Figure 2, becomes completely depleted at a zero volt bias; b) The uniform, "blanket” type implantation 5 of the back side of the wafer with the implant of the same polarity as the one of the majority carriers of the wafer bulk 1 provides excellent majority carrier conductivity across the wafer back side; and ensures a vertical electric field for carrier collection beneath the first electrode to minimize cross talk; c) The second electrode, diffusion 8, is applied from the front surface of the wafer using the implantation and drive protocols that allow for the diffusion to reach the wafer back side, overlapping thereby with the blanket implantation 5 and providing perfect electrical contacts between the second electrode network across the entire wafer
• FIG. 3 An example of a real structure built using a n-type bulk Si with the resistivity of approximately 400 ohm-cm is shown schematically in Figure 3.
• the width of a depletion region is approximately 9 ⁇ m and extends up to and into (but not through) the blanket implantation 5 in the wafer back side.
• the blanket diffusion 5 is only approximately 0.6 ⁇ m thick, so the depletion region extends approximately to, but not quite all the way to, the wafer back side.
• the built-in potential creates an electric field across the depletion region and facilitates rapid collection of non-equilibrium carriers created by light near the back surface of the die.
• the non-equilibrium carriers have no or very little possibility of being collected by the electrodes from adjacent cells because:
• the electric field near the die back surface, where the carriers photo-generation predominantly occurs is directed perpendicular to the die surface; therefore, the carriers move (drift) primarily toward the junction of the same cell, having almost no possibility of being trapped by an adjacent cell;
• the second electrode diffusion region 8 which is n+ diffusion in the case of Figure 3, spans the entire thickness of the die and acts as an effective carrier isolator from adjacent cells.
• the first electrode diffusion 2 may overlap with the second electrode diffusion 8 close to the front surface of the die as shown in Figure 3. This overlapping may significantly decrease the breakdown voltage, which is not important for a zero bias device.
• first electrode 2 and second electrode 8 are shown in Figure 3.
• the depth of the first electrode diffusion 2 should be less than the finished substrate thickness (typically less than 50 ⁇ m, and more typically approximately 30 ⁇ m as shown in Figure 3 ) by an amount that approximately equals the depletion depth for the substrate material 1 at zero bias .
• the second electrode diffusion 8 should span the entire thickness of the substrate, or at least to a sufficient depth to provide a reliable low resistance contact with the blanket implantation 5 of the back side of the wafer. Note that the dopants 5 and 8 are of the same polarity.
• Such a structure may be fabricated starting with a thicker substrate (for example 300 ⁇ m) for structural stiffness and integrity during the processing, using three masking steps :
• the second electrode 8 implantation/diffusion is applied followed by a drive.
• the difference in the final diffusion depths for the first electrodes 2 and second electrodes 8 (approximately 9 ⁇ m) is formed.
• the second electrode 8 receives an additional enhancement followed by a drive to ensure superior electrical contacts and to activate dopants.
• the profiles of both the cathode and anode diffusions reach their final configurations (see the solid lines and hatched areas in Figure 4c) .
• the diffusion profiles prior to this third step of dopants implantation/diffusion/drive are shown schematically with the dashed lines in Figure 4c.
• the future back surface of the wafer after back side grinding and polishing is shown schematically with the dashed line 10.
• the array is then reduced in thickness by grinding the back side of the array, preferably to provide a substrate thickness of under approximately 50 ⁇ m, and more preferably to approximately 30 ⁇ m.
• the final thickness achieved is preferably selected in accordance with the resistivity of the substrate and the depth of the first electrode diffusion so that the diffusion is spaced away form the back side of the substrate an amount that approximately equals the depletion depth for the substrate material at zero bias.
• a blanket implant of the first conductivity type is made to the back side of the wafer, which implant improves both the charge collection efficiency and DC/AC electrical performance of the photodiode arrays . Activation of the implant does not significantly alter the first and second electrode diffusions.
• a diffusion for the back side could be used if desired.
• the blanket implant is quite thin compared to the depletion region, with the depletion region extending into, but not through, the blanket implant in the final array.
• the oxide layer 12 is evenly patterned and the metal pads 14 contacting the first electrode 2 and second electrode 8 are evenly spaced across the surface of the die 16 and made the same size to provide identical ball bumping conditions throughout the wafer (see Figures 5 and 6) .
• the oxide layer 12 and metal pads 14 are represented by the larger diameter circles in Figure 5, with the smaller diameter circles describing the contact openings.
• the present invention photodiode arrays exhibit very low cross talk because of the excellent isolation of each pixel. Also, because of the small depletion volume, the arrays exhibit low noise and low temperature sensitivity. When used in X-ray systems, they exhibit low radiation damage, and have thermal characteristics similar to scintillators to which they will are mounted.
• the technique of using a deep diffusion in conjunction with a thin substrate for making electrical contact to the back side of the substrate may, of course be used in other semiconductor devices . While the deep diffusion in the preferred embodiment is of the same conductivity type as the substrate, this is not a limitation of the invention, as the deep diffusion may be of the opposite conductivity type, if desired.

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• Solid State Image Pick-Up Elements (AREA)

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Cited By (17)

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• 2003
  • 2003-06-25 US US10/606,053 patent/US6762473B1/en not_active Expired - Fee Related
• 2004
  • 2004-06-08 US US10/863,558 patent/US7112465B2/en not_active Expired - Fee Related
  • 2004-06-22 EP EP04777237A patent/EP1636856B1/en not_active Expired - Lifetime
  • 2004-06-22 AT AT04777237T patent/ATE531082T1/de not_active IP Right Cessation
  • 2004-06-22 CN CNB2004800247278A patent/CN100533775C/zh not_active Expired - Fee Related
  • 2004-06-22 EP EP10075651A patent/EP2270873A3/en not_active Withdrawn
  • 2004-06-22 JP JP2006517765A patent/JP2007521657A/ja active Pending
  • 2004-06-22 WO PCT/US2004/020835 patent/WO2005001941A2/en not_active Ceased
• 2005
  • 2005-12-11 IL IL172495A patent/IL172495A0/en unknown

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