WO2004093190A3 - Multichipmodul mit mehreren halbleiterchips sowie leiterplatte mit mehreren komponenten - Google Patents

Multichipmodul mit mehreren halbleiterchips sowie leiterplatte mit mehreren komponenten Download PDF

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Publication number
WO2004093190A3
WO2004093190A3 PCT/DE2004/000750 DE2004000750W WO2004093190A3 WO 2004093190 A3 WO2004093190 A3 WO 2004093190A3 DE 2004000750 W DE2004000750 W DE 2004000750W WO 2004093190 A3 WO2004093190 A3 WO 2004093190A3
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WIPO (PCT)
Prior art keywords
semiconductor chip
contact surfaces
semiconductor chips
multichip module
components
Prior art date
Application number
PCT/DE2004/000750
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English (en)
French (fr)
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WO2004093190A2 (de
Inventor
Georg Meyer-Berg
Original Assignee
Infineon Technologies Ag
Georg Meyer-Berg
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Filing date
Publication date
Application filed by Infineon Technologies Ag, Georg Meyer-Berg filed Critical Infineon Technologies Ag
Priority to EP04726437A priority Critical patent/EP1614158A2/de
Publication of WO2004093190A2 publication Critical patent/WO2004093190A2/de
Publication of WO2004093190A3 publication Critical patent/WO2004093190A3/de
Priority to US11/246,563 priority patent/US7317251B2/en

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  • Power Engineering (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

Ein erfindungsgemäßes Multichipmodul umfasst wenigstens einen ersten Halbleiterchip (2) sowie wenigstens einen zweiten Halbleiterchip (3). Die Halbleiterchips (2, 3) sind koplanar auf oder in einem Trägermedium (51) angeordnet und weisen jeweils übereinstimmende Bauelemente und auf ihrer aktiven Oberseiten angeordnete Kontaktflächen (A1, A5) auf. Wenigstens ein zweiter Halbleiterchip (3) weist eine in bezug zu einem ersten Halbleiterchip (2) spiegelbildliche Anordnung von Kontaktflächen (A1, A5) auf. Wenigstens ein erster Halbleiterchip (2) und wenigstens ein zweiter Halbleiterchip (3) sind so neben- und/oder hintereinander angeordnet, dass diejenigen ihrer Ränder einander gegenüberliegen, die jeweils eine übereinstimmende Anordnung von Kontaktflächen (A1, A5) aufweisen. Verdrahtungen (55, 56) erstrecken sich zwischen jeweils gegenüberliegenden Kontaktflächen (A1, A5) sowie zwischen Kontaktflächen (A1) an den äußeren Rändern der Halbleiterchips (2, 3) und Außenkontakten (54).
PCT/DE2004/000750 2003-04-11 2004-04-08 Multichipmodul mit mehreren halbleiterchips sowie leiterplatte mit mehreren komponenten WO2004093190A2 (de)

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EP04726437A EP1614158A2 (de) 2003-04-11 2004-04-08 Multichipmodul mit mehreren halbleiterchips sowie leiterplatte mit mehreren komponenten
US11/246,563 US7317251B2 (en) 2003-04-11 2005-10-11 Multichip module including a plurality of semiconductor chips, and printed circuit board including a plurality of components

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DE10317018.9 2003-04-11
DE2003117018 DE10317018A1 (de) 2003-04-11 2003-04-11 Multichipmodul mit mehreren Halbleiterchips sowie Leiterplatte mit mehreren Komponenten

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