WO2004059576A1 - 画像処理装置 - Google Patents

画像処理装置 Download PDF

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Publication number
WO2004059576A1
WO2004059576A1 PCT/JP2003/015976 JP0315976W WO2004059576A1 WO 2004059576 A1 WO2004059576 A1 WO 2004059576A1 JP 0315976 W JP0315976 W JP 0315976W WO 2004059576 A1 WO2004059576 A1 WO 2004059576A1
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Prior art keywords
data
address
output
processing
unit
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English (en)
French (fr)
Japanese (ja)
Inventor
Tetsujiro Kondo
Hiroshi Sato
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Sony Corp
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Sony Corp
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Priority to US10/540,641 priority Critical patent/US7782959B2/en
Publication of WO2004059576A1 publication Critical patent/WO2004059576A1/ja
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H04N19/43—Hardware specially adapted for motion estimation or compensation

Definitions

  • the present invention relates to an image processing apparatus suitable for application to, for example, motion vector detection processing.
  • the present invention distributes process data including an instruction for executing each process for performing image processing to a plurality of serially-connected execution means for executing the process.
  • a route selecting means is provided on the input side for each set of a predetermined number of continuous executing means, and the route selecting means is associated with input process data.
  • the input process data is supplied to the output side of the immediately succeeding set, thereby reducing processing time and power consumption.
  • the present invention relates to an image processing apparatus configured to achieve the above.
  • the present invention performs image processing by moving process data including an instruction for executing each process for performing image processing, by moving a plurality of serially connected execution means for executing the process.
  • the execution means when the process related to the input process data is not executed by itself, immediately outputs the input process data as the output process data, thereby reducing the processing time. It relates to a processing device. Background art
  • a motion vector is detected for a target block of interest among blocks of a certain size, and further based on the motion vector.
  • a predicted image of the block of interest is obtained.
  • a difference between each pixel of the block of interest and a corresponding pixel of the predicted image is calculated, and the difference value is encoded, thereby achieving high-efficiency compression.
  • a motion vector detection algorithm for example, a block matching method is known.
  • a block having an f-th frame is set as a target block, and an f + 1-th frame is set as a reference frame referred to for detecting a motion vector ⁇ /.
  • the block matching method uses a predetermined motion centered on the position of the block of interest in the (f + 1) th frame.
  • the range is set as the search range to search for the motion vector.
  • a block having the same size as the block of interest is selected as a candidate block that is a candidate for a predicted image of the block of interest from the search range of the (f + 1) th frame, and difference information relating to the difference between the block of interest and the candidate block is selected. Is required.
  • the difference between each pixel of the block of interest and the corresponding pixel of the candidate block is obtained.
  • the absolute value of the difference (absolute difference value) is calculated. Further, the sum of the absolute differences is obtained, and the sum of the absolute differences as described above is obtained for all the candidate blocks that can be selected in the search range. Then, among the candidate blocks that can be selected in the search range, a candidate block that minimizes the sum of the absolute differences (hereinafter, appropriately referred to as a “minimum catching block”) is obtained.
  • the heading vector is determined as the motion vector of the block of interest.
  • search range a range larger than the block of interest and the candidate block is used. If the block of interest and the candidate block are 4 ⁇ 4 pixel blocks as described above, for example, 30 ⁇ 30 A range from pixels to about 50 ⁇ 50 pixels is used as the search range.
  • FIG. 3 shows a configuration of an example of a conventional motion vector detecting device that obtains a motion vector by a block matching method.
  • the motion vector detection device shown in FIG. 3 includes an image memory 201 that stores image data, and a motion vector extraction unit 202 that obtains a motion vector by performing an operation using the image data. Have been. Image memory 201 and motion vector extraction The unit 202 is connected via a data path.
  • the image memory 201 stores the image data of the attention frame and the reference frame. Then, the motion vector extraction unit 202 reads the target block and the candidate block from the image memory 201 via the data bus, and obtains the sum of absolute differences between the target block and the candidate block. . Furthermore, the motion vector extraction unit 202 finds a candidate block (minimum candidate block) that minimizes the sum of absolute difference values among candidate blocks that can be selected within the search range, and calculates the minimum candidate block. The vector from the target block to the target block is obtained and output as the motion vector of the target block.
  • a candidate block minimum candidate block
  • the image memory 201 for storing image data is generally composed of a plurality of memories (semiconductor memories). That is, in FIG. 3, the image memory 201 is composed of six memories 201 i to 210.
  • Each of the memory 2 0 1 to 2 0 1 beta constituting the image memory 2 0 because occupies relatively not large area, from each of the memory 2 0 1 I ⁇ 2 0 1 6, the motion vector extraction unit 2 0 to transfer image data to 2, as a data path connecting the memory 2 0 1-2 0 1 6 each motion base vector extractor 2 0 2, relatively long is required. When driving a long data bus, various problems occur.
  • the wiring resistance (wiring resistance) will increase. It needs to be thick. When the distance between the wirings is reduced and the thickness of the wiring is increased, the capacitance between the wirings is increased, and the crosstalk cannot be ignored.
  • the capacitance between the wiring and the substrate may be considered, and since the potential of the substrate is constant, when simulating the image memory 201, Wiring capacitance was not a major issue.
  • the signal waveform is significantly disturbed due to reflection at the wiring end.
  • FIG. 4 there is a method in which a cache memory 203 is provided between the image memory 201 and the motion vector extraction unit 202 to configure a motion vector detection device.
  • the cache memory 203 reads out image data frequently used by the motion vector extraction unit 202 from the image memory 201 and stores it. Then, the motion vector extraction unit 202 uses the image data stored in the cache memory 203 to obtain a motion vector by a block matching method.
  • the image data transferred from the plane image memory 201 to the cache memory 203 does not need to be read from the image memory 201, so a long data path is required.
  • the frequency of the above-described problem can be reduced.
  • a redundant memory called a cache memory 203 is required separately from the image memory 201, and the overhead is a problem.
  • the present applicant firstly converts the process data including the instruction for executing each process for performing the motion vector detection processing into the serially connected complex for executing the process.
  • An image processing apparatus that moves several execution means to perform image processing has been proposed (see Japanese Patent Application No. 2002-2363687). According to this, for example, a motion vector can be detected by an easily designed hardware that does not require a long data path or a cache memory. Disclosure of the invention
  • the present invention is directed to performing image processing by moving a plurality of serially-connected execution means for executing process data to process data, and further reduces processing time. Aim.
  • An image processing apparatus generates a process for performing image processing that handles image data, a process generation unit that sequentially outputs process data including an instruction for executing each process, and a process according to the process data.
  • a plurality of execution means connected in series, wherein the process data includes an address of the execution means for executing the process related to the process data, and a set of a predetermined number of continuous execution means.
  • a route selecting means for selectively supplying input process data to the input side or the output side of the set is inserted into the input side of the set.
  • the route selection means includes a first address storage means for storing an address of each execution means constituting the immediately succeeding set, and a first address storage means for storing an address of the execution means included in the input process data.
  • a first address determination unit that outputs a determination signal that becomes a state when at least one of the addresses stored in the first address determination unit is present; and a determination signal output from the first address determination unit.
  • the judgment signal is in one state, the input process data is supplied to the input side of the immediately succeeding pair, and when the judgment signal is not in the one state, the input process data is supplied to the output side of the immediately succeeding pair.
  • first switching means When the judgment signal is in one state, the input process data is supplied to the input side of the immediately succeeding pair, and when the judgment signal is not in the one state, the input process data is supplied to the output side of the immediately succeeding pair.
  • the process generating means generates each process for performing image processing for handling image data, and sequentially outputs process data including an instruction for executing each process.
  • Image processing is performed by moving the sequentially output process data through a plurality of serially connected execution means for executing the process.
  • the image processing is, for example, image processing for detecting a motion vector.
  • the plurality of execution means are divided into a set of a predetermined number of continuous execution means. Then, for each set, a route selection means for selectively supplying input process data to the input side or the output side of the set is inserted at the input side of the set.
  • the route selection means has a first address storage means for storing an address of each execution means constituting the immediately succeeding set. Further, the process data includes an address of an execution unit for executing a process related to the process data. When at least one of the addresses stored in the address storage means is present in the address of the execution means included in the input process data, the route selection means transfers the input process data to the input side of the immediately subsequent set. If not, it supplies the input process data to the immediately following set of outputs.
  • the process data moves by bypassing the set in which there is no execution means for executing the process related to the process data, so that the processing time can be reduced.
  • power consumption can be reduced because useless movement of process data is eliminated.
  • an image processing apparatus generates a process for performing image processing for handling image data, and a process generating unit that sequentially outputs process data including an instruction for executing each process; And a plurality of execution means connected in series, wherein the process data includes an address of the execution means for executing the process related to the process data. Then, each of the plurality of execution means processes the image data according to an instruction included in the input process data, and changes the input process data based on the processing result to obtain process data to be output. Processing means for outputting a request signal which is in one state when the process data to be output is output; address storage means for storing its own address; and address for execution means included in the input process data.
  • Address determination means for outputting a determination signal which becomes the same state when its own address stored in the storage means exists; and a determination signal output from the address determination means and a request signal output from the processing means.
  • the request signal is in one state
  • the process data to be output obtained by the processing means is output to the output process.
  • outputs as a data request signal is not one state, and the determination signal And switching means for outputting the input process data as the output process data when the state is not “-”.
  • the process generating means generates each process for performing image processing for handling image data, and sequentially outputs process data including an instruction for executing each process.
  • Image processing is performed by moving the sequentially output process data through a plurality of serially connected execution means for executing the process.
  • the process data includes an address of an execution unit for executing a process related to the process data.
  • Each of the plurality of execution units further includes, for example, a data storage unit for storing image data, and writes the image data into the data storage unit as processing of the image data, and stores the image data from the data storage unit.
  • the image processing is, for example, image processing for detecting a motion vector.
  • Each of the plurality of execution units has a processing unit, an address storage unit, an address determination unit, and a switching unit.
  • the processing means processes the image data in accordance with the instructions included in the input process data, changes the input process data based on the processing result, obtains the process data to be output, and outputs the process data to be output. When this is done, a request signal that is in one state is output.
  • the address determination means outputs a determination signal which becomes one state when the address of the execution means included in the input process data has its own address stored in the address storage means.
  • the switching means When the request signal is in one state, the switching means outputs the process data to be output obtained by the processing means as output process data, and when the request signal is not in one state and the determination signal is one state, If not, output the input process data as output process data.
  • the switching means is configured so that the request signal is not in one state and the determination signal is in one state. If, high-level or low-level data may be output. In this case, the process related to the process data input to the execution unit is executed by the execution unit. If the input process data is not supplied to the subsequent stage, or if the process data to be output from the processing unit is not supplied to the subsequent stage, high-level or low-level data is output, and the wrong process is output to the subsequent stage. Data can be prevented from being supplied.
  • FIG. 1 is a diagram illustrating the block matching method.
  • FIG. 2 is a diagram illustrating the block matching method.
  • FIG. 3 is a block diagram showing a configuration of an example of a conventional motion vector detection device.
  • FIG. 4 is a block diagram showing a configuration of another example of the conventional motion vector detection device.
  • FIG. 5 is a block diagram illustrating a configuration of a motion vector detection device as an embodiment.
  • FIG. 6 is a diagram showing the format of the process bucket.
  • FIG. 7 is a flowchart for explaining the process generation processing.
  • FIG. 8 is a block diagram illustrating a configuration example of a route selection unit.
  • FIG. 9 is a block diagram illustrating a configuration example of an arithmetic unit.
  • FIG. 10 is a diagram showing the relationship between the determination signal S l , the request signal s 2, and the switching of the switching switch.
  • FIG. 11 is a flowchart illustrating a process execution process of the calculation unit.
  • FIG. 12 is a diagram for explaining the process execution process (in the case of a write instruction) of the arithmetic unit.
  • FIGS. 13A and 13B are diagrams showing a state in which image data is written in the memory.
  • FIG. 14 is a diagram for explaining the process execution process (in the case of a read instruction) of the arithmetic unit.
  • FIG. 15 shows the process execution process of the arithmetic unit (in the case of the absolute difference sum operation instruction)
  • FIG. 16 is a diagram for explaining the processing of the arithmetic processing unit.
  • FIG. 17A and FIG. 17B are diagrams showing changes in the process bucket. BEST MODE FOR CARRYING OUT THE INVENTION
  • FIG. 5 shows a configuration of a motion vector detection device 100 as an embodiment.
  • the motion vector detection device 100 detects a motion vector by the above-described block matching method.
  • This motion vector detection device 100 has a process generation unit 101.
  • the process generation unit 101 generates each process for performing a process of detecting a motion vector, and sequentially processes packet (process data) which is a bucket including an instruction for executing each process. Output.
  • the process generation unit 101 is supplied with image data to be detected as a motion vector.
  • the process generation unit 101 also arranges the image data in the process packet as needed.
  • the motion base Kutonore detector 1 0 0 executes a process in accordance with the process bucket DOO, serially connected plurality, 1 2 pieces in this embodiment of the arithmetic processing Yunitto 1 0 2 to l 0 2 1 2 Have. Processing Yunitto 1 0 2 ⁇ l 0 2 1 2 are their respective constitutes the execution unit. These 1 two processing Yunitto 1 0 2 to 1 0 2 1 2 is connected to the subsequent stage of the process generating unit 1 0 1.
  • the arithmetic processing unit 102 n 1 to 12 is the arithmetic processing unit 102 in the preceding stage. -Receives a process packet supplied from (or a route selection unit) and performs processing according to the instructions included in the process packet.
  • the route selection unit and the tally unit will be described later.
  • the motion vector detection device 1 0 0, three route selection unit 1 0 4 -1 0 4 3 have. 12 processing Yuet 1 02i ⁇ l 02 12 described above is divided into four communication set of processing Yunitto to continue to. That is, a set 102 a unit 102i ⁇ l 02 4, a set 102 b of Yunitto 102 5-102 8, is divided into a set 102 c of Yuet 102 9-102 12. Three route selection unit 104 i to 104 3 as described above is inserted into the input side of the respective sets 102 a to 102 c. Note that the number of sets does not have to be three, and the number of arithmetic processing units 102 n constituting each set may not be the same.
  • Each selector 104i ⁇ l 04 3 selectively supplies the input process packet, on the input side or output side of the set 102 a to 102 c located immediately.
  • the arithmetic processing Yunitto 102 n to perform engagement Ru process the input process packet is present in the set 102 a to 102 c located immediately after the input process packet Is supplied to the input of the set, otherwise the input process bucket is supplied to the output of the set.
  • the motion vector detection device 100 includes a counting unit 103.
  • the counting unit 103 is connected to the output side of the last processing Yunitto 102 12, the arithmetic process Interview - difference between Tsu bets 102 12 is placed into the process bucket you want to output target plots click and candidate Proc
  • the motion vector is calculated from the sum of absolute values and output.
  • output from the process generating unit 101 described above moves the processing unit 1 02i ⁇ l 02 12, illustrating the Fomatsuto process bucket bets.
  • Figure 6 shows an example of the format of a process packet.
  • a process packet includes a processing unit address section, a PID (Process Identification) section, a state section, an instruction section, an address section, and a data section provided in that order from the top.
  • PID Process Identification
  • addresses of one or more arithmetic processing units for executing a process related to the process packet are arranged.
  • a PID is arranged in the PID section.
  • the PID any information can be adopted as long as it can distinguish individual processes to be performed before obtaining a motion vector of a certain target block.
  • the PID for example, the address indicating the position of the block of interest and the It is possible to employ a combination with an address indicating a position.
  • the number information can be used as PID.
  • the process packet of all the serial numbers is aligned in the counting unit 103, so that a certain block of interest is connected to all the candidate blocks that can be selected in the search range. It is possible to recognize that the sum of the absolute difference sums has been obtained.
  • the state unit includes, for example, an image writing state unit, an image reading state unit, a target block reading state unit, a candidate block reading state unit, and a difference absolute value calculation state unit.
  • state information “not yet written” indicating that certain image data has not yet been written to the memory 120 of the arithmetic processing unit 102 n described later,
  • One of state information “medium” indicating that writing is being performed and “end” indicating that writing of the image data has been completed is set.
  • the memory 120 constituting the arithmetic processing unit 102 n is represented as the memory 120n
  • certain image data is stored in the memory 120 of the arithmetic processing unit 102 i.
  • the image data is separately written to the memory 1 0 2 and the memory 1 2 0 j of the arithmetic processing unit 1 0 2; the image data is written to both the memory 1 2 0!
  • the status information “unknown” is set in the image writing status section.
  • the status information “medium” is set in the image writing status portion.
  • the memory 1 2 0 i and memory 1 2 0 5 both image data of when written, the image write state portion, status information "end" is set.
  • the status information set in the status portion serves as a message for notifying the arithmetic processing unit 102 # of the status of the image data writing or the like.
  • state information “not yet” indicating that certain image data has not been read from the memory 120, and reading of the image data are performed.
  • One of state information “medium” indicating that the image data is being read and state information “end” indicating that the reading of the image data has been completed is set.
  • state information “not yet” indicating that the image data of the target block has not been read from the memory 120, and the image data of the target block are read.
  • One of the state information “medium” indicating that the image data is being read and the state information “end” indicating that reading of the image data of the target block is completed is set.
  • state information “not yet” indicating that image data of the candidate block has not been read from the memory 120, and image data of the candidate block are read.
  • the difference absolute value calculation status section includes state information “not yet” indicating that the calculation of the sum of the difference absolute values (sum of difference absolute values) of a certain block of interest and the catching block has not been performed, and the difference absolute value. State information indicating that the sum operation is being performed
  • the status information is, for example, 2 bits, and “11”, “10”, and “00” can be assigned to “not yet”, “medium”, and “end”, respectively.
  • instructions for instructing processing to be performed are arranged.
  • examples of the instruction include a write instruction instructing writing of image data to the memory 120, a read instruction instructing reading of image data from the memory 120, and a difference between the target block and the candidate block.
  • At least four instructions, the minimum value judgment instruction are provided.
  • the instruction section has two bits, taking into account future expansion of instruction types. For example, it is desirable to set it to 4 bits.
  • the address section is composed of a field designation section, a read address section, a write address section, a block address section of interest, and a candidate block address section.
  • Field information indicating a field of the candidate block is set in the field designating section. That is, in the present embodiment, as will be described later, five fields of image data are stored in the memory 120 of the arithmetic processing unit 102 n , and the memory 120 is stored in the field designating section. Field information indicating a field in which the candidate block exists in the image data stored in. When storing 5 bytes of image data, 3 bits are sufficient for the field information. However, in consideration of future expansion, it is desirable to use more than 3 bits, for example, 4 bits. .
  • the address of the memory 120 from which the image data is read is arranged in the read address section. Is done.
  • the write address section when writing image data to the memory 120, that is, when a write instruction is set in the instruction section, the address of the memory 120 to write the image data is arranged. Is done.
  • the address of the block of interest is arranged in the block of interest block.
  • the address of the trap block is arranged.
  • the data section is composed of the block data section of interest, the trap block data section, the sum of absolute differences, and the candidate vector section.
  • the candidate block data section image data of the candidate block, that is, pixels constituting the candidate block are arranged. Therefore, if the candidate block is composed of, for example, the same 4 ⁇ 2 pixels as the target block as described above, and if one pixel is assigned, for example, 8 bits,
  • the sum of absolute differences of the target block and the candidate block is arranged in the sum of absolute differences.
  • the absolute difference between the pixel of the block of interest and the pixel of the candidate block corresponding to that pixel is represented by 9 bits.
  • a vector from the candidate block to the target block is arranged as a motion vector candidate (candidate vector) of the target block.
  • the candidate vector can be obtained from the address of the block of interest placed in the block address of interest block and the address of the candidate block placed in the address block of candidate blocks.
  • the search range is 63 x 63 pixels or less
  • step SI the process generation unit 101 determines at least image data of the block of interest in the field of interest in which the block of interest exists and image data of the search range in the reference field in which the candidate block exists. Then, a part or all of the write process for writing to the memory 120 is generated, a process packet including a write instruction for executing the write process is generated, and the process proceeds to step S2.
  • step S1 the process generation unit 101 arranges a write instruction in the instruction part of the process bucket shown in FIG. 6, and also writes the image data of the target block or candidate block to be written in the memory 120 into the target block data part. It is arranged in the candidate block data section, and the address of the memory 120 for writing the image data is arranged in the write address section.
  • the process generation unit 101 arranges, in the processing unit address section, the address of one or a plurality of arithmetic processing units 102 ⁇ for executing the writing process. Further, the process generation unit 101 arranges state information in the state part of the process packet as needed.
  • step S2 the process generation unit 101 outputs the process packet generated in the immediately preceding step S1, and proceeds to step S3.
  • step S3 the process generation unit 101 converts the necessary image data, that is, the image data of the block of interest and the image data of the search range in the reference field in which the candidate block exists, into at least the memory Determine whether all of the processes to write to 120 have been created. If it is determined in step S3 that all the processes for writing the necessary image data to the memory 120 have not been generated yet, the process returns to step S1, and the process generation unit 101 stores the required image data in the memory 120. A process for writing image data that has not yet been written is generated among the processes for writing to 120, and the same processing is repeated thereafter.
  • step S3 when the process generation unit 101 determines that all processes for writing necessary image data to the memory 120 have been generated, the process proceeds to step S4.
  • step S4 the process generation unit 101 selects From a certain candidate block that can be selected, for a vector to a block of interest (capture vector), a difference absolute value sum calculation process for calculating the sum of absolute differences between the block of interest and the block of capture is generated.
  • a process bucket including a difference absolute value sum operation instruction for executing the value sum operation process is generated, and the process proceeds to step S5.
  • step S4 the process generation unit 101 places an absolute difference sum operation instruction in the instruction part of the process bucket shown in FIG.
  • the address of the trap block is placed in the block address section of interest and the trap block address section, and the candidate vector is placed in the trap vector section.
  • the process generation unit 101 arranges, in the processing unit address unit, an address of one or a plurality of operation processing units 102 n for executing the absolute difference sum operation process. Further, the process generation unit 101 arranges the field information representing the field of the candidate block in the field designating unit and, if necessary, arranges the state information in the state unit of the process packet.
  • step S5 the process generation unit 101 outputs the process packet generated in the immediately preceding step S4, and proceeds to step S6.
  • step S6 is the process generation unit 101 generated a difference absolute value sum calculation process for calculating a difference absolute value sum for all of the candidate vectors that can be selected in the search range of the target block? Determine whether
  • step S6 the process generation unit 101 still generates a difference absolute value sum calculation process for calculating the sum of difference absolute values for all of the candidate vectors that can be selected within the search range of the target block. If it is determined that there is no difference absolute value sum calculation process, the process returns to step S4 to generate a difference absolute value sum calculation process for calculating the difference absolute value sum for candidate vectors for which the difference absolute value sum calculation process has not yet been generated. Repeat the same process.
  • step S6 the process generation unit 101 generates a difference absolute value sum calculation process for calculating a difference absolute value sum for all candidate vectors that can be selected within the search range of the target block. If it is determined, the process proceeds to step S7.
  • step S7 the process generator 101 selects a block within the search range of the block of interest. The minimum value of the sum of absolute differences obtained for all of the candidate vectors that can be selected is determined, and a minimum value determination process for determining the motion vector of the block of interest is generated based on the minimum value, and the minimum value determination is performed. A process packet including a minimum value determination command for executing the process is generated, and the process proceeds to step S8.
  • step S8 the process generation unit 101 outputs the process packet generated in step S7, and ends the processing thereafter.
  • the process generation unit 101 In the motion vector detecting apparatus 100 shown in FIG. 5, the process generation unit 101 generates each process for performing the process of detecting the motion vector as described above, and executes each process. Outputs a process bucket containing instructions sequentially. Each of these process packets travels through the arithmetic processing units 10 2 i to 10 2 1 2 , whereby the operation units 10 2 L to 10 2 12 are used to detect motion vectors. Each process is executed sequentially.
  • the process bucket in which the sum of absolute differences of the candidate vectors that can be selected within the search range of the target block is arranged is received by the totaling unit 103.
  • the counting unit 103 selects the one in which the minimum absolute difference value is arranged from the process packets corresponding to the absolute difference sum calculation process,
  • the candidate vector arranged in the process packet is output as the motion vector of the block of interest.
  • each Purosesupa packets output from the process generation unit 1 0 1 Not moves all the processing Yunitto 1 0 2 t ⁇ l 0 2 2 / rate selection unit 1 0 According to 4 i to l 0 4 3 , each process packet is appropriately bypassed and moves.
  • each of the route selection units 104 i to 104 3 includes a set 10 2 a to 10 0 in which an arithmetic processing unit 10 2 n for executing a process related to an input process packet is located immediately after the processing unit. If it does not exist in c, the input process packet is supplied not to the input of the set 102a to 102c but to the output of the set. As described above, since the process packet moves by bypassing the group in which the arithmetic processing unit 102 ⁇ for executing the process related to the process bucket does not exist, the processing time can be reduced. Also, since unnecessary movement of process packets is eliminated, Power consumption can be reduced.
  • Figure 8 shows a configuration example of a route selection selecting section 104 n.
  • the route selection unit 104 n has a FI FO (First-In First-Out) memory 131.
  • the FIFO memory 131 holds a process packet (input process packet) supplied via a data path from the preceding process generation unit 101 (or a route selection unit or an arithmetic processing unit). This FIFO memory 131 takes in the input process packet in synchronization with the system clock supplied thereto, and temporarily stores it.
  • the route selection unit 104 # has an address storage unit 132 and an address determination unit 133.
  • the address storage unit 132 stores in advance all of the arithmetic processing units 102 n existing in the immediately succeeding set. Adoresu is stored. for example, with respect to the route selection unit 104, the address storage unit 132, the arithmetic processing Yunitto 102i ⁇ l 02 4 of Adoresu present in pairs 10 2 a corresponding immediately is stored The same applies to the route selection units 104 2 and 104 3 .
  • the address determination unit 133 is a process related to the process packet PPe output from the FIFO memory 131. It is determined whether or not a force is to be executed in one of the arithmetic processing units 102 ⁇ existing in the set located immediately after.
  • the address determination unit 133 stores the address storage unit 132 in one or a plurality of addresses stored in the processing unit address portion (see FIG. 6) of the process packet PPe output from the FIFO memory 131. It is determined whether or not at least one of the addresses stored in the memory exists, and if it exists, it is determined to be in one state, for example, “1”, and if not, to another state, for example, to “0”. and it outputs the S 3.
  • the route selection unit 104 ' is have a switching switch 134 as switching means.
  • the switching switch 134 based on the determination signal s 3, the process bucket bets PP e output from the FI FO memory 131 The switch is selectively supplied to the input side or the output side of the set located immediately after the route selection unit 104 n . 34 is connected to the A side when the judgment signal S 3 is “1”, and is connected to the B side when the judgment signal S 3 is “0”.
  • the output side of the FIFO memory 131 is connected to the movable terminal of the switching switch 134 via a delay circuit 135 for time adjustment.
  • the fixing pin of the A side of the switching switch 134 is connected to a set of input-side located immediately after the route selection unit 104 [pi, fixed terminal of the ⁇ side is located immediately after the route selection unit 104 eta Connected to the output side of the set.
  • the process related to the process packet PPe is routed based on the address stored in the processing route address unit of the process packet PPe output from the FIFO memory 131. It is determined whether or not the processing is to be executed by the arithmetic processing unit 102 ⁇ existing in the set located immediately after the selecting unit 104. As described later, based on the determination signal s 3 is a result of the determination, switching of the switching switch 1 34 is controlled, the Purosesupa packet PP e is set to be located immediately after the route selection section 104 n Supplied to the input or output side.
  • part of the processing Yuetsutadoresu of the process packets PP e is in a state already be output from the FI FO memory 131, switching the output side of the FI FO memory 131 Suitsuchi If it is directly connected to the movable terminal of 134, the process packet PPe may not be output from the switching switch 134 in a complete state without missing.
  • the above-described delay circuit 135 for time adjustment is for outputting the process bucket PPe from the switching switch 134 in a complete state without any loss, and at least the process bucket PPe from the FIFO memory 131. There is a delay time from when the output of PP e is started to when the address determination unit 133 outputs a determination result.
  • the route selection unit 104 n operation shown in FIG. 8 will be described.
  • Process packets (input process buckets) supplied via the data path from the preceding process generation unit 101 (or route selection unit or arithmetic processing unit) are taken into the FIFO memory 131 and temporarily stored. Is done. And The process packet PPe output from the FIFO memory 131 is supplied to the movable terminal of the switching switch 134 via the delay circuit 135.
  • Adoresu determination unit 133 processing Yunittadoresu part of the process the bucket bets PP e to the address stored in (see FIG. 6), it determines whether at least one of the addresses stored in the address storage unit 132 is present I do.
  • the process related to the process bucket PP e is executed by the arithmetic processing unit 102 ⁇ in the set located immediately after the route selection unit 104 n.
  • the judgment signal s 3 is set to “1”.
  • the switching switch 134 is connected to the ⁇ side, and the process bucket PPe is supplied via the A side of the switching switch 134 to the input side of the set located immediately after the route selection unit 104 n .
  • the process related to the process bucket PPe is performed by the route selection unit 104.
  • the switching switch 134 is connected to the B side, and the process packet PPe is supplied to the output side of the set located immediately after the route selection unit 104 n via the B side of the switching switch 134.
  • FIG. 9 shows a configuration example of the arithmetic processing unit 102 n .
  • the arithmetic processing unit 102 n includes a PE (Processing Element) 110 and a memory 120.
  • the PE 110 has FIFO memories 111 and 112 and an operation unit 113. These FIFO memories 111 and 112 and the operation unit 113 are connected in series.
  • the FIFO memory 111 holds the process packets (input process packets) supplied via the data path from the previous processing unit (or route selection unit). This FIFO memory 111 captures an input process packet and stores it temporarily, in synchronization with the system clock supplied thereto.
  • the FIFO memory 112 holds the process bucket input to the operation unit 113. The FIFO memory 112 fetches and temporarily stores the process packets PPa sequentially output from the FIFO memory 111 in synchronization with the system clock supplied thereto.
  • the operation unit 113 performs a process according to an instruction included in the process bucket PPb sequentially output from the FIFO memory 112, and changes the process packet based on the processing result to output the process bucket. To obtain PP c. Further, the arithmetic unit 1 1 3, one state when outputting process packet PP c to be output, for example, "1", and other other conditions when the request signal s 2, for example a "0" Output.
  • the operation unit 113 has at least the functions of decoding an instruction included in the process bucket, executing the decoded instruction, generating a process packet to be output, and outputting the process bucket.
  • the operation unit 113 decodes an instruction included in the input process bucket P Pb and executes the instruction if the instruction can be executed. Then, the operation unit 113 changes the input process bucket PPb based on the result of the processing performed by executing the instruction to obtain a process packet PPc to be output, and outputs the process packet PPc. I do.
  • the operation unit 113 sets the input process bucket PPb as a process packet PPc to be output as it is, and outputs the process packet PPc.
  • the operation unit 113 can execute the instruction included in the input process packet PPb, but the same process bucket as the input process packet PPb has been input in the past, and the processing by that Does not perform any processing for the input process packet PP b. This is because the input process packet P Pb in this case is an unnecessary process packet.
  • the memory 120 is connected to the operation unit 113 via a data bus.
  • the operation unit 113 stores the image data in the memory 120 or reads out the image data from the memory 120 as necessary.
  • the command placed in the process packet The commands include a write command to instruct writing of image data and a read command to instruct reading of image data.
  • the arithmetic unit 113 supplies the image data to the memory 120 via the data path and writes the image data.
  • the arithmetic unit 113 reads out the image data via the memory 120, a data path, and the like, and arranges the image data in the process packet. I do.
  • the memory area of the memory 120 is divided into five banks, so that the image data of five fields is divided into separate punctures. Can be memorized.
  • each puncture of the memory 120 need not have a storage capacity enough to store image data for one field.
  • each bank of memory 1 2 0 1 2 pieces of processing Yunitto 1 0 2 to 1 0 2 1 2 in total has a storage capacity of image data can be stored at least search range It should just be. That is, in the present embodiment, it is sufficient that the storage capacity of 12 times the storage capacity of one bank is equal to or larger than the amount of image data in the search range.
  • one puncture in the memory 120 has a storage capacity capable of storing image data for one to twenty-two fields. Therefore, as the memory 120, a memory in which the wiring capacity does not matter as described in FIG. 3, that is, the storage capacity is not so large, and the data path between the memory 110 and the PE 110 can be shortened. Memory can be adopted.
  • the PE 110 has an address storage unit 114 and an address determination unit 115.
  • the address storage unit 114 stores in advance the address of the arithmetic processing unit 102 n itself, that is, its own address.
  • Adoresu determination unit 1 1 5 the process according to the process packets PP a output from the FIFO memory 1 1 1 is equal to or intended to be executed by the arithmetic process Yuet 1 0 2 n. That is, the address determination unit 115 stores one or more addresses stored in the processing unit address unit (see FIG. 6) of the process packet PPa output from the FIFO memory 111 into the address storage unit 1. 14 It is determined whether or not the address of its own stored in 4 exists. The status signal, for example, becomes “1”, and when it does not exist, outputs a judgment signal si that becomes another status, for example, “0”.
  • the PE 110 is provided with a switching switch 116 as switching means for selectively taking out the process packet PPa output from the FIFO memory 111 or the process bucket PPc output from the arithmetic unit 113, And a switching control section 117 for controlling the switching of the switching switch 116.
  • the output side of the operation unit 113 is connected to the fixed terminal on the A side of the switching switch 116, and the output side of the FIFO memory 111 is connected to the fixed terminal on the B side of the switching switch 116 via a delay circuit 118 for time adjustment.
  • the fixed terminal on the OFF side of the switching switch 116 is connected to a power supply terminal.
  • the OFF fixed terminal is supplied with high-level data “1”.
  • the fixed terminal on the OFF side may be grounded, and low-level “0” data may be supplied to it.
  • the movable terminal of the switching switch 116 becomes the output terminal of the arithmetic processing unit 102 n .
  • this movable terminal is connected to a subsequent processing unit (or a route selection unit or a tallying unit) via the data path.
  • the process related to the process packet PPa performs this arithmetic processing packet. It is determined whether or not the force is to be executed at the unit 102 ⁇ .
  • process packet PP a when not intended that process packet PP a is executed in the arithmetic process Yuyu' DOO 102 n, but and outputs the process packet PP a immediately subsequent stage via the switching sweep rate Tutsi 116 At least at the time of determination, the processing unit address portion of the process bucket PPa has already been output from the FIFO memory 111, and the output side of the FIFO memory 111 is fixed to the B side of the switching switch 116. If it is directly connected to the terminal, the process packet PPa cannot be supplied to the subsequent stage in a complete state without missing.
  • the above-described delay circuit 118 for time adjustment is used to supply the process packet PPa to the subsequent stage in a complete state without any chipping.
  • the delay time from when the output of the process bucket PPa is started by the memory 111 until the determination result is obtained in the address determination unit 115 is provided.
  • the switching control unit 1 1 7, the request signal s 2 Oyopia judgment signal S l output from address determination unit 1 1 5 outputted from the arithmetic unit 1 1 3 is supplied. Then, switching control unit 1 1 7, when the request signal s 2 is "1", the determination signal s is regardless of whether it is "1" Der Luke “0", the switching switch 1 1 6 Control to connect to A side. Further, the switching control unit 1 1 7, the request signal s 2 is "0", and when the determination signal S l is "0", to control such switching switch 1 1 6 is connected to the B-side You. Further, the switching control unit 1 1 7, the request signal s 2 is "0", and when the determination signal s is "1", the control so switching Suitsuchi 1 1 6 is connected to the OFF side.
  • Figure 1 0 is the decision signal si and the request signal s 2, shows the switching of the relationship between the switching Suitsuchi 1 1 6.
  • Process packets (input process packets) supplied from the preceding processing unit (or route selection unit) via the data bus are taken into the FIFO memory 111 and temporarily stored.
  • the process packet PPa output from the FIFO memory 111 is taken into the FIFO memory 112 and temporarily stored. Further, the process packet PPa output from the FIFO memory 111 is supplied to the B-side fixed terminal of the switching switch 116 via the delay circuit 118.
  • the process bucket PPb sequentially output from the FIFO memory 112 is supplied to the operation unit 113.
  • the operation unit 113 decodes an instruction included in the process bucket P Pb and executes the instruction if the instruction can be executed. Then, the operation unit 113 changes the input process packet PPb based on the result of the processing performed by executing the instruction, generates the process packet PPc to be output, and generates the process packet PPc. Outputs PP c.
  • This process bucket PPc is supplied to the fixed terminal on the A side of the switching switch 116.
  • the operation unit 113 can execute the instruction included in the input process bucket PPb, but the same process bucket as the input process packet PPb is generated. If it has been input in the past and the processing based on it has been completed, no processing is performed for the input process bucket PPb. Whether or not the process packet is the same can be determined based on the PID arranged in the PID section (see Fig. 6). On the other hand, when the execution of the instruction is not possible, the operation unit 113 sets the input process.
  • the packet PPb is a process packet PPc to be output as it is, and outputs the process packet PPc.
  • the process bucket PPc output from the operation unit 113 is supplied to the fixed terminal on the A side of the switching switch 116. Arithmetic unit 1 1 3 when outputting thus process packet PP c, the request signal s 2 to "1".
  • the address determination unit 115 determines whether or not the address stored in the address storage unit 114 exists in the address stored in the processing unit address unit of the process packet PPa. .
  • the address determination unit 115 executes the process related to the process bucket PPa in this arithmetic processing unit 102 n .
  • the judgment signal S l is set to “1”.
  • the address determination section 115 determines that the process related to the process bucket PPa is in the arithmetic processing cut 102 n .
  • the judgment signal S i is set to “0” because it is not to be executed.
  • Switching control unit 1 1 7 when the request signal s 2 is "1", connecting the changeover switch 1 1 6 A side. That is, when the operation unit 113 finishes the processing of the process bucket PPb and outputs the process packet PPc, the switching switch 116 is connected to the A side. In this case, the process bucket PPc output from the operation unit 113 is sent to the subsequent processing unit (or the route selection unit or the summation unit) via the A side of the switching switch 116. Supplied as
  • the switching control unit 1 1 7, the request signal s 2 is "0", and when the determination signal S l is "0", connecting the changeover switch 1 1 6 to the B side. That is, the operation unit 1 1 When 3 are performing the processing of process packet PP b, and not intended process according to process bucket preparative PP a output Ri good FI FO memory 1 1 1 is executed in the arithmetic process Yunitto 1 02 1>, The switching switch 116 is connected to the B side. In this case, the process packet PPa is immediately supplied as an output process packet to a subsequent processing unit (or a route selection unit or a counting unit) via the B side of the switching switch 116. As a result, the processing time can be reduced.
  • the switching control unit 1 1 7, the request signal s 2 is "0", and when the determination signal S l is "lj connects the changeover switch 1 16 to the OFF position. That is, the arithmetic unit 1 13 Is processing the process bucket PPb, and the process related to the process packet PPa output from the FIFO memory 111 is to be executed by the arithmetic processing unit 102 #, The switching switch 116 is connected to the OFF side. In this case, the high-level “1” or low-level “0” data is supplied to the subsequent processing unit (or the route selection unit or the counting unit).
  • an erroneous process packet for example, the process packet PPa output from the FIFO memory 111 (the bucket PPa is output to the arithmetic processing unit (or the route selection unit or the counting unit) in the subsequent stage) Is required to be processed by the operation unit 113 of the unit 102 n , but has not been processed).
  • step S11 the arithmetic unit 113 decodes the instruction arranged in the input process packet PPb, and proceeds to step S12.
  • step S12 the operation unit 113 determines whether the instruction decoded in step S11 can be executed.
  • step S12 the operation proceeds to step S13, and the same process packet as the input process packet PPb is input in the past. It is determined whether or not the processing has been completed.
  • the arithmetic units 113 determine that the processing has been completed, they do nothing with respect to the input process packet PPb and end the processing. In this case, the input process packet PPb is an unnecessary process packet, and the arithmetic unit 113 does not output a process packet corresponding to the input process packet PPb.
  • step S13 When determining that the processing has not been completed in step S13, the operation unit 113 proceeds to step S14, executes the instruction arranged in the input process bucket PPb, and follows the instruction. Perform processing. Then, in step S14, the operation unit 113 places the data obtained by performing the processing according to the instruction placed in the process packet in the input process packet PPb as necessary. Proceed to step S15.
  • step S15 the operation unit 113 rewrites the state part of the input process packet P Pb as necessary in accordance with the processing performed in step S14, and proceeds to step S16.
  • Step S 1 6 operation unit 1 1 3 a request signal s 2 to "1". Then, in step S17, the operation unit 113 outputs the input process bucket PPb changed in steps S14 and S15 as a process packet PPc to be output, and then in step S17. At 18, the request signal s 2 is returned to “0”, and the processing is terminated.
  • At least the input process packet PPb includes at least image data to be written to the memory 120 and a write address for writing the image data to the memory 120. It is assumed that
  • step SI1 the operation unit 113 decodes the instruction arranged in the input process packet PPb, and proceeds to step S12.
  • step S12 the operation unit 113 determines whether or not the instruction decoded in step S111 can be executed. It is determined whether or not the write address allocated in the input process bucket PPb is the address of the memory 12 On of the arithmetic processing unit 102 ⁇ .
  • step S12 determines that the write address arranged in the process bucket in step S12 is not the address of the memory 12
  • the arithmetic unit 113 performs steps S13 to S15. skip, the process proceeds to step S 16, a request signal s 2 to "1".
  • step S17 the arithmetic unit 113 outputs the input process bucket PPb as the process bucket PPc to be output as it is, and then in step S18, sets the request signal s2 to "0". Return and end the process.
  • the arithmetic unit 1 1 3 when it is determined that writing Adoresu disposed in the process bucket preparative step S 12 is a Adore scan memory 12 On having processing Yuni' DOO 102 n is, in step S 13 Then, it is determined whether the same process bucket as the input process packet PPb has been input in the past and has been processed. When judging that the processing has been completed, the operation unit 113 does not perform any processing on the input process packet PPb, and ends the processing. In this case, the input process packet PPb is an unnecessary process packet, and the operation unit 113 does not output a process bucket corresponding to the input process bucket PPb.
  • step S13 When determining that the processing has not been completed in step S13, the operation unit 113 proceeds to step S14 and executes the instruction arranged in the input process bucket PPb. That is, the arithmetic unit 1 13 writes the image data arranged in the input process packet PP b in the memory 120 n, the process proceeds to step S 1 5.
  • step S15 the operation unit 113 rewrites the state part of the input process packet PPb as necessary in accordance with the processing performed in step S14, and proceeds to step S16.
  • step S 16 the arithmetic unit 1 13, a request signal s 2 to "1". Then, in step S17, the arithmetic unit 113 outputs the input process bucket PPb changed in steps S14 and S15 as a process bucket PPc to be output, and then in step S18, return the request signal s 2 to "0", the process is terminated.
  • the process generation unit 101 performs steps S1 to S3 of the process generation process in FIG. And generates and outputs a process packet having a write instruction (hereinafter, referred to as a “write process packet” as appropriate).
  • the write process packet sequentially moves through the arithmetic processing units 102 to 102 i 2 , so that, for example, as shown in FIG. 13A and FIG.
  • the image data of the block is written to the memory 120.
  • the image data of the block of interest is represented by cross-hatching
  • the image data of the catch block is represented by hatching.
  • step S11 the operation unit 113 decodes the instruction arranged in the input process packet PPb, and proceeds to step S12.
  • step S12 the operation unit 113 determines whether or not the instruction decoded in step S11 can be executed.
  • the read address arranged in the input process bucket PP b is the operation processing unit. 1 0 determines whether Adoresu memory 1 2 O n where 2 n has.
  • Arithmetic unit 1 1 3 address, which occurs read out being arranged to process the bucket preparative Step S 1 2 is, when the arithmetic processing unit 1 0 2 n is the Most determined Do an address of the memory 1 2 O n having the steps skip the S 1 3 ⁇ S 1 5, the process proceeds to step S 1 6, the request signal s 2 to "1". Then, the arithmetic unit 1 3, in step S 1 7, the input process bucket preparative PP b directly to the process bucket preparative PP c to be output to output, in a subsequent step S 1 8, the request signal s 2 to "0 And end the process. You.
  • the arithmetic unit 1 1 3 reads Adoresu disposed in the process bucket preparative Step S 1 2 is, processing Interview - that the Adore scan memory 1 having the Tsu preparative 1 0 2 n 2 O n determined
  • the process proceeds to step S13 to determine whether the same process packet as the input process packet PPb has been input in the past and has been processed.
  • the operation unit 113 determines that the processing has been completed, it does not perform any processing on the input process bucket PPb, and ends the processing. In this case, the input process packet PPb is an unnecessary process packet, and the operation unit 113 does not output a process packet corresponding to the input process packet PPb.
  • step S13 When the arithmetic unit 113 determines that the processing has not been completed in step S13, the operation proceeds to step S14, and executes the instruction arranged in the input process packet PPb. That is, the operation unit 113 reads the image data from the memory 120 ⁇ ⁇ ⁇ , arranges the image data in the input process bucket PPb, and proceeds to step S15.
  • step S15 the operation unit 113 rewrites the state part of the input process packet P Pb as necessary in accordance with the processing performed in step S14, and proceeds to step S16.
  • Step S 1 6 operation unit 1 1 3 a request signal s 2 to "1". Then, in step S17, the operation unit 113 outputs the input process bucket PPb changed in steps S14 and S15 as the process bucket PPc to be output, and in S 1 8, it returns a request signal s 2 to "0", the process ends.
  • the image data of the target block and the candidate block for which the difference absolute value sum is to be calculated have been written in the memory 120. Furthermore, in addition to the difference absolute value sum operation instruction, the address of the target block and the candidate block stored in the memory 120, and the candidate vector from the candidate block to the target block are arranged at least in the input process packet PPb. Shall be You.
  • step SI1 the operation unit 113 decodes the instruction arranged in the input process packet PPb, and proceeds to step S12.
  • step S12 the operation unit 113 determines whether or not the instruction decoded in step S11 can be executed.
  • at least one pixel of the block of interest or the candidate block is an operation processing unit 102 n determines whether the stored memory 12 (to have. here, the pixel block of interest, whether stored in the memory 12 O n arithmetic processing Yunitto 102. has, in the input process bucket preparative PP b Whether the pixel of the candidate block is stored in the memory 120 n of the arithmetic processing unit 102 n can also be determined from the address of the allocated block of interest. Can be determined from this address.
  • Arithmetic unit 1 1 3 when determining that none of the target proc Contact Yopi Couto blocks in Step S 1 2, not stored in the memory 120 "having processing Yunitto 102 n is, step S. 13 to skips S 15, step S viewed 16 binary, the request signal s 2 to "1". Then, the arithmetic unit 1 13, in Step S 1 7, the input process packet PPb directly as a process packet PP c to be output to the output, then in step S 18, returns the request signal s 2 to "0", the processing Exit.
  • step S14 the instruction arranged in the input process bucket PPb is executed. That is, first, in step S21, the arithmetic unit 113 determines whether or not the pixel of the block of interest is stored in the memory 12On of the arithmetic processing unit 102 ⁇ . I do. When the calculation unit 113 determines that the pixel of the block of interest is not stored in the memory 12 On of the calculation processing unit 102 in step S21, the calculation unit 113 skips step S222. Proceed to step S23.
  • step S 21 when it is determined in step S 21 that the pixel of the block of interest is stored in the memory 120 of the arithmetic processing unit 102 n , Then, the pixel of the block of interest stored in the memory 12 ⁇ ⁇ is read out, placed in the input process packet PPb, and the flow advances to step S 23.
  • step S 2 arithmetic unit 1 1 3, memory 1 2 0 pixels of the candidate block has the processing Yuni' preparative 1 0 2 n. It is determined whether or not it is stored in the.
  • the operation unit 113 is a memory 120 in which the pixel of the candidate block is included in the operation processing unit 102 n in step S23. When it is determined that the information is not stored in step S24, step S24 is skipped and the process proceeds to step S25.
  • arithmetic unit 1 1 3 when it is determined that the pixel of the candidate blocks in Step S 2 3 is stored in the memory 1 2 O n having the "processing Interview Interview Tsu sheet 1 0 2, Step S 2 4 Then, the pixel of the candidate block stored in the memory 12 (is read out and arranged in the input process bucket PPb, and the process proceeds to step S25.
  • step S25 the operation unit 113 determines whether it is possible to calculate the sum of absolute differences.
  • the calculation unit 113 determines whether the pixel of the target block is arranged in the input process packet PPb and whether the pixel of the candidate block corresponding to the pixel of the target block is also arranged. Then, it is determined whether the sum of absolute differences can be calculated.
  • step S25 determines that the calculation of the sum of absolute differences is not possible in step S25, that is, the pixel of the block of interest is not arranged or is not arranged in the input process packet PPb. However, if the pixel of the candidate block corresponding to the pixel of the target block is not arranged, step S26 is skipped, thereby ending the execution of the difference absolute value sum calculation instruction and completing step S26. Go to 1-5.
  • step S25 when it is determined in step S25 that the sum of absolute differences can be calculated, that is, when the pixel of the block of interest is arranged in the input process packet PPb.
  • step S26 the pixels of the target block arranged in the input process packet PP and the candidate blocks corresponding to the pixels are selected. Calculate the absolute value of the difference with each pixel, and then calculate the sum.
  • the operation unit 113 adds the sum of the difference absolute values and the sum of the difference absolute values arranged in the difference absolute value sum unit of the input process packet PPb, and calculates the added value as a new difference absolute value.
  • the difference absolute value sum part of the input process bucket PPb is overwritten, thereby ending the execution of the difference absolute value sum calculation instruction and proceeding to step S15.
  • step S15 the operation unit 113 rewrites the state part of the input process packet P Pb as necessary in accordance with the processing performed in step S14, and proceeds to step S16.
  • Step S 1 6 operation unit 1 1 3 a request signal s 2 to "1". Then, in step S17, the arithmetic operation unit 113 outputs the input process packet PPb changed in steps S14 and S15 as a process packet PPc to be output, and thereafter, in step S1 At step 8, the request signal S2 is returned to "0", and the process is terminated.
  • the process generation unit 101 processes the process packet having the absolute difference sum operation instruction (hereinafter referred to as “difference absolute sum process packet” as appropriate). ) Is generated and output.
  • the difference absolute value sum process packet sequentially moves through the operation processing units 102 to 102 i 2 , so that the difference absolute value sum between the target block and the candidate block is calculated as shown in FIG. 16 and FIG. It is determined as shown in Figure 17A and Figure 17B.
  • FIG. 1 6 This, in memory 1 2 0 eta, a part power memory 1 2 0 eta + 1 of the target block, a part of the remaining candidate blocks of the target block, the memory 1 2 0 It is assumed that the remaining power of the candidate block is stored in ⁇ + 2 .
  • the kneaded rice 110 of the arithmetic processing unit 102 will be appropriately represented as ⁇ 110 ⁇ ⁇ .
  • the operation processing unit 102 n receives a process packet, PE 1 10 n reads out a portion of the target block stored in the memory 120 n, arranged to process packets, the next stage of processing Transfer to cut 102 n + 1 .
  • the process packets shown in FIGS. 17A and 17B are transmitted and received.
  • the process packet includes a PID part, a block of interest reading state part, a candidate block reading state part, Only the instruction section, the block address section of interest, the candidate block address section, the block section of interest section, the candidate block data section, and the sum of absolute difference values are shown.
  • Block of interest and candidate proc as described in FIG. 16, from being stored in the memory 120 ⁇ ⁇ 120 n + 2, the process packets, before being received by PE 110 n, attention Proc and candidate proc Neither reading has been performed, and therefore, the state information of the target block reading state section and the state information of the candidate block reading state section are both “not yet” as shown in FIG. 17B. Further, in this case, the address block addl of the block of interest and the address add2 of the candidate block are set in the block address section of interest and the candidate block address section, respectively. In addition, 0 is set as an initial value in the sum of absolute difference values. In the instruction section, “ME” indicating the sum of absolute difference sum operation instruction is set.
  • the process packet as described above is input to PE 11 On and processed as described in FIG. 16, so that the following process packet is transferred from PE 110 n to PE 11 On + 1 . Is done.
  • PE 11 In the process packet transferred to the PE 11 on + 1 , as shown in FIG. 17B, a part of the pixel data_al of the block of interest stored in the memory 12C is newly arranged. Furthermore, in the PE 11 O n, since the portion of the pixel data- al attention proc from the memory 12 O n is read, the status information of the target block read state of the process the packet, "medium from the" Not " Is rewritten as Processing Yunitto 102 n + 1 has received a process packets from processing Yunitto 102 n, PE 11 O n + 1 , as shown in FIG. 16, stored in the memory 12 O n + 1 Read the rest of the block of interest and part of the candidate block.
  • the PE 110 n + 1 calculates a sum of absolute differences that can be calculated using the pixels of the entire block of interest and some pixels of the candidate block read from the memory 120 n + 1 , and arranges the sum in the process packet. Further, the PE 110 n + 1 arranges the pixel of the block of interest not used in the calculation of the sum of absolute differences in the process packet, and transfers it to the next processing unit 102 n + 2 .
  • the process packet transferred from PE 110 n + 1 to PE 110 n + 2 includes, among the pixels of the block of interest, pixels that are not used for calculating the sum of absolute differences, — A2 is placed in place of the pixel data_al in the block of interest block, and the sum of absolute differences suml obtained by PE110 n + 1 is placed in place of the initial value 0 of the sum of absolute differences. Furthermore, in PE 110 n + 1 , all the pixels of the block of interest are obtained, and some pixels of the target block are obtained.
  • the state information of the candidate block read state part is rewritten from “not yet” to “medium” while being rewritten from “medium J” to “end”.
  • Processing Yunitto 102 n + 2 has received the Purosesupa packets from processing Yunitto 102 "+1, PE 11 On + 2 , as shown in FIG. 16, the candidate Proc stored in the memory 120n +2 Read the rest.
  • PE 11 On + 2 calculates the sum of absolute differences that can be calculated using the remaining pixels of the trap block read from the memory 120 n + 2 and the pixels of the block of interest arranged in the process packet. Add it to the sum of absolute difference values located in the process bucket. Then, the PE 110 n + 2 places the added value as a new sum of absolute differences in the form of overwriting the process packet and sends it to the next processing unit 102 n + 3 (not shown). Forward.
  • PE 110 n + 2 the sum of absolute differences sum2 for all pixels of the block of interest and the candidate block is obtained, and is transferred from PE 110 n + 2 to PE 110 n + 3 (not shown).
  • the resulting process packet contains the The sum of absolute differences sum2 is arranged in place of the sum of absolute differences suml of the sum of absolute differences. Also, since all the pixel data-a2 of the block of interest placed in the block of interest block in the process bucket are used in the calculation of the sum of absolute differences, the pixel data of the block of interest from the block of interest block One a2 is deleted. Further, in PE 110n + 2 , since the remaining pixels of the candidate block have been obtained, the state information of the candidate block read state portion of the process packet is rewritten from “medium” to “end”.
  • the process packet when the process packet is output from the PE 110n + 2 , the sum of the absolute differences sum2 of all the pixels of the target block and the catch block is arranged in the process bucket. . Therefore, in the arithmetic processing unit 102 n + 3 or later, the process packet is simply transferred and finally received by the counting unit 103 (see FIG. 5).
  • Tabulation unit 1 0 3 is also constructed similarly to the arithmetic processing unit 1 0 2 n. That is, the counting unit 103 is composed of the PE 110 and the memory 120. However, the counting unit 103 can have a configuration different from that of the arithmetic processing unit 102 ⁇ , but the same configuration as that of the arithmetic processing unit 102 pertainmakes it possible to detect the motion vector. The manufacturing cost of the apparatus 100 can be kept low.
  • the process generation unit 101 executes the processing of steps S4 to S6 in FIG. A sum of absolute difference calculation process for calculating the sum of absolute differences is generated. When all process packets corresponding to this process are received by the counting unit 103, the counting unit 103 The sum of absolute differences is obtained for all candidate vectors that can be selected within the search range of the target block.
  • a minimum value determination process is generated, and a process packet including a minimum value determination instruction is output.
  • This process packets via the arithmetic processing unit 1 0 2 i-l 0 2 1 2, is received by the counting unit 1 0 3.
  • the counting unit 103 obtains the minimum sum of absolute differences from the process bucket corresponding to the difference absolute value sum calculation process received up to that time.
  • the selected vector is selected, and the candidate vector allocated to the process packet is output as the motion vector of the block of interest.
  • the process for detecting the motion vector is performed by transferring (moving) the process packet in which the instruction and the necessary data are arranged, so that it is possible to drive a long data path. For example, it is possible to avoid, for example, wiring delay and crosstalk between wiring and the effects of reflection.
  • the twelve arithmetic processing units 102 to 102 i 2 are divided into four continuous arithmetic processing unit sets, and route selection is performed on the input side of each of the sets 102 a to 102 c. part 104 it to 104 3 is inserted. Then, each of the route selection section 104t ⁇ l 04 3, when the arithmetic processing Yunitto 102 n to perform processes according to the input process packet does not exist in the set 102 a to 102 c located immediately after, the input process Rather than supplying packets to the input side of the set 102a-l02c, it supplies the packets to the output side of the set.
  • the processing time can be reduced, and the process packet is moved wastefully. Power consumption can be reduced.
  • the arithmetic unit 113 processes the process packet PPb, and the process bucket PP output from the FIFO memory 111.
  • the switch 116 is connected to the B side. Therefore, the process packet PPa is immediately transmitted to the switching switch 11
  • the processing time can be shortened because it is supplied as an output process packet to the subsequent processing unit (or the route selection unit or the aggregation unit) via the B side of 6 above.
  • the arithmetic unit 1 1 3 has performed the processing of process packet PP b, and the process according to the process bucket preparative PP a output from the FIFO memory 1 1 1 is executed in the arithmetic process Yuyutto 1 0 2 n
  • the switching switch 1 16 is connected to the OFF side.
  • the high-level “1” or low-level “0” data is supplied to the subsequent processing unit (or the route selection unit or the counting unit).
  • the present invention is applied to the motion vector detecting device.
  • the present invention can be similarly applied to a device that performs other image processing that handles image data.
  • the present invention can be suitably applied to a device that performs a difference calculation of image data in the same manner as the above-described motion vector detection device and searches for a predetermined image or character in a reference field based on the difference calculation result. it can.
  • processing steps described with reference to the flowcharts described above do not necessarily need to be processed in chronological order according to the order described as the flowchart, and may be performed in parallel or individually (for example, Parallel processing or object-based processing).
  • image data is processed by moving process data including an instruction to execute each process for performing image processing by moving a plurality of serially connected execution means for executing the process.
  • a route selection means is inserted on the input side, and the route selection means is an execution means which constitutes a set immediately following a process related to the input process data.
  • the input process data is supplied to the output side of the set located immediately after the input process data, so that the processing time and the power consumption can be reduced.
  • image data is processed by moving process data including an instruction for executing each process for performing image processing by moving a plurality of serially-connected execution means for executing the process.
  • the execution means when the execution means does not execute the process related to the input process data, the execution means copies the input process data as it is. It is also output as output process data, so that processing time can be reduced.
  • the image processing apparatus can reduce the processing time and the power consumption, and can be applied to, for example, an application for detecting a motion vector by block matching.

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US7912126B2 (en) * 2005-06-30 2011-03-22 Intel Corporation Systems and methods for improved motion estimation
JP2014170556A (ja) * 2005-08-18 2014-09-18 D.E. Shaw Research LLC 粒子相互作用を計算するための並行計算アーキテクチャ
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US20080225948A1 (en) * 2007-03-13 2008-09-18 National Tsing Hua University Method of Data Reuse for Motion Estimation
US10122735B1 (en) * 2011-01-17 2018-11-06 Marvell Israel (M.I.S.L) Ltd. Switch having dynamic bypass per flow

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