WO2004047017A1 - Ic tag - Google Patents

Ic tag Download PDF

Info

Publication number
WO2004047017A1
WO2004047017A1 PCT/JP2003/014827 JP0314827W WO2004047017A1 WO 2004047017 A1 WO2004047017 A1 WO 2004047017A1 JP 0314827 W JP0314827 W JP 0314827W WO 2004047017 A1 WO2004047017 A1 WO 2004047017A1
Authority
WO
WIPO (PCT)
Prior art keywords
circuit
adhesive layer
electronic circuit
chip
tag
Prior art date
Application number
PCT/JP2003/014827
Other languages
French (fr)
Japanese (ja)
Inventor
Taiga Matsushita
Masateru Yamakage
Yasukazu Nakata
Original Assignee
Lintec Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lintec Corporation filed Critical Lintec Corporation
Priority to DE60332551T priority Critical patent/DE60332551D1/en
Priority to EP03811542A priority patent/EP1564678B1/en
Priority to US10/535,843 priority patent/US7294917B2/en
Publication of WO2004047017A1 publication Critical patent/WO2004047017A1/en

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06KGRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077Constructional details, e.g. mounting of circuits in the carrier
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06KGRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • G06K19/07758Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card arrangements for adhering the record carrier to further objects or living beings, functioning as an identification tag
    • G06K19/0776Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card arrangements for adhering the record carrier to further objects or living beings, functioning as an identification tag the adhering arrangement being a layer of adhesive, so that the record carrier can function as a sticker
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06KGRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/073Special arrangements for circuits, e.g. for protecting identification code in memory
    • G06K19/07309Means for preventing undesired reading or writing from or onto record carriers
    • G06K19/07372Means for preventing undesired reading or writing from or onto record carriers by detecting tampering with the circuit
    • G06K19/07381Means for preventing undesired reading or writing from or onto record carriers by detecting tampering with the circuit with deactivation or otherwise incapacitation of at least a part of the circuit upon detected tampering
    • G06K19/0739Means for preventing undesired reading or writing from or onto record carriers by detecting tampering with the circuit with deactivation or otherwise incapacitation of at least a part of the circuit upon detected tampering the incapacitated circuit being part of an antenna
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06KGRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card

Definitions

  • the present invention breaks the built-in electronic circuit when peeled off after attaching to an article
  • goods have been managed by attaching IC tags to goods such as goods, stored goods, and luggage.
  • IC tags that records information such as manufacturing conditions, purchasing status, price information, and usage status is attached to products, and interrogators are used as necessary.
  • Interrogator is used to check and manage recorded information.
  • the adhesive used for the IC tag attached to an article has insufficient adhesive strength, it may be replaced with another article for some reason such as error or carelessness.
  • it is intentionally replaced with another article.
  • the circuit line has a detour on the surface of the first adhesive layer, and the angle between the tangent of the detour and the tangent of the circuit line at the connection point of the detour and the circuit line is changed.
  • An electronic circuit having an angle of 10 degrees or more and an IC chip connected to the electronic circuit are provided, a second adhesive layer covering them is laminated, and an interface between the base material sheet and the first adhesive layer is further provided.
  • a first adhesive layer is laminated on the surface of the base sheet, and the first adhesive layer is laminated.
  • a structure in which an electronic circuit having planar protrusions extending on the surface of an adhesive layer and a chip connecting to the electronic circuit are provided, and a second adhesive layer covering the electronic circuit and the IC chip is laminated. And an interface between the substrate sheet and the first adhesive layer, which is formed by an electronic circuit and an IC chip.
  • a first adhesive layer is laminated on a surface of a base sheet, and a circuit line has a detour on a surface of the first adhesive layer, and the connection between the detour and the circuit line is performed.
  • An electronic circuit having an angle between the tangent of the detour at the point and the tangent of the circuit line of 10 degrees or more and an IC chip connected to the electronic circuit, and a second contact covering the electronic circuit and the IC chip. It has a structure in which an adhesive layer is laminated, and is partially located at the interface between the base sheet and the first adhesive layer, which corresponds to the circuit surface formed by the electronic circuit and the IC chip. And a release agent layer is provided on the IC chip. Further, the present invention provides the above-described IC tag, wherein at least one detour is provided in the circuit surface at a position where a release agent layer is provided.
  • the present invention provides the above-mentioned IC tag, wherein the planar protrusion is extended and connected to the detour.
  • the present invention provides an electronic circuit in which a first adhesive layer is laminated on a surface of a base sheet, and a planar projection is extended on a surface of the first adhesive layer, and a connection to the electronic circuit.
  • An IC chip is provided, and a second adhesive layer covering the electronic circuit and the IC chip is laminated; and an interface between the base material sheet and the first adhesive layer, wherein the electronic circuit And an IC tag characterized in that a release agent layer is partially provided at a position corresponding to a circuit surface formed by an IC chip.
  • the present invention provides an electronic circuit in which a first adhesive layer is laminated on a surface of a base sheet, and a planar projection is extended on a surface of the first adhesive layer, and a connection to the electronic circuit.
  • the chip has a structure in which a C chip is provided, and a second adhesive layer covering the electronic circuit and the IC chip is laminated, and furthermore, an interface between the base material sheet and the first adhesive layer, It is an object of the present invention to provide an IC tag characterized in that release agent layers are provided at positions corresponding to both ends of a circuit surface formed by a slave circuit and an IC chip.
  • the present invention provides the IC tag according to the above IC tag, wherein at least one planar protrusion is provided in the circuit surface at a position where the release agent layer is provided. .
  • the present invention provides the above-described IC tag, wherein the planar protrusion has an area determined by the following equation.
  • the present invention provides the above IC tag, wherein the release agent layer is provided so as to cover 20 to 90% of the area surrounded by the outer periphery of the circuit surface via the first adhesive layer. It offers IC evenings.
  • the present invention provides an IC tag in which the release sheet is laminated on the surface of the second adhesive layer in the above-described IC tag.
  • FIG. 1 is a schematic sectional view of an example of the IC tag of the present invention.
  • FIG. 2 is a perspective plan view showing an electronic circuit as an example of the IC tag of the present invention.
  • FIG. 3 is a perspective plan view showing another example of an electronic circuit of the IC tag of the present invention.
  • FIG. 4 is a schematic sectional view of an example after the IC tag of the present invention has been peeled off.
  • FIG. 5 is a plan view showing an example of the shapes of circuit lines and detours in the IC tag of the present invention.
  • FIG. 6 is a perspective plan view showing another example of an electronic circuit of the IC tag of the present invention.
  • FIG. 7 is a schematic perspective sectional view of an example of the IC tag of the present invention.
  • FIG. 8 is a perspective plan view showing an electronic circuit as an example of the IC tag of the present invention.
  • FIG. 9 is a perspective plan view showing another example of an electronic circuit of the IC tag of the present invention.
  • FIG. 10 is a schematic perspective sectional view of an example after the IC tag of the present invention is peeled off.
  • FIG. 11 is a plan view showing an example of the shape of a planar projection extending to a circuit line in the IC tag of the present invention.
  • 1 indicates a substrate sheet
  • 2 indicates a first adhesive layer
  • 3 indicates an electronic circuit
  • 4 indicates a circuit line
  • 5 indicates a second adhesive layer
  • 6 indicates a second adhesive layer.
  • 7 indicates an IC chip
  • 7 indicates a release agent layer
  • 8 indicates a detour
  • 9 indicates a planar protrusion
  • 10 indicates a bonding line
  • 11 indicates a release sheet
  • 1 2 indicates an article.
  • 13 indicates a circuit surface
  • 14 indicates a connection point between the circuit line and the detour
  • 15 indicates a tangent of the detour at the connection point between the circuit line and the detour
  • 16 indicates a circuit line. The tangent of the circuit line at the connection point with the detour is shown, and 17 indicates a cut.
  • FIG. 1 and FIG. 7 are schematic cross-sectional views of an example of the IC tag of the present invention.
  • the base sheet 1 is preferably a sheet made of a thermoplastic resin.
  • thermoplastic resin sheets include polyethylene resins such as high-density polyethylene, medium-density polyethylene, and low-density polyethylene; polypropylene resins such as polypropylene; polymethyl_1-pentene / ethylene / cyclic-olefin copolymer; Polyolefin resins such as ethylene-vinyl acetate copolymer, polyethylene terephthalate, polyethylene naphtholate, polyester resins such as polybutylene terephthalate, polyvinyl chloride resin, polyvinyl alcohol resin, polycarbonate Sheets made of various synthetic resins such as copolymer resins, polyamide resins, polyimide resins, fluororesins, or copolymers containing any of these resins, polymer blends, and polymer alloys can be used.
  • a sheet comprising is preferably used.
  • the base sheet 1 may be uniaxially stretched or biaxially stretched.
  • the base sheet 1 may be a single layer or a multilayer of two or more layers of the same type or different types. Further, the base sheet 1 is preferably one having water resistance. If it is water-resistant, it will not break even if it gets wet.
  • the thickness of the substrate sheet 1 is not particularly limited, but may be usually from 10 to 25 Oim, and preferably from 20 to L0zm.
  • the surface of the base sheet 1 may be surface-treated to increase the adhesive strength between the base sheet 1 and the first adhesive layer 2.
  • Examples of the surface treatment method include corona discharge treatment, chemical treatment, and resin coating.
  • Examples of the adhesive used for the first adhesive layer 2 include various adhesives such as a hot-melt adhesive, a pressure-sensitive adhesive, and a thermosetting adhesive.
  • Examples of adhesives include natural rubber adhesives, synthetic rubber adhesives, acrylic resin adhesives, polyester resin adhesives, polyvinyl ether resin adhesives, urethane resin adhesives, and silicone resins. And the like.
  • the synthetic rubber-based adhesive examples include styrene-butadiene rubber, polyisobutylene rubber, isobutylene-isoprene rubber, isoprene rubber, styrene-isoprene block copolymer, styrene-butadiene block copolymer, styrene-ethylene-butylene block copolymer.
  • acrylic resin-based adhesive examples include acrylic acid, methyl acrylate, ethyl acrylate, propyl acrylate, butyl acrylate, monoethyl hexyl acrylate, methyl methacrylate, ethyl methacrylate, and methacrylic. Homopolymers or copolymers such as acid butyl and acrylonitrile are exemplified.
  • the polyester resin-based adhesive is a copolymer of a polyhydric alcohol and a polybasic acid. Examples of the polyhydric alcohol include ethylene glycol, propylene glycol, and vinyldiol.
  • the polybasic acids include terephthalic acid, adipic acid, and maleic acid.
  • polyvinyl ether resin adhesive examples include polyvinyl ether, polyvinyl isobutyl ether, and the like.
  • silicone resin-based adhesive examples include dimethylpolysiloxane. These adhesives can be used alone or in combination of two or more.
  • polyester resin-based adhesives are preferred.
  • the first adhesive layer 2 may contain a tackifier, a softener, an anti-aging agent, a filler, and a coloring agent such as a dye or a pigment, if necessary.
  • a tackifier include a rosin resin, a terpene-6-enol resin, a terpene resin, an aromatic hydrocarbon-modified terpene resin, a petroleum resin, a coumarone'indene resin, a styrene resin, a phenolic resin, and a xylene resin.
  • Softeners include process oils, liquid rubbers, plasticizers, and the like. Fillers include silica, talc, clay, calcium carbonate, and the like.
  • the thickness of the first adhesive layer 2 is not particularly limited, but may be usually 1 to 100 ⁇ m, and preferably 3 to 50 zm.
  • the interface between the base sheet 1 and the first adhesive layer 2 is partially located at a position corresponding to the circuit surface 13 formed by the electronic circuit 3 and the IC chip 6.
  • An exfoliating agent layer 7 is provided.
  • Two or more release agent layers 7 are provided at intervals.
  • the shape and size of the release agent layer 7 and the interval between the release agent layers 7 are not particularly limited, and may be various shapes, sizes, and intervals.
  • the release agent layer 7 may be provided so as to cover the entire surface at positions corresponding to both ends of the circuit surface 13; As shown in FIG. 3, a release agent layer 7 may be further provided at a position corresponding to an intermediate portion of the circuit surface 13, but a portion not covered by the release agent layer 7 is left. In addition, as shown in FIG. 6, the entire surface at positions corresponding to both ends of the circuit surface 13 may not be covered, and some portions may not be covered. Further, the release agent layer ⁇ ⁇ may be provided at a position corresponding to an intermediate portion of the circuit surface 13 without being provided at positions corresponding to both ends of the circuit surface 13.
  • the first adhesive layer 2 is directly laminated on the surface of the base material sheet 1 at the position where the release agent layer 7 is not provided, and at the position where the release agent layer ⁇ is located. , The first adhesive layer 2 is directly laminated on the release agent layer 7.
  • the first adhesive layer 2 is peeled off at the interface with the release agent layer 7, and the release agent layer 7 is removed.
  • the electronic circuit 3 is cut off at the interface between the article 1 2 and the second adhesive layer 5 or inside the second adhesive layer 5, and the electronic circuit 3 remains adhered to the first adhesive layer 2, The electronic circuit 3 is cut off together with the base sheet 1.
  • the release agent layer 7 is preferably provided so as to cover 20 to 90% of an area surrounded by the outer periphery of the circuit surface 13 via the first adhesive layer 2, and 40 to 80% is provided. It is particularly preferable to be provided so as to cover.
  • the release agent layer 7 is preferably provided so as to protrude beyond the outer periphery of the circuit surface 13, and the protruding width is not particularly limited, but is preferably 1 mm or more.
  • the shape of the release agent layer 7 is preferably a triangle, a quadrangle, a pentagon or more polygon, an ellipse, a circle, or the like (see FIGS. 2, 3, and 6).
  • the shapes of the two release agent layers 7 may be the same or different.
  • the two release agent layers 7 are completely separated and independent, but may be partially connected.
  • Examples of the release agent used in the release agent layer 7 include release agents such as a silicone resin, a long-chain alkyl resin, and a fluorine resin.
  • the thickness of the release agent layer 7 is not particularly limited, but is preferably from 0.01 to 5 ⁇ m, and particularly preferably from 0.03 to 1 ⁇ m.
  • the electronic circuit 3 is provided on the surface of the first adhesive layer 2.
  • the electronic circuit 3 includes a circuit line 4 formed of a conductive material.
  • the conductive material include a metal simple substance such as a metal foil, a vapor-deposited film, and a thin film formed by sputtering. Gold, silver, nickel, copper, aluminum, etc. can be used as the metal simple substance. Further, as the conductive substance, a conductive paste in which metal particles such as gold, silver, nickel, and copper are dispersed in a binder can be used.
  • the average particle size of the metal particles is preferably from 1 to 15 ⁇ m, and particularly preferably from 2 to 10 ⁇ m.
  • the binder include polyester resin, polyurethane resin, epoxy resin, and phenol resin.
  • the thickness of the circuit line 4 constituting the sub-circuit is not particularly limited, but is 5 to 50 m in the case of metal foil, and 0.01 to 1 in the case of metal film by vapor deposition and sputtering. In the case of a conductive paste, the thickness is preferably 5 to 30 ⁇ m.
  • the width of the circuit line 4 is not particularly limited, but is preferably from 0.1 to 10 mm, particularly preferably from 0.1 to 3 mm.
  • a metal foil is bonded to the base sheet 1 with an adhesive, and the metal foil is etched to remove portions other than the circuit.
  • the etching process can be performed by a process similar to a normal etching process.
  • the formation of the electronic circuit 3 on the surface of the first adhesive layer 2 can also be performed by attaching a conductive paste to the shape of the electronic circuit 3 by means of printing, coating, or the like.
  • Examples of the shape of the electronic circuit 3 include those shown in FIGS. 2 and 3.
  • FIGS. 2 and 3 show that a circuit line 4 composed of a single conductive material line is spaced from the outer periphery of the rectangular base sheet 1 in a doubly annular manner at a predetermined interval.
  • the electronic circuit 3 may be arranged in a doubly annular shape as shown in FIGS. 2 and 3, but may be a single to ninefold annular shape, or may be a ⁇ -or more annular shape. Good.
  • the circuit line 4 of the electronic circuit 3 has a bypass 8.
  • the circuit line 4 having the detour 8 may be the innermost circuit line 4, the outermost circuit line 4, or any intermediate circuit line 4. .
  • the angle between the tangent 15 of the detour 8 and the tangent 16 of the circuit 4 at the connection point 14 between the detour 8 and the circuit line 4 is described as an angle ⁇ ⁇ ⁇ ⁇ in FIG.
  • the angle ⁇ is 10 degrees or more, preferably 45 degrees or more, and particularly preferably 80 degrees or more.
  • the upper limit of the angle 0 may be less than 180 degrees. With such a structure, as shown in FIG. 4, the portion of the detour 8 where the release agent layer 7 is located remains bonded to the first adhesive layer 2 and the second adhesive layer 5.
  • the first adhesive layer 2 is peeled off at the interface with the release agent layer 7, and where the release agent layer 7 is not provided, the first adhesive layer 2 is cut off inside the second adhesive layer 5, and the electronic circuit is cut off. 3 is peeled off together with the base sheet 1 while being adhered to the first adhesive layer 2, and the electronic circuit 3 is cut.
  • the shape of the detour 8 is not particularly limited, and a part of the outer line such as a circle and an ellipse is missing. Shape, shape missing one side of triangle outer shape, shape missing one side of square outer shape such as square, rectangle, diamond, trapezoid, etc., shape missing one side of polygonal outer shape of pentagon or more, etc. There are various shapes.
  • the size of the detour 8 may be smaller than the empty space surrounded by the electronic circuit. If it is provided on the circuit line 4, it may be smaller than the size of the IC chip.
  • the distance from the furthest part of the detour 8 farthest from the circuit line 4 to the circuit line 4 is preferably 2 mm or more.
  • the thickness of the detour 8 is not particularly limited, but is the same as the thickness of the electronic circuit, and the preferred range is also the same.
  • the line width of the detour 8 is not particularly limited, but is preferably from 0.11 to 10 mm, particularly preferably from 0.10 to 3 mm.
  • the number of the detours 8 is preferably 1 to 10, more preferably 1 to 5.
  • the plurality of detours 8 may be the same or different in shape and / or size.
  • circuit wire 4 has a planar protrusion 9 extending therefrom.
  • the shape of the planar protrusion 9 is preferably a target shape such as a square, a regular hexagon, a regular octagon, a regular decagon, a polygonal shape, a circular shape, or a shape similar thereto.
  • the area of the planar projection 9 is determined by the following equation: S ⁇ (2W) 2 (where S is the area of the planar projection and W is the line width of the circuit line adjacent to the planar projection).
  • S is the area of the planar projection and W is the line width of the circuit line adjacent to the planar projection.
  • S (4W) 2 is particularly preferable.
  • the upper limit of the area of the planar projection 9 is preferably 10% or less, more preferably 5% or less, and particularly preferably 3% or less, with respect to the area of the empty portion surrounded by the electronic circuit.
  • the thickness of the planar projection 9 is the same as the thickness of the electronic circuit, and the preferred range is also the same.
  • the planar projection 9 may be directly extended to the bypass 8 of the circuit line 4 of the electronic circuit 3, or may be planar with the bypass 8 of the circuit line 4.
  • the connecting line 10 may be connected and extended between the protrusions 9.
  • the detour 8 or the flat protrusion 9 adheres the first adhesive layer 2 and the second adhesive layer 5 where the release agent layer 7 is located.
  • the first adhesive layer 2 is peeled off at the interface with the release agent layer 7, and when there is no release agent layer 7, the interface between the article 12 and the second adhesive layer 5 Alternatively, the electronic circuit 3 is cut off inside the second adhesive layer 5, the electronic circuit 3 is peeled off together with the base sheet 1 while being adhered to the first adhesive layer 2, and the electronic circuit 3 is cut.
  • the planar projection 9 may be directly extended to the circuit line of the electronic circuit, or a coupling line 10 may be provided between the circuit line and the planar projection 9. May be connected and extended. By doing so, even if the antenna is not cut off at the interface of the release agent layer, some of the planar protrusions are peeled off while being adhered to the base sheet side as shown in FIG. Therefore, the antenna function is destroyed.
  • the flat protrusion 9 may extend to the circuit wire 4 of the innermost ring of the electronic circuit or may extend to the circuit wire 4 of the outermost ring. Any of the circuit lines 4 on the route 4 may be extended.
  • the planar protrusion 9 extends to the intermediate circuit line 4, the outer circuit line 4 is formed avoiding the planar protrusion 9.
  • the number of the planar projections 9 is preferably 1 to 10, and particularly preferably 1 to 5.
  • the material of the detour 8 is the same as the material of the circuit line 4 of the electronic circuit, and is preferably integrated.
  • the material of the planar projection 9 is such that the planar projection 9 does not peel off from the circuit line 4, the detour 8 or the coupling line 10 of the electronic circuit when the IC ring of the present invention is peeled off.
  • Any material may be used, for example, a conductive material that is a material of the electronic circuit, various resins such as acrylic resin and polyester resin, etc., and the same material as the circuit wire 4 or the coupling wire 10 of the electronic circuit. It is preferable from the viewpoint of production, and an integrated one is particularly preferable.
  • the material of the bonding wire 10 is such that the bonding wire 10 does not peel off from the detour 8 of the circuit wire 4 and the planar projection 9 of the electronic circuit when the IC tag of the present invention is peeled off.
  • a conductive material that is a material of the electronic circuit may be used, and the same material as the circuit line 4 or the coupling line 10 of the electronic circuit is particularly preferable.
  • planar projection 9 or the detour 8 When the planar projection 9 or the detour 8 is provided, it may be provided in a place where the release agent layer 7 is not provided, but at least one of the planar projection 9 or the detour 8 is peeled off in the circuit plane. It is particularly preferable to provide it at the place where the agent layer 7 is located.
  • the planar protrusion 9 when the planar protrusion 9 is extended in the detour 8, at least one of the detours 8 in which the planar protrusion 9 is extended, at least ⁇ , the surface of the release agent layer 7 in the circuit surface. Preferably, it is provided at a certain place.
  • an electronic circuit a planar projection without providing a detour 8 or a coupling line 10 in the circuit line 4 of FIG. 9 can be extended directly to the electronics, circuit 3 ⁇ circuit line 4.
  • the planar projection 9 may be provided at a location where the release agent layer 7 is not provided, but at least one of the planar projections 9 is provided at a location where the release agent layer 7 exists in the circuit plane. Is preferred.
  • the number of the planar projections 9 is preferably 1 to: L 0, and particularly preferably 1 to 5.
  • the plurality of planar projections 9 may have the same shape and / or size, and may be different from each other, or may be different.
  • the JC chip 6 is connected to both ends of the electronic circuit 3.
  • the JC chip 6 may be provided inside the electronic circuit 3, may be provided outside the electronic circuit 3, or may be provided above the electronic circuit 3.
  • the terminals of the outermost and innermost electronic circuits 3 do not short-circuit with the ring heater circuit 3 without jumping over. It is preferable that the drawer (jumper circuit) extend inside or outside the electronic circuit 3 and be connected to the IC chip 6.
  • the method of forming the jumper circuit is as follows. From the end of the electronic circuit 3, traverse the portion of the ring-shaped electronic circuit 3, mark the insulating ink linearly by screen printing or the like, and conduct the conductive ink on the printed insulating ink.
  • the conductive paste is printed in a line by screen printing or the like, A method of forming the conductive circuit line 4 is exemplified. Examples of the conductive paste include those described above. Examples of the insulating ink include a photo-curable ink such as an ultraviolet curing type ink.
  • a method of connecting the IC chip 6 to the end of the electronic circuit 3 there is a method of connecting the IC chip 6 to the surface of the end of the electronic circuit 3 via an anisotropic conductive film by a flip chip bonding method.
  • a wire pump is provided on the electrode portion of the IC chip 6, and the surface of the IC chip 6 where the wire bumps are located is pressed on the anisotropic conductive film coated on the terminal surface of the heater circuit 3.
  • the second adhesive layer .5 is laminated so as to cover the surface of the first adhesive layer 2 where the electronic circuit 3 is not provided, the electronic circuit 3 and the IC chip 6. . '':,.: '
  • the adhesive used for the second adhesive layer 5 include various adhesives such as a hot-melt adhesive, a pressure-sensitive adhesive, and a thermosetting adhesive.
  • the type of the adhesive include: the same as the adhesive used for the first adhesive layer 2 described above. These adhesives can be used alone or in combination of two or more. Among these adhesives, a pressure-sensitive adhesive is preferable, and an acrylic pressure-sensitive adhesive is particularly preferable.
  • the surface of the second adhesive layer 5 is preferably flat.
  • the thickness of the second adhesive layer 5 is not particularly limited, the thickness is different between a place where the electronic circuit 3 and the T Ci chip 6 are covered and a place where the first adhesive layer 2 is covered. It is usually 10 to 100 / m, preferably 15 to 50 m.
  • the surface of the second adhesive layer 5 may be covered with a release sheet 11.
  • any release sheet may be used as the release sheet 11.
  • films made of various resins such as polyethylene terephthalate, polyethylene terephthalate, polyethylene, polypropylene, ren, and polyarylate, and polyethylene laminate — Paper, polypropylene-laminated paper, clay-coated paper, resin-coated paper, glass paper, and other various paper materials.
  • the surface of this base material that is to be bonded to the second adhesive layer 5 is subjected to a peeling treatment according to necessity: What was done can be used.
  • a 3.5-meter-thick copper foil was heat-pressed on the surface of the first adhesive layer 2 with a 100 ° C. heat roll.
  • a ten-fold rectangular circuit wire 4 (antenna) having a long side of 45 mm and a short side of 15 mm and the innermost ring
  • the resist ink was printed (line width: 0.15 mm) on the circuit line 4 in the form of a detour 8 by screen printing. This was treated with a ferric chloride solution to remove the portions other than the loop circuit line 4 and the bypass 8.
  • the etching resist ink was removed with an alkaline aqueous solution to form an electronic circuit 3 provided with the same detour 3 as in FIG.
  • the detour 8 and the tangent angle 0 are 5 mm long, 7 'mm wide, and 90 ° at 0 ° for a detour 8 that lacks one long side of the rectangular outer peripheral line.
  • a wire bump is provided on the electrode part of the IC chip (manufactured by Philips, product name "I / CODE”) 6 using a gold wire, and this IC chip 6 is attached to an anisotropic conductive film (manufactured by Sony Chemical Co., Ltd.).
  • the circuit was connected to both ends of the circuit using the flip-chip bonding method under the name “FP2322D”).
  • the release sheet with the second adhesive layer 5 and the second adhesive layer 5 of 11 were attached to the entire surface of the sheet 1 on which the electronic circuit 3 and the IC chip 6 were provided.
  • the adhesive layer 2, the electronic circuit 3 and the IC chip 6 were covered with the second adhesive layer 5 to prepare an IC chip.
  • a non-contact transmission / reception test was performed on the obtained ⁇ tag, and transmission / reception was performed normally.
  • the peeling seed 11 of this IC tag was peeled off, and the IC tag was affixed to a polypropylene plate. Twenty-four hours later, from the end of this IC tag, make a cut in the second adhesive shoulder with a 5 mm ⁇ knife from the one end of the IC tag, and cut 17 with this finger and peel off the polypropylene resin plate.
  • Layer 7 Covered electronic circuit S & 3 part is polypropylene Remaining on the resin plate, other non-stripping agent If part is polyethylenetere tere of base sheet 1;., : Phthalate layer, polypropylene Peeled from the resin plate. The electronic circuit 3 was cut off due to the separation, and a non-contact transmission / reception test was performed.
  • the shape of the release agent layer 7 is located at both ends of the circuit surface.
  • the angle of the hypotenuse of the right triangle is 45 degrees
  • the width of the uncoated portion is 3 mm
  • the right angle at both ends of the circuit surface is the square and the center of the circuit surface
  • the area enclosed by the outer periphery of the electronic circuit 3 and the IC chip 6 covered by the parallelogram is approximately 70% of the area enclosed by the outer periphery of the electronic circuit.
  • the shape and size of the detour 8 are the same as those in the first embodiment.
  • the size of the planar protrusion 9 is a circle having a diameter of 2 mm, a thickness of 35 ⁇ m, and a length of the coupling line 10.
  • the width was 0.1 mm, and the thickness was 35 m.
  • transmission / reception was performed normally.
  • a peeling / cutting test was performed on 30 of the obtained IC tags in the same manner as in Example 1. All were cut.
  • the planar projection 9 was directly extended to the circuit line 4 without providing the detour 8 and the planar projection 9 and the release agent layer 7 were formed as shown in FIG. I created an IC-tag.
  • the shape of the release agent layer 7 is as follows: the angle of the hypotenuse is 45 degrees, the width of the coated part is 3 mm, and the outer periphery of the electronic circuit 3 is covered by two pentagons. About 60% of the enclosed area, the length between the edge of the pentagon and the outer edge of the base sheet 1 was 1 mm.
  • the size of the planar projection 9 is a circle having a diameter of 2 mm and a square having a side of 2 mm, the thickness is 35 m, the length of the coupling wire 10 is 0, 5 mm, the width is 0.1 mm, and the thickness is 0.1 mm. It was 35 m.
  • a non-contact transmission / reception test was performed on the obtained IC tag, and transmission / reception was performed normally.
  • a peeling / cutting test was performed on 3.0 rogue IC tags in the same manner as in Example 1. Taro. IC evening 30 pieces were cut.
  • a polyester-based hot-melt adhesive (Toyobo Co., Ltd., product name “Pai-Kin 30S S”) is dried on the surface of the release agent layer 7 and the base material seed 1 all over the gravure cup. To a thickness of 3 m.
  • an electro-deposited copper foil having a thickness of 35 ⁇ m was heat-pressed on the surface of the first adhesive layer 2 with a 100 ° C. heat-sealing roll.
  • a ten-fold annular circuit wire (antenna) having a long side of 45 mm and a short side of 15 mm and a planar projection 9 and The etching resist ink was printed (line width: 0.15 mm) on the bonding lines 10 by screen printing.
  • the portion of the electronic circuit 3 covered with the release agent layer 7 remains on the polypropylene resin plate, and the other non-release agent layer portion is a polyethylene terephthalate sheet of #sheet 1; It was peeled off from the resin plate or peeled off at the planar projection. : The electronic circuit 3 was cut off due to the separation, and a non-contact transmission / reception test could not be performed (peel-off test).
  • Peripheral protrusion 9 and release agent layer ⁇ (periphery of electronic circuit covered with two 0-gons ::: area enclosed by: electronic circuit and]: about 75% of area enclosed by outer periphery of C chip ) was formed as in Example 9 in the same manner as in Example 1 to produce an IC tag.
  • the size of the planar projection 9 was a square with a diameter of 2 mm and a thickness of 35 m.
  • 'A contactless transmission / reception test was performed on the obtained IC tag, and transmission / reception was successful.
  • An I: C tag was prepared in the same manner as in Example 2, except that the shape of the planar projection 9 was changed as shown in FIG.
  • the size of the planar projection 9 was 2 mm in diameter, and the thickness was 35 mm.
  • transmission / reception was normally performed.
  • a peeling / cutting test was performed on 10 of the obtained IC dougs as in Example 1; however, a peeling / cutting test was performed in the same manner as in Example 1. disconnected.
  • ..IC tag was created in the same manner as in Example 1 except that the detour & was not provided. When a non-contact transmission / reception test was performed on the obtained IC tag, transmission / reception was performed normally.
  • the IC tag of the present invention can be used as a tag for managing articles such as merchandise, stored goods, and luggage.

Abstract

A first adhesive layer is formed on a base sheet. On the first adhesive layer, an electronic circuit having a circuit line and a bypath line, and/or an electronic circuit having a planar projection extended, and an IC chip connected to the electronic circuit are fabricated. The angle formed by the tangent of the bypath line at the connection between the bypath line and the circuit line and the tangent of the circuit line at the connection is 10 degrees or greater. A second adhesive layer covers the electronic circuit and IC chip. A releasing agent layer is partly formed at the interface between the base sheet and the first adhesive layer which the interface is the circuit surface where the electronic circuit and the IC chip are provided. Thus, an IC tag is produced.

Description

明細書  Specification
I Cタグ 技術分野 Technical field of IC tag
本発明は、 物品に貼付後に剥がした場合、 内蔵している電子回路を破損する The present invention breaks the built-in electronic circuit when peeled off after attaching to an article
I Cタグに関する。 背景技術 Regarding IC tag. Background art
近年、 商品、 貯蔵物、 荷物などの物品に I Cタグを貼り付けて、 物品を管理す ることが行われている。 例えば、 商品に製造条件、 仕入れ状況、 価格情報、 使用 状況などの情報が記録された I Cタグを貼付し、 必要に応じてインテロゲ一ター In recent years, goods have been managed by attaching IC tags to goods such as goods, stored goods, and luggage. For example, an IC tag that records information such as manufacturing conditions, purchasing status, price information, and usage status is attached to products, and interrogators are used as necessary.
(質問器) などにより、 記録情報を確認して、 管理することが行われている。 しかし、 物品に貼られた I Cタグに使用されている粘着剤の粘着力が十分でな い場合などに、 過誤、 不注意などの何らかの原因で別の物品に貼り替わることが ある。 また、 故意に別の物品に貼りかえる場合などもある。 (Interrogator) is used to check and manage recorded information. However, when the adhesive used for the IC tag attached to an article has insufficient adhesive strength, it may be replaced with another article for some reason such as error or carelessness. In addition, there are cases where it is intentionally replaced with another article.
このような事態になると、 もはや物品管理を正確に行うことができなくなる。 従来の I Cタグとしては、 タグ表面に貼り合わせた基材が、 改ざんを行う際、 表面基材が層内破壊を起こし偽造防止効果を高める技術が記載されている (特開 平 1 0— 1 7 1 9 6 2号公報)。  In such a situation, it is no longer possible to accurately manage goods. As a conventional IC tag, a technology has been described in which, when a base material bonded to the tag surface is tampered with, the surface base material is destructed in the layer to enhance the effect of preventing forgery (Japanese Patent Laid-Open No. 10-1). No. 7,196,2).
しかし、 物品に貼付された I Cタグの接着剤層と物品の界面にカッターなどで 切り込みを入れ、 その切り込みに指などを差し込んで I Cタグの端を摘み、 I C タグを剥がすと、 電子回路面を破壊することなく、 電子回路面と表面基材とを簡 単に剥がすことができてしまうという問題点がある。 発明の開示  However, when a cut is made with a cutter or the like at the interface between the adhesive layer of the IC tag attached to the article and the article, a finger or the like is inserted into the cut, the end of the IC tag is picked, and the IC tag is peeled off. There is a problem that the electronic circuit surface and the surface substrate can be easily peeled off without breaking. Disclosure of the invention
上記問題点を解決する方法として、 別の物品に貼りかえると、 I Cタグの機能 が損なわれるようにして、 物品の管理を正確に行うことが求められている。 本発明者は、 上記課題を解決するために鋭意検討した結果、 基材シートに第 1 の接着剤層を積層し、 その第 1の接着剤層の表面に、 回路線が迂回路を有し、 該 迂回路と回路線の連結点における迂回路の接線と回路線の接線の角度が 1 0度以 上である電子回路及び該電子回路に接続する I Cチップを設け、 それらを覆う第 2の接着剤層を積層し、 さらに、 基材シートと第 1の接着剤層の界面に、 電子回 路と I Cチップで形成される回路面に相当する位置に部分的に剥離剤層を設ける ことにより、 また、 基材シートの表面に第 1の接着剤層を積層し、 該第 1の接着 剤層の表面に平面状突起が延設されている電子回路及び該電子回路に接続するェ Cチヅプを設け、 該電子回路及び I Cチップを覆う第 2の接着剤層を積層してい る構造を有し、 さらに基材シートと第 1の接着剤層の界面であって、 電子回路と I cチップで形成される回路面に相当する位置に部分的に剥離剤層を設けること により、 上記課題を解決できることを見い出し、 本発明を完成するに至った。 すなわち、 本発明は、 基材シートの表面に第 1の接着剤層が積層され、 該第 1 の接着剤層の表面に、 回路線が迂回路を有し、 該迂回路と回路線の連結点におけ る迂回路の接線と回路線の接線の角度が 1 0度以上である電子回路及び該電子回 路に接続する I Cチップが設けられ、 該電子回路及び I Cチップを覆う第 2の接 着剤層が積層されている構造を有し、 さらに基材シ一トと第 1の接着剤層の界面 であって、 電子回路と I Cチップで形成される回路面に相当する位置に部分的に 剥離剤層が設けられていることを特徴とする I C夕グを提供するものである。 また、 本発明は、 上記 I Cタグにおいて、 迂回路が、 前記回路面内であって剥 離剤層の設けられている位置に少なくとも 1つ設けられている I Cタグを提供す るものである。 As a method of solving the above problems, it is required that the function of the IC tag be impaired if it is put on another article, and that the article be managed accurately. The present inventors have conducted intensive studies to solve the above-mentioned problems, and as a result, The circuit line has a detour on the surface of the first adhesive layer, and the angle between the tangent of the detour and the tangent of the circuit line at the connection point of the detour and the circuit line is changed. An electronic circuit having an angle of 10 degrees or more and an IC chip connected to the electronic circuit are provided, a second adhesive layer covering them is laminated, and an interface between the base material sheet and the first adhesive layer is further provided. By providing a release agent layer partially at a position corresponding to a circuit surface formed by the electronic circuit and the IC chip, a first adhesive layer is laminated on the surface of the base sheet, and the first adhesive layer is laminated. A structure in which an electronic circuit having planar protrusions extending on the surface of an adhesive layer and a chip connecting to the electronic circuit are provided, and a second adhesive layer covering the electronic circuit and the IC chip is laminated. And an interface between the substrate sheet and the first adhesive layer, which is formed by an electronic circuit and an IC chip. It has been found that the above problems can be solved by partially providing a release agent layer at a position corresponding to the circuit surface, and the present invention has been completed. That is, according to the present invention, a first adhesive layer is laminated on a surface of a base sheet, and a circuit line has a detour on a surface of the first adhesive layer, and the connection between the detour and the circuit line is performed. An electronic circuit having an angle between the tangent of the detour at the point and the tangent of the circuit line of 10 degrees or more and an IC chip connected to the electronic circuit, and a second contact covering the electronic circuit and the IC chip. It has a structure in which an adhesive layer is laminated, and is partially located at the interface between the base sheet and the first adhesive layer, which corresponds to the circuit surface formed by the electronic circuit and the IC chip. And a release agent layer is provided on the IC chip. Further, the present invention provides the above-described IC tag, wherein at least one detour is provided in the circuit surface at a position where a release agent layer is provided.
また、 本発明は、 上記 I Cタグにおいて、 平面状突起が、 迂回路に延接されて いる I Cタグを提供するものである。  Further, the present invention provides the above-mentioned IC tag, wherein the planar protrusion is extended and connected to the detour.
また、 本発明は、 基材シートの表面に第 1の接着剤層が積層され、 該第 1の接 着剤層の表面に平面状突起が延設されている電子回路及び該電子回路に接続する Further, the present invention provides an electronic circuit in which a first adhesive layer is laminated on a surface of a base sheet, and a planar projection is extended on a surface of the first adhesive layer, and a connection to the electronic circuit. Do
I Cチップが設けられ、 該電子回路及び I Cチップを覆う第 2の接着剤層が積層 されている構造を有し、 さらに基材シートと第 1の接着剤層の界面であって、 電 子回路と I Cチップで形成される回路面に相当する位置に部分的に剥離剤層が設 けられていることを特徴とする I Cタグを提供するものである。 また、 本発明は、 基材シートの表面に第 1の接着剤層が積層され、 該第 1の接 着剤層の表面に平面状突起が延設されている電子回路及び該電子回路に接続する ェ Cチップが設けられ、 該電子回路及び I Cチヅプを覆う第 2の接着剤層が積層 されている構造を有し、 さらに基材シートと第 1の接着剤層の界面であって、 電 子回路と I Cチップで形成される回路面の両端部に相当する位置に剥離剤層が設 けられていることを特徴とする I Cタグを提供するものである。 An IC chip is provided, and a second adhesive layer covering the electronic circuit and the IC chip is laminated; and an interface between the base material sheet and the first adhesive layer, wherein the electronic circuit And an IC tag characterized in that a release agent layer is partially provided at a position corresponding to a circuit surface formed by an IC chip. Further, the present invention provides an electronic circuit in which a first adhesive layer is laminated on a surface of a base sheet, and a planar projection is extended on a surface of the first adhesive layer, and a connection to the electronic circuit. The chip has a structure in which a C chip is provided, and a second adhesive layer covering the electronic circuit and the IC chip is laminated, and furthermore, an interface between the base material sheet and the first adhesive layer, It is an object of the present invention to provide an IC tag characterized in that release agent layers are provided at positions corresponding to both ends of a circuit surface formed by a slave circuit and an IC chip.
また、 本発明は、 上記 I Cタグにおいて、 平面状突起が、 前記回路面内であつ て剥離剤層の設けられている位置に少なくとも 1つ設けられている I c夕グを提 供するものである。  Further, the present invention provides the IC tag according to the above IC tag, wherein at least one planar protrusion is provided in the circuit surface at a position where the release agent layer is provided. .
また、 本発明は、 上記 I Cタグにおいて、 平面状突起が、 下記式で求められる 面積を有する I Cタグを提供するものである。  Further, the present invention provides the above-described IC tag, wherein the planar protrusion has an area determined by the following equation.
Figure imgf000005_0001
Figure imgf000005_0001
(式中、 Sは平面状突起の面積であり、 Wは平面状突起に隣接する回路線の線幅 である。)  (Where S is the area of the planar protrusion, and W is the line width of the circuit line adjacent to the planar protrusion.)
また、 本発明は、 上言己 I Cタグにおいて、 剥離剤層が、 第 1の接着剤層を介し て回路面の外周で囲まれる面積の 2 0〜9 0 %を覆うように設けられている I C 夕グを提供するものである。  Further, the present invention provides the above IC tag, wherein the release agent layer is provided so as to cover 20 to 90% of the area surrounded by the outer periphery of the circuit surface via the first adhesive layer. It offers IC evenings.
また、 本発明は、 上記 I C夕グにおいて、 第 2の接着剤層の表面に剥離シート が積層されている I Cタグを提供するものである。  Further, the present invention provides an IC tag in which the release sheet is laminated on the surface of the second adhesive layer in the above-described IC tag.
本発明の I Cタグは、 物品に貼付された後に剥がした場合、 内蔵している電子 回路を確実に破損することができる。 図面の簡単な説明  When the IC tag of the present invention is peeled off after being attached to an article, the built-in electronic circuit can be surely damaged. BRIEF DESCRIPTION OF THE FIGURES
第 1図は、 本発明の I Cタグの一例の概略断面図である。  FIG. 1 is a schematic sectional view of an example of the IC tag of the present invention.
第 2図は、 本発明の I Cタグの一例の電子回路を示す透視平面図である。 第 3図は、本発明の I Cタグの他の一例の電子回路を示す透視平面図である。 第 4図は、 本発明の I Cタグが剥がされた後の一例の概略断面図である。 第 5図は、 本発明の I Cタグにおける回路線及び迂回路の形状の一例の平面 図である。 FIG. 2 is a perspective plan view showing an electronic circuit as an example of the IC tag of the present invention. FIG. 3 is a perspective plan view showing another example of an electronic circuit of the IC tag of the present invention. FIG. 4 is a schematic sectional view of an example after the IC tag of the present invention has been peeled off. FIG. 5 is a plan view showing an example of the shapes of circuit lines and detours in the IC tag of the present invention.
第 6図は、本発明の I Cタグの他の一例の電子回路を示す透視平面図である。 第 7図は、 本発明の I Cタグの一例の概略透視断面図である。  FIG. 6 is a perspective plan view showing another example of an electronic circuit of the IC tag of the present invention. FIG. 7 is a schematic perspective sectional view of an example of the IC tag of the present invention.
第 8図は、 本発明の I Cタグの一例の電子回路を示す透視平面図である。 第 9図は、本発明の I Cタグの他の一例の電子回路を示す透視平面図である。 第 1 0図は、 本発明の I Cタグが剥がされた後の一例の概略透視断面図であ る。  FIG. 8 is a perspective plan view showing an electronic circuit as an example of the IC tag of the present invention. FIG. 9 is a perspective plan view showing another example of an electronic circuit of the IC tag of the present invention. FIG. 10 is a schematic perspective sectional view of an example after the IC tag of the present invention is peeled off.
第 1 1図は、 本発明の I Cタグにおける回路線に延接された平面状突起の形 状の一例の平面図である。  FIG. 11 is a plan view showing an example of the shape of a planar projection extending to a circuit line in the IC tag of the present invention.
図中、 1は基材シートを示し、 2は第 1の接着剤層を示し、 3は電子回路を示 し、 4は回路線を示し、 5は第 2の接着剤層を示し、 6は I Cチップを示し、 7 は剥離剤層を示し、 8は迂回路を示し、 9は平面状突起を示し、 1 0は結合線を 示し、 1 1は剥離シートを示し、 1 2は物品を示し、 1 3は回路面を示し、 1 4 は回路線と迂回路との連結点を示し、 1 5は回路線と迂回路との連結点における 迂回路の接線を示し、 1 6は回路線と迂回路との連結点における回路線の接線を 示し、 1 7は切り込みを示す。 発明を実施するための好ましい態様  In the figure, 1 indicates a substrate sheet, 2 indicates a first adhesive layer, 3 indicates an electronic circuit, 4 indicates a circuit line, 5 indicates a second adhesive layer, and 6 indicates a second adhesive layer. 7 indicates an IC chip, 7 indicates a release agent layer, 8 indicates a detour, 9 indicates a planar protrusion, 10 indicates a bonding line, 11 indicates a release sheet, and 1 2 indicates an article. , 13 indicates a circuit surface, 14 indicates a connection point between the circuit line and the detour, 15 indicates a tangent of the detour at the connection point between the circuit line and the detour, and 16 indicates a circuit line. The tangent of the circuit line at the connection point with the detour is shown, and 17 indicates a cut. BEST MODE FOR CARRYING OUT THE INVENTION
本発明の I Cタグを図面に基づいて説明する。 第 1図及び第 7図には、 本発明 の I Cタグの一例の概略断面図が示されている。  The IC tag of the present invention will be described with reference to the drawings. FIG. 1 and FIG. 7 are schematic cross-sectional views of an example of the IC tag of the present invention.
基材シート 1は、 好ましくは熱可塑性樹脂からなるシートである。 熱可塑性樹 脂のシートとしては、 例えば、 高密度ボリエチレン、 中密度ポリエチレン、 低密 度ポリェチレン等のポリエチレン系樹脂、 ポリプロピレン等のポリプロピレン系 樹脂、 ポリメチル _ 1一ペンテン /ェチレン /環状ォレフィン共重合体、 ェチレ ン一酢酸ビニル共重合体などのポリオレフィン系樹脂、 ポリエチレンテレフタレ —ト、 ポリエチレンナフ夕レート、 ポリブチレンテレフ夕レートなどのポリエス テル系樹脂、 ポリ塩化ビニル樹脂、 ポリビニルアルコール樹脂、 ポリカーボネー ト樹脂、 ポリアミド樹脂、 ポリイミド樹脂、 フッ素系樹脂、 またはこれらのいず れかを含む共重合体、 ポリマーブレンド、 ポリマーァロイなどの各種合成樹脂か らなるシートが使用できるが、 特に、 ポリエステル系樹脂から成るシートが好ま しく用いられる。 The base sheet 1 is preferably a sheet made of a thermoplastic resin. Examples of thermoplastic resin sheets include polyethylene resins such as high-density polyethylene, medium-density polyethylene, and low-density polyethylene; polypropylene resins such as polypropylene; polymethyl_1-pentene / ethylene / cyclic-olefin copolymer; Polyolefin resins such as ethylene-vinyl acetate copolymer, polyethylene terephthalate, polyethylene naphtholate, polyester resins such as polybutylene terephthalate, polyvinyl chloride resin, polyvinyl alcohol resin, polycarbonate Sheets made of various synthetic resins such as copolymer resins, polyamide resins, polyimide resins, fluororesins, or copolymers containing any of these resins, polymer blends, and polymer alloys can be used. A sheet comprising is preferably used.
基材シート 1は、 一軸延伸または二軸延伸されたものであってもよい。 基材シ ート 1は、 単層であってもよいし、 同種又は異種の 2層以上の多層であってもよ い。 また、 基材シート 1は、 耐水性のあるものが好ましい。 耐水性があると、 水 に濡れても破れる等の破損が生じることがない。  The base sheet 1 may be uniaxially stretched or biaxially stretched. The base sheet 1 may be a single layer or a multilayer of two or more layers of the same type or different types. Further, the base sheet 1 is preferably one having water resistance. If it is water-resistant, it will not break even if it gets wet.
基材シート 1の厚みは、特に制限ないが、通常 1 0〜2 5 O imであればよく、 好ましくは 2 0〜: L 0 0 zmである。  The thickness of the substrate sheet 1 is not particularly limited, but may be usually from 10 to 25 Oim, and preferably from 20 to L0zm.
基材シート 1と第 1の接着剤層 2との接着力を増すために、 基材シート 1の表 面を表面処理してもよい。 表面処理方法としては、 例えば、 コロナ放電処理、 化 学処理、 樹脂コーティング等が挙げられる。  The surface of the base sheet 1 may be surface-treated to increase the adhesive strength between the base sheet 1 and the first adhesive layer 2. Examples of the surface treatment method include corona discharge treatment, chemical treatment, and resin coating.
第 1の接着剤層 2に使用される接着剤としては、 熱溶融型接着剤、 感圧型接着 剤、 熱硬ィ匕型接着剤など種々の接着剤が挙げられる。 接着剤の種類としては、 例 えば、 天然ゴム系接着剤、 合成ゴム系接着剤、 アクリル樹脂系接着剤、 ポリエス テル樹脂系接着剤、 ポリビニルエーテル樹脂系接着剤、 ウレタン樹脂系接着剤、 シリコーン樹脂系接着剤などが挙げられる。  Examples of the adhesive used for the first adhesive layer 2 include various adhesives such as a hot-melt adhesive, a pressure-sensitive adhesive, and a thermosetting adhesive. Examples of adhesives include natural rubber adhesives, synthetic rubber adhesives, acrylic resin adhesives, polyester resin adhesives, polyvinyl ether resin adhesives, urethane resin adhesives, and silicone resins. And the like.
合成ゴム系接着剤の具体例としては、 スチレン一ブタジエンゴム、 ポリイソブ チレンゴム、 イソプチレン一イソプレンゴム、 イソプレンゴム、 スチレン一イソ プレンブロック共重合体、 スチレン一ブタジエンブロック共重合体、 スチレン一 エチレン一プチレンプロヅク共重合体、 エチレン一酢酸ビニル熱可塑性エラスト マーなどが挙げられる。  Specific examples of the synthetic rubber-based adhesive include styrene-butadiene rubber, polyisobutylene rubber, isobutylene-isoprene rubber, isoprene rubber, styrene-isoprene block copolymer, styrene-butadiene block copolymer, styrene-ethylene-butylene block copolymer. Polymers, ethylene vinyl acetate thermoplastic elastomers, and the like.
アクリル樹脂系接着剤の具体例としては、 アクリル酸、 アクリル酸メチル、 ァ クリル酸ェチル、 アクリル酸プロピル、 アクリル酸プチル、 アクリル酸一 2—ェ チルへキシル、メタクリル酸メチル、メタクリル酸ェチル、メタクリル酸プチル、 ァクリロ二トリルなどの単独重合体もしくは共重合体などが挙げられる。 ポリエ ステル樹脂系接着剤は、 多価アルコールと多塩基酸の共重合体であり、 多価アル コールとしてはエチレングリコール、 プロピレングリコール、 プ夕ンジオールな どが,举げられ、 多塩基酸としては、 テレフタル酸、 アジピン酸、 マレイン酸など , 挙げられる。 ポリビニルエーテル樹脂系接着剤の具体例としては、 ポリビニル エーテル、 ポリビニルイソブチルエーテルなどが挙げられる。 シリコーン樹脂系 接着剤の具体例としては、 ジメチルポリシロキサンなどが挙げられる。 これらの 接着剤は、 1種単独でまたは 2種以上を組み合わせて用いることができる。 Specific examples of the acrylic resin-based adhesive include acrylic acid, methyl acrylate, ethyl acrylate, propyl acrylate, butyl acrylate, monoethyl hexyl acrylate, methyl methacrylate, ethyl methacrylate, and methacrylic. Homopolymers or copolymers such as acid butyl and acrylonitrile are exemplified. The polyester resin-based adhesive is a copolymer of a polyhydric alcohol and a polybasic acid. Examples of the polyhydric alcohol include ethylene glycol, propylene glycol, and vinyldiol. The polybasic acids include terephthalic acid, adipic acid, and maleic acid. Specific examples of the polyvinyl ether resin adhesive include polyvinyl ether, polyvinyl isobutyl ether, and the like. Specific examples of the silicone resin-based adhesive include dimethylpolysiloxane. These adhesives can be used alone or in combination of two or more.
これらの接着剤のうち、 ポリエステル樹脂系接着剤が好ましい。  Of these adhesives, polyester resin-based adhesives are preferred.
また、 上記第 1の接着剤層 2には、 必要に応じて粘着付与剤、 軟化剤、 老化防 止剤、 填料、 染料又は顔料などの着色剤などを配合することができる。 粘着付与 剤としては、 ロジン系樹脂、 テルペンフ -6エノール樹脂、 テルペン樹脂、 芳香族炭 化水素変性テルペン樹脂、石油樹脂、クマロン'インデン樹脂、スチレン系樹脂、 フエノール系樹脂、 キシレン樹脂などが挙げられる。 軟化剤としては、 プロセス オイル、 液状ゴム、 可塑剤などが挙げられる。 填料としては、 シリカ、 タルク、 クレー、 炭酸カルシウムなどが挙げられる。  The first adhesive layer 2 may contain a tackifier, a softener, an anti-aging agent, a filler, and a coloring agent such as a dye or a pigment, if necessary. Examples of the tackifier include a rosin resin, a terpene-6-enol resin, a terpene resin, an aromatic hydrocarbon-modified terpene resin, a petroleum resin, a coumarone'indene resin, a styrene resin, a phenolic resin, and a xylene resin. . Softeners include process oils, liquid rubbers, plasticizers, and the like. Fillers include silica, talc, clay, calcium carbonate, and the like.
第 1の接着剤層 2の厚みは、 特に制限ないが、 通常 1〜1 0 0〃mであればよ く、 好ましくは 3〜5 0 z mである。  The thickness of the first adhesive layer 2 is not particularly limited, but may be usually 1 to 100 μm, and preferably 3 to 50 zm.
本発明の I C夕グにおいては、 基材シ一ト 1と第 1の接着剤層 2の界面には、 電子回路 3と I Cチップ 6で形成される回路面 1 3に相当する位置に部分的に剥 離剤層 7が設けられている。 剥離剤層 7は、 それぞれ間隔を設けて 2以上の複数 設けられている。 剥離剤層 7の形状及び大きさや、 各剥離剤層 7の間隔は、 特に 制限なく、 種々の形状、 大きさ及び間隔にすることができる。  In the IC chip of the present invention, the interface between the base sheet 1 and the first adhesive layer 2 is partially located at a position corresponding to the circuit surface 13 formed by the electronic circuit 3 and the IC chip 6. An exfoliating agent layer 7 is provided. Two or more release agent layers 7 are provided at intervals. The shape and size of the release agent layer 7 and the interval between the release agent layers 7 are not particularly limited, and may be various shapes, sizes, and intervals.
例えば、第 2図、第 8図及び第 9図に示すように、 剥離剤層 7は、 回路面 1 3の 両端部に相当する位置の全面を覆うように設けてもよいし、 また、 第 3図に示す ように、 回路面 1 3の中間部に相当する位置に、 さらに剥離剤層 7を設けてもよ いが、剥離剤層 7で覆わない部分を残すようにする。また、第 6図に示すように、 回路面 1 3の両端部に相当する位置の全面を覆わないで、 一部覆わない部分があ つてもよい。 また、 回路面 1 3の両端部に相当する位置に設けないで、 回路面 1 3の中間部に相当する位置に、 剥離剤層 Ίを設けてもよい  For example, as shown in FIGS. 2, 8, and 9, the release agent layer 7 may be provided so as to cover the entire surface at positions corresponding to both ends of the circuit surface 13; As shown in FIG. 3, a release agent layer 7 may be further provided at a position corresponding to an intermediate portion of the circuit surface 13, but a portion not covered by the release agent layer 7 is left. In addition, as shown in FIG. 6, the entire surface at positions corresponding to both ends of the circuit surface 13 may not be covered, and some portions may not be covered. Further, the release agent layer よ い may be provided at a position corresponding to an intermediate portion of the circuit surface 13 without being provided at positions corresponding to both ends of the circuit surface 13.
このような構造にすることにより、 剥離剤層 7がない位置には、 基材シート 1 の表面には第 1の接着剤層 2が直接積層されており、剥離剤層 Ίがある位置には、 第 1の接着剤層 2は剥離剤層 7に直接積層されている。 I Cタグを物品 1 2に貼 付後に剥がす際には、 例えば、 剥離剤層 7がある位置では、 第 1の接着剤層 2が 剥離剤層 7との界面で剥がされ、 剥離剤層 7がない位置では、 物品 1 2と第 2の 接着剤層 5との界面又は第 2の接着剤層 5の内部で引き千切られ、 電子回路 3は 第 1の接着剤層 2に接着されたまま、 基材シート 1と共に剥がされ、 電子回路 3 が切断される。 By adopting such a structure, the first adhesive layer 2 is directly laminated on the surface of the base material sheet 1 at the position where the release agent layer 7 is not provided, and at the position where the release agent layer Ί is located. , The first adhesive layer 2 is directly laminated on the release agent layer 7. When the IC tag is peeled off after being attached to the article 12, for example, at the position where the release agent layer 7 is present, the first adhesive layer 2 is peeled off at the interface with the release agent layer 7, and the release agent layer 7 is removed. In the position where it is not, the electronic circuit 3 is cut off at the interface between the article 1 2 and the second adhesive layer 5 or inside the second adhesive layer 5, and the electronic circuit 3 remains adhered to the first adhesive layer 2, The electronic circuit 3 is cut off together with the base sheet 1.
剥離剤層 7は、 第 1の接着剤層 2を介して回路面 1 3の外周で囲まれる面積の 2 0 - 9 0 %を覆うように設けられることが好ましく、 4 0〜8 0 %を覆うよう に設けられることが特に好ましい。  The release agent layer 7 is preferably provided so as to cover 20 to 90% of an area surrounded by the outer periphery of the circuit surface 13 via the first adhesive layer 2, and 40 to 80% is provided. It is particularly preferable to be provided so as to cover.
剥離剤層 7は、 回路面 1 3の外周を超えて外側にはみ出すように、 設けられる ことが好ましく、 はみ出し巾は、 特に制限ないが、 1 mm以上が好ましい。 剥離剤層 7の形状は、 三角形、 四角形、 五角形以上の多角形、 楕円、 円などの 形状が好ましい (第 2図、 第 3図及び第 6図参照)。 2つの剥離剤層 7の形状は、 同一であってもよいし、 異なってもよい。 なお、 2つの剥離剤層 7は、 完全に分 離独立されていることが好ましいが、 一部で連結されていてもよい.。  The release agent layer 7 is preferably provided so as to protrude beyond the outer periphery of the circuit surface 13, and the protruding width is not particularly limited, but is preferably 1 mm or more. The shape of the release agent layer 7 is preferably a triangle, a quadrangle, a pentagon or more polygon, an ellipse, a circle, or the like (see FIGS. 2, 3, and 6). The shapes of the two release agent layers 7 may be the same or different. Preferably, the two release agent layers 7 are completely separated and independent, but may be partially connected.
剥離剤層 7に使用される剥離剤としては、 例えば、 シリコーン系樹脂、 長鎖ァ ルキル系樹脂、 フヅ素系樹脂等の剥離剤などが挙げられる。  Examples of the release agent used in the release agent layer 7 include release agents such as a silicone resin, a long-chain alkyl resin, and a fluorine resin.
剥離剤層 7の厚みは、特に制限されないが、 0 . 0 l〜5〃mが好ましく、 0 . 0 3 ~ 1〃mが特に好ましい。  The thickness of the release agent layer 7 is not particularly limited, but is preferably from 0.01 to 5 μm, and particularly preferably from 0.03 to 1 μm.
本発明の I Cタグにおいては、 第 1の接着剤層 2の表面に電子回路 3が設けら れている。  In the IC tag of the present invention, the electronic circuit 3 is provided on the surface of the first adhesive layer 2.
電子回路 3は、 導電性物質で形成された回路線 4で構成されている。 導電性物 質としては、 例えば、 金属箔、 蒸着膜、 スパッタリングによる薄膜等の金属単体 等が挙げられる。 金属単体としては金、 銀、 ニッケル、 銅、 アルミニウムなどが 使用できる。 また、 導電性物質としては、 金、. 銀、 ニッケル、 銅等の金属の粒子 をバインダ一に分散させた導電性ペーストが使用できる。  The electronic circuit 3 includes a circuit line 4 formed of a conductive material. Examples of the conductive material include a metal simple substance such as a metal foil, a vapor-deposited film, and a thin film formed by sputtering. Gold, silver, nickel, copper, aluminum, etc. can be used as the metal simple substance. Further, as the conductive substance, a conductive paste in which metal particles such as gold, silver, nickel, and copper are dispersed in a binder can be used.
金属粒子の平均粒径は、 1〜 1 5〃mが好ましく、 2〜 1 0〃mが特に好まし い。 バインダ一としては、 例えば、 ポリエステル樹旨、 ポリウレタン樹脂、 ェポ キシ樹脂、 フエノール樹脂などが挙げられる。 子回路を構成する回路線 4の厚みは、 特に制限されないが、 金属箔の場合は 5〜 5 0 m、蒸着膜ゃスパッ夕リングによる金属月莫の場合は 0 . 0 1〜: L〃m、 導電ペーストの場合は 5〜3 0〃mであることが好ましい。 The average particle size of the metal particles is preferably from 1 to 15 μm, and particularly preferably from 2 to 10 μm. Examples of the binder include polyester resin, polyurethane resin, epoxy resin, and phenol resin. The thickness of the circuit line 4 constituting the sub-circuit is not particularly limited, but is 5 to 50 m in the case of metal foil, and 0.01 to 1 in the case of metal film by vapor deposition and sputtering. In the case of a conductive paste, the thickness is preferably 5 to 30 μm.
回路線 4の幅は、 特に制限ないが、 0 . 0 1〜1 0 mmが好ましく、 0 . 1〜 3 mmが特に好ましい。  The width of the circuit line 4 is not particularly limited, but is preferably from 0.1 to 10 mm, particularly preferably from 0.1 to 3 mm.
第 1の接着剤層 2上に電子回路 3を形成するには、 例えば、 金属箔を接着剤で 基材シート 1に貼り合わせ、 金属箔をエッチング処理して回路以外の部分を除去 することにより、電子回路 3を形成する方法等が挙げられる。エツチング処理は、 通常のエッチング処理と同様な処理により行うことができる。 また、 第 1の接着 剤層 2の表面への電子回路 3の形成は、 導電性ペーストを、 印刷、 塗布などの手 段により電子回路 3の形状に付着させることによっても行うことができる。  To form the electronic circuit 3 on the first adhesive layer 2, for example, a metal foil is bonded to the base sheet 1 with an adhesive, and the metal foil is etched to remove portions other than the circuit. And a method of forming the electronic circuit 3. The etching process can be performed by a process similar to a normal etching process. The formation of the electronic circuit 3 on the surface of the first adhesive layer 2 can also be performed by attaching a conductive paste to the shape of the electronic circuit 3 by means of printing, coating, or the like.
電子回路 3の形状は、 例えば、 第 2図及び第 3図に示された形状のものが挙げ られる。 第 2図及び第 3図には、 一本の導電性物質の線から成る回路線 4が長方 形状の基材シ一ト 1の外周から内側に向けて十重の環状に所定間隔を空けて配置 されてアンテナとしての電子回路 3を形成している。 電子回路 3は、 第 2図及び 第 3図のように十重の環状に配置されていてもよいが、 一重〜九重の環状であつ てもよいし、 ^—重以上の環状であってもよい。  Examples of the shape of the electronic circuit 3 include those shown in FIGS. 2 and 3. FIGS. 2 and 3 show that a circuit line 4 composed of a single conductive material line is spaced from the outer periphery of the rectangular base sheet 1 in a doubly annular manner at a predetermined interval. To form an electronic circuit 3 as an antenna. The electronic circuit 3 may be arranged in a doubly annular shape as shown in FIGS. 2 and 3, but may be a single to ninefold annular shape, or may be a ^-or more annular shape. Good.
電子回路 3の回路線 4は、 迂回路 8を有する。 迂回路 8を有する回路線 4は、 最内輪の回路線 4であってもよいし、 最外輪の回路線 4であってもよく、 また、 その中間のいずれの回路線 4であってもよい。 迂回路 8と回路線 4の連結点 1 4 における迂回路 8の接線 1 5と回路線 4の接線 1 6の角度は、 第 5図において角 度 Θと記載されている。角度 Θは、 1 0度以上であるが、 4 5度以上が好ましく、 8 0度以上が特に好ましい。また、角度 0の上限は、 1 8 0度未満であればよい。 このような構造にすることにより、 第 4図に示すように剥離剤層 7がある位置 の迂回路 8の部分が、 第 1の接着剤層 2と第 2の接着剤層 5を接着したままの状 態で、 第 1の接着剤層 2が剥離剤層 7との界面で剥がされ、 剥離剤層 7がない位 置では、 第 2の接着剤層 5の内部で引き千切られ、 電子回路 3は第 1の接着剤層 2に接着されたまま、 基材シート 1と共に剥がされ、 電子回路 3が切断される。 迂回路 8の形状は、 特に制限なく、 円形、 楕円形などの外周線の一部を欠いた · 形状、 三角形の外周線の一辺を欠いた形状、 正方形、 長方形、 ひし形、 台形など の四角形の外周線の一辺を欠いた形状、 五角形以上の多角形の外周線の一辺を欠 レ、た形状など種々の形状が挙げられる。 The circuit line 4 of the electronic circuit 3 has a bypass 8. The circuit line 4 having the detour 8 may be the innermost circuit line 4, the outermost circuit line 4, or any intermediate circuit line 4. . The angle between the tangent 15 of the detour 8 and the tangent 16 of the circuit 4 at the connection point 14 between the detour 8 and the circuit line 4 is described as an angle に お い て in FIG. The angle Θ is 10 degrees or more, preferably 45 degrees or more, and particularly preferably 80 degrees or more. Further, the upper limit of the angle 0 may be less than 180 degrees. With such a structure, as shown in FIG. 4, the portion of the detour 8 where the release agent layer 7 is located remains bonded to the first adhesive layer 2 and the second adhesive layer 5. In this state, the first adhesive layer 2 is peeled off at the interface with the release agent layer 7, and where the release agent layer 7 is not provided, the first adhesive layer 2 is cut off inside the second adhesive layer 5, and the electronic circuit is cut off. 3 is peeled off together with the base sheet 1 while being adhered to the first adhesive layer 2, and the electronic circuit 3 is cut. The shape of the detour 8 is not particularly limited, and a part of the outer line such as a circle and an ellipse is missing. Shape, shape missing one side of triangle outer shape, shape missing one side of square outer shape such as square, rectangle, diamond, trapezoid, etc., shape missing one side of polygonal outer shape of pentagon or more, etc. There are various shapes.
迂回路 8の大きさは、 迂回路 8が最内輪の回路線 4に設けられている場合、 電 子回路に囲まれている空き部より小さくすればよく、 また、 迂回路 8が最外輪の 回路線 4に設けられている場合、 I C夕グの大きさより小さくすればよい。また、 回路線 4力ら最も遠く離れている迂回路 8の最遠部から回路線 4までの距離は、 2 mm以上が好ましい。  When the detour 8 is provided on the innermost circuit line 4, the size of the detour 8 may be smaller than the empty space surrounded by the electronic circuit. If it is provided on the circuit line 4, it may be smaller than the size of the IC chip. The distance from the furthest part of the detour 8 farthest from the circuit line 4 to the circuit line 4 is preferably 2 mm or more.
迂回路 8の厚みは、 特に制限されないが、 電子回路の厚みと同様であり、 好ま しい範囲も同様である。  The thickness of the detour 8 is not particularly limited, but is the same as the thickness of the electronic circuit, and the preferred range is also the same.
迂回路 8の線幅は、 特に制限ないが、 0 . 0 1 ~ 1 0 mmが好ましく、 0 . 1 0〜 3 mmが特に好ましい。  The line width of the detour 8 is not particularly limited, but is preferably from 0.11 to 10 mm, particularly preferably from 0.10 to 3 mm.
迂回路 8の数は、 1〜1 0個カ 子ましく、 1〜5個が特に好ましい。 迂回路 8 が複数設けられている場合、 複数の迂回路 8は、 形状及び/又は大きさが同じで あってもよいし、 異なっていてもよい。  The number of the detours 8 is preferably 1 to 10, more preferably 1 to 5. When a plurality of detours 8 are provided, the plurality of detours 8 may be the same or different in shape and / or size.
回路線 4には、 平面状突起 9が延設されていることが好ましい。  It is preferable that the circuit wire 4 has a planar protrusion 9 extending therefrom.
平面状突起 9の形状は、 正方形、 正六角形、 正八角形、 正十角形などの対象形 状多角形、 円形などの対象形状や、 それに近似した形状が好ましい。  The shape of the planar protrusion 9 is preferably a target shape such as a square, a regular hexagon, a regular octagon, a regular decagon, a polygonal shape, a circular shape, or a shape similar thereto.
平面状突起 9は、 次式 S≥ ( 2 W) 2 (式中、 Sは平面状突起の面積であり、 Wは平面状突起に隣接する回路線の線幅である。)で求められる面積を有するもの が好ましく、 さらには、 次式 S ( 4 W) 2 (式中、 Sと Wは前記と同じである。) で求められる面積を有するものが特に好ましい。 The area of the planar projection 9 is determined by the following equation: S≥ (2W) 2 (where S is the area of the planar projection and W is the line width of the circuit line adjacent to the planar projection). The one having an area determined by the following formula S (4W) 2 (where S and W are the same as described above) is particularly preferable.
平面状突起 9の面積の上限は、 電子回路に囲まれている空き部の面積に対して 1 0 %以下が好ましく、 5 %以下がより好ましく、 3 %以下が特に好ましい。 平面状突起 9の厚みは、 電子回路の厚みと同様であり、 好ましい範囲も同様で ある。  The upper limit of the area of the planar projection 9 is preferably 10% or less, more preferably 5% or less, and particularly preferably 3% or less, with respect to the area of the empty portion surrounded by the electronic circuit. The thickness of the planar projection 9 is the same as the thickness of the electronic circuit, and the preferred range is also the same.
第 3図及び第 6図に示すように、 平面状突起 9は、 電子回路 3の回路線 4の迂 回路 8に直接延設されていてもよいし、 回路線 4の迂回路 8と平面状突起 9の間 に結合線 1 0を連結して延設されていてもよい。 これにより、 第 4図に示すよう に物品 1 2に貼付された I C夕グの第 2の接着剤層 5と物品 1 2の界面に力ッ夕 一などで切り込み 1 7を入れ、 その切り込み 1 7に指などを差し込んで I Cタグ の端を摘み、 I Cタグを剥がすと、 剥離剤層 7がある位置では、 迂回路 8又は平 面状突起 9の部分が、 第 1の接着剤層 2と第 2の接着剤層 5を接着したままの状 態で、 第 1の接着剤層 2が剥離剤層 7との界面で剥がされ、 剥離剤層 7がない位 置では、 物品 1 2と第 2の接着剤層 5との界面又は第 2の接着剤層 5の内部で引 き千切られ、 電子回路 3は第 1の接着剤層 2に接着されたまま、 基材シート 1と 共に剥がされ、 電子回路 3が切断される。 As shown in FIGS. 3 and 6, the planar projection 9 may be directly extended to the bypass 8 of the circuit line 4 of the electronic circuit 3, or may be planar with the bypass 8 of the circuit line 4. The connecting line 10 may be connected and extended between the protrusions 9. As a result, as shown in FIG. Insert a notch 17 into the interface between the second adhesive layer 5 of the IC tag attached to the article 12 and the article 1 and the article 12 with a force, and insert a finger or the like into the notch 17 to insert the IC tag. When the IC tag is peeled off, the detour 8 or the flat protrusion 9 adheres the first adhesive layer 2 and the second adhesive layer 5 where the release agent layer 7 is located. In the state as it is, the first adhesive layer 2 is peeled off at the interface with the release agent layer 7, and when there is no release agent layer 7, the interface between the article 12 and the second adhesive layer 5 Alternatively, the electronic circuit 3 is cut off inside the second adhesive layer 5, the electronic circuit 3 is peeled off together with the base sheet 1 while being adhered to the first adhesive layer 2, and the electronic circuit 3 is cut.
また、 第 8図及び第 9図に示すように、 平面状突起 9は、 電子回路の回路線に 直接延設されていてもよいし、 回路線と平面状突起 9の間に結合線 1 0を連結し て延設されていてもよい。 そうすることにより、 剥離剤層の界面でアンテナが切 断されなかった場合でも、 第 1 0図に示すように一部の平面状突起の部分が、 基 材シート側に接着したまま剥離されるためアンテナ機能が破壊される。  As shown in FIGS. 8 and 9, the planar projection 9 may be directly extended to the circuit line of the electronic circuit, or a coupling line 10 may be provided between the circuit line and the planar projection 9. May be connected and extended. By doing so, even if the antenna is not cut off at the interface of the release agent layer, some of the planar protrusions are peeled off while being adhered to the base sheet side as shown in FIG. Therefore, the antenna function is destroyed.
平面状突起 9は、 電子回路の最内輪の回路線 4に延設してもよいし、 最外輪の 回路線 4に延設してもよいし、 また、 平面状突起 9は、 中間の回路線 4のいずれ の回路線 4にも延設してもよい。 平面状突起 9が中間の回路線 4に延設されてい る場合は、 その外側の回路線 4は、 平面状突起 9を回避して形成される。  The flat protrusion 9 may extend to the circuit wire 4 of the innermost ring of the electronic circuit or may extend to the circuit wire 4 of the outermost ring. Any of the circuit lines 4 on the route 4 may be extended. When the planar protrusion 9 extends to the intermediate circuit line 4, the outer circuit line 4 is formed avoiding the planar protrusion 9.
平面状突起 9の数は、 1〜 1 0個が好ましく、 1〜5個が特に好ましい。 迂回路 8の材質は、 電子回路の回路線 4と同一の材質であり、 一体としたもの が好ましい。  The number of the planar projections 9 is preferably 1 to 10, and particularly preferably 1 to 5. The material of the detour 8 is the same as the material of the circuit line 4 of the electronic circuit, and is preferably integrated.
平面状突起 9の材質は、 本発明の I C夕グを剥がした際に平面状突起 9が電子 回路の回路線 4、 迂回路 8又は結合線 1 0と剥がれないような接着性を有するも のであればよく、 例えば、 電子回路の材質である導電性物質、 アクリル樹脂、 ポ リエステル樹脂等の種々の樹脂等が挙げられるが、 電子回路の回路線 4又ば結合 線 1 0と同一の材質が製造上好ましく、 一体としたものが特に好ましい。  The material of the planar projection 9 is such that the planar projection 9 does not peel off from the circuit line 4, the detour 8 or the coupling line 10 of the electronic circuit when the IC ring of the present invention is peeled off. Any material may be used, for example, a conductive material that is a material of the electronic circuit, various resins such as acrylic resin and polyester resin, etc., and the same material as the circuit wire 4 or the coupling wire 10 of the electronic circuit. It is preferable from the viewpoint of production, and an integrated one is particularly preferable.
結合線 1 0の材質は、 本発明の I Cタグを剥がした際に結合線 1 0が電子回路 の回路線 4の迂回路 8及び平面状突起 9と剥がれないような接着性を有するもの であればよく、 例えば、 電子回路の材質である導電性物質等が挙げられ、 電子回 路の回路線 4又は結合線 1 0と同一の材質が特に好ましい。 迂回路 8、 平面状突起 9及び/又ほ結合線 1 0を電子回路 3の回路線 4に延設 する方法は、 種々の方法があり、 例えば、 金属箔から迂回路 8、 平面状突起 9及 び/又は結合線 1 0と共に電子回路をェヅチングで形成する方法、 電子回路 3の 回路線 4に迂回路 8を印刷又は塗布により形成する方法等が挙げられるが、 金属 =箔から迂回路 8、 平面状突起.9及び 又は結合線 1 0と共に電子回路をェヅチン で形成する方锌が特に好ましい。 . The material of the bonding wire 10 is such that the bonding wire 10 does not peel off from the detour 8 of the circuit wire 4 and the planar projection 9 of the electronic circuit when the IC tag of the present invention is peeled off. For example, a conductive material that is a material of the electronic circuit may be used, and the same material as the circuit line 4 or the coupling line 10 of the electronic circuit is particularly preferable. There are various methods for extending the detour 8, the planar protrusion 9 and / or the connecting line 10 to the circuit line 4 of the electronic circuit 3, and there are various methods, for example, a detour 8, the planar protrusion 9 from a metal foil. And / or a method of forming an electronic circuit together with the coupling line 10 by etching, a method of forming a detour 8 on the circuit line 4 of the electronic circuit 3 by printing or coating, etc. It is particularly preferable to form the electronic circuit with a resin, together with the planar protrusions 9 and / or the connection lines 10. .
:平面状突起 9又は迂回路 8を設ける場合は、 剥離剤層 7のない場所に設けられ ていてもよいが、 平面状突起 9又は迂回路 8の少なくとも 1つは、 回路面内で、 剥離剤層 7のある場所に設けることが特に ^ましい。 また、 迂回路 8に平面状突 起 9が延設されている場合は、 平面状突起 9が延設されている迂回路 8の少なく 人とも ίόは、 回路面内で、 剥離剤層 7のある場所に設けることが好ましい。  : When the planar projection 9 or the detour 8 is provided, it may be provided in a place where the release agent layer 7 is not provided, but at least one of the planar projection 9 or the detour 8 is peeled off in the circuit plane. It is particularly preferable to provide it at the place where the agent layer 7 is located. In addition, when the planar protrusion 9 is extended in the detour 8, at least one of the detours 8 in which the planar protrusion 9 is extended, at least 人, the surface of the release agent layer 7 in the circuit surface. Preferably, it is provided at a certain place.
: 本発明の I C夕グの別の態様として、 第 9図及び第 1 0図のように、 電子回路 : 3の回路線 4に迂回路 8又は結合線 1 0を設けないで、 平面状突起 9を直接電子 , 回路 3 ©回路線 4に延設することができる。 この場合も、 平面状突起 9は、 剥離 剤層 7のない場所に設けられていてもよいが、平面状突起 9の少なくとも 1つは、 回路面内で、 剥離剤層 7のある場所に設けることが好ましい。平面状突起 9の数 は、 1〜: L 0個が好ましく、 1〜5個が特に好ましい。 平面状突起 9が複数設け られている場合、 複数の平面状突起 9は、 形状及び/又は大きさが同じであって ::, もよいし、 異なっていてもよい。  : As another embodiment of the IC circuit of the present invention, as shown in FIGS. 9 and 10, an electronic circuit: a planar projection without providing a detour 8 or a coupling line 10 in the circuit line 4 of FIG. 9 can be extended directly to the electronics, circuit 3 © circuit line 4. Also in this case, the planar projection 9 may be provided at a location where the release agent layer 7 is not provided, but at least one of the planar projections 9 is provided at a location where the release agent layer 7 exists in the circuit plane. Is preferred. The number of the planar projections 9 is preferably 1 to: L 0, and particularly preferably 1 to 5. When a plurality of planar projections 9 are provided, the plurality of planar projections 9 may have the same shape and / or size, and may be different from each other, or may be different.
電子回路 3の両末端には I Cチップ 6が連結されている。 J Cチヅプ 6は、 電 子回路 3の内側に設けてもよいし、 電子回路 3の外側に設けてもよいし、 電子回 路 3の上部に設けてもよい。  An IC chip 6 is connected to both ends of the electronic circuit 3. The JC chip 6 may be provided inside the electronic circuit 3, may be provided outside the electronic circuit 3, or may be provided above the electronic circuit 3.
最外輪及び最内輪の電子回路 3の末端を I Cチップ 6と連結するためには、 最 外輪又は最内輪の電子回路 3の末端は、その環状竃子回路 3と短絡することなく、 • 飛び越えて引き出し(ジヤンパ回路)、電子回路 3の内側又は外側に延設し、 I C チップ 6と.連結することが好ましい。  In order to connect the terminals of the outermost and innermost electronic circuits 3 to the IC chip 6, the terminals of the outermost or innermost electronic circuits 3 do not short-circuit with the ring heater circuit 3 without jumping over. It is preferable that the drawer (jumper circuit) extend inside or outside the electronic circuit 3 and be connected to the IC chip 6.
ジヤンパ回路の形成方法は、 電子回路 3の末端から、 その環状電子回路 3の部 分を横断して、 絶縁ィンクをスクリーン印刷等により線状に印 その印刷さ ' れた絶縁ィンクの上に導電性ペーストをスクリーン印刷等により線状に印刷し、 導電性回路線 4を形成する方法等が挙げられる。 導電性ペーストは前記したもの が例示される。 絶縁インクとしては、 紫外線硬ィ匕型インク等の光硬化型インクな どが挙げられる。 The method of forming the jumper circuit is as follows. From the end of the electronic circuit 3, traverse the portion of the ring-shaped electronic circuit 3, mark the insulating ink linearly by screen printing or the like, and conduct the conductive ink on the printed insulating ink. The conductive paste is printed in a line by screen printing or the like, A method of forming the conductive circuit line 4 is exemplified. Examples of the conductive paste include those described above. Examples of the insulating ink include a photo-curable ink such as an ultraviolet curing type ink.
電子回路 3の末端に I Cチップ 6を連結させる方法としては、 電子回路 3の末 端の表面に異方性導電フィルムを介して、 フリッブチップボンディング法により 連結する方法等が挙げられる。 フリップチップボンディング法は、 I Cチヅプ 6 の電極部にワイヤパンプを設け、 竃子回路 3の末端の表面に被覆された異方性導 電フィルムの上に、 I Cチヅプ 6のワイヤバンプがある面を押し付けて、 異方性 導電フィルムの中にワイヤバンプが入り込み、 電子回路 3の末端と I Cチヅプ.6 を導通させる方法であ 。  As a method of connecting the IC chip 6 to the end of the electronic circuit 3, there is a method of connecting the IC chip 6 to the surface of the end of the electronic circuit 3 via an anisotropic conductive film by a flip chip bonding method. In the flip chip bonding method, a wire pump is provided on the electrode portion of the IC chip 6, and the surface of the IC chip 6 where the wire bumps are located is pressed on the anisotropic conductive film coated on the terminal surface of the heater circuit 3. This is a method in which wire bumps penetrate into the anisotropic conductive film to make the end of the electronic circuit 3 conductive with the IC chip.
本発明の I Cタグにおいては、 電子回路 3が設けられてい い第 1の接着剤層 2の表面、 電子回路 3及び I Cチヅプ 6を覆うように、 第 2の接着剤層.5が積層 される。. ' ': , .: ' 第 2の接着剤層 5に使用される接着剤としては、 熱溶融型接着剤、 感圧型接着 剤、 熱硬化型接着剤など種々の接着剤が挙げちれる。接着剤の種類としては、:前 記第 1の接着剤層 2に使用される接着剤と同様なものが挙げられる。 これちの接 着剤は、 1種又は 2種以上を組合せて使用するごとができる。 とれらの接着剤の うち、 感圧型接着剤が好ましく、 アクリル系感圧型接着剤が特に好ましい。  In the IC tag of the present invention, the second adhesive layer .5 is laminated so as to cover the surface of the first adhesive layer 2 where the electronic circuit 3 is not provided, the electronic circuit 3 and the IC chip 6. . '':,.: 'Examples of the adhesive used for the second adhesive layer 5 include various adhesives such as a hot-melt adhesive, a pressure-sensitive adhesive, and a thermosetting adhesive. Examples of the type of the adhesive include: the same as the adhesive used for the first adhesive layer 2 described above. These adhesives can be used alone or in combination of two or more. Among these adhesives, a pressure-sensitive adhesive is preferable, and an acrylic pressure-sensitive adhesive is particularly preferable.
第 2の接着剤層 5の表面は平面であることが好ましい。  The surface of the second adhesive layer 5 is preferably flat.
第 2の接着剤層 5の厚みは、 特に制限ないが、 電子回路 3及び T Ciチップ 6を 覆う場所と、 第 1の接着剤層 2を覆う場所では、 厚みが異なり、 最大厚みは、 通 常 1 0〜1 0 0 /mであればよく、 好ましくは 1 5〜5 0〃mである。  Although the thickness of the second adhesive layer 5 is not particularly limited, the thickness is different between a place where the electronic circuit 3 and the T Ci chip 6 are covered and a place where the first adhesive layer 2 is covered. It is usually 10 to 100 / m, preferably 15 to 50 m.
第 2の接着剤層 5の表面は、 剥離シ一ト 1 1で覆ってもよい。  The surface of the second adhesive layer 5 may be covered with a release sheet 11.
剥離シート 1 1としては、 いずれのものを使用してもよく、 例えば、 ポリェチ レンテレフ夕レート、 ポリプチレンテレフ夕レート、 ポリエチレン、 ポリプロピ, レン、 ポリアリレートなどの各種樹脂よりなるフィルムや、 ポリエチレンラミネ —ト紙、 ポリプロピレンラミネート紙、 クレーコート紙、 樹脂コート紙、 グラシ ン紙等の各種紙材を とし、 この基材の第 2の接着剤層 5との接合面に、 必要: により剥離処理が施されたものを用いることができる。 Any release sheet may be used as the release sheet 11. For example, films made of various resins such as polyethylene terephthalate, polyethylene terephthalate, polyethylene, polypropylene, ren, and polyarylate, and polyethylene laminate — Paper, polypropylene-laminated paper, clay-coated paper, resin-coated paper, glass paper, and other various paper materials. The surface of this base material that is to be bonded to the second adhesive layer 5 is subjected to a peeling treatment according to necessity: What was done can be used.
Figure imgf000015_0001
ィロン 3 0 S S」)をグラビアコ一夕一で乾燥して厚さ 5 mになるように塗布し て第 1の接着剤層 2を積層した。
Figure imgf000015_0001
Was dried overnight at gravure and applied to a thickness of 5 m to laminate the first adhesive layer 2.
さらに、 この第 1の接着剤層 2の表面に 3.5 m厚の霉解銅箔を 1 0 0 °Cのヒ —トシ一ルロールにて加熱圧着した。次に、 前記電解銅箔の表面に、 第.2図の.よ うに、 長辺 4 5 mm、 短辺 1 5 mmの十重の璟状回路線 4 (アンテナ)状及びそ の最内輪の回路線 4に迂回路 8状に、 スクリーン印刷法により、 ェヅチン レジ- ストインクを印刷 (線幅: 0 . 1 5 mm) した。 これを塩化第二鉄溶液にて: tヅ チング処理を行い、 環状回路線 4、 迂回路 8以外の部分を除去した。 この後、 ァ ルカリ水溶液にてエツチングレジストインクを除去し、 第 2図と同じ迂回路 3.が 設けられている電子回路 3を形成した。 なお、 迂回路 8め大きさ及び接線め角度 0は、 長方形の外周線の長辺一辺を欠いた形状の迂回路 8が縦が 5 mm、 .横 7' mm、 角度 0が 9 0度であり、 正三角形の外周線の一辺を欠いた形状め 回路 8 がー辺が 7 mm、 角度 6>が 6 0度であり、 半円形の円周線形状の迂回路.8が 径 3 mm、 角度 6>が 8 5度であり、 台形の外周線の上底を欠いた形状の迂回路 8が 下底が 1 0 mm、 上底が 3 mm、 高さ 5 mm、 角度 0が 1 4 5度であった 6 ; 最内輪の電子回路 (アンテナ) 3の末端と、 そめ最外輪の電子囱路 3の末端を 導通させるために、 それらの間を紫外線硬化型ィンクをスクリーン印刷法により, 線状に印刷後、 紫外線を照射して硬化させ、 その紫外線硬化型インクの硬化線の 表面に銀ペースト (銀粒子の平均粒径: 5〃m、バインダ一:ポリエステル樹脂) をスクリーン印刷法により線状 (長さ 1 0 mm) に印刷し、 乾燥させ、 ジヤンパ 回路を形成した。 , Further, a 3.5-meter-thick copper foil was heat-pressed on the surface of the first adhesive layer 2 with a 100 ° C. heat roll. Next, as shown in Fig. 2, on the surface of the electrolytic copper foil, as shown in Fig. 2, a ten-fold rectangular circuit wire 4 (antenna) having a long side of 45 mm and a short side of 15 mm and the innermost ring The resist ink was printed (line width: 0.15 mm) on the circuit line 4 in the form of a detour 8 by screen printing. This was treated with a ferric chloride solution to remove the portions other than the loop circuit line 4 and the bypass 8. Thereafter, the etching resist ink was removed with an alkaline aqueous solution to form an electronic circuit 3 provided with the same detour 3 as in FIG. Note that the detour 8 and the tangent angle 0 are 5 mm long, 7 'mm wide, and 90 ° at 0 ° for a detour 8 that lacks one long side of the rectangular outer peripheral line. There is a shape that lacks one side of the outer line of the equilateral triangle.Circuit 8 is 7 mm on the negative side, angle 6> is 60 degrees, and a semicircular circular detour.8 is 3 mm in diameter, Angle 6> is 85 degrees, trapezoidal detours without upper base 8 are 10 mm lower base, 3 mm upper base, 5 mm height, 0 angle is 1 4 5 6 ; In order to make the end of the electronic circuit (antenna) 3 of the innermost ring and the end of the electronic circuit 3 of the outermost ring conductive, an ultraviolet-curing ink was applied between them by screen printing, After printing in a shape, the resin is cured by irradiating ultraviolet rays, and a silver paste (average particle size of silver particles: 5〃m, binder: polyester resin) is applied to the surface of the curing line of the ultraviolet curable ink. Printed on the linear (length 1 0 mm) by screen printing method and dried to form a jumper circuit. ,
次いで、 I Cチヅプ(フイリヅプス社製、商品名「I /C O D E」) 6の電極部 に金線を用いてワイヤバンプを設け、この I Cチヅプ 6を異方性導電フィルム(ソ 二一ケミカル社製、商品名「F P 2 3 2 2 D」)を介して、 回路め両末端に、 フリ ヅプチップボンディング法を用いて、 連結した。  Next, a wire bump is provided on the electrode part of the IC chip (manufactured by Philips, product name "I / CODE") 6 using a gold wire, and this IC chip 6 is attached to an anisotropic conductive film (manufactured by Sony Chemical Co., Ltd.). The circuit was connected to both ends of the circuit using the flip-chip bonding method under the name “FP2322D”).
一方、 厚さ 7 0 mのグラシン紙の片側全面にシリコーン樹脂により剥 処理 した剥離シート 1 1の剥離処理面に、 ロールナイフコー夕一を用いて、 'ァクリル 系低接着性感圧型接着剤 (リンテック (株)製、 商品名 「P A— T 1」).を塗布、 乾燥して厚さ 2 0〃mの第 2の接着剤層 5を形成した第 2の接着剤層 5付き剥離 .シート 1 1を用意した。 . On the other hand, a 70 m thick glassine paper was peeled off with silicone resin on the entire surface on one side. Using a roll knife coater, the acryl-based low-adhesion pressure-sensitive adhesive (LINTEC Co., Ltd., product name "PA-T 1"). Apply and dry to form a 20〃m-thick second adhesive layer 5 and peel off with second adhesive layer 5 .Sheet 1 1 was prepared. .
次に、電子回路 3及び I Cチヅプ 6が設けられた ¾ シート 1の表面の全体に、 第 2の接着剤層 5付き剥離シート, 1 1の第 2の接着剤層 5を貼り合わせ、 第 1の ; 接着剤層 2、 電子回路 3及び I Cチヅズ 6を第 2の接着剤層 5で被覆し、 I C夕 :グを作成した。 ,  Next, the release sheet with the second adhesive layer 5 and the second adhesive layer 5 of 11 were attached to the entire surface of the sheet 1 on which the electronic circuit 3 and the IC chip 6 were provided. The adhesive layer 2, the electronic circuit 3 and the IC chip 6 were covered with the second adhesive layer 5 to prepare an IC chip. ,
得られた ι σタグについて、 非接触送受信試験を行ったところ、 正常に送受信 ' を行うことができた。  A non-contact transmission / reception test was performed on the obtained ισ tag, and transmission / reception was performed normally.
この I Cタグの剥離シード 1 1を剥がし、 I Cタグをポリプロピレン観旨板に . 貼付しだ。 2 4時間後、 この I Cタグの一端から 5 mmカヅ夕一ナイフで第 2の 接着剤肩に切り込み 1 7を入れ、 この部分を指で摘んでポリプロピレン樹脂板か : 剥 させおところ、 剥離剤層 7 覆われた電子回 S& 3の部分がポリプロピレン 镦脂板に残留レ、 それ以外の非剥離剤 if部分は基材シ一ト 1のポリェチレンテレ ;., :フタレ一ト^ードと共に、 ポリプロピレン樹脂板から剥離された。 その剥離に伴 , い電子回路 3が切断され、 非接触送受信試験を行づたところ、 送受信を行うこと ができなかった (剥離切断試験)。 The peeling seed 11 of this IC tag was peeled off, and the IC tag was affixed to a polypropylene plate. Twenty-four hours later, from the end of this IC tag, make a cut in the second adhesive shoulder with a 5 mm ヅ knife from the one end of the IC tag, and cut 17 with this finger and peel off the polypropylene resin plate. Layer 7 Covered electronic circuit S & 3 part is polypropylene Remaining on the resin plate, other non-stripping agent If part is polyethylenetere tere of base sheet 1;., : Phthalate layer, polypropylene Peeled from the resin plate. The electronic circuit 3 was cut off due to the separation, and a non-contact transmission / reception test was performed.
この剥離切断試験ほ、 I Cタグ 3 0個について行ったところ、 3 0個が切断さ • れた。  When this peeling / cutting test was performed on 30 IC tags, 30 pieces were cut.
: (実施例 2 ) ·, '  : (Example 2) ·, '
平面状突起 9及び剥離剤層 7を第 3図のように形成した以外は、 実施例 1と同 ; ; 様にして、 I C夕グを作成した。 剥離剤層 7の形状は、 回路面の両端に位置する . 直角三角形の斜辺の角度が 4 5度、 未塗布部分の巾が 3 mm、 回路面の両端の直 角 Ξ角形及び回路面の中央部の平行四辺形で被覆されている電子回路 3及 I C チップ 6の外周で囲まれる面積が電子回路の外周で囲まれる面積の約 7 0 %、 直 .角三角形の端部と基材シート 1の外縁との長さが l mmであった。 なお、 迂回路 8の形状及び大きさは実施例 1と同様であり、平面状突起 9の大きさは、 直径 2 mmの円形で、 厚さ 3 5〃mであり、 結合線 1 0 長さは 0 . 5 mm、 幅は 0 . 1 mm、 厚さ 3 5〃mであった。得られた I Cタグについて、 非接触送受信試験 を行ったところ、 正常に送受信を行うことができた。 また、 得られた I Cタグ 3 0個について、 実施例 1と同様に剥離切断試験を行ったところ、 I Cタグ 3 0個 全て切断された。 The planar projection 9 and the release agent layer 7, except that were formed as FIG. 3, the first embodiment; in the like to prepare a IC Yugu. The shape of the release agent layer 7 is located at both ends of the circuit surface. The angle of the hypotenuse of the right triangle is 45 degrees, the width of the uncoated portion is 3 mm, the right angle at both ends of the circuit surface is the square and the center of the circuit surface The area enclosed by the outer periphery of the electronic circuit 3 and the IC chip 6 covered by the parallelogram is approximately 70% of the area enclosed by the outer periphery of the electronic circuit. Was 1 mm in outer edge and length. The shape and size of the detour 8 are the same as those in the first embodiment. The size of the planar protrusion 9 is a circle having a diameter of 2 mm, a thickness of 35 μm, and a length of the coupling line 10. Was 0.5 mm, the width was 0.1 mm, and the thickness was 35 m. When a non-contact transmission / reception test was performed on the obtained IC tag, transmission / reception was performed normally. Further, a peeling / cutting test was performed on 30 of the obtained IC tags in the same manner as in Example 1. All were cut.
(実施例 3)  (Example 3)
迂回路 8を設けないで、 平面状突起 9を回路線 4に直接延設し、 平面状突起 9 : 及び剥離剤層 7を第 6図のように形成した以外は、 実施例 1と同様にして、 I C - タグを作成した。 剥離剤層 7の形状は、 斜辺の角度が 45度、 禾塗布部分の巾が 3 mm、 2つの五角形で被覆されている電子回路 3の外周で.囲まれる面積が電午: 回路の外周で囲まれる面積の約 60%、 五角形の端部と基材シート 1の外縁との . 長さが lmmであった。 なお、 平面状突起 9の大きさは、 直径 2mmの円形及び 一辺が 2 mmの正方形で、厚さ 35 mであり、結合線 10の長さは 0 , 5 mm、 幅は 0. lmm、 厚さ 35 mであった。得られた I Cタグについ"^ 非接触送 受信試験を行ったところ、 正常に送受信を行うことができた。 また .獰られた I Cタグ 3.0個について、 実施例 1と同様に剥離切断試験を行ったと ろ. I C夕 グ 30個が切断された。  In the same manner as in Example 1 except that the planar projection 9 was directly extended to the circuit line 4 without providing the detour 8, and the planar projection 9 and the release agent layer 7 were formed as shown in FIG. I created an IC-tag. The shape of the release agent layer 7 is as follows: the angle of the hypotenuse is 45 degrees, the width of the coated part is 3 mm, and the outer periphery of the electronic circuit 3 is covered by two pentagons. About 60% of the enclosed area, the length between the edge of the pentagon and the outer edge of the base sheet 1 was 1 mm. The size of the planar projection 9 is a circle having a diameter of 2 mm and a square having a side of 2 mm, the thickness is 35 m, the length of the coupling wire 10 is 0, 5 mm, the width is 0.1 mm, and the thickness is 0.1 mm. It was 35 m. A non-contact transmission / reception test was performed on the obtained IC tag, and transmission / reception was performed normally. In addition, a peeling / cutting test was performed on 3.0 rogue IC tags in the same manner as in Example 1. Taro. IC evening 30 pieces were cut.
(実施例 4) :  (Example 4):
基材シート 1としての、ポリエチレンテレフ夕レート 7イルム(横 100mm、 縦 50mm、 厚さ 50〃m) ,の片側の表面に、 第 8図に示すような形状 (台形の 斜線の角度: 45度、 未塗布部分の巾: 3mm、 2つの台形で被覆されている電 子回路の外周で囲まれる面積:電子回路の外周で囲まれる面積の約 75%、 台形 の端部と基材シート 1の外縁との長さ: lmm) にシリコーン樹脂系剥 剤をグ ラビアコ一ターで乾燥して厚さ 0. 05 /mになるように塗布し、 130°Cで 1 分間硬ィ匕させて剥離剤層 7を形成した。 次に この剥離剤層 7及び基材シード 1 の表面にポリエステル系の熱溶融型接着剤 (東洋紡績 (株) 製、 商品名 「パイ口 ン 30S S」)をグラビアコ一夕一で乾燥して厚さ 3 mになるように塗布して第 On one surface of polyethylene terephthalate 7 film (width 100mm, length 50mm, thickness 50〃m) as the base sheet 1, a shape as shown in Fig. 8 (angle of the trapezoidal oblique line: 45 degrees) The width of the uncoated part: 3 mm, the area enclosed by the outer periphery of the electronic circuit covered by two trapezoids: about 75% of the area enclosed by the outer periphery of the electronic circuit, the end of the trapezoid and the base sheet 1 Dry with a gravure coater to a thickness of 0.05 / m and apply a silicone resin-based release agent to the outer edge (length: lmm) to a thickness of 0.05 / m. Layer 7 was formed. Next, a polyester-based hot-melt adhesive (Toyobo Co., Ltd., product name “Pai-Kin 30S S”) is dried on the surface of the release agent layer 7 and the base material seed 1 all over the gravure cup. To a thickness of 3 m.
1©接着剤層 2を積層した。 1 © adhesive layer 2 was laminated.
さらに、 この第 1の接着剤層 2の表面に 35〃m厚の電解銅箔を 100°Cのヒ , —トシールロールにて加熱圧着した。 次に、 前記電解銅箔の表面に、 第 8図のよ うに、 長辺 45mm、 短辺 15 mmの十重の環状回路線 (アンテナ)状及びその 最内輪の回路線に平面状突起 9及びその結合線 10状に、 スクリーン印刷法によ り、 エッチングレジストインクを印刷 (線幅: 0. 15 mm) した。 これを塩化
Figure imgf000019_0001
ころ、剥離剤層 7で覆われた電子回路 3の部分がポリプロピレン樹脂板に残留し、 それ以外の非剥離剤層部分は ¾#シ一ト 1のポリエチレンテレフ夕レートシ一卜 ; , と共に、ポリプロピレン樹脂板から剥離されるか、平面状突起部分で剥離された。 : その剥離に伴い電子回路 3が切断され、 非接触送受信試験を行ったところ、 送受 ' '信 ¾行うことができなかった (剥離切断試験)。
Further, an electro-deposited copper foil having a thickness of 35 μm was heat-pressed on the surface of the first adhesive layer 2 with a 100 ° C. heat-sealing roll. Next, on the surface of the electrolytic copper foil, as shown in FIG. 8, a ten-fold annular circuit wire (antenna) having a long side of 45 mm and a short side of 15 mm and a planar projection 9 and The etching resist ink was printed (line width: 0.15 mm) on the bonding lines 10 by screen printing. Chloride this
Figure imgf000019_0001
At this time, the portion of the electronic circuit 3 covered with the release agent layer 7 remains on the polypropylene resin plate, and the other non-release agent layer portion is a polyethylene terephthalate sheet of #sheet 1; It was peeled off from the resin plate or peeled off at the planar projection. : The electronic circuit 3 was cut off due to the separation, and a non-contact transmission / reception test could not be performed (peel-off test).
... .こ 0剥離切断試験は、 I Cタグ 1 0個について行ったところ、 1 0個全て切断 ' されだ。■ ' ' ,  .... This 0 peeling test was performed on 10 IC tags, and all 10 were cut. ■ '',
(難例 5 )  (Problem 5)
: 面状突起 9及び剥離剤層 Ί ( 2つの 0角形で被覆されている電子回路の外周 :: : で囲まれる面積:電子回路及び]: Cチップの外周で囲まれる面積の約 7 5 %) を 第 9 のように形成した以外は、 実施例 1と同様にして、 I Cタグを作成した。 : なお、平面状突起 9の大きさは、直径 2 mmの正方形で、厚さ 3 5 mであった。 ; : ' 得られだ I Cタグについて、 非接触送受信試験を行ったところ、 正常に送受信を 行うことができた。 また、 得られた I Cタグ 1 0個について、 実施例 1と同様に :剥離切断試験を行ったところ、 I Cタグ 1 0個全て切断された。 : Peripheral protrusion 9 and release agent layer Ί (periphery of electronic circuit covered with two 0-gons ::: area enclosed by: electronic circuit and]: about 75% of area enclosed by outer periphery of C chip ) Was formed as in Example 9 in the same manner as in Example 1 to produce an IC tag. The size of the planar projection 9 was a square with a diameter of 2 mm and a thickness of 35 m. : 'A contactless transmission / reception test was performed on the obtained IC tag, and transmission / reception was successful. When the obtained 10 IC tags were subjected to the peeling / cutting test in the same manner as in Example 1, all of the 10 IC tags were cut.
(実施例 6 )  (Example 6)
平面状突起 9の形状を第 1 1図のようにした以外は、 実施例 2と同様にして I : Cタグを作成した。 なお、.平面状突起 9の大きさ.は、 直径 2 mmの 形で、 厚さ : : 3 5〃mであった。得られた I Cタグについて.、 非接触送受信試験を行ったとこ . ろ、正常に送受信を行うことができた。また、得られた I Cダグ 1 0個について、 : 実施例 1ど^様に剥離切断試験を行つ; ところ、 実施例 1と同様に剥離切断試験. を行ったところ、 I Cダグ 1 0個全て切断された。  An I: C tag was prepared in the same manner as in Example 2, except that the shape of the planar projection 9 was changed as shown in FIG. The size of the planar projection 9 was 2 mm in diameter, and the thickness was 35 mm. When a non-contact transmission / reception test was performed on the obtained IC tag, transmission / reception was normally performed. In addition, a peeling / cutting test was performed on 10 of the obtained IC dougs as in Example 1; however, a peeling / cutting test was performed in the same manner as in Example 1. disconnected.
(比較例 1 ) ノ .  (Comparative Example 1)
..迂回路 &を設けなかった以外は、 実施例 1と同様にして I Cタグを作成した。 得られた I Cタグについて、 非接触送受信試験を行ったところ、 正常に送受信 を行うことができた。  ..IC tag was created in the same manner as in Example 1 except that the detour & was not provided. When a non-contact transmission / reception test was performed on the obtained IC tag, transmission / reception was performed normally.
この I Cタグ 1 0個について、 実施 1と同様に剥離切断試験を行ったところ、 A peeling / cutting test was performed on the 10 IC tags in the same manner as in Example 1.
I Cタグ 1 .0個のうち、 6個は 電子回路を破壌することなく、 剥離することが できだ。 電子回路を破壊することなく剥離した I Cタグについて、 非接触送受信 試験を行ったところ、 正常に送受信を行うことができた。 Of the 1.0 IC tags, 6 could be peeled off without breaking the electronic circuit. Non-contact transmission / reception of IC tags peeled without destroying electronic circuits After conducting the test, transmission / reception was successful.
本発明の I Cタグは、 商品、 貯蔵物、 荷物などの物品を管理するタグとして利 用できる。  The IC tag of the present invention can be used as a tag for managing articles such as merchandise, stored goods, and luggage.

Claims

請求の範囲 : The scope of the claims :
1 . シ一トの表面に第 1の接着剤層が積層され、該第 1の接着剤層の表面に、 回路線が迂回路を有し、 該迂回路と回路線の連結点における迂回路の接線と回路 線の接線の角度が 1.0度以上である電子回路及び該電子回路に接続する I Cチッ プが設けちれ、 .該電子回路及び I Cチップを覆う第 2の接着剤層が積層されてい る #造を有し、 さらに ¾ ^シ一トと第 1の接着剤層の界面であって、 電子回路と I Cチヅフ'で形成される回路面に相当する位置に部分的に剥離剤層が設けられて い ことを特徴とする I Cタグ。: 1. A first adhesive layer is laminated on a surface of the sheet, and a circuit line has a detour on a surface of the first adhesive layer, and a detour at a connection point between the detour and the circuit line. An electronic circuit having an angle of a tangent between the tangent line and the circuit line of at least 1.0 degree and an IC chip connected to the electronic circuit are provided, and a second adhesive layer covering the electronic circuit and the IC chip is laminated. In addition, the release agent layer is partially located at the interface between the シ ^ sheet and the first adhesive layer, which corresponds to the circuit surface formed by the electronic circuit and the IC chip. An IC tag characterized by being provided with a tag. :
:2 .: 迂回路が、前記回路面内であって剥離细層の設けられている位置に少なくと も 1っ^けられている請求項 1に記載の I C夕グ。  : 2.: The IC block according to claim 1, wherein the bypass is at least one in the circuit plane at a position where the release layer is provided.
3 , 平面状突 が、:迂回路に延接されてい!)請求項 1又は 2に記載の I C夕グ。 3, Planar protrusion is extended to the detour! ) The IC evening bag according to claim 1 or 2.
. 基材シートの表面に第 1の接着剤層が積層され、該第 1の接着剤層の表面に 平面状突起が延設されている電子回路 ¾び該電子回路に接続する I Cチップが設 :けられ、 該電子 tU路及び I Cチ プを覆う第 2の接着剤層が積層されている構造 :を有し、 らに基材シードと第 1の接着剤層の界面であって、 電子回路と I Cチ • ップで形成される回路面に相当する位置に部分的に剥離剤層が設けられているこ を特像とする ι σタグ。,  An electronic circuit in which a first adhesive layer is laminated on the surface of the base material sheet, and a planar protrusion extends on the surface of the first adhesive layer, and an IC chip connected to the electronic circuit are provided. Having a structure in which a second adhesive layer covering the electron tU path and the IC chip is laminated; and an interface between the substrate seed and the first adhesive layer, An i-σ tag featuring a release agent layer partially at the position corresponding to the circuit surface formed by the circuit and IC chip. ,
5 . ,基材シ トの表面に第 1の接着剤層が積層され、該第.1の接着剤層の表面に 平面状突起が延設されている電子回路及び該電子回路に接続する I Cチップが設 jナられ、 該電子回路及び I Cチップを覆う第 2の接着剤層が積層されている構造 .を有し、 さらに基材シ一小と第 1の接着剤層の界面であって、 電子回路と I Cチ ヅプで形成される回路面の両端部に相当する位置に剥離剤層が設けられているこ とを特徴とする I Cタグ。  5. An electronic circuit in which a first adhesive layer is laminated on the surface of a base material sheet, and a planar projection extends on the surface of the first adhesive layer, and an IC connected to the electronic circuit. A chip is provided, and a second adhesive layer covering the electronic circuit and the IC chip is laminated. Further, at the interface between the base material and the first adhesive layer, An IC tag, wherein release agent layers are provided at positions corresponding to both ends of a circuit surface formed by an electronic circuit and an IC chip.
6 . 平面状突起が、前記回路面内であって剥離剤層の設けられている位置に少な くとも 1つ設けられている請求項 4又は 5 (こ記載の I Cタグ。  6. The IC tag according to claim 4, wherein at least one planar protrusion is provided in the circuit surface at a position where the release agent layer is provided.
7. 平面状突起が、下記式で求められる面積を有する請求項 4〜 6のいずれかに 記載の I Cタグ。
Figure imgf000023_0001
7. The IC tag according to claim 4, wherein the planar projection has an area determined by the following equation.
Figure imgf000023_0001
PCT/JP2003/014827 2002-11-21 2003-11-20 Ic tag WO2004047017A1 (en)

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DE60332551D1 (en) 2010-06-24
EP1564678A1 (en) 2005-08-17
KR100973877B1 (en) 2010-08-03
EP1564678B1 (en) 2010-05-12
KR20050086663A (en) 2005-08-30
TW200416614A (en) 2004-09-01
US7294917B2 (en) 2007-11-13
TWI338863B (en) 2011-03-11
EP1564678A4 (en) 2007-05-23

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