WO2004036640A1 - 誘電体膜の形成方法 - Google Patents
誘電体膜の形成方法 Download PDFInfo
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- WO2004036640A1 WO2004036640A1 PCT/JP2003/013323 JP0313323W WO2004036640A1 WO 2004036640 A1 WO2004036640 A1 WO 2004036640A1 JP 0313323 W JP0313323 W JP 0313323W WO 2004036640 A1 WO2004036640 A1 WO 2004036640A1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/66—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials
- H10P14/662—Laminate layers, e.g. stacks of alternating high-k metal oxides
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
- C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
- C23C16/40—Oxides
- C23C16/405—Oxides of refractory metals or yttrium
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
- H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
- H10D64/01332—Making the insulator
- H10D64/01336—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid
- H10D64/01342—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid by deposition, e.g. evaporation, ALD or laser deposition
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
- H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
- H10D64/01332—Making the insulator
- H10D64/01336—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid
- H10D64/01344—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid in a nitrogen-containing ambient, e.g. N2O oxidation
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
- H10D64/681—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered
- H10D64/685—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered being perpendicular to the channel plane
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
- H10D64/691—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator comprising metallic compounds, e.g. metal oxides or metal silicates
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
- H10P14/6326—Deposition processes
- H10P14/6328—Deposition from the gas or vapour phase
- H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/69—Inorganic materials
- H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
- H10P14/6938—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides
- H10P14/6939—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides characterised by the metal
- H10P14/69392—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides characterised by the metal the material containing hafnium, e.g. HfO2
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/69—Inorganic materials
- H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
- H10P14/6938—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides
- H10P14/6939—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides characterised by the metal
- H10P14/69395—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides characterised by the metal the material containing zirconium, e.g. ZrO2
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/69—Inorganic materials
- H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
- H10P14/6938—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides
- H10P14/6939—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides characterised by the metal
- H10P14/69397—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides characterised by the metal the material containing two or more metal elements
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/69—Inorganic materials
- H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
- H10P14/6938—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides
- H10P14/69398—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides the material having a perovskite structure, e.g. BaTiO3
Definitions
- the present invention relates generally to the field of removal, and more particularly to the removal of a dielectric film that forms a dielectric film on an image using decorative materials. Disgusting background
- the CVD method has been widely used in the manufacturing process of rolling equipment. With today's ultra-high-speed solid-state equipment, gut lengths of less than 0.1 ⁇ m are becoming possible with the progress of the Grace process. In general, the operating speed of this device increases with the use of the lift system. Reduced according to the law.
- such a high dielectric film can be deposited at a temperature of 600 ° C or less.
- high-dielectric films formed by the MOCVD method in this manner generally have an average roughness (R a) exceeding several angstroms, for example, 0.3 nm. If it is applied to the gate feB) film of the ultra-high-speed transistor described above or the super capacitor of the Tsuruta DRAM, the local tunnel leak path force S is formed in the thin film, and the unevenness of the film surface Due to electricity Field concentration occurs, and problems such as a further increase in tunnel leak m3 ⁇ 43 ⁇ 4 occur in such a local leak 3 ⁇ 4s path.
- H f 0 2 film tetra tertiary butoxy hafnium as a raw material
- 3 ⁇ 43 ⁇ 43 ⁇ 43 ⁇ 43 ⁇ 4 is 5 5 0 ° C
- the average table ffif ⁇ of the film processing ® ⁇ force is obtained ⁇ of 0. 3 T orr R a is about 0.45 nm.
- the present invention generally addresses the need for a new and useful solution to the above problems.
- a more specific object of the present invention is to provide a method capable of reducing the surface roughness of a formed dielectric film by removing the dielectric film by the MOC VD method. Another recitation of the present invention is:
- the process of forming the tOIB dielectric film includes the step of mixing the S compound raw material into the processing container in which the t-type dielectric material is twisted, and forming the ttllB dielectric film in a hollow shape.
- FIG. 1 is a diagram showing a configuration of an MOCVD apparatus used in the present invention
- Figure 2 shows the relationship between 3 ⁇ 4 ⁇ reaction and Hl ⁇ of H f 0 2 film, the processing as a parameter
- H f 0 2 film JiD FIG indicated as the organic group compound raw material »time relationship;?
- FIG 5 Alpha, 5 beta is, H f 0 is Murasaki ⁇ Te relatively high processing SIB Kooi Diagram showing outline of two- film wisteria process;
- Figures 6 ⁇ and 6 ⁇ are diagrams showing the outline of the process of the H f 0 2 film that is ⁇ 1 at relatively low processing;
- FIG. 8 is a flowchart showing a process of forming a high dielectric film according to the present invention
- FIGS. 9A and 9B are diagrams schematically showing the process of FIG. 8;
- FIG. 10 is a diagram showing the effect of the present invention superimposed on FIG.
- FIGS. 11A to 1ID are diagrams showing a manufacturing process of a semiconductor device according to a first example of the present invention. The best to make an invention! ⁇
- FIG. 1 shows a configuration of a MOC VDj device 10 used in the first example of the present invention.
- the MOC VD apparatus 10 includes a container 11 provided by a pump (not shown) at port 11A, and a disposable as3 ⁇ 4 f ⁇ ⁇ 3 ⁇ 43 ⁇ 4 ⁇ stand 1 2 force s is provided.
- the t! If self-container 11 further includes a sheath 13 made of aluminum or the like so as to face the S3 ⁇ 4W f to be processed on the nozzle 12.
- S is provided, and oxygen gas is supplied to the k
- a liquid supply source S for supplying a liquid organic ⁇ compound raw material such as tetratertiary butoxy hafnium held in a bubbler 15 to the container 11 via a vapor phase raw material controller 16 and a line 17 is provided. ing.
- an additional force S consisting of a lamp is provided to heat the leaked aswf to a desired level.
- the inventors of the present invention was performed using MOC VD apparatus 10 of FIG. 1, the formation ⁇ 3 ⁇ 4 «results of H f 0 2 film on silicon emission substrate surface is shown.
- the vertical axis represents Lin of the resulting a H f 0 2 film shows a horizontal axis Kasokehan.
- ⁇ represents the deposition ⁇ at 40 Pa (0.3 To rr) treated SiE
- ⁇ represents ⁇ ⁇ deposited at 93 Pa (0.7 To rr) treatment E.
- OOPa 3. OTo rr
- Figure 3 shows the Hf obtained in this experiment. The relationship between the melding of the two membranes and the squad is shown for various low flow rates. However in Figure 3, the vertical axis represents the resulting H ⁇ 0 2 film, the horizontal axis shows the processing. In Fig. 3, * indicates that the deposition was performed at a flow rate of 1500 SCCM, ⁇ indicates that deposition was performed at a flow rate of 1000 SCCM, and ⁇ indicates that the deposition was performed at a flow rate of 500 SCCM. ⁇ indicates that deposition was performed at an oxygen flow rate, and ⁇ indicates that deposition was performed at a ⁇ flow rate of 100 SCCM: ⁇ . Experiments 3 the deposition of the H f ⁇ 2 film, Slight substrate temperature of 5 5 0 ° C, shows the 1 0 0 seconds Gyotsu were result Te, Ru.
- the deposition of the organic compound raw material on the inner wall of the processing container 11 or on the shower head 13 is performed while the organic compound raw material is kept in the processing container. It is thought to be caused by collision with the inner wall surface of 11 and the shower head 13. That is, it is considered that the deposition of the experimental compound raw material on the inner wall of the processing vessel or on the shower head is governed by the if3 ⁇ 4 time in the processing cloth 11 of the compound raw material.
- the deposition of the H f O 2 film on the ttlf self-neutral f flows along the surface of the gas power S »SS3 ⁇ 4W f introduced from the shower head 13, This is caused by the generation of f ⁇ WS at that time, and it is considered that there is no relation to the time in the processing container 11 for the raw material of the organic compound.
- FIG der representing the results of Figure 3 in relation to the H f 0 2 film setup time.
- the sculpture time is
- Figures 5 A and 5B are shown in Figure 4;
- the surface of Ne 2; S®j3 ⁇ 4W f has S ⁇ S ⁇ / leakage time of the raw material S Long, crystal nuclei 21 with a relatively large areal density on the shelf of the deposition
- a H f O 2 film 22 consisting of crystals having a relatively small grain size and growing from strong crystal nuclei 21 is formed.
- the raw material molecules of the raw material of the organic compound are not covered with the shower head 13 or the inner wall of the key container 11.
- 6 beta shows you in FIG. 4, Te containing compound feedstock time force S Tanre, the progress of H f 0 2 film deposition in Ne OSS3 ⁇ 4W f surface schematically.
- the distribution of H f O 2 nuclei 21 formed on the surface of i MS3 ⁇ 4W f is relatively sparse
- the distribution of H f O 2 nuclei 21 on the surface of i MS3 ⁇ 4W f is relatively sparse.
- H f O2 crystal particles are interfering with other particles having a sparse distribution It is considered that the crystal grows freely and as a result, the grain size of each H f 0 2 crystal increases, and the surface roughness force S of the obtained H f 0 2 film 22 increases. Also nucleation occurs on the surface of Ne ⁇ S3 ⁇ 4Wf, H f 0 2 grain growth occurs even from such nuclei while growing H f 0 2 film 2 2 force S is also FIG. 6 B step but the H f 0 2 crystal grains grown in this way delay sister inhibitory Marete in H f 0 2 grains growing on the growth potential S destination, as a result, a large crystal grains in the film A state in which small crystal grains and force S are mixed occurs.
- FIG. 7 is a graph in which the relationship between the time of the activated ⁇ raw material in the processing vessel 11 and the surface roughness of the HfO 2 film is superimposed on the graph of FIG.
- the plot of ⁇ and the vertical axis on the right side show the average surface roughness Ra expressed in angstrom units (0.1 nm units).
- Figure 8 shows the removed by by H f 0 2 film MO CVD method according to the first flame example in which the cage ⁇ was persists, the present invention based on the findings of Iyaonore.
- the MOC VD apparatus 10 shown in FIG. 1 was used, and it was used in step 1;
- Tetra tert-butoxy hafnium used as a metal compound raw material 11 The working time in the medium is set to the first value, for example, 3.2 seconds, and the processing from 5 to: L 0 seconds is performed.
- the fiber of the fiber f was set to 550 ° C, and the WiE was relatively high at 200-40 OPa (1.5-3 OTorr).
- V set the value to fiilB ⁇ Bra 15 and supply Ar gas at a flow rate of 20 SCCM to T. Charbutoxy hafnium is supplied.
- oxygen gas is supplied from the venom line 14 at a flow rate of 1500 SCCM.
- Te is H f 0 2 crystal nuclei at a high surface density in 3 ⁇ 4WS3 ⁇ 4W f surface is made form as shown in FIG. 9 A.
- the step 1 5 to: Canceled in a relatively short time within L 0 seconds.
- the knitting time was set to a second, smaller value, for example, 0.03 seconds in the step 2 and the deposition of the HfOs film was performed under the same conditions as in step 1 except for the time value.
- perform the time for obtaining the desired HI force S for example, 30 to 100 seconds. More specifically, to reduce the processing of tiflB processing ⁇ 11 to about 4 OPa (0. 3To rr) hereinafter and other conditions are shaped formed a H f 0 2 film is the same as the previous step 1.
- H f 0 2 crystal nuclei on 3 ⁇ 43 ⁇ 4 f 2 crystals grow, but in the process of step 1, H f O 2 crystal nuclei 21 are formed at a high level and areal density on the surface of the substrate W f as shown in FIG. Unlike the age shown in Fig. 6 ⁇ , these crystal nuclei 21 have relatively small and uniform H f 0 2 crystal grains that grow uniformly and have a reduced surface roughness. H f 0 2 film is obtained. At this time, in the process shown in Fig.
- points indicated by arrows indicate the surface roughness Ra of the HfO 2 film formed by the two-step process of FIG.
- the surface roughness Ra of the H f O 2 film thus formed is about 0.19 nm, which is a table required as the gut mist of an ultra-high 33 ⁇ 4M ISFET.
- the surface roughness Ra satisfies (Ra ⁇ 0.2 nm). From Table 10, it can be seen that the time of ⁇ for the surface roughness Ra force S of 0.2 nm is about 0.25 seconds, so that the time exceeds 0.25 seconds in Step 1 of FIG.
- the Hfo 2 film with the desired small surface roughness can be used to remove the S3 ⁇ 4 It is possible to obtain while depositing the partial substance.
- Table 2 summarizes the effects of the two-step process according to the invention described above.
- H f 0 2 film can be formed in the same manner the formation of Z r 0 2 film.
- tetra-tert-butoxyzirconium can be used instead of tetra-tert-butoxy hafnium.
- the invention further H f 0 2 film tetrakis oxygenate chill amide Nono Funiumu (TD EA H: H f [ N (C2H5) 2] 4 or tetrakis dimethylcarbamoyl Honoré amide Seo, Funiumu (T DMAH: H f [N (CHa) 2] It is also useful to form using 4).
- H f 0 2 film or Z r 0 2 film Hough Yu arm silicate (H f S i O4) film or a zirconium silicate are one preparative (Z r S i O4) film It is also useful for forming a high dielectric film or a ferroelectric film such as a PZT (Pb (Zr, Ti) O3) film and a BST (BaSrTiO3) film.
- TEO S tetratertiary Help Toki Shihafuniumu and tetraethoxysilane as starting materials
- TEO S tetratertiary Help Toki Shihafuniumu and tetraethoxysilane as starting materials
- the control of the grace period in the processing of the raw materials of the organic compound is not limited to the control of the processing, but the supply of the raw materials of the organic compound to the raw material is not limited to the control of the processing.
- ⁇ * That is, it can be performed by controlling the flow rate.
- the flow rate of the raw material of the ttiia test compound is set to a small value
- the flow rate of the ttiia experimental compound raw material is set to a small value.
- It is also possible to control the venom time by setting the flow rate of the raw material of the metal compound to a larger value.
- the control of the occupation time can be performed by setting the flow rate of the carrier gas or the wisteria gas small in the step 1 of FIG. 8 and increasing it in the step 2.
- FIG. 11A-: L1E shows the manufacturing process of the rolling element device according to the second embodiment of the present invention.
- a SiO 2 layer having a thickness of 1 nm or less is formed.
- the base acid 14 composed of a film or a SiON film is subjected to a plasma radical treatment by, for example, performing a radical treatment using an ultraviolet radical or a tfria radical treatment.
- a polysilicon film 44 is deposited on the metal oxide film 43, and although not shown, after forming a silicide film on the surface thereof, furthermore, in the step of FIG. By pattering this, the gate 44A is opened.
- healing areas 41 A, 41 B on both sides of the gate 34 in the knitted silicon fiber 41 by performing ion 3 ⁇ 4 ⁇ with the mask of disgusting gate ®
- the surface roughness of the gate mist formed from 3 can be suppressed to within 0.2 nm, and the tunnel leak current through the gate II can be effectively suppressed.
- It can be formed by Z r 0 2 film.
- the high dielectric film such as H f 0 2 film or Z r 0 2 film by the present invention OCVD method
- decomposition products of organic ⁇ S compound precursor to such head to shower or parts min It is edible to suppress the surface roughness of the simultaneously formed film while suppressing the deposition of ⁇ substances.
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- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
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- Inorganic Chemistry (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
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- Chemical Vapour Deposition (AREA)
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- Insulated Gate Type Field-Effect Transistor (AREA)
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Abstract
Description
Claims
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/527,683 US7105362B2 (en) | 2002-10-21 | 2003-10-17 | Method of forming dielectric film |
| AU2003301469A AU2003301469A1 (en) | 2002-10-21 | 2003-10-17 | Method of forming dielectric film |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002-305872 | 2002-10-21 | ||
| JP2002305872A JP2004140292A (ja) | 2002-10-21 | 2002-10-21 | 誘電体膜の形成方法 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2004036640A1 true WO2004036640A1 (ja) | 2004-04-29 |
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| Application Number | Title | Priority Date | Filing Date |
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| PCT/JP2003/013323 Ceased WO2004036640A1 (ja) | 2002-10-21 | 2003-10-17 | 誘電体膜の形成方法 |
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| Country | Link |
|---|---|
| US (1) | US7105362B2 (ja) |
| JP (1) | JP2004140292A (ja) |
| AU (1) | AU2003301469A1 (ja) |
| WO (1) | WO2004036640A1 (ja) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4522900B2 (ja) * | 2005-03-30 | 2010-08-11 | 東京エレクトロン株式会社 | 成膜方法および記録媒体 |
| JP4689324B2 (ja) * | 2005-04-04 | 2011-05-25 | 東京エレクトロン株式会社 | 成膜装置、成膜方法および記録媒体 |
| US7833904B2 (en) * | 2005-06-16 | 2010-11-16 | The Trustees Of Columbia University In The City Of New York | Methods for fabricating nanoscale electrodes and uses thereof |
| JP4722876B2 (ja) * | 2007-04-16 | 2011-07-13 | 東京エレクトロン株式会社 | 金属酸化膜の形成方法 |
| US20090071687A1 (en) | 2007-09-13 | 2009-03-19 | Medtronic, Inc. | Medical electrical lead |
| US8012822B2 (en) | 2007-12-27 | 2011-09-06 | Canon Kabushiki Kaisha | Process for forming dielectric films |
| US8148275B2 (en) | 2007-12-27 | 2012-04-03 | Canon Kabushiki Kaisha | Method for forming dielectric films |
| JP2011003620A (ja) * | 2009-06-16 | 2011-01-06 | Toyota Central R&D Labs Inc | 電磁気素子用絶縁膜及び電界効果素子 |
| EP3260164A1 (de) * | 2014-08-19 | 2017-12-27 | BIOTRONIK SE & Co. KG | Einführvorrichtung für ein implantat |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001075956A1 (en) * | 2000-03-30 | 2001-10-11 | Tokyo Electron Limited | Method of forming a dielectric film |
| WO2002073679A1 (en) * | 2001-03-09 | 2002-09-19 | Nec Corporation | Vapor growth method for metal oxide dielectric film and pzt film |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6475854B2 (en) * | 1999-12-30 | 2002-11-05 | Applied Materials, Inc. | Method of forming metal electrodes |
| US6709989B2 (en) * | 2001-06-21 | 2004-03-23 | Motorola, Inc. | Method for fabricating a semiconductor structure including a metal oxide interface with silicon |
| US6664116B2 (en) * | 2001-12-12 | 2003-12-16 | Sharp Laboratories Of America, Inc. | Seed layer processes for MOCVD of ferroelectric thin films on high-k gate oxides |
| US7122415B2 (en) * | 2002-09-12 | 2006-10-17 | Promos Technologies, Inc. | Atomic layer deposition of interpoly oxides in a non-volatile memory device |
-
2002
- 2002-10-21 JP JP2002305872A patent/JP2004140292A/ja active Pending
-
2003
- 2003-10-17 US US10/527,683 patent/US7105362B2/en not_active Expired - Lifetime
- 2003-10-17 AU AU2003301469A patent/AU2003301469A1/en not_active Abandoned
- 2003-10-17 WO PCT/JP2003/013323 patent/WO2004036640A1/ja not_active Ceased
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001075956A1 (en) * | 2000-03-30 | 2001-10-11 | Tokyo Electron Limited | Method of forming a dielectric film |
| WO2002073679A1 (en) * | 2001-03-09 | 2002-09-19 | Nec Corporation | Vapor growth method for metal oxide dielectric film and pzt film |
Also Published As
| Publication number | Publication date |
|---|---|
| US7105362B2 (en) | 2006-09-12 |
| US20060008969A1 (en) | 2006-01-12 |
| JP2004140292A (ja) | 2004-05-13 |
| AU2003301469A1 (en) | 2004-05-04 |
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