WO2004027995A3 - Integrated circuit comprising an sstl (stub series terminated logic) pre-driver stage using regulated power supply and method for performing an sstl operation - Google Patents

Integrated circuit comprising an sstl (stub series terminated logic) pre-driver stage using regulated power supply and method for performing an sstl operation Download PDF

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Publication number
WO2004027995A3
WO2004027995A3 PCT/US2003/024817 US0324817W WO2004027995A3 WO 2004027995 A3 WO2004027995 A3 WO 2004027995A3 US 0324817 W US0324817 W US 0324817W WO 2004027995 A3 WO2004027995 A3 WO 2004027995A3
Authority
WO
WIPO (PCT)
Prior art keywords
sstl
driver stage
voltage
virtual
power supply
Prior art date
Application number
PCT/US2003/024817
Other languages
French (fr)
Other versions
WO2004027995A2 (en
Inventor
Brian W Amick
Lynn Warriner
Claude R Gauthier
Tri K Tran
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/247,082 external-priority patent/US6873503B2/en
Priority claimed from US10/247,127 external-priority patent/US6734716B2/en
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Priority to GB0506134A priority Critical patent/GB2408642B/en
Priority to AU2003259060A priority patent/AU2003259060A1/en
Publication of WO2004027995A2 publication Critical patent/WO2004027995A2/en
Publication of WO2004027995A3 publication Critical patent/WO2004027995A3/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Control Of Electrical Variables (AREA)
  • Amplifiers (AREA)
  • Dc-Dc Converters (AREA)

Abstract

A SSTL memory interface pre-driver stage (24) that uses a voltage regulator (32) to generate “virtual” supply and ground voltages is provided. The “virtual” supply, being lower than a power supply voltage of the pre-driver stage (24), and the “virtual” ground voltage, being greater than a zero volt ground voltage, allows low voltage transistors to be used, thereby improving interface performance and decreasing system power consumption. The pre-driver stage (24) uses a biasing circuit (30) to bias the voltage regulator (32), formed by a transistor arranged in a source follower configuration, to generate the “virtual” supply and ground voltages off which a voltage translator stage (36) of the pre-driver stage operates to generate an output of the pre-driver stage (24).
PCT/US2003/024817 2002-09-19 2003-08-08 Integrated circuit comprising an sstl (stub series terminated logic) pre-driver stage using regulated power supply and method for performing an sstl operation WO2004027995A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
GB0506134A GB2408642B (en) 2002-09-19 2003-08-08 SSTL pre-driver design using regulated power supply
AU2003259060A AU2003259060A1 (en) 2002-09-19 2003-08-08 Integrated circuit comprising an sstl (stub series terminated logic) pre-driver stage using regulated power supply and method for performing an sstl operation

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US10/247,082 US6873503B2 (en) 2002-09-19 2002-09-19 SSTL pull-up pre-driver design using regulated power supply
US10/247,127 2002-09-19
US10/247,127 US6734716B2 (en) 2002-09-19 2002-09-19 SSTL pull-down pre-driver design using regulated power supply
US10/247,082 2002-09-19

Publications (2)

Publication Number Publication Date
WO2004027995A2 WO2004027995A2 (en) 2004-04-01
WO2004027995A3 true WO2004027995A3 (en) 2004-06-17

Family

ID=32033231

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2003/024817 WO2004027995A2 (en) 2002-09-19 2003-08-08 Integrated circuit comprising an sstl (stub series terminated logic) pre-driver stage using regulated power supply and method for performing an sstl operation

Country Status (3)

Country Link
AU (1) AU2003259060A1 (en)
GB (1) GB2408642B (en)
WO (1) WO2004027995A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8148962B2 (en) 2009-05-12 2012-04-03 Sandisk Il Ltd. Transient load voltage regulator

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4006491A (en) * 1975-05-15 1977-02-01 Motorola, Inc. Integrated circuit having internal main supply voltage regulator
US4430582A (en) * 1981-11-16 1984-02-07 National Semiconductor Corporation Fast CMOS buffer for TTL input levels
GB2241845A (en) * 1990-01-18 1991-09-11 Mitsubishi Electric Corp Voltage adjusting circuit
EP0517375A2 (en) * 1991-06-06 1992-12-09 Hitachi, Ltd. Semiconductor integrated circuit device
US5731713A (en) * 1994-01-31 1998-03-24 Townsend And Townsend And Crew Llp TTL to CMOS level translator with voltage and threshold compensation
EP0905902A2 (en) * 1997-09-29 1999-03-31 Siemens Aktiengesellschaft Constant current cmos output driver circuit with dual gate transistor devices
US6087885A (en) * 1997-09-11 2000-07-11 Mitsubishi Denki Kabushiki Kaisha Semiconductor device allowing fast and stable transmission of signals
US6172524B1 (en) * 1998-06-29 2001-01-09 Hyundai Electronics Industries Co., Ltd. Data input buffer

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6023174A (en) * 1997-07-11 2000-02-08 Vanguard International Semiconductor Corporation Adjustable, full CMOS input buffer for TTL, CMOS, or low swing input protocols

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4006491A (en) * 1975-05-15 1977-02-01 Motorola, Inc. Integrated circuit having internal main supply voltage regulator
US4430582A (en) * 1981-11-16 1984-02-07 National Semiconductor Corporation Fast CMOS buffer for TTL input levels
GB2241845A (en) * 1990-01-18 1991-09-11 Mitsubishi Electric Corp Voltage adjusting circuit
EP0517375A2 (en) * 1991-06-06 1992-12-09 Hitachi, Ltd. Semiconductor integrated circuit device
US5731713A (en) * 1994-01-31 1998-03-24 Townsend And Townsend And Crew Llp TTL to CMOS level translator with voltage and threshold compensation
US6087885A (en) * 1997-09-11 2000-07-11 Mitsubishi Denki Kabushiki Kaisha Semiconductor device allowing fast and stable transmission of signals
EP0905902A2 (en) * 1997-09-29 1999-03-31 Siemens Aktiengesellschaft Constant current cmos output driver circuit with dual gate transistor devices
US6172524B1 (en) * 1998-06-29 2001-01-09 Hyundai Electronics Industries Co., Ltd. Data input buffer

Also Published As

Publication number Publication date
AU2003259060A8 (en) 2004-04-08
WO2004027995A2 (en) 2004-04-01
GB2408642B (en) 2006-08-09
GB2408642A (en) 2005-06-01
GB0506134D0 (en) 2005-05-04
AU2003259060A1 (en) 2004-04-08

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